Surface Micromachining of Microstructures Surface Micromachining

Microstructures are fabricated on Steps to realize a Poly a Silicon substrate by deposition anchored Cantilever and selective etching of multiple SiO2 layers of thin films Silicon substrate

Patterned Polysilicon

Polysilicon is structural layer Silicon substrate and SiO2 is the sacrificial layer

Free standing Cantilever

Silicon substrate Fabrication of Microsystems

Wafer Cleaning

Deposition (Evaporation, sputtering, CVD, etc) [Metals, Semiconductors, Dielectrics] Processing ofbondedwafer

Resist processing & Pattern Repeat transfer for each new layer Etching (wet; dry: RIE, DRIE) [Substrate: isotropic, anisotropic; thin films]

Wafer level Bonding /Packaging

Dicing Microsystems may require non-electrical interfaces Die attach

Final Packaging, Required only for Testing Release etch devices with surface micromachined parts Surface Micromachining

Microstructures are fabricated on Steps to realize a Poly a Silicon substrate by deposition anchored Cantilever and selective etching of multiple SiO2 layers of thin films Silicon substrate

Patterned Polysilicon

Polysilicon is structural layer Silicon substrate and SiO2 is the sacrificial layer

Free standing Cantilever

Silicon substrate Process Steps

 Deposit or Grow thick silicon dioxide layer on the top surface of Si wafer.

 Deposit photoresist by spin coating and pattern transfer by UV lithography.

 Develop photoresist to expose regions of silicon dioxide for etching. As in lithography, the resist is baked to withstand the etching step that follow.

 Remove silicon dioxide from those areas at which the cantilever beam (polysilicon) anchors on the Si wafer. This involves coating with photoresist, its exposure, developing, etching of oxide and dissolving the photoresist.

 Deposit polysilicon all over theon the surface by CVD process.Thisis doped to change its etch characteristics and conductivity. The beam area is defined by patterning through steps similar to that followed for etching oxide.

 Dope, pattern and harden polysilicon layer to form the cantilever beam. Patterning of polysilicon invoves coating with photoresist, its exposure, developing, etching of polysilicon and dissolving the photoresist

 Remove SiO2 sacrificial layer by release etch. Unit processes Required in Surface Micromachining

 Deposition of thin films

 Physical or Chemical vapor deposition (for polySi, SiO2, Si3N4)

 Plating (for metals)

 Spin coating (for SU-8)

 Doping

 To change conductivity of PolySi  conducting electrodes

 To change chemical (etch rate) characteristics

 Pattern transfer & Etching

 Lithography

 Dry Etching

 Thin films used in MEMS

 Thermal silicon dioxide

 Dielectric layers  polymeric Role of Thin films  ceramic Structural

 silicon-compound Sacrificial Dielectric  Polycrystalline silicon Semiconductor  poly-Si (epi-layers)  Metal films Conductor  predominantly aluminum

 Active Materials

 Ferroelectrics

 Piezoelectrics

 Usually thin film materials may have multiple functions Thin Film Deposition process

 Source

 Transport

 Condensation on substrate

 The nature of the film deposited depends on process parameters like substrate, deposition temperature, gaseous environment, rate of deposition etc.

 In Physical vapor Deposition (PVD) process, this transfer takes place by a physical means such as evaporation or impact

 Favorable conditions are created to transfer the material from the source (target) to the destination (substrate).

 In chemical Vapor Deposition (CVD) process films are deposited through a chemical reaction. Sputtering

 A physical phenomenon involving

 The creation of plasma by discharge of Vacuum neutral gas such as helium enclosure

 Acceleration of ions via a potential

gradient and the bombardment of a Cathode (Target) ‘target’ or cathode Ions  Through momentum transfer atoms Sputtered atoms near the surface of the target metal Wafer become volatile and are transported as Anode vapors to a substrate

 Film grows at the surface of the substrate via deposition Vacuum pump Process in CVD

 Mass transport of reactant (and diluent gases ) in the bulk gases flow region from the reactor inlet to the deposition zone.

 Gas phase reactions leading to film precursors and by-products.

 Mass transport of film pre-cursors and reactants to the growth surface.

 Adsorption of film precursors and reactants on the growth surface.

 Mass transport of by-products in the bulk gas flow region away from the deposition zone towards the reactor exit

 Types

 Plasma enhanced (PECVD)

 Atmospheric pressure (APCVD)

 Low pressure (LPCVD)

 Very low pressure (VLCVD)

 Metallographic (MOCVD) LPCVD of Si Compounds

CVD is used to form SiO2 layers that are much thicker in relatively very short times than thermal oxides.

SiO2 can be deposited from reacting silane and oxygen in LPCVD reactor at 300 to 500°C where 500C SiH4  O2  SiO2  2H2

SiO2 can also be LPCVD deposited by decomposing dichlorosilane 900C SiCl 2H2  2H2O  SiO 2  2H2  2HCl

SiO2 can also be LPCVD deposited by from tetraethyl orthosilicate (TEOS or, Si(OC2H5)4) by vaporizing this from a liquid source.

Si3N4 can be LPCVD or PECVD process. In the LPCVD process, dichlorosilane and ammonia react according to the reaction

~ 800C 3SiCl 2H 2  4NH 3  Si3 N 4  6HCl  6H 2 Polysilicon

 Polysilicon comprises of small crystallites of single crystal silicon, separated by grain boundaries.

 This is also used in MEMS and microelectronics for electrode formation and as a conductor or high-value resistor, depending on its doping level (must be highly doped to increase conductivity).

 When doped, resistivity 500-525cm

 Polysilicon is commonly used for MOSFET Gate electrode:

 Poly can form ohmic contact with Si.

 Easy to pattern

 Carried out at low pressure (200mTorr to 1000mTorr) by pyroletic

decomposition of silane (SiH4 ). in the temperature range 500-625C SiH42 Si 2H

 Most common low-pressure processes used for polysilicon

 Pressures between 0.2 and 1.0 Torr using 100% silane. Pattern Transfer Techniques

 In Lithography

 Resist coating  Spin coating  Soft baking  UV exposure  Development  Post baking  Etching of thin film  Resist striping

 In lift-off process a photoresist pattern is generated initially on the substrate instead of etching the unwanted material.

 The basic criterion for the lift off technique is that the thickness of deposited film should be significantly less than that of the photoresist and the developed patterns have vertical side walls.  Metal layers with high resolution can be patterned using lift off technique. Metals such as gold (which can be etched with aqua regia) can be patterned with simple processes by lift- off.

Lithography Thin film Coating of UV exposure & Removal of Deposition Resist Development unwanted material

Lift-off

Coating of UV exposure & Metal Removal of resist & Resist Development Deposition unwanted metal Etching of thin films

 Silicon Nitride etching

 1%HF  60nm/min

 10%HF  500nm/min

 H3PO4  10nm/min (180C)

 Silicon Dioxide Etching

 Buffered HF  100-250nm/min

 HF (very fast)

 Etch rates depends on how the film was deposited (film quality)

 Copper or Nickel

 FeCl3

 Gold Chromium

 Aqua regia or Iodine Aquaregia or HCl:Glycerine Doped regions

 For doping of semiconductors, controlled quantities of impurity Phosphorus Diffusion atoms are introduced into the Make Tempress selected regions of the surface Temperature Range 800- 1200 ˚C through masks on the top of the Dopant Source POCl wafer. 3 Bubbler Gas Nitrogen (0.4ltr/min)  Diffusion and Ion implantation are common methods for this. Carrier Gas Nitrogen (4 ltr/min) Flow rate of Oxygen 0.6 l/min  Used as etch stop layers  N and P regions can be formed for active semiconductors  Diffusion  Wafer placed in a high temp furnace Boron Diffusion and a carrier gas is passed. Boron and phosphorous are commonly used Make Tempress dopants Temperature Range 900-1200˚C  The deposited wafer is heated in a Dopant Source Boron Nitride Disc furnace for drive in; oxidising or inert gas to redistribute dopants in the wafer Process Ambient Nitrogen

to desired depth Flow rate of N2 4 ltr/min  Silicon dioxide is used as the masking layer Surface Micromachining

 Structural layer

 A layer of thin film material that comprises a mechanical device.

 This layer is deposited on the sacrificial layer, and then released by etching it away.

 Sacrificial Layer

 A layer of material that is deposited between the structural layer and the substrate to provide mechanical separation and isolation between them.

 This is removed after the mechanical components on the structural layer are fully formed, by release etch. This approach facilitates the free movement of the structural layer with respect to the substrate.

 But of course, these materials should be chemically distinct..

 So that suitable etchant can be selected to remove the sacrificial layer without removing the structural layer AND the substrate etc. Detailed Process Steps in Surface Micromachining

 Sacrificial Layer deposition and etching

 LPCVD of PSG 2µm

 PSG by adding phosphorous to SiO2 → improved etch rate

 Controlled window taper

 Easier to make poly layer

 PSG is densified at 950°C for 30min

 Conductive (phosphorous goes up as dopant)

 Windows in the base layer for anchoring structures.  Deposition of structural material by CVD (or sputtering – PVD)

 Poly Si : LPCVD (25-150 Pa) in a furnace at 600°C from pure Silane

SiH4 → Si+2H2

 Typical process conditions: 605°C; 73 Pa (550 mTorr); Flow rate : 125 sccm

 Deposition rate: 100Å/min.

 To make the structure conductive, dopants are introduced

 Along with silane or by ion implantation.

 Structures are patterned by RIE in SF6 plasma  Selective etching of spacer material

 Structures are freed from substrate by undercutting of the sacrificial layer

 Immersed in HF solution to remove sacrificial layer

 PSG is removed by concentrated/ dilute / buffered HF

 To shorten etch time, extra apertures are usually provided in the structure.

 Thicker layers etch faster. Material Pairs

 Poly/SiO2

 LPCVD deposited poly as structural layer;

 Thermal or LPCVD oxide as sacrificial layer

 Oxide dissolves in HF, and not poly.

 Both materials are used in IC fabrication.

 Deposition and etching technologies are matured

 Material systems are compatible with IC processing

 Poly has good mechanical properties. Its electrical properties can be improved by doping

 Nitride can be used in this system for insulation

 Silicon Nitride/Poly-Silicon

 LPCVD nitride is used as structural layer; Poly Si as sacrificial layer

 EDP or KOH to dissolve poly. Additional material Pairs

 Tungsten/SiO2  CVD tungsten as the structural layer; Oxide as sacrificial layer

 HF for etchant

 Polyimide/Aluminum

 Polyimide as structural layer, aluminum as sacrificial layer

 Acid based etchants to etch aluminum

 Polyimide has small elastic modulus

 Can take large strains

 Both can be fabricated at low temperatures <400C

 Other possible structural materials :

 Al, SiO2, Si3N4, Silicon oxynitride, polyimide, diamond, SiC, sputtered Si, GaAs, Tungsten, α-Si:H, Ni, W Surface micromachined device: SOI accelerometer

SOI or polySi Patterned mechanical structure

(polysi or single crystal ) over the sacrificial SIO2 Oxide Etch, Release the mechanical structure

Mass

Beam Si or PoySi

SiO2 (1 μm)

Bulk Si Metallization of electrodes

Mass

Electrodes (Cr / Au) Beam Si or PolySi

SiO2 (1 μm)

Bulk Si Removal of Sacrificial Material

 Removal of scrificial layer below a large area structure is difficult.

 Etch holes are provided to improve etch characteristics Stress in Thin film

 Stress can be due to

 Mismatch of thermal expansion itself

 Non-uniform plastic deformation

 Substitutional / interstitial impurities

 Growth process

 It causes

 Film cracking

 Delamination

 Void formation

 Special cases

 Al films are usually stress free

 Tungsten accumulates more stress when sputter deposited Stiction: A limitation in Micromachining

 The free –standing structure is obtained by etching the sacrificial layer using HF solution. The etchant is rinsed with de-ionized water. The water is simply dried through evaporation.

 During drying, the flexible micro-structure is pulled down to the substrate due to capillary pressure induced by the droplet in the gap.

 If the adhesion force between the contacted areas is larger than the elastic restoring force of the deformed structure, the structure remains stuck to the substrate even after being completely dried

 Large surface area of the cantilever beam tend to deflect through stress gradient or surface tension induced by trapped liquids attach to the substrate/isolation layer during the final rinsing and drying steps

 A stiction phenomena that may be related to hydrogen bombarding or residual contamination or Vander waal’s forces.

SEM micrograph of polysilicon Cross section of cantilevers illustrating (a) the upward deflection of the beam and cantilever with stiction (b) the stiction problem. problem STICTION

 Static Friction = Stiction

 Stiction occurs whenever

 microstructure adhere to adjacent surfaces

 flexible and smooth surfaces are brought in contact with one another.

 Stiction is a major failure mechanism in Surface Micromachining

 It may be classified into two types

 Release Stiction : During the final steps of the micro-machining processing(sacrificial layer etching). This happens during the sacrificial layer etching and drying process – caused primarily by capillary forces due to surface tesion

 In-Use Stiction : This occurs due to Mechanical Shocks, Electrostatic forces etc during operation or during packaging. This causes eventual collapse and permanent adhesion of microstructures when released microstructures are exposed to humid environment Surface Profiler Pictures

Released Beam Unreleased Beam

SEM Pictures Examples of Stiction

SEM of beams stuck to the Ground plane

Released Beam (intended) Oxide Silicon Substrate anchor Approaches to Overcome Stiction

 By forming bumps

 Increases process steps

 Use of sacrificial polymer columns (along with oxide)

 Use isotropic oxygen plasma to etch the polymer after oxide etch.

 Reduce surface tension of the final rinse solution

 Roughening opposite surface faces

 Making Si surface hydrophobic

 Freeze drying

 Super critical drying with CO2 at 35°C, 1100 psi

 Release etch is done after all other wet processes are completed ( packaging) Fabrication of Microsystems

Wafer Cleaning

Deposition (Evaporation, sputtering, CVD, etc) [Metals, Semiconductors, Dielectrics] Processing ofbondedwafer

Resist processing & Pattern Repeat transfer for each new layer Etching (wet; dry: RIE, DRIE) [Substrate: isotropic, anisotropic; thin films]

Wafer level Bonding /Packaging

Dicing Microsystems may require non-electrical interfaces Die attach

Final Packaging, Required only for Testing Release etch devices with surface micromachined parts Use of CPD to Avoid Stiction

 If a liquid was heated in a closed system so that the Critical Pressure could be attained, at the Critical Temperature, any visible meniscus would disappear, the surface tension would be zero and it would not be possible to distinguish between the properties of a liquid or gas.

 We therefore have continuity of state. Above this temperature the gas cannot be liquefied by the application of pressure and strictly speaking a substance should only be classified as a gas above its Critical Temperature, below this temperature where it could possibly be liquefied by the application of pressure, it is more precisely termed a vapour. The Critical Phenomena in CO2 Supercritical Drying with CO2

For CO2 supercritical region is for temperature above 31.1C and pressures above 72.8 Atmospheres (1072 psi)

Pressure Supercritical Drying

Critical Point 1200psi

25C 35C Temperature Super Critical Drying

For CO2 supercritical region is for temperature above 31.1C and pressures above 72.8 Atmospheres (1072 psi) Super critical Drying steps: • After HF etch, the structure is rinsed in DI water without letting them dry • The water is exchanged with methanol by dilution • The wafer is then transferred to pressure vessel in which

the methanol is replaced by liquid CO2 at 25C and 1200psi • The contents of the pressure vessel are then heated to

35C and CO2 is vented at temperature above 35C (ensuring that it only exits in gaseous form) CRITICAL CONSTANTS

Substance Critical Temp. C Critical Pressure P.S.I Hydrogen -234.5 294 Oxygen -118 735 Nitrogen -146 485 Carbon Dioxide +31.1 1072 Carbon Monoxide +141.1 528 Water +374 3212 In-use Stiction and methods to Overcome

 Mechanical Shocks, Electrostatic forces etc during operation or during packaging can also cause stiction.

 For example, as the sensitivity of micromechanical accelerometer is increased, the stiffness of the proof mass suspension will have to be lower. As a consequence the mechanical shock required to bring the mechanical elements into contact with each other will decrease.

 In-use stiction can also occur when released micro-structures are exposed to humid environment.

 Water vapor can condense and the water droplets, formed in narrow gaps present between these surfaces, exert an attractive force by pulling the microstructure toward the substrate. This causes eventual collapse and permanent adhesion of microstructures Other Approaches for Reducing of Stiction

 Reducing adhesion Energy by providing hydrophobic surface coating

 This can eliminate water mediated adhesion.. Weakly adhesive material such as fluorinated polymer (eg PTFE) still has a surface tension of about 20mJ/ m2 . (note that an adhesion energy of 100J/m2 is high enough to counter balance restoring elastic force).

 Reducing the Geometrical area contact.

 This is done using bumps and side-wall spacers, side-wall-spacing, supports on substrate .

 Increase surface roughness

 References

 Niels Tas et.al, “ Stiction in Surface micromachining”, J. Micromech. Micreng., Vol6.pp. 385-397, 1996.

 Chang-Jim Kim et.al., “Comparative Evaluation of Drying Techniques for Surface Micromachining” Sensors and Actuators-A 64, pp.17-26, 1998.

 Lingbo Zhu et.al., “Lotus Effect Surface for prevention of Microelectromechanical Systems (MEMS) Stiction”, 2005 IEEE Electronic Components and Technology Conference, pp1798-1801 Examples

 Microstructures fabricated with surface Micromachining

 Complex structures require dry etching techniques

 Note that all these can have large lateral dimensions, but relatively small “thickness” Recall Sputtering

 A physical phenomenon involving

 The creation of plasma by discharge of Vacuum neutral gas such as helium enclosure

 Acceleration of ions via a potential

gradient and the bombardment of a Cathode (Target) ‘target’ or cathode Ions  Through momentum transfer atoms Sputtered atoms near the surface of the target metal Wafer become volatile and are transported as Anode vapors to a substrate

Vacuum pump Dry Etching Techniques

 Material removal for IC’s , MEMS

 By physical

 By ion bombardment

 By chemical

 Chemical reaction through a reactive species at the surface

 Or Combination

 Plasma etch

Steps involved in RIE Etching

1. Reactive etching species are generated by electron/molecule collisions 2. Etchant species diffuse through stagnant region to the surface of the film to be etched 3. Etchant species adsorb onto surface 4. Reaction takes place 5. Etched product desorbs from the surface 6. Etch products diffuse back into bulk gas and removed by vacuum Reactive Ion Etching (RIE)

 Wet etching causes undercut

 Unidirectional etching is possible with RIE

 High fidelity pattern transfer

http://www.ee.byu.edu/cleanroom/rie_etching.phtml Integration with Electronics

MEMS  CMOS First Electronics

 MEMS First MEMS Electronics

 Notice that in both cases, electronics are integrated on chip

 It is also possible to have the electronics in a separate die and integrate these on a package (Multi-chip modules)

 Thicker structures and closed cavities can be formed by Wafer bonding techniques

Cathode - V Glass + Silicon Anode Bulk Micromachined Geomtries

Grooves/ Microchannels Pressure Sensor membrane

AFM Tip Cantilever High Aspect Ratio Microsystems

 Wafer Bonding techniques

 High Aspect Ratio Methods for Silicon

 LIGA and other molding techniques

 Polymeric microsystems (low cost fabrication)

 Low Temperature Co-fired Ceramics (LTCC)