The Surface/Bulk Micromachining (SBM) Process: a New Method for Fabricating Released MEMS in Single Crystal Silicon

JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 8, NO. 4, DECEMBER 1999 409 The Surface/Bulk Micromachining (SBM) Process: A New Method for Fabricating Released MEMS in Single Crystal Silicon

Sangwoo Lee, Sangjun Park, and Dong-il (Dan) Cho, Member, IEEE

Abstract—This paper presents the surface/bulk micromachin- limitations are imposed by the crystallographic constraints, and ing (SBM) process to allow fabricating released microelectro- complicated structures are difficult to fabricate. mechanical systems using bulk silicon. The process starts In surface micromachining, the structural shape is defined by with a (111)-oriented silicon wafer. The structural patterns are defined using the reactive ion etching technique used reactive ion etching (RIE), which allows fabricating arbitrary in surface micromachining. Then the patterns, as well as patterns. The most common structural material used in sur- sidewalls, are passivated with an oxide film, and bare silicon face micromachining is polysilicon deposited by low-pressure is exposed at desired areas. The exposed bare silicon is chemical vapor deposition [6], [7]. However, depositing a 2- further reactive ion etched, which defines sacrificial gap m-thick film takes several hours or more. Moreover, the dimensions. The final release is accomplished by undercutting the exposed bulk silicon sidewalls in aqueous alkaline etchants. material properties of amorphous silicon and polysilicon vary Because {111} planes are used as etch stops, very clean significantly with deposition conditions and postdeposition structural surfaces can be obtained. Using the SBM process, 5-, processes [8]. Thus, accurately controlling the residual stress, 10-, and 100-"m-thick arbitrarily-shaped single crystal silicon stress gradient, and Young’s modulus of polysilicon is difficult. structures, including comb-drive resonators, at 5-, 30-, and 100- In addition, it is very difficult to grow and control the "m sacrificial gaps, respectively, are fabricated. An electrostatic actuation method using p-n junction isolation is also developed properties of thick polysilicon films. in this paper, and it is applied to actuate comb-drive resonators. To solve these limitations, there have been many attempts The leakage current and junction capacitance of the reversed- to develop a surface-micromachining-like process using single biased p-n junction diodes are also found to be sufficiently crystal silicon. There are several well-known methods for small for sensor applications. The developed SBM process is a fabricating single crystal silicon microstructures. They include plausible alternative to the existing micromachining methods in fabricating microsensors and microactuators, with the advantage single crystal reactive etching and metallization (SCREAM) of using single crystal silicon. [430] [9], silicon micromachining by plasma etching (SIMPLE) [10], black silicon method [11], merged epitaxial lateral overgrowth Index Terms—Aqueous alkaline etching, deep silicon reactive ion etching, p-n junction isolation, surface/bulk micromachining (MELO) [12], silicon-on-insulator (SOI) wafer process [13], (SBM) process, (111)-oriented silicon. dissolved wafer process [14], and porous silicon method [15]. Compared to the conventional bulk micromachining method, these techniques allow the fabrication of released, arbitrary- I. INTRODUCTION shaped microstructures in single crystal silicon. However, each ULK and surface micromachining technologies have been process has its own limitations. In the SCREAM process, the Bwidely used to fabricate silicon microelectromechanical width of released structures cannot be large, and the structure systems (MEMS). Bulk micromachining utilizes the etch se- undersurfaces are unevenly etched during the isotropic release lectivity between {111} planes and {100} and/or {110} planes etch using a SF -based chemistry. In the SIMPLE process, in aqueous alkaline etchants to fabricate structures [1]. Silicon a high-concentration n-type buried layer is needed, and the wafers with (100) and (110) orientations have been used in limitation on the structural width is similar to that of the bulk micromachining. Using (100) silicon, simple structures SCREAM process. In the black silicon method, a buried oxide such as diaphragms, V-grooves, and nozzles, as well as more layer is required. In the MELO process, the structural layer is complicated structures such as corner cubes and rectangular laterally grown epitaxial silicon on top of an oxide or nitride masses, can be fabricated [1]–[3]. On a (110) silicon wafer, film. Therefore, fabricating a released structure with large area there are four {111} planes that intersect the wafer surface is difficult. In the porous silicon method, lightly doped n-type vertically. Thus, vertical microstructures can be fabricated [4], silicon is used as a structural material and p-type silicon as a [5]. However, in either (100) or (110) silicon, severe geometric sacrificial material. Although there are various approaches in preparing structural and sacrificial materials, it is difficult to Manuscript received March 11, 1999; revised June 12, 1999. This research was supported by the Ministry of Science and Technology and the Ministry prevent unwanted areas from becoming porous silicon. This of Industry and Energy under the Micromachine Technology Development results in underetching of anchoring areas during sacrificial Program. Subject Editor, N. de Rooij. etching. In the SOI wafer process, complicated structures can The authors are with the School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea. be fabricated, but the thickness of oxide sacrificial layers is Publisher Item Identifier S 1057-7157(99)08240-2. limited. In the dissolved wafer process, high-concentration

1057–7157/99$10.00  1999 IEEE 410 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 8, NO. 4, DECEMBER 1999

(a) (b)

(c) Fig. 1. Crystallography of (111)-oriented silicon. (a) hIIIi directions. (b) Six normal hIIHi directions. (c) Six oblique hIIHi directions. boron doping as well as topside bonding with another wafer is of p-n junction diodes, which determines the maximum voltage needed. The backside etch process can also take a long time. difference between electrodes, is sufficiently high for most This paper presents a new method for micromachining MEMS. An example of electrostatically actuating an SBM- released structures with single crystal silicon. The developed fabricated comb-drive resonator is shown. The depletion layer surface/bulk micromachining (SBM) process utilizes (111) at the p-n junction is also found to be sufficiently large. silicon wafers. First, a (111) silicon wafer is reactive ion etched This results in a very low paracitic capacitance, which is leaving the structural patterns to be released later, and the advantageous in sensor applications. bulk silicon under the patterns is etched in an aqueous alkaline Micromachining with (111) silicon has been attempted etchant to release the patterns. In the developed technology, the previously [16]. However, the structures must be crystallo- thickness of the structural layer as well as the thickness of the graphically aligned to three special directions, and complex sacrificial gap are defined by deep silicon RIE. The release of structures cannot be fabricated. In addition, the process in [16] structure is accomplished by aqueous alkaline etching, utilizing requires two photoresist exposure steps that limit the structural the slow etching {111} planes as the etch stop. This results in thickness. The electrostatic actuation method using junction very smooth and flat bottom surfaces. The required release etch isolation of single crystal silicon microstructure is reported time in a KOH solution, a commonly used alkaline etchant, first in this paper. is comparable to that of etching the sacrificial oxide in HF. The ensuing sections present the complete fabrication method II. PRINCIPLES OF SBM PROCESS AND as well as examples of SBM fabricated complex structures, (111) SILICON CRYSTALLOGRAPHY including mesa-island anchored structures and comb-drive To understand the salient features of the SBM process, resonators. consider the six {111} planes on a (111)-oriented silicon For electrostatic actuation of released microstructures, an wafer, as shown in Fig. 1(a). These {111} planes represent electrical isolation method with reverse-biased p-n junction six of eight {111} planes, the others being the top and bottom diodes is also developed in this paper. The breakdown voltage planes. These six {111} planes are tilted at 19.47 from LEE et al.: FABRICATING RELEASED MEMS IN SINGLE CRYSTAL SILICON 411

ides to perform the sacrificial etch. In this final step, the lower parts of the sidewalls without oxide passivation will be etched in the lateral direction. This wet etch will terminate when etch fronts meet {111} planes. This results in released patterns, as shown in Fig. 2(d). Note that nitrides films can be used together with the PECVD oxide films, if the required release (a) (b) etch time is long, or if KOH is used as the sacrificial etchant. Fig. 3 shows some examples of SBM-processed microstructures. Fig. 3(a) and (b) shows released letters “MEMS” and a released beam-supported round plate. Because the structures are patterned by RIE, the patterns are sharply defined, and arbitrary shapes with arbitrary sacrificial gaps can be fabricated. The examples show a 10- m structural thickness with a 30- m sacrificial gap. The structures are very smooth since (c) (d) they are made of single crystal silicon. The bottom surface is also smooth, which is the (111) plane. An example of the structural bottom surface, which is the plane, is shown in Fig. 3(c). The bottom surface is also smooth. The slight Fig. 2. Detailed process flow. (a) Silicon etch using RIE. (b) Passivation nitride and oxide deposition. (c) Oxide and nitride etch. (d) Silicon wet etch scaling phenomenon is due to a slight wafer misorientation and in aqueous alkaline etchant. the finite etch selectivity. Fig. 3(d) shows a released 100- m- thick round plate with a 100- m sacrificial gap. Fig. 3(b)–(d) the vertical as indicated. The eight {111} planes are the slow shows that large plates can be cleanly released without requir- etching planes in an alkaline etchant, and they are used as the ing additional etch holes. One of the advantages of the SBM etch stops in fabricating released structures. process is that sacrificial gaps can be made very large. This The fast etching planes of (111) silicon in alkaline etchants alleviates stiction problems and reduces air damping. are {110} planes. There are total of 12 {110} planes. Six are found by rotating the equilateral triangles in Fig. 1(a) by 30 III. MORE ON THE SBM PROCESS in either a clockwise or counterclockwise direction, as shown in Fig. 1(b). These {110} planes form 90 angles to the (111) plane. Six more {110} planes are aligned to the (111) plane, as A. Undercut Mechanism of (111) Silicon in shown in Fig. 1(c). These {110} planes are tilted by 54.7 Aqueous Alkaline Etchants from the vertical. The six {110} planes that intersect the (111) Since aqueous alkaline etching is used in the final release plane vertically, i.e., those identified in Fig. 1(b), are the fastest step, understanding the directions of etch front propagation in etching planes. The other six {110} planes as well as all the alkaline etchants at convex and concave corners is important. {100} planes etch slower due to the various intersecting {111} The prediction of the etch front is based on the two conditions planes that must etch with them. In KOH, the etch selectivity stated in Batterman [18]. On a concave surface, etch fronts between the fast etching vertical {110} planes and the slow will develop at the plane with a relatively minimum etch rate etching {111} planes is on the order of 100 [17]. versus orientation, while on a convex surface the converse will The fabrication steps of the SBM process are shown hold. Aqueous alkaline etching of (111) silicon has not been in Fig. 2. A plasma-enhanced chemical vapor deposition studied in detail previously, we start with the fact that in most (PECVD) oxide layer is deposited and patterned as shown in alkaline etchants, etch rate is slowest in the 111 directions. Fig. 2(a). Next, a vertical silicon RIE process is used to define Therefore, on a concave surface, the six tilted {111} planes the structural patterns. The first oxide layer should be thick should develop during wet etch in the SBM process. The enough to withstand the vertical silicon RIE steps for structure etching process will terminate where {111} planes intersect. patterning and sacrificial-gap definition, as well as the final In fact, this is evident in Fig. 3(b). aqueous alkaline etching. Then, a second PECVD oxide film is On a convex surface, the etching process will continue in deposited, as shown in Fig. 2(b). The film is used to protect the the direction of etch front propagation until the pattern is structure sidewalls in alkaline etching. The second oxide film completely released. However, the fastest etch direction is is then anisotropically etched using RIE to expose bare silicon generally dependent on the concentration, temperature, and at the bottom of the etched trenches, as shown in Fig. 2(c). additives of etchants, and it is not practical to determine This step does not require a photoresist/lithography step and the exact direction of etch front propagation for all etch must not etch the pattern sidewalls. Then, the silicon wafer is conditions. However, in the SBM process, the direction of vertically etched again using deep silicon RIE. The etch depth etch propagation must lie on the (111) plane. There are many is the same as the desired spacing between the structural layer possible directions, but generally, the six 110 directions that and the bottom surface. This is the same concept as the oxide lie on the (111) plane, shown in Fig. 1(b), have to be the fastest sacrificial layer in surface micromachining. Finally, the wafer etching directions based on the crystallography. The directions is dipped into an aqueous alkaline solution such as KOH, ethy- of etch propagation should be then those six 110 directions lene diamine pyrocatechol, or tetramethyl ammonium hydrox- on a convex corner. 412 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 8, NO. 4, DECEMBER 1999

(a) (b)

(c) (d) Fig. 3. Examples of fabricated structures. (a) Released letters “MEMS” (structural thickness a 10 "m, sacrificial gap a 30 "m). (b) Released beam-supported round plate (structural thickness a 10 "m, sacrificial gap a 30 "m). (c) Backside of the round plate. (d) Released beam-supported thick round plate (structural thickness a 100 "m, sacrificial gap a 100 "m).

solution. Fig. 4 shows the optical micrographs of fabricated test structures. To inspect the etch propagation, a 1.5- m- thick PECVD oxide mask is used. Fig. 4 shows three identical convex test structures with different crystallographic orientations etched for 17 min in a 30wt%, 90 C KOH solution. In Fig. 4(a), the sides of the hexagonal pattern are aligned to lie on the intersection of six tilted {111} planes and the (a) (b) (111) plane. In Fig. 4(b) and (c), the hexagonal patterns are rotated by 30 and 45 from the 111 directions, respectively. Clearly, the results show that the etch front planes are the six {110} planes that are vertical to the wafer as identified in Fig. 1(b). The calculated etch rate in 110 directions is about 170 m/h. This etch rate is slightly larger than that of underetching an oxide sacrificial layer in concentrated HF. The scaling phenomenon shown in the figures is due to a slight wafer misorientation. However, the roughness of the scales is (c) (d) very small, as shown earlier in Fig. 3(d). In the SBM process, the shape of released structure is Fig. 4. Convex corner underetch mechanism of (111) silicon. (a) This figure shows the convex corner underetch mechanism. The outer hexagon is the defined by RIE. Therefore, arbitrary shape can be defined. patterned oxide mask and aligned to the hIIIi directions. The inner hexagon is However, if etch fronts do not intersect under the structure to a silicon mesa developed by the underetch mechanism; the sides are aligned to be released, the release process cannot be completed. When the hIIHi directions. (b) The outer hexagon is aligned to the hIIHi directions. The inner hexagon is developed by the underetch mechanism; the sides are the structures to be released have only concave corners, care aligned to the hIIHi directions. (c) The sides of outer hexagon are rotated must be taken so that the etch front planes intersect under the from the hIIHi directions by 15 . The inner hexagon is developed by the structures to be released. underetch mechanism; the sides are aligned to the hIIHi directions. (d) Cross section of (a)–(c) before aqueous alkaline etch. B. Fabrication of Mesa-Island Anchors To verify the assumptions, test structures with convex To fabricate folded-type comb-drive resonators, mesa is- corners are fabricated and wet etched in a 30wt%, 90 C KOH lands are needed for the anchor points. Since mesa islands LEE et al.: FABRICATING RELEASED MEMS IN SINGLE CRYSTAL SILICON 413

(a) (b)

Fig. 6. SEM micrography of a compensation pattern.

(c) (d) or nitride films are used to electrically isolate electrodes. Fig. 5. Examples of compensation patterns etched in a 90 C, 30 wt% KOH However, in the SBM process, microstructures are made from solutions. (a) Before etch. (b) After 37 min. bulk silicon, and the use of dielectric films is difficult. In the SCREAM process, electrical isolation is accom- have convex corners, it will be etched during the alkaline plished after the release step, using a PECVD oxide inter- sacrificial etch. This will result in unwanted changes in the mediate layer and a sputtered metal layer [9]. The method support boundary conditions. Therefore, to fabricate mesa- can be exactly duplicated for the SBM process. However, island supported released beams, a suitable compensation this approach can have limitations, since the isolation and pattern is required. Generally, a small anchor size and small metallization steps are performed after releasing the structures. compensation patterns are desirable. These will be functions of In addition, sidewalls cannot be metallized easily. the etch time as well as crystallographic orientation of patterns. In this paper, a p-n junction isolation method using reverse- Consider equilateral triangle mesa patterns for a simple biased diodes is developed. In the developed method, isolation calculation to determine compensation patterns. When the is accomplished in two steps. The first step is done at the very three sides of a triangle are aligned to 110 directions, side beginning of the process by forming a p-n junction. The p-n etching will take place at an equal rate on all three sides. When junction is formed by diffusion doping of an n-type impurity the sides are aligned to 111 directions, side etching occurs into a p-type wafer, and vice versa. The diffusion-doped area only at the three vertices. This implies that for the fabrication can be isolated from the substrate using a reverse-biased junc- of mesa islands, the combined pattern of triangles aligned to tion. The second isolation step is done during the main SBM 111 directions will result in the smallest patterns. process by etching away the parts of doped areas. By etching Fig. 5 shows examples of compensation pattern to fabricate deeper than the junction depth, the isolation between electrodes mesa islands. In these examples, the areas to be anchored to is accomplished. One drawback of the developed isolation the substrate are designed with a solid hexagon or triangle. The method is that it is difficult to dope bulk silicon to a depth patterns that protect the anchoring area from being underetched larger than several micrometers. The use of epitaxially grown are designed with diapered triangles with void inner areas. low-resistivity (111) silicon is an alternative if a junction depth All sides of compensation patterns are aligned to the 111 of more than several micrometers is required. directions. Since the (111) silicon is of threefold symmetry, the This junction isolation method is applied to fabricate a sides of triangular compensation patterns etch with the same comb-drive resonator. The process steps for achieving elec- speed from all convex corners. Fig. 5(b) is the results after 37 trical isolation are as follows. With the starting material of min in a 30wt%, 90 C KOH solution. If the time to release (111) silicon wafers, a 1.6- m-thick oxide film is thermally one triangular compensation pattern is known in a specific grown. Then, the oxide film is patterned to expose bare etching condition, the number of triangular compensation silicon for doping. After patterning of the masking oxide, patterns needed for protecting an anchor area can be easily the wafer is diffusion-doped. The doped area covers the calculated. Fig. 6 shows a mesa island fabricated with a region used as electrodes and the region used as a main triangular compensation pattern. It clearly shows that a mesa- body of resonator. Both n- and n-type wafers are used for island support with true boundary conditions can be fabricated. fabrication. For the n-type wafer, a solid boron source is used for doping. The predeposition process is performed IV. JUNCTION ISOLATION FOR ELECTROSTATIC ACTUATION at atmospheric pressure with 1.5 sL/min (standard liter per Electrostatic actuation is the most widely used method for minute) of N for 12 h. Before the predeposition step, the solid actuating microstructures. The actuation voltages can be in boron source is activated for 30 min in the O environment. excess of several tens of volts, and a proper electric isolation The drive-in process is performed with 1.5 slpm of O at of electrodes is required. In surface micromachining, oxide atmospheric pressure for 1 h, with the boron source removed. 414 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 8, NO. 4, DECEMBER 1999

(a) (a)

(b) (b) Fig. 8. Doping profiles and resistivity of doped region. (a) Boron doping. Fig. 7. Fabricated comb-drive resonator for electrostatic actuation. (a) Dou- (b) Phosphorus doping. bly-clamped comb-drive resonator. (b) Close-up view of (a). In capacitive sensing applications, the leakage current For the p-type wafer, a liquid POCl source is used for through the junction diodes can become a problem. The doping. The predeposition of phosphorus-containing oxide is insets of Fig. 9 shows the reverse-bias leakage current as a performed at atmospheric pressure with 2 slpm of N , 0.4 slpm function of reverse-bias voltage in the range of 0–30 V. The of POCl -containing N , and 0.2 slpm of O for 1 h. The drive- leakage current is about 4.3 A at 30 V and about 560 nA at in process is performed with 2 slpm of N at the atmospheric 10 V, for the case of n-type wafer. In this case, capacitance pressure for 16 h. The diffusion temperature is 1000 C in all sensing circuits with a low-impedance input node, such as cases. After the removal of the masking oxide, the main SBM a transresistance amplifier and charge amplifier, cannot be process steps are used to complete fabrication. The isolation of implemented because of the large leakage current. However, electrodes is accomplished by the silicon RIE steps in defining even in such a case, a buffer circuit that has a high-impedance the structure patterns and sacrificial gaps. Fig. 7(a) shows the input node can be implemented. For the case of p-type wafer, four electrodes which are located at each of the four sides. the leakage current is only about 44 nA at 30 V and 20 nA Fig. 8 shows the doping profiles of n- and p-type wafers. at 10 V. The leakage current of tens of nanometers would not The doping concentration and resistivity is plotted as a func- cause a problem in circuits. Thus, p-type wafer process would tion of the diffusion depth. The junction depths of n- and be preferred in sensor applications. p-type wafers are 6 and 5 m, respectively. For a proper electrical isolation, the junction depth should be less than the sum of structural height and sacrificial gap. Fig. 9 shows the I–V traces of the reverse-biased junction V. ELECTROSTATIC ACTUATION OF diodes. For the case of n-type wafer, measurements are done SBM-FABRICATED RESONATORS at five different locations. The breakdown voltage ranges from Comb-drive resonators [19] represent the most widely used 150 to 180 V. For the case of p-type wafer, measurements are configuration for microsensors and microactuators. After dop- done at four different locations, and the breakdown voltage ing (111) wafers for junction isolation, the SBM process is is about 150 V for all cases. These breakdown voltages applied to fabricate comb-drive resonators in both n- and p- are sufficiently large for electrostatically actuating almost all type silicon. Fig. 7 shows comb-drive resonators fabricated MEMS devices. using a phosphorus-doped p-type wafer. In Fig. 7, the small LEE et al.: FABRICATING RELEASED MEMS IN SINGLE CRYSTAL SILICON 415

Fig. 10. Experimental setup for electrostatic actuation. (The ﬁgure corre- sponds to the n-type, boron-doped wafer. In the case of a p-type, phospho- (a) rus-doped wafer, the polarity of P must be reversed.)

(b) Fig. 9. I-V curves of fabricated junction diodes. (a) Boron-doped junction diode. (b) Phosphorus-doped junction diode. Fig. 11. Calculated junction capacitance and depletion width. steps around the electrodes are due to the thermal oxide grown number of combs. Note that by varying , this configuration at the doping step. can be used for a simultaneous vertical actuation. Fig. 10 shows experimental setup for electrostatic actuation. For high performance sensor applications, one could be For the n-type wafer, the tested comb-drive resonator has a concerned with the junction capacitance and leakage current spring length of 380 m and a structural thickness of 5 m. of the junction isolation method. The junction capacitance For the p-type wafer, the tested comb-drive resonator has a between the electrodes and the substrate can be interpreted spring length of 228 m and a structural thickness of 10 m. as a parasitic capacitance between the anchoring area and For the n-type wafer, a 20-V peak-to-peak sinusoidal voltage the substrate. For the calculation of junction capacitance as with a 10-V offset was applied to , with the positive output a function of reverse-bias voltage, the depletion width should terminal connected to the fixed electrode. A 30-V dc voltage be known. The depletion width is calculated assuming a was applied to with the positive output terminal connected breakdown voltage of 165 V. The results can be applied to to the substrate. The actuator resonated at 36 kHz with a comb both n- and p-type wafers. In the calculation, since diffusion amplitude of approximately 5 m in atmospheric pressure. doping is used, the doping concentration can be approximated For the p-type wafer, a 140-V peak-to-peak sinusoidal voltage as a linear function of distance [20]. The results are plotted with a 70-V offset was applied to , with the positive output in Fig. 11. As the reverse-bias voltage increases, the depletion terminal connected to the fixed electrode. A 30-V dc voltage width increases, and the junction capacitance decreases. The was applied to with the negative output terminal connected calculated junction capacitance is smaller than that of the to the substrate. The actuator resonated at 50 kHz with a comb conventional dielectric isolation. For a comparison, let us amplitude of approximately 10 m in atmospheric pressure. assume that a nitride film with the thickness of 6000 Ais˚ The different voltage requirements are due to the fact that used between a highly phosphorus-doped silicon wafer and the resonator sizes are different and the fact that the doped a highly phosphorus-doped polysilicon electrode. Assuming a depth is less than the structural height in the p-type. Note that pad size of 100 m by 100 m, the calculated capacitance of if the experiments are performed in a reduced pressure, the the nitride isolation is 1.107 pF. When a 30 V of reverse-bias displacement would be much larger. The comb displacement voltage is applied to the junction isolation case, the junction is proportional to the factor. Also, the actuation voltage capacitance is only 0.116 pF. With no reverse-bias, which has seems large, but this can be reduced by simply increasing the the maximum value, the junction capacitance is 0.4495 pF. 416 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 8, NO. 4, DECEMBER 1999

VI. SUMMARY AND CONCLUSIONS [10] Y. X. Li, P. J. French, P. M. Sarro, and R. F. Wolffenbuttel, “Fabrication of a single crystalline silicon capacitive lateral accelerometer using In this paper, the SBM process is developed, which allows micromachining based on single step plasma etching,” in Proc. IEEE surface micromachining with bulk silicon. The SBM process Workshop Microelectromech. Syst., Amsterdam, The Netherlands, 1995, pp. 398–403. defines structural patterns using RIE on a (111) silicon wafer [11] M. de Boer, H. Jansen, and M. Elwenspoek, “The black silicon method and releases the patterned structures using aqueous alkaline V: A study of the fabrication of movable structures for micro electro- etch. The SBM process can fabricate sharply defined, arbi- mechanical systems,” in Tech. Dig. 8th Int. Conf. Solid-State Sensors and Actuators (Transducers ’95), Stockholm, Sweden, 1995, pp. 565–568. trarily thick, and arbitrarily shaped released microstructures in [12] P. J. Schubert, and G. W. Neudek, “Confined lateral selective epitaxial single crystal silicon with arbitrarily large sacrificial gaps. growth of silicon for device fabrication,” IEEE Electron Device Lett., Examples presented include sharply defined 5-, 10-, and vol. 11, pp. 181–183, 1990. [13] B. Diem, M. T. Delaye, F. Michel, S. Renard, and G. Delapoerre, 100- m-thick structures with 5-, 30-, and 100- m sacrificial “SOI(SIMOX) as a substrate for surface micromachining of single gaps, respectively. Diapered triangle compensation patterns crystalline silicon sensors and actuators,” in Tech. Dig. 7th Int. Conf. were also developed and applied to fabricate mesa-island Solid-State Sensors and Actuators (Transducers ’93), Yokohama, Japan, 1993, pp. 233–236. supported structures. Using phosphorus and boron diffusion [14] S. T. Cho, “A batch dissolved wafer process for low cost sensor appli- doping on p- and n-type wafers, respectively, a p-n junction cations,” in SPIE Proc. Micromachining and Microfabrication Process Technology, Austin, TX, 1995, pp. 10–17. isolation method was developed to actuate SBM-processed res- [15] T. E. Bell, P. T. J. Gennissen, D. DeMunter, and M Kuhl, “Porous onators. The breakdown voltage of reverse-biased p-n junction silicon as a sacrificial material,” J. Micromech. Microeng., vol. 6, pp. diodes are sufficiently large in both p- and n-type wafers for 361–369, 1996. [16] G. Ensell, “Free standing single-crystal silicon microstructures,” J. electrostatic actuation. The leakage current and capacitance of Micomech. Microeng., vol. 5, pp. 1–4, 1995. reverse-biased junctions were also studied. The leakage current [17] S. Lee, S. Park, and D. Cho, “A new micromachining technique with (111) silicon,” Jpn. J. Appl. Phys., vol. 38, pp. 2699–2703, 1999. was measured to be on the order of A for the n-type wafer and [18] R. J. Jaccodine, “Use of modified free energy theorems to predict lower than 40 nA for the p-type wafer for voltage up to 30 V. equilibrium growing and etching shapes,” J. Appl. Phys., vol. 33, no. 8, Thus, p-type wafers can be used in capacitive sensing devices. pp. 2643–2646, 1962. [19] W. C. Tang, T.-C. H. Nguyen, M. W. Judy, and R. T. Howe, “Electro- The SBM process can duplicate almost all surface micro- static combdrive of lateral polysilicon resonators,” Sens. Actuators, vol. machined microsensors and microactuators that use a single A21-23, pp. 328–331, 1990. layer of structural polysilicon. For most applications, however, [20] D. A. Neamen, Semiconductor Physics and Devices. Boston, MA: IRWIN, 1992, pp. 257–259. the developed SBM process can offer an advantage of more predictable and stable material properties of single crystal sil- Sangwoo Lee received the B.S. degree in con- icon. Furthermore, the SBM process can fabricate high-aspect trol and instrumentation engineering and the M.S. ratio microstructures, which is difficult with the polysilicon degree in biomedical engineering from Seoul Na- tional University, Seoul, Korea, in 1993 and 1995, technology. The SBM process also allows large sacrificial respectively. He is currently working toward the gaps, which is beneficial for preventing stiction and reducing Ph.D degree at the School of Electrical Engineering, air damping. We believe that the advantages of bulk properties, Seoul National University. His current research interests are material charac- high-aspect ratio structures, and large sacrificial gaps of the terization, micromachining technology, and fabrica- SBM process are suitable for high performance sensors and tion of micromachined gyroscope. large force actuators.

Sangjun Park received the B.S. and M.S. degrees in REFERENCES electrical engineering from Seoul National Univer- sity, Seoul, Korea, in 1997 and 1999, respectively. [1] K. E. Pertersen, “Silicon as a mechanical material,” Proc. IEEE, vol. He is currently working toward the Ph.D. degree at 70, pp. 420–457, 1982. the School of Electrical Engineering, Seoul National [2] C. Strainerman, L. Rosengren, H. G. A. Elderstig, and Y. Backlund, University. “Fabrication of 45 mirrors together with well-deﬁned V-grooves using His research interests include design, optimiza- wet anisotropic etching of silicon,” IEEE J. Microelectromech. Syst., tion, and fabrication of microactuators and microin- vol. 4, pp. 213–219, Dec. 1995. ertial sensors. [3] G. Schropfer, S. Ballandras, M. D. Labachelerie, P. Blind, and Y. Ansel, “Fabrication of a new highly-symmetrical, in-plane accelerometer structure by anisotropic etching of (100) silicon,” J. Micromech. Microeng., vol. 7, pp. 71–78, 1997. [4] D. R. Ciarlo, “A latching accelerometer fabricated by the anisotropic Dong-il (Dan) Cho (M’88) received the B.S.M.E. degree from Carnegie- etching of (110) oriented silicon wafers,” J. Micromech. Microeng., vol. Mellon University, Pittsburgh, PA, in 1980, and the S.M. and Ph.D. degrees 2, pp. 10–13, 1992. [5] B. Kim, and D. Cho, “Aqueous KOH etching of (110) silicon—Etch from Massachusetts Institute of Technology, Cambridge, in 1984 and 1987, characteristics and compensation methods for convex corners,” J. Elec- respectively. trochem. Soc., vol. 145, pp. 2499–2508, 1998. From 1987 to 1993, he was Assistant Professor in the Mechanical and [6] R. T. Howe and R. S. Muller, “Polycrystalline silicon micromechanical Aerospace Engineering Department, Princeton University, Princeton, NJ. In beams,” J. Electrochem. Soc., vol. 130, pp. 1420–1423, 1983. 1993, he joined the Department of Control and Instrumentation Engineering, [7] , “Resonant microbridge vapor sensor,” IEEE Trans. Electron Seoul National University, Seoul, Korea, where is currently Associate Devices, vol. ED-33, pp. 499–507, 1986. Professor in the School of Electrical Engineering. His research interests [8] S. Lee, C. Cho, J. Kim, S. Park, S. Yi, J. Kim, and D. Cho, “The include variable structure control, mechatronics, ITS, and MEMS. From 1992 effects of post-deposition processes on polysilicon Young’s modulus,” to 1997, he was an Associate Editor for the IOP Journal of Micromechanics J. Micromech. Microeng., vol. 8, pp. 330–337, 1998. and Microengineering. He also served as an Acting Associate Editor for the [9] K. A. Shaw, Z. L. Zhang, and N. C. MacDonald, “SCREAM I: A ASME Transactions Journal of Dynamic Systems, Measurement and Control single mask, single-crystal silicon, reactive ion etching process for in 1993. microelectromechanical structures,” Sens. Actuators A, vol. 40, p. 63, Dr. Cho was an Associate Editor for the IEEE/ASME JOURNAL OF 1994. MICROELECTROMECHANICAL SYSTEMS from 1992 to 1997.