LMH0031 SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data Fifos Check for Samples: LMH0031
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LMH0031 www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 LMH0031 SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs Check for Samples: LMH0031 1FEATURES APPLICATIONS 2• SDTV/HDTV Serial Digital Video Standard • SDTV/HDTV Serial-to-Parallel Digital Video Compliant Interfaces for: • Supports 270 Mbps, 360 Mbps, 540 Mbps, – Video Editing Equipment 1.483 Gbps and 1.485 Gbps Serial Video Data – VTRs Rates with Auto-Detection – Standards Converters • LSB De-Dithering Option – Digital Video Routers and Switchers • Uses Low-Cost 27MHz Crystal or Clock – Digital Video Processing and Editing Oscillator Reference Equipment • Fast VCO Lock Time: < 500 µs at 1.485 Gbps – Video Test Pattern Generators and Digital • Built-in Self-Test (BIST) and Video Test Pattern Video Test Equipment Generator (TPG) – Video Signal Generators (1) Patent Applications Made or Pending • Automatic EDH/CRC Word and Flag DESCRIPTION Processing The LMH0031 SMPTE 292M / 259M Digital Video • Ancillary Data FIFO with Extensive Packet Deserializer/Descrambler with Video and Ancillary Handling Options Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps • Adjustable, 4-Deep Parallel Output Video Data (or 1.483Gbps) serial component video data, to 20-bit FIFO parallel data with a synchronized parallel word-rate • Flexible Control and Configuration I/O Port clock. It also deserializes and decodes SMPTE 259M, • LVCMOS Compatible Control Inputs and Clock 270Mbps, 360Mbps and SMPTE 344M (proposed) and Data Outputs 540Mbps serial component video data, to 10-bit parallel data. Functions performed by the LMH0031 • LVDS and ECL-Compatible, Differential, Serial include: clock/data recovery from the serial data, Inputs serial-to-parallel data conversion, SMPTE standard • 3.3V I/O Power Supply and 2.5V Logic Power data decoding, NRZI-to-NRZ conversion, parallel data Supply Operation clock generation, word framing, CRC and EDH data checking and handling, Ancillary Data extraction and • Low Power: Typically 850mW automatic video format determination. The parallel • 64-Pin TQFP Package video output features a variable-depth FIFO which • Commercial Temperature Range 0°C to +70°C can be adjusted to delay the output data up to 4 parallel data clock periods. Ancillary Data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse LSB dithering is also implemented. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2006–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. LMH0031 SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com DESCRIPTION (CONTINUED) The unique multi-functional I/O port of the LMH0031 provides external access to functions and data stored in the configuration and control registers. This feature allows the designer greater flexibility in tailoring the LMH0031 to the desired application. The LMH0031 is auto-configured to a default operating condition at power-on or after a reset command. Separate power pins for the PLL, deserializer and other functional circuits improve power supply rejection and noise performance. The LMH0031 has a unique Built-In Self-Test (BIST) and video Test Pattern Generator (TPG). The BIST enables comprehensive testing of the device by the user. The BIST uses the TPG as input data and includes SD and HD component video test patterns, reference black, PLL and EQ pathologicals and a 75% saturation, 8 vertical colour bar pattern, for all implemented rasters. The colour bar pattern has optional transition coding at changes in the chroma and luma bar data. The TPG data is output via the parallel data port. The LMH0030, SMPTE 292M / 259M Digital Video Serializer with Ancillary Data FIFO and Integrated Cable Driver, is the ideal complement to the LMH0031. The LMH0031's internal circuitry is powered from +2.5 Volts and the I/O circuitry from a +3.3 Volt supply. Power dissipation is typically 850mW. The device is packaged in a 64-pin TQFP. TYPICAL APPLICATION VDD 75: SMPTE 292M SMPTE Video 1% or 259M Data Input Serial Data LMH0030 SD/HD Encoder/ Serializer/ Cable Driver Parallel Ancilliary 1 mF Data Input 75: Coaxial Cable 1 mF LMH0034 Adaptive Cable Equalizer 75: 1% SMPTE Video Data Output LMH0031 SD/HD Decoder/ Deserializer Parallel Ancilliary Data Output 2 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 LMH0031 www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 Block Diagram XTALi/Ext Clk XTALo REFERENCE CLOCK/OSCILLATOR PLL/CLOCK SYSTEM PCLK SDI INPUT DATA SAMPLERS CLOCK/DATA RECOVERY SDI BIST & TPG RBB SDI R REF BIAS TRS & SMPTE NRZI-NRZ CONVERTER PCLK FORMAT DESCRAMBLER/ DETECTOR DESERIALIZER EDH / CRC DE-DITHERING GENERATORS/CHECKERS ANCILLIARY MASTER BUS FRAMING AD[9:0] DATA FIFO CONTROL VIDEO DATA BUS ACLK RD / WR CONFIGURATION & CONTROL DV[19:10] REGISTERS ANC / CTRL VIDEO DATA FIFO & OUTPUT DV[9:0] VCLK I/O[7:0] MULTI-FUNCTION I/O PORT PCLK SYSTEM RESET RESET MASTER CONTROL INT. RESET CONTROLLER Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LMH0031 LMH0031 SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com Connection Diagram 1 0 2 3 9 8 7 4 6 5 7 CLK SSD DDD V A V AD AD AD AD AD AD AD AD AD AD IO IO5 IO6 16 15 14 13 12 11109 87 6 5 4 3 2 1 IO4 17 64 RD/WR IO3 18 63 ANC/CTRL IO2 19 62 VDDD XTALo VSSIO 20 61 DV19 21 60 XTALi/Ext Clk DV18 22 59 VSSIO DV17 23 58 VDDSI DV16 24 57 SDI LMH0031 DV15 25 56 SDI VDDIO 26 55 VSSSI DV14 27 54 R BB DV13 28 53 RREF DV12 29 52 VSSPLL DV11 30 51 VDDPLL DV10 31 50 VCLK RESET VSSD 32 49 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 1 5 2 7 3 4 1 0 0 IO IO SSD DDD DV DV DV DV DV6 DV DV DV9 DV8 DV SSIO DDIO V V V V Figure 1. 64-Pin TQFP See Package Number PAG0064A 4 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: LMH0031 LMH0031 www.ti.com SNLS218A –JANUARY 2006–REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings(1)(2) CMOS I/O Supply Voltage (VDDIO–VSSIO): 4.0V SDI Supply Voltage (VDDSI–VSSSI): 4.0V Digital Logic Supply Voltage (VDDD–VSSD): 3.0V PLL Supply Voltage (VDDPLL–VSSPLL): 3.0V CMOS Input Voltage (Vi): VSSIO −0.15V to VDDIO +0.15V CMOS Output Voltage (Vo): VSSIO −0.15V to VDDIO +0.15V CMOS Input Current (single input): Vi = VSSIO −0.15V: −5 mA Vi = VDDIO +0.15V: +5 mA CMOS Output Source/Sink Current: ±6 mA IBB Output Current: +300 μA IREF Output Current: +300 μA SDI Input Voltage (Vi): VSSSI −0.15V to VDDSI +0.15V Package Thermal Resistance θJA @ 0 LFM Airflow 40.1°C/W θJA @ 500 LFM Airflow 24.5°C/W θJC 5.23°C/W Storage Temp. Range: −65°C to +150°C Junction Temperature: +150°C Lead Temperature (Soldering 4 Sec): +260°C ESD Rating (HBM): 6.0 kV ESD Rating (MM): 400 V (1) Absolute Maximum Ratings are those parameter values beyond which the life and operation of the device cannot be ensured. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics” specifies acceptable device operating conditions. (2) It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and specifications. Recommended Operating Conditions Symbol Parameter Conditions Reference Min Typ Max Units VDDIO CMOS I/O Supply Voltage VDDIO−VSSIO 3.150 3.300 3.450 V VDDSD SDI Supply Voltage VDDSI−VSSSI VDDD Digital Logic Supply Voltage VDDD–VSSD 2.375 2.500 2.625 V VDDPLL PLL Supply Voltage VDDPLL–VSSPLL Operating Free Air T 0 +70 °C A Temperature Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMH0031 LMH0031 SNLS218A –JANUARY 2006–REVISED APRIL 2013 www.ti.com Required Input Conditions(1)(2) Symbol Parameter Conditions Reference Min Typ Max Units VIN Input Voltage Range All LVCMOS VSSIO VDDIO V Inputs tr, tf Rise Time, Fall Time 10%–90% 1.0 1.5 3.0 ns SMPTE 259M, Level C 270 SMPTE 259M, Level D 360 BRSDI Serial Input Data Rate SMPTE 344M SDI, SDI 540 MBPS SMPTE 292M 1,483 SMPTE 292M 1,485 V V V Common Mode Voltage V = 125 mV SSSI DDSI V CM(SDI) IN P-P +1.0V −0.05V V SDI Serial Input Voltage, IN(SDI) 125 800 880 mV Single-ended P-P V SDI Serial Input Voltage, IN(SDI) SDI, SDI 125 800 880 mV Differential P-P 20%–80%, SMPTE 259M 0.4 1.0 1.5 ns Data Rates tr, tf Rise Time, Fall Time 20%–80%, SMPTE 292M 270 ps Data Rates Ancillary / Control Data Clock f V MHz ACLK Frequency CLK DCACLK Duty Cycle, Ancillary Clock ACLK 45 50 55 % Ancillary / Control Clock and t , t 10%–90% 1.0 1.5 3.0 ns r f Data Rise Time, Fall Time Setup Time, AD to A or t N CLK 3.0 1.5 ns S IO to A Rising Edge N CLK Control Data Input or ION, ADN, ACLK I/O Bus Input Timing Diagram Hold Time, Rising Edge ACLK tH 3.0 1.5 ns to ADN or ACLK to ION Bias Supply Reference R Tolerance 1% 4.75k Ω REF Resistor fEXT CLK External Clock Frequency Ext Clk −100 +100 27.0 MHz ppm ppm fXTAL Crystal Frequency See Figure 7 XTALo, XTALi (1) Required Input Conditions are the electrical signal conditions or component values which shall be supplied by the circuit in which this device is used in order for it to produce the specified DC and AC electrical output characteristics.