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LMH0030 SMPTE 292M/259M Digital Video Serializer with Video And

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LMH0030 SMPTE 292M/259M Digital Video Serializer with Video And Integrated Cable Driver LMH0030 SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and August 2006 LMH0030 SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver General Description The LMH0030’s internal circuitry is powered from +2.5V and the I/O circuitry from a +3.3V supply. Power dissipation is The LMH0030 SMPTE 292M/259M Digital Video Serializer typically 430mW at 1.485 Gbps including two 75Ω AC- with Ancillary Data FIFO and Integrated Cable Driver is a coupled and back-matched output loads. The device is pack- monolithic integrated circuit that encodes, serializes and aged in a 64-pin TQFP. transmits bit-parallel digital video data conforming to SMPTE 125M and 267M standard definition, 10-bit wide component video and SMPTE 260M, 274M, 295M and 296M high- Features definition, 20-bit wide component video standards. The n SDTV/HDTV serial digital video standard compliant LMH0030 operates at SMPTE 259M serial data rates of n Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps 270 Mbps, 360 Mbps, the SMPTE 344M serial data rate of and 1.485 Gbps SDV data rates with auto-detection 540 Mbps, and the SMPTE 292M serial data rates of 1483.5 n Low output jitter: 125ps max, 85ps typical and 1.485 Gbps. The serial data clock frequency is internally n Low power: typically 430mW generated and requires no external frequency setting, trim- n No external serial data rate setting or VCO filtering ming or filtering components. components required* The LMH0030 performs functions which include: parallel-to- n Fast PLL lock time: < 150µs typical at 1.485 Gbps serial data conversion, SMPTE standard data encoding, n Adjustable depth video FIFO for timing alignment NRZ to NRZI data format conversion, serial data clock gen- n Built-in self-test (BIST) and video test pattern generator eration and encoding with the serial data, automatic video (TPG)* rate and format detection, ancillary data packet manage- n Automatic EDH/CRC word and flag generation and ment and insertion, and serial data output driving. The insertion LMH0030 has circuitry for automatic EDH/CRC character and flag generation and insertion per SMPTE RP-165 (stan- n On-chip ancillary data FIFO and insertion control dard definition) or SMPTE 292M (high definition). Optional circuitry LSB dithering is implemented which prevents pathological n Flexible control and configuration I/O port pattern generation. Unique to the LMH0030 are its video and n LVCMOS compatible data and control inputs and ancillary data FIFOs. The video FIFO allows the video data outputs to be delayed from 0 to 4 parallel data clock periods for video n 75Ω ECL-compatible, differential, serial cable-driver timing purposes. The ancillary data port and on-chip FIFO outputs and control circuitry store and insert ancillary flags, data n 3.3V I/O power supply and 2.5V logic power supply packets and checksums into the ancillary data space. The operation LMH0030 also has an exclusive built-in self-test (BIST) and n 64-pin TQFP package video test pattern generator (TPG) with SD and HD compo- * Patent applications made or pending. nent video test patterns: reference black, PLL and EQ patho- logicals and color bars in 4:3 and 16:9 raster formats for NTSC and PAL standards*. The color bar patterns feature Applications optional bandwidth limiting coding in the chroma and luma n SDTV/HDTV parallel-to-serial digital video interfaces for: transitions. — Video cameras The LMH0030 has a unique multi-function I/O port for imme- — VTRs diate access to control and configuration settings. This port — Telecines may be programmed to provide external access to control — Digital video routers and switchers functions and indicators as inputs and outputs. The designer — Digital video processing and editing equipment can thus customize the LMH0030 to fit the desired applica- — Video test pattern generators and digital video test tion. At power-up or after a reset command, the LMH0030 is equipment auto-configured to a default operating condition. Separate — Video signal generators power pins for the output driver, PLL and the serializer improve power supply rejection, output jitter and noise per- formance. Order Number LMH0030VS 64-Pin TQFP NS Package Number VEC-64A © 2006 National Semiconductor Corporation DS201803 www.national.com Typical Application LMH0030 20180301 www.national.com 2 LMH0030 Block Diagram 20180302 3 www.national.com Connection Diagram LMH0030 20180303 64-Pin TQFP Order Number LMH0030VS See NS Package Number VEC-64A www.national.com 4 LMH0030 Absolute Maximum Ratings (Note 1) It CMOS Output Voltage VSSIO −0.15V to is anticipated that this device will not be offered in a (Vo): VDDIO +0.15V military qualified version. If Military/Aerospace specified CMOS Input Current (single input): devices are required, please contact the National Semicon- ductor Sales Office / Distributors for availability and specifi- Vi=VSSIO −0.15V: −5 mA cations. Vi=VDDIO +0.15V: +5 mA CMOS I/O Supply Voltage CMOS Output Source/Sink Current: ±10 mA SDO Output Sink Current: 40 mA (VDDIO–VSSIO): 4.0V SDO Supply Voltage Package Thermal Resistance θ @ (VDDSD–VSSSD): 4.0V JA 0 LFM Airflow 47˚C/W θ Digital Logic Supply Voltage JA @ 500 LFM Airflow 27˚C/W θ (VDDD–VSSD): 3.0V JC 6.5˚C/W PLL Digital Supply Voltage Storage Temp. Range: −65˚C to +150˚C (VDDPLL–VSSPLL): 3.0V Junction Temperature: +150˚C PLL Analog Supply Voltage Lead Temperature (Soldering 4 Sec): +260˚C (VDDPLLA–VSSPLLA), (VDDZ −VSSD ) : 3.0V ESD Rating (HBM): 2 kV CMOS Input Voltage VSSIO −0.15V to ESD Rating (MM): 250V (Vi): VDDIO +0.15V Recommended Operating Conditions Symbol Parameter Conditions Reference Min Typ Max Units VDDIO CMOS I/O Supply Voltage VDDIO−VSSIO 3.150 3.300 3.450 V VDDSD SDO Supply Voltage VDDSD−VSSSD 3.150 3.300 3.450 V V Digital Logic Supply V –V DDD DDD SSD 2.375 2.500 2.625 V Voltage VDDPLL PLL Supply Voltage VDDPLL–VSSPLL 2.375 2.500 2.625 V VDDZ Analog Supply Voltage VDDZ–VSSD 2.375 2.500 2.625 V V CMOS Input Voltage, Low IL V V Level SSIO V CMOS Input Voltage High IH V V Level DDIO T Operating Free Air A 0 +70 ˚C Temperature tJIT Video Clock Jitter VCLK 30 psP-P DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter Conditions Reference Min Typ Max Units VIH Input Voltage High Level All LVCMOS 2.0 VDDIO V VIL Input Voltage Low LevelInputs VSSIO 0.8 V IIH Input Current High Level VIH =VDDIO +90 +150 µA IIL Input Current Low Level VIL =VSSIO −1 −20 µA V CMOS Output Voltage I = −6.6 mA All LVCMOS OH OH 2.4 2.7 V V High Level Outputs DDIO V CMOS Output Voltage I = +6.6 mA V V OL OL V SSIO SSIO V Low Level SSIO +0.3 +0.5V V Serial Driver Output Test Circuit, Test Loads SDO, SDO SDO 720 800 880 mV Voltage Shall Apply P-P IDD (3.3V) Power Supply Current, VCLK = 27 MHz, NTSC VDDIO,VDDSD 3.3V Supply, Total color Bar Pattern, Test 48 65 mA Circuit, Test Loads Shall Apply 5 www.national.com DC Electrical Characteristics (Continued) Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). LMH0030 Symbol Parameter Conditions Reference Min Typ Max Units IDD (3.3V) Power Supply Current, VCLK = 74.25 MHz, NTSC VDDIO,VDDSD 3.3V Supply, Total color Bar Pattern, Test 66 90 mA Circuit, Test Loads Shall Apply IDD (2.5V) Power Supply Current, VCLK = 27 MHz, NTSC VDDD,VDDZ, 2.5V Supply, Total color Bar Pattern, Test V DDPLL 66 85 mA Circuit, Test Loads Shall Apply IDD (2.5V) Power Supply Current, VCLK = 74.25 MHz, NTSC VDDD,VDDZ, 2.5V Supply, Total color Bar Pattern, Test V DDPLL 85 110 mA Circuit, Test Loads Shall Apply AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). Symbol Parameter Conditions Reference Min Typ Max Units f Parallel Video Clock V VCLK CLK 27 74.25 MHz Frequency DC Video Clock Duty V V CLK 45 50 55 % Cycle f Ancillary Clock A ACLK CLK V MHz Frequency CLK DC Ancillary Clock Duty A A CLK 45 50 55 % Cycle t ,t Input Clock and Data 10%–90% V ,A ,DV , r f CLK CLK N 1.0 1.5 3.0 ns Rise Time, Fall Time ADN BRSDO Serial Data Rate (Notes 5, 6) SDO, SDO 270 1,485 Mbps tr,tf Rise Time, Fall Time 20%–80%, (Note 6) SDO, SDO 270 ps tr,tf Rise Time, Fall Time 20%–80%, (Note 5) SDO, SDO 500 ps Output Overshoot (Note 4) SDO, SDO 5% t Serial Output Jitter, 270 M , (Notes 5, 9, 10, 11) SDO, SDO j bps 270 350 ps Intrinsic P-P t Serial Output Jitter, 1,485 M , (Notes 6, 9, 10, 11) SDO, SDO j bps 85 125 ps Intrinsic P-P tLOCK Lock Time (Notes 5, 7) (SD Rates) 15 ms tLOCK Lock Time (Notes 6, 7) (HD Rates) 15 ms t Setup Time, Video Timing Diagram, (Note 4) DV to V S N CLK 1.5 2.0 ns Data tH Hold Time, Video Data Timing Diagram, (Note 4) VCLK to DVN 1.5 2.0 ns t Setup Time, Anc. Data Timing Diagram, (Note 4) AD to A S N CLK 1.5 2.0 ns Port t Hold Time, Anc.
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