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Logic Synthesis Lab Hours Lab hours: eds.mit.edu/labs Sun 1-11:45p, M-R 9-11:45p, F 9-5p Logic Synthesis • Primitive logic gates, universal gates • Truth tables and sum-of-products • Logic simplification • Karnaugh Maps, Quine-McCluskey • General implementation techniques: muxes and look-up tables (LUTs) Reminder: Lab #1 due this Thursday! 6.111 Fall 2017 Lecture 2 1 6.111 Fall 2017 Lecture 2 2 Conflicts Late Policies • Lab 1 check-offs – sign-up on checkoff queue in lab – FIFO during staffed lab hours. Note bench number… • Please don’t assume that you can wait until the last minute! • No check-offs Saturday • Checkoff must start no later than 9PM • Lab grade = Checkoff + Verilog grade (equal weighting) • Late labs: • 20%/day late penalty (no penalty for Saturday) • Max penalty 80% reduction. • Penalty waived for first 5 slack days.This covers illness, interviews, overload, etc. without S^3 involvement. • A missing lab will result in a failing grade. We’ve learned that if you’re struggling with the labs, the final project won’t go very well. • Lpset – must be submitted on time. 6.111 Fall 2017 Lecture 2 3 6.111 Fall 2017 Lecture 2 4 Wire Gauge Schematics & Wiring • Wire gauge: diameter is inversely • IC power supply connections generally not proportional to the wire gauge number. drawn. All integrated circuits need power! Diameter increases as the wire gauge decreases. 2, 1, 0, 00, 000(3/0) up to 7/0. • Use standard color coded wires to avoid confusion. • Resistance – red: positive – 22 gauge .0254 in 16 ohm/1000 feet – black: ground or common reference point – 12 gauge .08 in 1.5 ohm/1000 feet – Other colors: signals – High voltage AC used to reduce loss • Circuit flow, signal flow left to right • Higher voltage on top, ground negative voltage • 1 cm cube of copper has a resistance of 1.68 micro ohm (resistance of copper wire scales on bottom linearly : length/area) • Neat wiring helps in debugging! 6.111 Fall 2017 5 6.111 Fall 2017 6 CMOS Forever? CMOS Forever? 6.111 Fall 2017 Lecture 2 7 6.111 Fall 2017 Lecture 2 8 * Timing Specifications Propagation delay (tPD):An upper bound on the delay from valid inputs to valid outputs (aka “tPD,MAX”) VIN VIH VIL Design goal: minimize V OUT < tPD < tPD propagation delay VOH VOL * Intel 6.111 Fall 2017 Lecture 2 9 6.111 Fall 2017 Lecture 2 10 Contamination Delay The Combinational Contract an optional, additional timing spec Contamination delay(t ):A lower bound on the delay CD A B t propagation delay from invalid inputs to invalid AB 0 1 PD “ ” tCD contamination delay outputs (aka tPD,MIN ) 1 0 VIN Do we really need A VIH t ? CD B V IL Usually not… it’ll be important when we design circuits with Must be ___________> tCD VOUT > tCD > tCD registers (coming soon!) V < t OH Note: Must be ___________PD If tCD is not 1. No Promises during VOL specified, safe to assume it’s 0. 2. Default (conservative) spec: tCD = 0 6.111 Fall 2017 Lecture 2 11 6.111 Fall 2017 Lecture 2 12 Functional Specifications Here’s a Design Approach ABCY 1. Write out our functional spec as a truth table 0000 ABCY 2. Write down a Boolean expression with Output “1” if at 0010 terms covering each ‘1’ in the output: input A least 2 out of 3 of 0000 my inputs are a “1”. 0100 Otherwise, output “0”. input B output Y 0010 0111 input C I will generate a valid 0100 output in no more than 1000 Y A B C A B C A B C A B C 2 minutes after 0111 1011 seeing valid inputs 1000 1101 1011 1111 1101 This approach creates equations of a 3 binary inputs particular form called so 23 = 8 rows in our truth table 1111 An concise, unambiguous technique for giving the functional SUM-OF-PRODUCTS -it’s systematic! specification of a combinational device is to use a truth table to -it works! -it’s easy! Sum (+): ORs specify the output value for each possible combination of input values -are we done yet??? (N binary inputs -> 2N possible combinations of input values). Products (•): ANDs 6.111 Fall 2017 Lecture 2 13 6.111 Fall 2017 Lecture 2 14 S-O-P Building Blocks Straightforward Synthesis Y A B C A B C A B C A B C AZ We can use INVERTER: A 01 SUM-OF-PRODUCTS Bubble indicates 10 to implement any logic inversion function. ABZ 000 Only need 3 gate types: AND: A B 010 INVERTER, AND, OR 100 111 Propagation delay: • 3 levels of logic ABZ • No more than 3 gate delays assuming gates with an arbitrary 000 number of inputs. But, in general, we’ll only be able to use gates OR: A B 011 with a bounded number of inputs (bound is ~4 for most logic 101 families). 111 6.111 Fall 2017 Lecture 2 15 6.111 Fall 2017 Lecture 2 16 ANDs and ORs with > 2 inputs SOP w/ 2-input gates Previous example restricted to 2-input gates: A B C Y A B C A B C A B C A B C Chain: Propagation delay increases linearly with number of inputs A B C D Which one should I use? Using the timing specs given to the left, what are tPD and tCD for this INV AND2 OR2 combinational circuit? A B C D tPD 8ps 15ps 18ps Tree: Propagation delay increases Hint: to find overall tPD we need to tC 1ps 3ps 3ps logarithmically with number of inputs D find max tPD considering all paths from inputs to outputs. 6.111 Fall 2017 Lecture 2 17 6.111 Fall 2017 Lecture 2 18 More Building Blocks NAND – NOR Internals ABZ ABZ NAND (not AND) NOR (not OR) 001 001 011 010 A B A B 101 100 110 110 Y CMOS gates are naturally inverting so we want to use NANDs and NORs Y in CMOS designs… XOR is very useful when implementing XOR (exclusive OR) ABZ parity and arithmetic logic. Also used 000 as a “programmable inverter”: if A=0, A B 011 Z=B; if A=1, Z=~B 101 Wide fan-in XORs can be created with 110 chains or trees of 2-input XORs. 6.111 Fall 2017 Lecture 2 19 6.111 Fall 2017 Lecture 2 20 Universal Building Blocks SOP with NAND/NOR NANDs and NORs are universal: When designing with NANDs and NORs one often makes use of De Morgan’s laws: De Morgan-ized NAND symbol = = NAND form: A B A B = NOR form: A B A B = = = De Morgan-ized NOR symbol So the following “SOP” circuits are all equivalent (note the use = = of De Morgan-ized symbols to make the inversions less confusing): De Morgan-ized Inverter Any logic function can be implemented using only NANDs (or, equivalently, NORs). Note that chaining/treeing technique doesn’t work directly for creating wide fan-in NAND or NOR gates. But wide fan-in gates can be AND/OR form NAND/NAND form NOR/NOR form created with trees involving both NANDs, NORs and This will be handy in Lab 1 since All these “extra” inverters may seem less inverters. you’ll be able to use just 7400’s than ideal but often the buffering they to implement your circuit! provide will reduce the capacitive load on the inputs and increase the output drive. 6.111 Fall 2017 Lecture 2 21 6.111 Fall 2017 Lecture 2 22 Logic Simplification Boolean Minimization: An Algebraic Approach • Can we implement the same function with fewer gates? Before trying we’ll add a few more tricks in our bag. Lets simplify the equation from slide #3: • BOOLEAN ALGEBRA: OR rules: a 11 a 0 aa a a Y A B C A B C A B C A B C AND rules: a 1 a a 0 0 a a a Commutative: a b b aa b b a Using the identity Associative: (a b) c a (b c)(a b) c a (b c) Distributive: a (b c) a b a ca b c (a b) (a c) A A Complements: a a 1 a a 0 Absorption: a a b aa a b a ba (a b) aa (a b) a b For any expression α and variable A: De Morgan’s Law: a b a b a b a b Reduction: a b a b b (a b) (a b) b Y A B C A B C A B C A B C Key to simplification: equations that match the pattern of the LHS Y B C A C A B (where “b” might be any expression) tell us that when “b” is true, the value of “a” doesn’t matter. So “a” can be eliminated from the equation, The tricky part: some terms participate in more than one getting rid of two 2-input ANDs and one 2-input OR. reduction so can’t do the algebraic steps one at a time! 6.111 Fall 2017 Lecture 2 23 6.111 Fall 2017 Lecture 2 24 Karnaugh Maps: A Geometric Approach On to Hyperspace K-Map: a truth table arranged so that terms which differ by exactly one Here’s a 4-variable K-map: variable are adjacent to one another so we can see potential reductions easily. AB ABCY Here’s the layout of a 3-variable K-map filled in Z00011110 0000 with the values from our truth table: 00 1 0 0 1 0010 010000 Why did he CD 0100 shade that AB row Gray? 11 1 1 0 1 0111 Y00011110 10 1 1 0 1 1000 000 1 0 1011 C 101 1 1 Again it’s cyclic.
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