Lab Hours
Lab hours: eds.mit.edu/labs Sun 1-11:45p, M-R 9-11:45p, F 9-5p
Logic Synthesis
• Primitive logic gates, universal gates • Truth tables and sum-of-products • Logic simplification • Karnaugh Maps, Quine-McCluskey • General implementation techniques: muxes and look-up tables (LUTs)
Reminder: Lab #1 due this Thursday!
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Conflicts Late Policies
• Lab 1 check-offs – sign-up on checkoff queue in lab – FIFO during staffed lab hours. Note bench number… • Please don’t assume that you can wait until the last minute! • No check-offs Saturday • Checkoff must start no later than 9PM • Lab grade = Checkoff + Verilog grade (equal weighting) • Late labs: • 20%/day late penalty (no penalty for Saturday) • Max penalty 80% reduction. • Penalty waived for first 5 slack days.This covers illness, interviews, overload, etc. without S^3 involvement. • A missing lab will result in a failing grade. We’ve learned that if you’re struggling with the labs, the final project won’t go very well.
• Lpset – must be submitted on time.
6.111 Fall 2017 Lecture 2 3 6.111 Fall 2017 Lecture 2 4 Wire Gauge Schematics & Wiring • Wire gauge: diameter is inversely • IC power supply connections generally not proportional to the wire gauge number. drawn. All integrated circuits need power! Diameter increases as the wire gauge decreases. 2, 1, 0, 00, 000(3/0) up to 7/0. • Use standard color coded wires to avoid confusion. • Resistance – red: positive – 22 gauge .0254 in 16 ohm/1000 feet – black: ground or common reference point – 12 gauge .08 in 1.5 ohm/1000 feet – Other colors: signals – High voltage AC used to reduce loss • Circuit flow, signal flow left to right • Higher voltage on top, ground negative voltage • 1 cm cube of copper has a resistance of 1.68 micro ohm (resistance of copper wire scales on bottom linearly : length/area) • Neat wiring helps in debugging!
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CMOS Forever? CMOS Forever?
6.111 Fall 2017 Lecture 2 7 6.111 Fall 2017 Lecture 2 8 * Timing Specifications
Propagation delay (tPD):An upper bound on the delay from valid inputs to valid outputs (aka “tPD,MAX”)
VIN
VIH
VIL Design goal: minimize V OUT < tPD < tPD propagation delay VOH
VOL
* Intel
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Contamination Delay The Combinational Contract an optional, additional timing spec Contamination delay(t ):A lower bound on the delay CD A B t propagation delay from invalid inputs to invalid AB 0 1 PD “ ” tCD contamination delay outputs (aka tPD,MIN ) 1 0
VIN Do we really need A VIH t ? CD B V IL Usually not… it’ll be important when we design circuits with Must be ______> tCD VOUT > tCD > tCD registers (coming soon!) V < t OH Note: Must be ______PD If tCD is not 1. No Promises during VOL specified, safe to assume it’s 0. 2. Default (conservative) spec: tCD = 0
6.111 Fall 2017 Lecture 2 11 6.111 Fall 2017 Lecture 2 12 Functional Specifications Here’s a Design Approach
ABCY 1. Write out our functional spec as a truth table 0000 ABCY 2. Write down a Boolean expression with Output “1” if at 0010 terms covering each ‘1’ in the output: input A least 2 out of 3 of 0000 my inputs are a “1”. 0100 Otherwise, output “0”. input B output Y 0010 0111 input C I will generate a valid 0100 output in no more than 1000 Y A B C A B C A B C A B C 2 minutes after 0111 1011 seeing valid inputs 1000 1101 1011 1111 1101 This approach creates equations of a so 2 3 binary inputs particular form called 3 = 8 rows in our truth table 1111
An concise, unambiguous technique for giving the functional SUM-OF-PRODUCTS -it’s systematic! specification of a combinational device is to use a truth table to -it works! -it’s easy! Sum (+): ORs specify the output value for each possible combination of input values -are we done yet??? (N binary inputs -> 2N possible combinations of input values). Products (•): ANDs
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S-O-P Building Blocks Straightforward Synthesis Y A B C A B C A B C A B C AZ We can use INVERTER: A 01 SUM-OF-PRODUCTS Bubble indicates 10 to implement any logic inversion function. ABZ 000 Only need 3 gate types: AND: A B 010 INVERTER, AND, OR 100 111 Propagation delay: • 3 levels of logic ABZ • No more than 3 gate delays assuming gates with an arbitrary 000 number of inputs. But, in general, we’ll only be able to use gates OR: A B 011 with a bounded number of inputs (bound is ~4 for most logic 101 families). 111
6.111 Fall 2017 Lecture 2 15 6.111 Fall 2017 Lecture 2 16 ANDs and ORs with > 2 inputs SOP w/ 2-input gates Previous example restricted to 2-input gates:
A B C Y A B C A B C A B C A B C
Chain: Propagation delay increases linearly with number of inputs
A B C D
Which one should I use? Using the timing specs given to the
left, what are tPD and tCD for this INV AND2 OR2 combinational circuit? A B C D tPD 8ps 15ps 18ps Tree: Propagation delay increases Hint: to find overall tPD we need to tC 1ps 3ps 3ps logarithmically with number of inputs D find max tPD considering all paths from inputs to outputs.
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More Building Blocks NAND – NOR Internals ABZ ABZ NAND (not AND) NOR (not OR) 001 001 011 010 A B A B 101 100 110 110
Y CMOS gates are naturally inverting so we want to use NANDs and NORs Y in CMOS designs…
XOR is very useful when implementing XOR (exclusive OR) ABZ parity and arithmetic logic. Also used 000 as a “programmable inverter”: if A=0, A B 011 Z=B; if A=1, Z=~B 101 Wide fan-in XORs can be created with 110 chains or trees of 2-input XORs.
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NANDs and NORs are universal: When designing with NANDs and NORs one often makes use of De Morgan’s laws: De Morgan-ized NAND symbol
= = NAND form: A B A B =
NOR form: A B A B = = = De Morgan-ized NOR symbol So the following “SOP” circuits are all equivalent (note the use = = of De Morgan-ized symbols to make the inversions less confusing): De Morgan-ized Inverter Any logic function can be implemented using only NANDs (or, equivalently, NORs). Note that chaining/treeing technique doesn’t work directly for creating wide fan-in NAND or NOR gates. But wide fan-in gates can be AND/OR form NAND/NAND form NOR/NOR form created with trees involving both NANDs, NORs and This will be handy in Lab 1 since All these “extra” inverters may seem less inverters. you’ll be able to use just 7400’s than ideal but often the buffering they to implement your circuit! provide will reduce the capacitive load on the inputs and increase the output drive.
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Logic Simplification Boolean Minimization: An Algebraic Approach
• Can we implement the same function with fewer gates? Before trying we’ll add a few more tricks in our bag. Lets simplify the equation from slide #3: • BOOLEAN ALGEBRA: OR rules: a 11 a 0 aa a a Y A B C A B C A B C A B C AND rules: a 1 a a 0 0 a a a Commutative: a b b aa b b a Using the identity Associative: (a b) c a (b c)(a b) c a (b c) Distributive: a (b c) a b a ca b c (a b) (a c) A A Complements: a a 1 a a 0 Absorption: a a b aa a b a ba (a b) aa (a b) a b For any expression α and variable A: De Morgan’s Law: a b a b a b a b Reduction: a b a b b (a b) (a b) b Y A B C A B C A B C A B C
Key to simplification: equations that match the pattern of the LHS Y B C A C A B (where “b” might be any expression) tell us that when “b” is true, the value of “a” doesn’t matter. So “a” can be eliminated from the equation, The tricky part: some terms participate in more than one getting rid of two 2-input ANDs and one 2-input OR. reduction so can’t do the algebraic steps one at a time! 6.111 Fall 2017 Lecture 2 23 6.111 Fall 2017 Lecture 2 24 Karnaugh Maps: A Geometric Approach On to Hyperspace
K-Map: a truth table arranged so that terms which differ by exactly one Here’s a 4-variable K-map: variable are adjacent to one another so we can see potential reductions easily. AB ABCY Here’s the layout of a 3-variable K-map filled in Z00011110 0000 with the values from our truth table: 00 1 0 0 1 0010 010000 Why did he CD 0100 shade that AB row Gray? 11 1 1 0 1 0111 Y00011110 10 1 1 0 1 1000 000 1 0 1011 C 101 1 1 Again it’s cyclic. The left edge is adjacent to the right edge, 1101 and the top is adjacent to the bottom. 1111 010 011 000 001 We run out of steam at 4 variables – K-maps are hard to draw and It’s cyclic. The left edge is adjacent to the right 110 111 use in three dimensions (5 or 6 variables) and we’re not equipped edge. It’s really just a flattened out cube. to use higher dimensions (> 6 variables)! 100 101
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Finding Subcubes Write Down Equations
Write down a product term for the portion of each We can identify clusters of “irrelevent” variables by circling adjacent subcubes of 1s. A subcube is just a lower dimensional cluster/subcube that is invariant. You only need to include cube. enough terms so that all the 1’s are covered. Result: a minimal AB sum of products expression for the truth table. Z00011110 AB 00 1 0 0 1 AB Y00011110 010000 00 01 11 10 CD 000 1 0 11 1 1 0 1 000 1 0 Y A C B C A B C C 101 1 1 10 1 1 0 1 101 1 1
Three 2x1 subcubes We’re done! AB The best strategy is generally a greedy one. Z00011110 N - Circle the largest N-dimensional subcube (2 adjacent 1’s) 00 1 0 0 1 4x4, 4x2, 4x1, 2x2, 2x1, 1x1 010000 - Continue circling the largest remaining subcubesThree 2x2 subcubes CD Z B D B C A C (even if they overlap previous ones) 11 1 1 0 1 - Circle smaller and smaller subcubes until no 1s are left. 10 1 1 0 1
6.111 Fall 2017 Lecture 2 27 6.111 Fall 2017 Lecture 2 28 Morse Code to ASCII Exercise
• Morse code – variable length encoding, 6 bits max – Letter “e” – Period
• ASCII (American Standard Code for Information Interchange) - 8 bit binary representation of text
• How many bits are required to represent any morse code input?
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Two-Level Boolean Minimization Prime Term Generation F = f(W,X,Y,Z) Two-level Boolean minimization is used to find a sum-of-products Start by expressing your Boolean function using 0- W X Y Z label representation for a multiple-output Boolean function that is 0 0 0 0 0 terms (product terms with no don’t care care entries). 0 1 0 1 5 optimum according to a given cost function. The typical cost For compactness the table for example 4-input, 1- 0 1 1 1 7 functions used are the number of product terms in a two-level output function F(w,x,y,z) shown to the right includes 1 0 0 0 8 realization, the number of literals, or a combination of both. The only entries where the output of the function is 1 and 1 0 0 1 9 1 0 1 0 10 two steps in two-level Boolean minimization are: we’ve labeled each entry with it’s decimal equivalent. 1 0 1 1 11 1 1 1 0 14 1 1 1 1 15 •Generation of the set of prime product-terms for a given function. Look for pairs of 0-terms that differ in only one bit position and merge them in a 1-term (i.e., a term that has exactly one ‘–’ entry). Next 1-terms •Selection of a minimum set of prime terms to implement the are examined in pairs to see if the can be merged into 2-terms, etc. Mark function. k-terms that get merged into (k+1) terms so we can discard them later.
We will briefly describe the Quine-McCluskey method which was 1-terms: 0, 8 -000 [A] 2-terms: 8, 9,10,11 10--[D] 5, 7 01-1 [B] 10,11,14,15 1-1-[E] the first algorithmic method proposed for two-level minimization 7,15 -111 [C] and which follows the two steps outlined above. State-of-the-art 8, 9 100- 8,10 10-0 3-terms: none! logic minimization algorithms are all based on the Quine-McCluskey 9,11 10-1 Example due to 10,11 101- Label unmerged terms: method and also follow the two steps above. Srini Devadas 10,14 1-10 these terms are prime! 11,15 1-11 14,15 111- 6.111 Fall 2017 Lecture 2 31 6.111 Fall 2017 Lecture 2 32 Prime Term Table Logic that defies SOP simplification
An “X” in the prime term table in row R and column K signifies that the 0- Full Adder S term corresponding to row R is contained by the prime corresponding to C/AB 00 01 11 10 Ci A B S Co column K. 0 0 0 0 0 AB 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 A B C D E 0 1 0 1 0 CO Goal: select the minimum 0000 X . . . . A is essential -000 0 1 1 0 1 Co FA Ci C/AB 00 01 11 10 0101 . X . . . B is essential 01-1 set of primes (columns) 0 0 0 1 0 0111 . X X . . 1 0 0 1 0 such that there is at least 1 0 1 0 1 1 0 1 1 1 1000 X . . X . one “X” in every row. This 1001 . . . X . D is essential 10-- 1 1 0 0 1 S is the classical minimum 1010 . . . X X 1 1 1 1 1 covering problem. 1011 . . . X X 1110 . . . . X E is essential 1-1- 1111 . . X . X S A BC A BC A BC A BC A B Ci Each row with a single X signifies an essential prime term since any prime C A C B C A B implementation will have to include that prime term because the O corresponding 0-term is not contained in any other prime. The sum S doesn’t have a simple sum-of-products implementation In this example the essential primes “cover” all the 0-terms. even though it can be implemented using only two 2-input XOR gates. F = f(W,X,Y,Z) = XYZ + WXZ + WX + WY
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Logic Synthesis Using MUXes Systematic Implementation of Combinational Logic Truth Table A C B A Y 0 0 0 0 Consider implementation of some If C is 1 then Y B 0 0 1 1 arbitrary Boolean function, F(A,B) copy B to Y, Full-Adder 0 1 0 0 otherwise copy Carry Out Logic C 0 1 1 1 ... using a MULTIPLEXER A to Y A 4-input Mux 1 0 0 0 as the only circuit element: implemented as 1 0 1 0 a tree 0 0 1 1 0 1 ABCY 2-input Multiplexer I0 1 1 1 1 0 0 1 I1 0000 1S 0 Y 0 2 1 0010 I2 1S A 0 1 3 C B 0 I3 0100 out 1S 0 4 C 0111 Y B 1 1 5 A 1000 S0 S1 1 C 1011 6 1 7 schematic Gate 1101 symbol 1111 A,B,Cin
6.111 Fall 2017 Lecture 2 35 6.111 Fall 2017 Lecture 2 36 Systematic Implementation of Xilinx Virtex II FPGA Combinational Logic
Same function as on previous slide, but this time let’s use a 4-input mux
Full-Adder ABCY Carry Out Logic 0000 0010 0 0 0100 Cin 1 Cout 0111 Cin 2 1000 1 3 1011 XC2V6000: 1101 A,B • 957 pins, 684 IOBs • CLB array: 88 cols x 96/col = 8448 CLBs 1111 • 18Kbit BRAMs = 6 cols x 24/col = 144 BRAMs = 2.5Mbits • 18x18 multipliers = 6 cols x 24/col = 144 multipliers
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Virtex II CLB Virtex II Slice Schematic
16 bits of RAM which can be configured as a 16x1 Figures from Xilinx Virtex II datasheet single- or dual-port RAM, a 16-bit shift register, or a 16-location lookup table Figures from Xilinx Virtex II datasheet
6.111 Fall 2017 Lecture 2 39 6.111 Fall 2017 Lecture 2 40 Virtex II Sum-of-products Spartan 6 FPGA
Figures from Xilinx Virtex II datasheet
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Spartan 6 SliceM Schematic Oscilloscope
Cursor controls
Figures from Xilinx Spartan 6 CLB datasheet
Menu driven soft key/buttons
6.111 Fall 2017 Lecture 2 43 6.111 Fall 2017 44 Oscilloscope Controls Gesture Controlled Drone Fall 2014 • Auto Set, soft menu • Signal measurement keys –time, • Track hands with a camera and – frequency, determine x,y coordinates – voltage • Trigger –cursors • Based on movement of the – channel, – single sweep coordinates, recognize gestures. – slope, – • Generate real time digital signals Level and convert to analog format for • Image capture transmission to drone – controlling • Input pitch, roll, hover – AC, DC coupling, – • Innovation: using hand motion and 10x probe, recognition of gestures to control – 1khz calibration flight source, – probe calibration, – bandwidth filter
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