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Repaso De Arquitectura Y Organización Criterios De Clasificación Repaso de Arquitectura y Organización Criterios de clasificación William Stallings, Organización y Arquitectura de Computadores Andrew S. Tanenbaum, Organización de Computadoras Linda Null y Julia Lobur, Computer Organization and Architecture John Hennessy – David Patterson Arquitectura de Computadores – Un enfoque cuantitativo (1a edición, capítulos 3, 4 y 5) (4th ed, ch 1 & ap. B) Arquitectura de Computadoras Introducción COMPUTADORA Dispositivo electrónico, digital y programable, utilizado para el procesamiento y/o manipulación de información. Representación digital de la información. Sistemas numéricos posicionales en base 2. Operaciones aritméticas implementadas con lógica. Otros tipos de información. El programa almacenado. Arquitectura de von Neumann. Tipos de instrucciones. Organización mínima. Datapath (REG y ALU) + UC. Buses. Programas y algoritmos. Re-programabilidad vs. sistemas dedicados. Hardware vs. software. El ciclo de instrucción. Interrupciones. La jerarquía de memoria. Localidad. Caches. Programación de alto nivel y sistemas operativos. 2 Arquitectura de Computadoras Arquitecturas de 8/16 bits 4004 (4-bit 640B) 1971 8008 (8-bit 16KB) 1972 8080 (8-bit 64KB) 1972 6800 (8-bit 64KB) 1973 8086 (16-bit 16MB) 1978 68000 (16/32-bit 16MB) 1979 8088 (8/16-bit) 1980 68008 (8/16-bit) 1982 IBM PC Apple II/Mac Personal Computer 3 Arquitectura de Computadoras Bibliografía básica Stallings Tanenbaum Null Introducción 1-2 1 1 Números A A-B 2 Sistemas digitales 8 3 3 Von Neumann y buses 3 2-3 4 Repertorio de instrucciones 9-10 4-5 5 Memoria 4-5 2 6 Entrada/salida 6 2 7 Sistemas operativos 7 6 8 Arquitectura II 11-16 8 9-10 4 Arquitectura de Computadoras Definición H-P Diseño de computadoras LÓGICA (Software?) ISA (INSTRUCTION SET ARCHITECTURE): Diseño a nivel del lenguaje de máquina, visible para el programador o compilador. Repertorio de instrucciones, registros, tipo y tamaño de operandos, modos de direccionamiento. IMPLEMENTACIÓN (Hardware?) ORGANIZACIÓN: Estructura del bus, diseño CPU, sistema de memoria, ciclo de instrucción. TECNOLOGÍA: Diseño lógico, integración, encapsulado, potencia. “La arquitectura de computadoras, como otras arquitecturas, es el arte de determinar las necesidades del usuario de una estructura y luego diseñarla para satisfacer dichas necesidades tan eficientemente como sea posible dentro de ciertas limitaciones económicas y tecnológicas.” Frederick P. Brooks, IBM, 1962. 5 Arquitectura de Computadoras Ejemplos Intel Dos procesadores con idéntica ISA pero diferente ORG: Celeron y Celeron D. Dos procesadores con idénticas ISA y ORG, pero diferente tecnología: Celeron 1GHz y Celeron 2.8GHz. Dos procesadores con diferentes ISA, ORG y Tecnología: Celeron e Itanium. ERROR COMÚN Suponer que dos procesadores con idéntica ISA se pueden comparar por su reloj OTROS EJEMPLOS Computadora óptica (cambiando Tec puedo mantener la ISA y ORG) Computadora analógica (cambia ORG) Computadora vectorial (cambia ISA y ORG) 6 Arquitectura de Computadoras Historia Después de 30 años de existencia de las computadoras y 10 de los microprocesadores [Null, Cap 1], se produce un renacimiento de la Arquitectura en la década del 80, principalmente por dos motivos: LENGUAJES DE ALTO NIVEL: Desaparece la programación en assembler, por lo tanto no es necesaria la compatibilidad de código objeto. SISTEMAS OPERATIVOS: Se reducen el costo y el riesgo de lanzar al mercado una nueva arquitectura. Nacimiento de las nuevas Arquitecturas RISC: − ILP (pipeline + superescalares) − CACHE Crecimiento sostenido durante 20 años (ley de Moore) 7 Número de transistores por integrado. Duplica cada dos años, crecimiento exponencial sostenido. 8 Capacidad de los discos rígidos para PC (en GB) Crecimiento exponencial sostenido. 9 Performance relativa a VAX-11 (1978) Crecimiento exponencial sostenido (1986-2002), luego desaceleración. El aumento del número de transistores no repercute directamente en la performance. Depende de los avances en ARQUITECTURA, tanto en hardware como en software. 10 Arquitectura de Computadoras Clasificación según la aplicación Por qué existen arquitecturas tan diferentes? Cuál es mejor? Equivalente con la industria automotriz. Diseño de alto rendimiento SERVERS ($5K) [cómputo masivo, gráficos] Availability, reliability, scalability, throughput. Diseño de bajo costo EMBEDDED SYSTEMS ($50) [consolas, switches] Minimización de memoria y potencia. Diseño costo/rendimiento DESKTOP ($500) [debe incluir sw!] Marketing vs. rendimiento, información incompleta o vaga, medidas inapropiadas, recurrir a la popularidad. 11 Arquitectura de Computadoras Clasificación a nivel lenguaje de máquina (ISA) 1. Clase: Número y almacenamiento de operandos. Además de memoria, dónde? Utilización de registros. 2. Direccionamiento de memoria. Byte ordering (endianness). Alineación. 3. Modos de direccionamiento. Cantidad. Puede cualquiera de los operandos estar en memoria? 4. Tipo y tamaño de los operandos. ORTOGONALIDAD Todos los modos de direccionamiento y todos los tipos de datos disponibles 5. Tipos y variedad de operaciones. para todas las instrucciones. Gran ventaja para los compiladores. 6. Control de flujo. 7. Codificación del repertorio de instrucciones. 12 8. Interrupciones y modos privilegiados (user, supervisor,protected). Clasificación a nivel lenguaje de máquina Almacenamiento de operandos Add A,B,C TAXONOMÍA DE PATTERSON: PILA, ACC, R-M, R-R, M-M 13 Clasificación a nivel lenguaje de máquina Número de operandos 14 15 EJEMPLO: Velocidad vs. Densidad de código Analizaremos el impacto de dos problemas diferentes: M3 = M1 + M2 Suma de dos enteros Bn = (An + An-1)/2 Filtro en punto fijo Sobre tres arquitecturas diferentes: MM Arquitectura Memoria-Memoria RM Arquitectura Registro-Memoria RR Arquitectura Registro-Registro 16 M3 = M1 + M2 MM ADD M1,M2,M3 9c F-D-CO1-TR1-C02-TR2-E-CO3-TR3 = 9c RM LOAD R1,M1 (4c) LOAD: F-D-CO-TR = 4c 13c ADD R1,M2 (5c) ADD: F-D-CO-TR-E = 5c STORE R1,M3 (4c) RR LOAD R1,M1 (4c) LOAD R2,M2 (4c) 15c LOAD: F-D-CO-TR = 4c ADD: F-D-E = 3c ADD R1,R2,R3 (3c) STORE R3,M3 (4c) 17 M3 = M1 + M2 Bn = (An + An-1)/2 MM MM ADD An,An-1,Bn ADD M1,M2,M3 9c 18c DIV Bn,#2,Bn F-D-CO1-TR1-C02-TR2-E-CO3-TR3 = 9c RM RM LOAD R1,M1 (4c) 13c LOAD R1,An-1 (4c) 18c ADD R1,M2 (5c) ADD R1,An (5c) STORE R1,M3 (4c) DIV R1,#2 (5c) STORE R1,Bn (4c) LOAD: F-D-CO-TR = 4c ADD: F-D-CO-TR-E = 5c RR RR LOAD R1,M1 (4c) LOAD R1,An (4c) 15c 17c LOAD R2,M2 (4c) ADD R1,R2,R3 (3c) ADD R1,R2,R3 (3c) DIV R3,#2,R3 (3c) STORE R3,M3 (4c) STORE R3,Bn (4c) LOAD: F-D-CO-TR = 4c ADD R1,#0,R2 (3c) 18 ADD: F-D-E = 3c M3 = M1 + M2 Bn = (An + An-1)/2 MM MM ADD An,An-1,Bn ADD M1,M2,M3 9c 18c 1 DIV Bn,#2,Bn 1 F-D-CO1-TR1-C02-TR2-E-CO3-TR3 = 9c RM RM LOAD R1,M1 (4c) 13c LOAD R1,An-1 (4c) 18c ADD R1,M2 (5c) ADD R1,An (5c) STORE R1,M3 (4c) 3 DIV R1,#2 (5c) STORE R1,Bn (4c) LOAD: F-D-CO-TR = 4c 2 ADD: F-D-CO-TR-E = 5c RR RR LOAD R1,M1 (4c) LOAD R1,An (4c) 15c 17c LOAD R2,M2 (4c) ADD R1,R2,R3 (3c) ADD R1,R2,R3 (3c) DIV R3,#2,R3 (3c) 4 STORE R3,M3 (4c) STORE R3,Bn (4c) 2.5 LOAD: F-D-CO-TR = 4c ADD R1,#0,R2 (3c) 19 ADD: F-D-E = 3c Clasificación a nivel lenguaje de máquina Modos de direccionamiento 20 Clasificación a nivel lenguaje de máquina Repertorio de instrucciones Todas las arquitecturas disponen de un repertorio compuesto al menos por las tres primeras categorías. 21 Clasificación a nivel lenguaje de máquina Tipo y tamaño de operandos Arquitecturas con operandos de 8, 16, 32 o 64 bits. Operandos enteros y/o punto flotante (simple y doble precisión). RISC vs CISC (largo fijo vs. variable) CODIFICACIÓN DEL SET DE INSTRUCCIONES Tamaño de los programas Implementación del procesador (ORG+TECH) 22 Arquitectura de Computadoras Clasificación según la organización Estructura interna de la CPU La unidad de control (microprogramada vs. cableada) El camino de los datos (Datapath = Registros + ALU) El ciclo de instrucción, segmentación Escalaridad Cache de datos e instrucciones CPI, latencia Productividad (throughput) 23 Clasificación según la organización CU & Datapath 24 Clasificación según la organización Registros Para llevar a cabo el ciclo de instrucción (CAPTACION- DECODIFICACION-EJECUCION-INTERRUPCION) la CPU necesita registros de almacenamiento temporario. Registros visibles a) Usos generales: pueden utilizarse en cualquier operación. b) Uso específico: para datos o direcciones (ej. puntero de segmento). Registros de control PC (puntero), IR (instrucción), MAR (dirección) y MBR (datos) Registros de estado PSW (program status word) 25 Clasificación según la organización El ciclo de instrucción CAPTACION DE MEMORIA F LA INSTRUCCION UC DECODIFICACION D ALU CALCULO DIR CO DEL OPERANDO MEMORIA CAPTACION DEL FO OPERANDO EJECUCION DE ALU LA INSTRUCCION E 26 Arquitectura de Computadoras TECNOLOGÍA Tecnologías que condiciona el diseño de la ISA: Circuitos integrados (densidad de transistores 55%/año) DRAM semiconductora (densidad celdas 40-60%/año) Discos magnéticos (capacidad 100%/año) Networking (ancho de banda 100%/año) La ISA debe sobrevivir a lo largo de ciclos de 5 años (2 de diseño + 3-2 de producción). 27 Tecnología INTEGRACIÓN Tecnología del proceso CMOS (½ celda DRAM, expected average half-pitch of a memory cell) 180 nm 1999/2000 PII 130 nm 2000/2001 90 nm 2002/2003 65 nm Actual PIV, Core (gate 35 nm) 45 nm 2008? Gate metálico ... 16 nm 2018? LIMITE? gate de 5 nm, tunneling Un elemento más pequeño implica mayor cantidad de transistores disponibles, conmutación más rápida, menor energía y menor temperatura. 28 Tecnología INTEGRACIÓN (cont) Límites al tamaño del intregrado: Potencia (max ~70W) Yield del waffer (cuántos fallan) Encapsulado (número de patas) Condiciona la cantidad disponible de transistores.
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