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82C5059 SINGLE CHIP PC·AT DISK CONTROLLER
Memory Controller Features • Multi-Sector Transfer Capability with Automatic Sector Increment ~ • Two Independent DMA Channels • Programmable Automatic ID Retries • 13 Megabyte Device Bandwidth at 40MHz Clock • ESDIID Sync Timeout Programmable
• 20-bit Address and 16-Bit Transfer Count • ESDI Write Gate to AM ENABLE Registers For Each Channel Programmable
• Holding Registers for Addresses Counts • Format Track With Data From Buffer for Non-Contiguous Memory Transfers • Programmable Write Gate Disable for Em· • Bus Access Resolved on Channel Priority bedded Servo Basis • 32,48, 56 Bit ECC Polynomial • Programmable: AT Interface Features - Interrupt Polarity • Direct Interface to AT-Compatible Sys - Auto-Count Re-Initialization tems, Including 40-Pin Bus Interface
- Memory Access Cycle Timing (2 To 5 • High Current Drivers for Host Interface Clock Cycles) • Schmidt Trigger Inputs Form Host Inter • Buffer Memory Address for 64K SRAM (2 face Memory Chip Enables for 32K x 8 SRAM) • Configurable Primary or Secondary Ad • DRAM Support For Up To 1 Megabyte dress
Programmable Data Sequencer • 2 Word FIFO Features • Automatic BUSY, INTRQ and ECC Mode • High Level Instruction Set • Flexible Interrupt Capability • Supports up to 20MHz Serial Bit Rate (NRZ) • Advanced 1.51' CMOS, Low Power Techonology • Programmable Disk Format • 100-Pin Quad Flat Pack Packaging • NRZ Serial Disk Interface • Direct Interface to ESDI Type Drives o I MEMORY INTERFACE rh % (\ (';. -== READ 82C5059 MEMORY REFERENCE SINGLE-CHIP CLOCK PC-AT CONTROLLER ADDRESS 161 9/ AND Ub CONTROL " DISK SEQUENCER WRITE CLOCK (SERIAL-TO- K :> PARALLEL PC-AT MEMORY DATA BUS V AND DATA '" PARALLEL- READ ...... TO-SERIAL) DATA (NRZ) ~ 9/ a.- FROM DISK
PC-AT TWO-CHANNEL HOST- DMA WRITE DATA INTERFACE CONTROLLER (NRZ) TO DISK FIFO HOST AND CONTROL CONTROL WINCHESTER CONTROL 2 x 20 BIT PC-AT 64 8 AND CIRCUITS ADDRESS x FLOPPY- BUS RAM COUNTER INDEX DISK PC-AT SEQUENCER INTERFACE CONTROL... AND SECTORI ) STATE ADDRESS- < 2 x 16 BIT CONTROL MARK 81 TRANSFER FOUND COUNTER
ADDRESS MARK 'o~'o, 1 ~fi ENABLE '). INTERNAL CONTROL AND STATUS BUS { i CONTROL I '\ CONTROL MIRCOPROCESSOR ADDRESS, DATA, Li CONTROL, AND STATUS INTERFACE ~ 81 f\ ~ ADDRESS SCSI SEQUENCE DMA MICROPROCESSOR 81 AND INTERRUPT INTERRUPT INTERRUPT CONTROL ADDRESS BUS DATA BUS
~ 7 V \7 MICROPROCESSOR INTERFACE
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Introduction The programmable data sequencer provides format control, error detection, and serial/ The 82C5059 Single Chip PC-AT Controller is parallel (SERDES) conversion functions nor a CMOS LSI Applications Specific Integrated mally associated with disk controllers. It is Circuit (ASIC) designed to be the primary designed to be used with NRZ (Non-Return to component in a high-performance intelligent Zero) interfaces such as those used in the PC-AT Winchester disk controller system. The ESDI (Enhanced Small Device Interface) or 82C5059 single chip controller provides three any of the CHIPS family of encode/decode essential functions in a disk controller system: VCO devices. Flexible operation of the se it manages the flow of data for a serial peri quencer is made possible by write registers pheral, it controls access to the external RAM that program its operation, while read registers buffer memory that is required for such trans allow the firmware to monitor operation. In fers and it directly interfaces to a PC-AT type addition, complete flexibility in disk formatting system bus. The 82C5059 is designed to be is permitted by a 54-byte on-device format used with a microprocessor havi ng either a Z8- RAM, which is accessed through three of the or 8051-type bus structure. data sequencer write registers (WR25, WR30 & WR31). The 82C5059 consists of three functional sec tions: In addition to an external RAM buffer, a byte oriented microprocessor such as. the Z8 or 1. A DMA controller 8051, with its associated memory, the 82C5059 may be connected with the CHIPS 10C5070 2. A data sequencer Encode/Decode/PLL for MFM encoding/ 3. A PC-AT interface controller decoding up to 5 Mbits/second, or the 10C5027 Encode/Decode/PLL for RLL 2,7 en The 82C5059 incorporates a dual-bus ar coding/decoding up to 10 Mbits/second thus chitecture, providing separate ports for providing a complete controller solution for an microprocessor and memory buffer opera embedded PC-AT interfacing disk drive. tions. With the goal of achieving the highest possible performance, this dual-bus structure Ordering Information is used so that disk data transfers can occur simultaneously with microprocessor opera The 82C5059 can be ordered using the follow tions. ing part number:
In the DMA controller, Channel 0 is used for F82C5059 (100-Pin QFP) moving blocks of data between the data se quencer and the external buffer, wh ile Channel Evaluation samples are available now. 1 is used for movi ng blocks of data between the Production orders accepted with standard PC-AT host interface and the buffer. When the leadtimes. data sequencer is not using Channel 0, this channel can also be used to allow the microprocessor to access the RAM buffer. DMA controller operation is programmed by writing the DMA controller registers, while operation may be monitored by reading the DMA controller registers. <:ttl~!i ______
RAM BUFFER MEMORY c '\ '\ ~ MEM ~MEM DATA ADD AT INTERNAL INTERFACE ) DRI VE BUS .'7 NRZ DATA BU S WRITE WRITE CHIPS - ENCODE/ -DATA NRZ DECODE READ K..... CHIPS READ VCO AT ... 82C5059 DATA SINGLE CHIP BUS PC-AT CONTROLLER - -CONTROL .. + K ~ STATUS ~ AT v CONTROL DRIVr BUS CONTROL'""" 1\ & STATUS ~ I \. MICRO CONTROL &INT "'-., I ./ MICRO MICRO COMPUTER ADDRESS/DATA BUS ... o ") V 1\ "\ \. V MICRO ADDRESS 1 MICRO 8-15 ADDRESS ROM/EPROM / LATCH ~ MEMORY "-...
F82C5059 Typical System Configuration ~i-liiFi::t ______
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l> < < 0 ~ l>N l> l> l> l> l> l> l> 000 0 ... °1°1;:"''''0 0 0 0 0 0 0 0 l> -1-,-Il>1 o ~ 0 ....
NOTES c
o CHiPS ______
NOTES
o CHIPS Chips and Technologies, Inc. 3050 Zanker Road, San Jose, CA 95134 408-434-0600 telex 272929 CHIPS UR
CHIPS, CHIPSet, NEAT, NEATsx, LeAPSet, LeAPSetsx, PEAK, CHIPS/280, CHIPS/250, CHIPS/230, CHIPS/450, MICROCHIPS, CHIPSPak, CHIPSPort, CHIPSlink are trademarks of Chips and Tech nologies, Inc. IBM AT, XT, PS/2, Micro Channel, Personal System/2, Enhanced Graphics Adapter, Color Graphics Adapter, IBM Color Display, IBM Monochrome Display are trademarks of International Business Machines. Intel, iAPX 386 are trademarks of Intel Corporation. Motorola is a trademark of Motorola. Lotus is a trademark of Lotus Corporation. Microsoft is a trademark of Microsoft. Copyright 1988, 1989 Chips and Technologies, Inc. These data sheets are provided for the general information of the customer. Chips and Technologies, Inc. reserves the right to modify these parameters as necessary and customer should ensure that it has the most recent revision of the data sheet. Chips makes no warranty for the use of its products and bears no responsibility for any errors which may appear in this document. The customer should be on notice that the field of personal computers is the subject of many patents held by different parties. Customers should ensure that they take appropriate action so that their use of the products does not infringe upon any patents. It is the policy of Chips and Technologies, Inc. to respect the valid patent rights of third parties and not to infringe upon or assist others to infringe upon such rights. .