Embedded Pentium Processors

Embedded Pentium® Processor- Based POS Terminal Sample Design

Application Note

November 1998

Order Number: 273218-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com.

Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

Contents

1.0 Introduction...... 7 1.1 Key Terms ...... 7 1.2 Related Documents...... 7 2.0 Embedded Applications Overview...... 8 2.1 Influence of PC Technology ...... 8 2.2 Embedded Pentium Processors...... 8 2.3 Operating Systems for POS Applications...... 9 3.0 Point-of-Sale Terminal...... 9 3.1 Proprietary Operating System Versus Off-the-Shelf ...... 9 3.2 POS Implementation ...... 10 3.3 Windows CE...... 11 4.0 Embedded Pentium Processors...... 11 4.1 Pentium Processor with MMX Technology...... 14 5.0 POS Terminal Design Overview...... 15 5.1 Core Components ...... 15 5.2 Processor Assembly Components ...... 16 6.0 Functional Description of Hardware ...... 16 6.1 Processor Assembly...... 17 6.1.1 Processor ...... 17 6.1.2 In-Target Probe (ITP) ...... 17 6.1.3 Voltage Regulator...... 17 6.1.4 Intel 430TX PCIset ...... 17 6.1.4.1 82439TX System Controller (MTXC)...... 17 6.1.4.2 Intel 82371AB PCI ISA IDE Xcelerator (PIIX4) ...... 18 6.1.4.3 IDE / Floppy...... 19 6.1.4.4 USB Host Controller ...... 19 6.1.5 Cache ...... 21 6.2 Video ...... 22 6.2.1 Chips and Technologies 69000 HiQVideo Accelerator with Integrated Memory22 6.2.2 High Performance Integrated Memory ...... 22 6.2.3 HiQColor Technology ...... 22 6.2.4 Versatile Panel Support...... 22 6.2.5 Television NTSC/PAL Flicker Free Output...... 23 6.2.5.1 Design Note...... 23 6.3 Audio ...... 26 6.3.1 AC ’97 Audio ...... 26 6.3.2 Ensoniq AudioPCI 97 ES1371 Digital Controller...... 27 6.3.2.1 Design Note...... 27 6.3.3 Analog Devices AC ’97 AD1819 SoundPort Codec ...... 27 6.3.3.1 Design Note...... 27 6.4 SMSC FDC37B78x Ultra I/O ...... 29

Application Note iii Embedded Pentium® Processor-Based POS Terminal Sample Design

6.4.1 Floppy Disk Controller (FDC) ...... 29 6.4.2 Serial Port Controller...... 29 6.4.3 Infrared Interface...... 29 6.4.3.1 Design Note...... 29 6.4.4 Parallel Port Controller ...... 30 6.4.5 Keyboard and Mouse ...... 30 6.4.5.1 Design Note for Ultra I/O...... 30 6.4.6 Additional Serial Ports with SMSC 37C669 Super I/O ...... 31 6.4.6.1 Design Note...... 31 6.5 Tritech Microelectronics TR88L803 Touch Screen Controller...... 32 6.5.1 Design Note ...... 32 6.6 PCMCIA (Strataflash & PC Card) Socket ...... 33 6.6.1 Texas Instruments PCI1221 PC Card (PCMCIA) Controller...... 33 6.6.1.1 Slot A: PCMCIA Socket with Texas Instruments TPS2206 PC Card Power-Interface Switch with Reset...... 33 6.6.1.2 Slot B: Intel StrataFlash Memory...... 33 6.6.1.3 Design Note...... 34 6.7 ISA PCI Expansion Cards ...... 35 6.7.1 Design Note ...... 35 6.8 Clocking ...... 36 6.8.1 Cypress Semiconductor CY2280 ...... 36 6.8.2 Cypress Semiconductor CY2309 ...... 36 6.8.3 Clocking for 430TX Chipset ...... 36 6.8.4 Clocking for 440BX Chipset ...... 37 7.0 Design Considerations...... 37

8.0 Windows CE...... 38 8.1 Windows CE for Embedded Applications...... 39 8.2 Windows CE Environment ...... 39 8.2.1 Kernel...... 39 8.2.2 Modularity...... 39 8.2.3 OEM Adaptation Layer (OAL) ...... 40 8.3 Windows CE Build Information...... 40 8.3.1 Getting Started ...... 40 8.3.2 Building a Windows CE Operating System Configuration...... 40 8.3.3 Building a New Project ...... 41 8.3.3.1 Create a New Platform Directory...... 41 8.3.3.2 Create a New Project Directory...... 41 8.3.3.3 Create a New Command Prompt Build Window ...... 42 8.3.3.4 Build the Windows CE Operating System Image for a New Project...... 42 8.3.3.5 Adding Files or Applications to the Windows CE Operating System Image ...... 42 9.0 Windows CE Device Drivers ...... 43 9.1 Dynamic Link Libraries (DLLs) ...... 43 9.2 Windows CE Device Driver Model ...... 43 9.3 Interaction with Application Software ...... 44 9.4 Incorporating Device Drivers...... 44 9.4.1 NE2000 ISA Network Interface Cards (NIC) ...... 45

iv Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

9.4.1.1 NE2000 NIC Configuration...... 45 9.4.2 ACTiSYS IR 2000B ...... 46 9.4.3 Audio ...... 46 A. Schematics...... 48 A.1 POS Terminal Baseboard Schematics...... 48

Figures

1 Stand-alone POS Terminal ...... 9 2 Back End and Front End System ...... 10 3 Pentium Processor with MMX Technology Block Diagram ...... 13 4 POS Terminal Baseboard Block Diagram ...... 15 5 Processor Assembly Block Diagram ...... 16 6 Fence Example ...... 38 7 Device Driver Architecture...... 44

Tables

1 Related Intel Documents ...... 7 2 Related Specifications and Technical Papers ...... 8 3 General Purpose Input and Output Pins ...... 21 4 Power and Ground Requirements...... 24 5 AD1819 Codec Filter Pins and Implementations...... 28 6 SYSOPT Pin Settings...... 30 7 SYSOPT Setting Options ...... 31 8 SYSOPT Settings...... 31 9 SYSOPT Setting Options ...... 32 10 Interrupt Implementations...... 34 11 Multifunction (MFUNC[6:0]) Board Connections ...... 35 12 Board Interrupt Configurations ...... 36

Revision History

Revision Date Notes

001 November 1998 First release of this document.

Application Note v

Embedded Pentium® Processor-Based POS Terminal Sample Design

1.0 Introduction

This application note provides a sample point-of-sale (POS) terminal design using the Pentium® processor and provides recommendations to enable shorter design cycles. Also described are the various peripherals commonly used in POS terminals and their interface to a Pentium processor platform.

The tested operating systems are: QNX*, DOS, BeOS*, Windows 95*, Windows 98*, Windows NT*, Windows 3.1*, and Windows CE*. Since Windows CE is a relatively new operating system, drivers have been tested and configuration information for pertinent drivers are provided.

Caution: The design has not been implemented in hardware. This document is for reference only. Customers are responsible for validating designs created using the information in this document.

1.1 Key Terms

PIIX4E refers to the Intel 82371EB PCI ISA IDE Xcelerator.

POS Terminal refers to point-of-sale terminal.

Design Features are items that allow the designer to fully use the capabilities of the embedded Pentium® processor with MMX™ technology and the Intel® 440TX AGPset, and the Pentium® II processor with the Intel® 430TX PCIset.

Design Notes are items that should be considered but may not apply to your design.

1.2 Related Documents

Table 1. Related Intel Documents

Document Order Number

Embedded Pentium® Processor Family Developer's Manual 273204 Embedded Pentium® Processor with MMX™ Technology datasheet 273214 Intel® 430TX PCIset: 82439TX System Controller (MTXC) datasheet 290559 Intel® 430TX PCIset Design Guide 290613 Intel® 82371EB PCI-to-ISA/IDE Xcelerator (PIIX4E) Specification Update 290635 Intel® 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) datasheet 290562 Embedded Pentium® Processor with MMX™ Technology Flexible Motherboard 273206 Design Guidelines

Application Note 7 Embedded Pentium® Processor-Based POS Terminal Sample Design

Table 2. Related Specifications and Technical Papers

Document URL

PCI Local Bus Specification, Revision 2.1 http://www.pcisig.com/specs.html http://developer.intel.com/design/flash/isf/wince/ Designing with Flash Memory in Windows CE Applications wince1.htm http://www.microsoft.com/windowsce/embedded/ Understanding Modularity in Microsoft Windows CE techpapers/wce20/modularity.asp http://www.microsoft.com/windowsce/embedded/ Introducing the Windows CE Embedded Toolkit techpapers/wce20/intro_etk.asp CHIPS 69000 HiQVideo Accelerator with Integrated http://www.chips.com/design/graphics/ Memory datasheet mobilegraphics/datashts/ds_69000.htm http://www.chips.com/design/graphics/ Application Notes for the HiQVideo Family mobilegraphics/applnots/

2.0 Embedded Applications Overview

2.1 Influence of PC Technology

Embedded systems come in a variety of forms and include POS terminals, industrial equipment, and telecommunication equipment.

High performance embedded processors are becoming increasingly popular in embedded applications, and PC technology is quickly filling the performance needs. Using desktop processors in the embedded space with standard operating systems allows embedded designers to get to market quickly. This discussion will address the use of embedded processors in POS terminals.

POS terminals, widely used in supermarkets, department stores, restaurants, convenience stores, and banks are PC-like platforms with peripherals added to address various needs. The main function of a POS is to process transactions including receipt generation, scanning, weighing, and inventory management. A POS can be a stand-alone system or used in conjunction with back- office systems for inventory management, training, and advertising. POS terminal users may need to look up products, re-index merchandise by product code, description or stock number, or track layaway and backorders. When discounts are offered, the POS terminal can support multiple price levels.

2.2 Embedded Pentium Processors

The embedded Pentium processor is inherited from the desktop PC, along with selected chipsets, and have been made available to the embedded systems designer. Intel offers the Pentium processor at 100, 133 and 166 MHz, the Pentium® processor with MMX™ technology at 166, 200 and 233 MHz, and the low-power embedded Pentium processor with MMX technology at 166 and 266 MHz.

Applications using the embedded Pentium processor family provide scalability to designs and offer a wide performance range and an easily alterable platform.

8 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

2.3 Operating Systems for POS Applications

In POS applications using the embedded Pentium processor, frequently used operating systems include DOS, QNX, Linux, BeOS, VxWorks, pSOS, Windows 3.1, Windows NT, Windows 95 and Windows 98. Windows 95 and Windows NT meet the increasing performance needs of many embedded applications. Windows NT, Windows 95, and Windows 98 have the advantage of having a large base of applications readily available, and features such as Desktop Management Interface (DMI), and support for interactivity.

Another operating system solution that is gaining momentum in POS applications is Windows CE, which can be used in smaller applications that require a ROM-able operating system.

3.0 Point-of-Sale Terminal

Figure 1. Stand-alone POS Terminal

A6263-01

3.1 Proprietary Operating System Versus Off-the-Shelf

A typical POS implementation can include a high performance back end system and a front end system with less functionality. In a traditional POS implementation, a company may have to develop and train people on two or more systems. At the machine level, or front end, where functionality is limited, applications may be developed based on proprietary operating systems. At the back end or supervisory level, applications are developed on open systems based on Windows 95 and Windows NT operating systems. Because these levels are built on different platforms the systems may not talk to each other, look the same, or share databases, graphics and other application files.

Alternatively, a POS implementation can have an embedded Pentium processor with MMX technology, or a Pentium II processor-based back end system with Windows NT as the operating system. This will enable POS system designers to add functions such as inventory management and disaster recovery. A front end POS terminal with an embedded Pentium processor, a Pentium processor with MMX technology, or a Pentium II processor platform running Windows 95, Windows 98, Windows NT, or Windows CE operating system can communicate with the back end

Application Note 9 Embedded Pentium® Processor-Based POS Terminal Sample Design

or supervisory level systems. This system allows the sharing of databases, graphics and applications. Refer to Figure 2. By using an off-the-shelf operating system, the added benefits are shorter design cycles and quick time-to-market. Figure 2. Back End and Front End System

PC Back Office System POS Back Office System

POS Workstations

A6262-01

3.2 POS Implementation

POS terminals are PC-like platforms adapted for retail and service environments like fast food restaurants. They may include liquid-crystal display (LCD) touch screens, which are especially important at fast food restaurants where numerous items have to be immediately selected.

Also, unlike a desktop system, a POS terminal can have an expanded number of serial and Universal Serial Bus (USB) ports. These additional serial ports are usually needed for peripherals such as bar code scanners, credit card readers, magnetic stripe readers, and pin pads.

USB keyboards, mice, and receipt printers can be used as hot plug-and-play peripherals. Some of the other peripherals common in POS terminals include cash drawers, digital scales, and pole displays.

In most cases, POS terminals must be available at all times. For this reason, hardware monitoring and the capability for fault recovery are crucial. Since a POS terminal is usually always on, the processor's power management features should be used. This will enable the terminal to be placed in a low-power mode when it is not being used.

This sample design tested peripherals and Windows CE drivers to provide support for: Infrared (IrDA), flash memory, PCMCIA cards, AC ’97-compliant audio codec, modem, LCD touch screen, and network interface cards. This sample design also discusses the components used for a PCMCIA card, touch screen controller, LCD/touch screen, additional serial ports, infrared, and AC ’97 audio codec.

10 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

3.3 Windows CE

All software for Windows CE is based on the Win32* application programming interface (API). Developers can write programs for Windows CE using familiar tools such as Visual C/C++*, or Visual Basic*. Windows CE helps in moving some embedded applications away from proprietary systems so products have a shorter development cycle, fewer costs and less user training. Since Windows CE is ROM-able, a hard disk drive may not be necessary.

Because Windows CE, Windows 95 and Windows NT are based on the same Microsoft technologies, the same development tools and utilities can be used on both systems allowing faster development and a similar look and feel.

For an application with reduced functionality, Windows CE can be used as the core OS since it requires a small footprint. A Windows CE-based device with the kernel, the file system, and the registry can fit into 512 Kbytes ROM, making it a candidate for some embedded systems.

Windows CE must be configured to meet the specific needs of the application. However, it is unique in that functionality must be added to it in the form of installable device drivers. Windows CE has numerous components allowing for different configurations. A small footprint is the key difference between Windows CE and Windows NT applications, something the developer must keep in mind.

4.0 Embedded Pentium Processors

The Pentium processor family uses bus fractioning so that the designer must take into account a 66- MHz bus while the processor clocks internally at 100, 133, 166, 200, 233, and 266 MHz. This technique allows the Pentium processor family of devices to have very good processing power internally while still being relatively easy to design into an application. Refer to the Embedded Pentium® Processor Family Developer's Manual (order number 273204).

There are two pipeline integer units (U and V) contained in the Pentium processor that gives it the ability to execute two instructions per clock cycle. The U pipeline can execute floating point and integer instructions while the V pipeline executes simple integer instructions and FXCH floating point instructions. Level one (L1) cache structure is separated into code and data, unlike the Intel486™ processor which has a unified (code + data) cache structure. The separate cache are 8 Kbytes each with two-way set associativity on the classic Pentium processors, and 16 Kbytes each with four-way set associativity on the Pentium with MMX technology-enhanced processors. The MESI protocol is also used. Implementing the Pentium processor is binary-compatible all the way back to the Intel 186 processor. Code written for the Intel386™ and Intel486 processors will execute on the Intel Pentium processors without modification. All the processors in the Pentium family are 32 bits internally and have 64 bit external data bus widths. The separate data and instruction caches on the Pentium processors also have separate Translation Look-aside Buffers (TLB) to translate linear addresses into physical addresses. The cache tag scheme employs triple porting to allow two data transfers and an inquiry cycle in only one clock. By default the code cache is write protected for safety. Again a multiporting scheme is employed on the code cache to support snooping.

Another performance enhancement is the implementation of branch prediction. To support this, it was necessary to design two prefetch buffers, the first buffer prefetches code linearly while the second buffer prefetches code according to requests from the branch target buffer (BTB). This technique makes sure that in almost all circumstances the code is prefetched and available before it is needed by the processor execution unit.

Application Note 11 Embedded Pentium® Processor-Based POS Terminal Sample Design

The external data bus is 64 bits wide. This is necessary to maximize the data transfer rate. Both burst read and burst write back are supported by the Pentium processor. Bus cycle pipelining allows two separate bus cycles to run concurrently. Memory management unit (MMU) allows 4 Kbytes to 4 Mbyte page sizes.

Figure 2 is a block diagram of the Pentium processor with MMX technology. Refer to the Embedded Pentium® Processor with MMX™ Technology datasheet (order number 273214).

12 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

Figure 3. Pentium Processor with MMX Technology Block Diagram

TLB Control DP Branch Prefetch Code Cache Logic Target Buffer Address 16 Kbytes

128

Instruction Prefetch Buffers Control Pointer Instruction Decode ROM Bus Branch Verification 64-Bit Unit and Target Address Data Bus Control Unit V-Pipeline Connection 32-Bit Page U-Pipeline Floating Point Address Unit Connection Bus Unit Address Address Generate Generate (U Pipeline) (V Pipeline) Control Control Unit Technology Register File ™ Integer Register File MMX Add ALU ALU 64-Bit (U Pipeline) (V Pipeline) 64 Divide Data Bus 32 Barrel Shifter 80 32-Bit Addr. Bus Multiply Data 80

APIC 32 32 Control Data Cache 32 32 16 Kbytes 32 TLB 32

A6180-01

The code cache, BTB and prefetch buffers are used to get the instructions into the Pentium processor execution units. Fetching can occur from either the code cache, or in the event of a cache miss, the instruction can be fetched directly from the external system DRAM. Referring to the block diagram in Figure 3, the decode unit decodes prefetched instructions for execution. The control ROM stores the code for the Pentium architecture in micro-code, this micro-code controls the sequence of operations in support of the Pentium architecture. Since the Pentium processor is based on CMOS technology, as the clock is slowed or stopped, the processor dissipates less and less power until at clock stop power dissipation is almost zero and comprises leakage currents through the silicon substrate. This clock stop capability makes the Pentium processor family ideal for energy efficient embedded applications.

With the many Pentium processors offered it should be a relatively easy task to choose a processor and chipset combination. With the fact that the chipsets support PCI v2.1, ISA, and IDE interfaces it is a safe bet that most if not all applications will be supported with this combination. The fact that the chipsets are 3.3 VCC with low-power dissipation in their own right makes integration into an application much more straightforward.

Application Note 13 Embedded Pentium® Processor-Based POS Terminal Sample Design

The Pentium processor and Pentium II processor families give the applications designer a plethora of performance and power choices. Whether the application utilizes a 100 MHz or a 233 MHz based processor, the fact that the processor is fabricated on small geometry CMOS technology gives the application designer a relatively low-power, very high performance processor in a small form factor package.

The Pentium processors also contain an Advanced Programmable Interrupt Controller or APIC. This supports I/O, is 8259A compatible and provides inter-processor interrupt support in multi- processor based systems.

4.1 Pentium Processor with MMX Technology

MMX technology is an outstanding addition to the capabilities of the Pentium processor family. Pentium processors with MMX technology are pin compatible with the classic versions of this processor. With the addition of voltage reduction technology the additional processing capabilities brought to bear with MMX technology result in thermal specifications that are within the Pentium processor Classic guidelines. The MMX enhanced processors utilizes a new Single Instruction Multiple Data or SIMD capability specifically targeted for motion video decode and communications applications. Fifty-seven new opcodes have been added to the base code set in support of MMX technology. Compatibility with the Pentium processor is assured by careful architectural design with a performance increase and no apparent penalty in power dissipation. The BTB has also been improved on the MMX enhanced processors to increase accuracy in operation. With the addition of four prefetch buffers on the MMX enhanced processors we can now simultaneously hold four separate code streams. In the MMX family of processors we also added another stage to the pipeline with other enhancements to further boost performance. For an in depth look at the Pentium processor with MMX technology see the Embedded Pentium Processor Family Developers Manual (order number 273204).

14 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

5.0 POS Terminal Design Overview

Figure 4 is the block diagram for the POS terminal design. Figure 4. POS Terminal Baseboard Block Diagram

72-pin DIMM Processor Assembly DRAM Bus

PCI PCI Connector Connector PCI Clock Bus PCMCIA Controller PCI1221

69000 HiQ AC 97 Audio USB Interface Video Accelerator ’ ES1371 PIIX4 with integrated 4-32 Mbyte IDE Interface memory Application Flash AD1819 28Fxx0J5 ISA AD725 256 K x 8 Connector Flash BIOS ISA Bus National 28F002BC Super I/O* FDC37C669 (for additional PS/2 Mouse Ports)

PS/2 Keyboard National Super I/O* FDC37B78X IEEE 1284 Parallel Port Floppy Drive

COM1 COM2 Touch- IR screen

5.1 Core Components

As shown in Figure 4, the core components of this reference design are: • Intel embedded processor assembly • 82371AB PCI-TO-ISA/IDE Xcelerator (PIIX4) — IDE connector — Universal Serial Bus host controller • Cache • Chips and Technologies 69000 HiQVideo* Accelerator with Integrated Memory • AC ’97 Audio Solution — Ensoniq AudioPCI* ES1371 — AD1819 SoundPort* Codec • SMSC FDC37B78x Ultra I/O

Application Note 15 Embedded Pentium® Processor-Based POS Terminal Sample Design

• SMSC FDC37C669* Super I/O for additional serial ports • TriTech Microelectronics TR88L803* Touch Screen Controller • Texas Instruments PCI1221* PC Card (PCMCIA) Controller Figure 5. Processor Assembly Block Diagram

Voltage ITP Regulator

L2 Cache

Low-power Front Side Bus Embedded Pentium® Processor Tag at 266 MHz RAM

66 MHz

On Baseboard

82439TX Clock Generator/ System Controller Buffer

A6233-01

5.2 Processor Assembly Components

• Low-power embedded Pentium processor at 266 MHz • 82439TX System Controller • Second Level (L2) Cache • Clock Generator/Buffer • In-Target Probe (ITP) • Voltage Regulator

6.0 Functional Description of Hardware

For more information about the POS terminal design, please refer to the schematics located in Appendix A.

16 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

6.1 Processor Assembly

The processor assembly is designed to aid in the design of the processor, the 82439TX system controller, and the level two cache interface. Integrating these three components resolves many of the high-speed design issues. This allows the POS vendor to focus on the added functions of the peripheral components described in this document.

Note: Although many design issues are resolved by the processor assembly, line lengths for PCI system and the memory bus must also be taken into consideration.

6.1.1 Processor

This reference design supports the Pentium processor with MMX technology at 266 MHz. This processor is available in a plastic ball grid array (PBGA) package and, if power consumption is a concern, can be operated at 166 MHz to save power and solve thermal issues that sometimes arise with certain designs.

This design provides scalability to a Pentium II processor module through an interposer card. For more information on using the Pentium II processor, refer to Intel’s Developer Site at: http://developer.intel.com.

6.1.2 In-Target Probe (ITP)

The processor assembly comes populated with an ITP, also called a Pentium debug port. This is a 20-pin interface that communicates directly to the processor, allowing access to the processor’s registers and signals. Using this debug utility will allow easier debugging of low-level code like BIOS and driver development.

The connectors for the ITP are provided by AMP Incorporated (part number 104068-1). Debuggers can be purchased through a variety of vendors. For information on implementing ITP in another design, refer to the Embedded Pentium® Processor Family Developer's Manual (order number 273204).

6.1.3 Voltage Regulator

The processor assembly comes equipped with a Linear Technologies voltage regulator (part number LTC 1438C6-ADJ).

6.1.4 Intel 430TX PCIset

The Inte 430TX PCIset (430TX) consists of the 82439TX System Controller (MTXC) and the 82371AB PCI ISA IDE Xcelerator (PIIX4). The 430TX supports both mobile and desktop architectures. The 430TX forms a Host-to-PCI bridge and provides second level cache control and a full function 64-bit data path to main memory.

6.1.4.1 82439TX System Controller (MTXC)

The MTXC integrates the L2 cache and main memory DRAM control functions and provides bus control to transfers between the CPU, L2 cache, main memory, and the PCI Bus. The L2 cache controller supports a write back cache policy for L2 cache sizes of 256 Kbytes and 512 Kbytes. Cacheless designs are also supported. The L2 cache memory can be implemented with pipelined burst SRAMs or DRAM. An external Tag RAM is used for the address tag and an internal TAG

Application Note 17 Embedded Pentium® Processor-Based POS Terminal Sample Design

RAM for the cache line status bits. For the MTXC DRAM controller, six rows are supported for up to 256 Mbytes of main memory. The MTXC is highly integrated by including the Data Path into the same BGA chip. Using the snoop ahead feature, the MTXC allows PCI masters to achieve full PCI bandwidth. For increased system performance, the MTXC integrates posted write and read prefetch buffers. The 430TX integrates many Power Management features that enable the system to save power when the system resources become idle.

Design Note

When using Pentium® II processor Mobile Module: EMC-2 at 266 MHz with an Intel 440BX AGPset through an interposer card, the MAB#9 signal must be pulled high to 3.3 V through a 10 KΩ resistor. This is to disable the advance graphics port (AGP) on the 440BX Chipset.

The MAB#12 signal is jumpered on the board to allow 66-MHz and 100-MHz bus speed for the 440BX Chipset.

Note: The Intel 440TX PCIset does not support AGP.

6.1.4.2 Intel 82371AB PCI ISA IDE Xcelerator (PIIX4)

The 82371AB PCI ISA IDE Xcelerator (PIIX4) is a multi-function PCI device implementing a PCI-to-ISA bridge function, a PCI IDE function, a Universal Serial Bus host/hub function, and an Enhanced Power Management function.

This device is compatible with both the Intel 440BX and 430TX chipsets, providing an easy processor upgrade path. The PIIX4 also allows complete Plug and Play compatibility. It supports two IDE connectors (Ultra DMA/33) to be used with up to four IDE devices in bus master mode.

As a PCI-to-ISA bridge, PIIX4 integrates many common I/O functions found in ISA-based PC systems-two 82C37 DMA Controllers, two 82C59 Interrupt Controllers, an 82C54 Timer/Counter, and a Real Time Clock. In addition to compatible transfers, each DMA channel supports Type F transfers. PIIX4 also contains full support for both PC/PCI and Distributed DMA protocols implementing PCI-based DMA. The Interrupt Controller has edge- or level-sensitive programmable inputs and fully supports the use of an external I/O Advanced Programmable Interrupt Controller (APIC) and Serial Interrupts. Chip select decoding is provided for BIOS, Real Time Clock, Keyboard Controller, second external microcontroller, as well as two Programmable Chip Selects. PIIX4 provides full plug-and-play compatibility. PIIX4 can be configured as a Subtractive Decode bridge or as a Positive Decode bridge. This allows the use of a subtractive decode PCI-to-PCI bridge such as the Intel 380FB PCIset which implements a PCI/ISA docking station environment.

PIIX4 supports Enhanced Power Management, including full Clock Control, Device Management for up to 14 devices, and Suspend and Resume logic with Power On Suspend, Suspend to RAM or Suspend to Disk. It fully supports Operating System Directed Power Management via the Advanced Configuration and Power Interface (ACPI) specification. PIIX4 integrates both a System Management Bus (SMBus) Host and Slave interface for serial communication with other devices. Refer to the 82371AB PCI-TO-ISA/IDE Xcelerator (PIIX4) datasheet (order number 290562) for further information.

18 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

Design Note

The Intel 82371AB is the PCI south bridge. It connects to the processor assembly via the PCI bus. The Intel 82371AB contains the PCI and ISA interrupt controller, along with various ISA legacy functions such as a DMA controller, a bus master IDE Interface, and ISA bus interface, an ISA bus clock control, a XD bus control, a USB interface and a BIOS ROM interface. • PCI: Refer to the PCI section for more information on PCI signals on the board. The PIIX4 is PCI device #7 (IDSEL connected to pin AD18 through a 220 Ω resistor per PCI Specification, v2.1). • ISA: Refer to the ISA section for more information on ISA signals on the board. The PIIX4's interrupt control unit provides interrupt handling to all ISA devices on the board including SMSC FDC37B78x Ultra I/O (floppy disk, serial ports, parallel port control), and SMSC 37C669 Super I/O (2 serial ports).

6.1.4.3 IDE / Floppy

The PIIX4 supports two IDE connectors for up to four IDE devices providing an interface for IDE hard disks and CDROMs. Up to four IDE devices can be supported in bus master mode. The PIIX4 contains support for “Ultra DMA/33” synchronous DMA compatible devices. This design uses one IDE connector with support for up to two devices.

6.1.4.4 USB Host Controller

The PIIX4 contains a Universal Serial Bus (USB) Host Controller that is Universal Host Controller Interface (UHCI) compatible. The Host Controller's root hub has two programmable USB ports. • X-Bus Signals XOE# and XDIR# are connected as control signals to the X-Bus transceiver, with XOE# connected to G# and XDIR# connected to DIR of the transceiver.The internal RTC of the PIIX4 is used, therefore RTCALE and RTCCS# become general purpose outputs (GPO25 and GPO24 respectively) by programming the General Configuration Register (GENCFG) in Function 0, Offset B0h–B3h. • Power Management Signals SUSA# of the PIIX4 is connected to the PWR_DWN# signal of the clock generator. SUSA# is asserted during power management suspend states, POS, STR, and STD suspend states. PWR_DWN# is an active low control input to the clock generator to power down the device. CPU_STP# and PCI_STP# of the PIIX4 are asserted low to disable the processor and PCI clock outputs respectively. They are connected to CPU_STOP# and PCI_STOP# of the clock generator. SUSC# of the PIIX4 is first inverted and then connected directly to PS_ON# of the ATX power supply. Therefore when SUSC# is asserted, during STD suspend state, all power rails including 3.3 V, 5 V, –5 V, 12 V, and –12 V power rails, are turned off. This is used for the remote-off function. The inverter described above must be connected to a Standby Power rail. ZZ is connected to the ZZ pin on the L2 cache on the processor assembly for low-power mode. RSMRST# connection requires a minimum time delay of one millisecond from the rising edge of the standby power supply voltage. A simple RC circuit is used to provide this time delay (t = RC, in the design this is ~2.7 KΩ * 10 µF ~ 2.7 ms) and a Schmitt trigger circuit is used to drive the signal on the board. • USB Interface

Application Note 19 Embedded Pentium® Processor-Based POS Terminal Sample Design

The following are general layout guidelines for the USB interface: — Any unused USB ports should be terminated with 15 Kbyte pull-down resistors on both P+/P- data lines — 27 Ω series resistors should be placed as close as possible to the PIIX4 (<1 inch). These series resistors are for source termination of the reflected signal. — 47 pF caps must be placed as close to the PIIX4 as possible and on the PIIX4 side of the series resistors on the USB data lines (P0+, P1+). These caps are there for signal quality (rise/fall time) and to help minimize electromagnetic interference (EMI). — 15 KΩ +5% pull-down resistors should be placed on the USB side of the series resistors on the USB data lines (P0+ and P1+), and are REQUIRED for signal termination by USB specification. The length of stub should be as short as possible. — The trace impedance for the P0+, P1+ signals should be 45 Ω (to referenced ground) for each USB signal P+ or P-. The impedance is 90 Ω between the differential signal pairs P+ and P- to match the 90 Ω USB twisted pair cable impedance. Note the twisted pair characteristic impedance of 90 Ω is the series impedance of both wires, resulting in an individual wire presenting a 45 Ω impedance. The trace impedance can be controlled by carefully selecting the trace width, trace distance from power or ground planes, and physical proximity of nearby traces. — USB data lines must be routed as 'critical signals' (i.e., hand routing preferred). The P+/P- signal pair must be routed together and not parallel with other signal traces to minimize crosstalk. Doubling the space from the P+/P= signal pair to adjacent signal traces will help to prevent crosstalk. Do not worry about crosstalk between the two P+/P- signal traces. The P+/P- signal traces must also be the same length. This will minimize the effect of common mode current on EMI. (Common mode current is caused by differential signals whose currents are not perfectly matched.) The following are general layout guidelines for the USB power and ground lines: — Ferrite beads are placed on each power and ground line to minimize EMI. They should be placed as close as possible to the USB connector. — Voltage divider circuits are used to drive the status of the SUB power line to the OC[1:0]# inputs. OC[1:0]# signals are 3.3 V inputs and have a leakage current of maximum + 1 µA. — Fuses are used on each power line for overcurrent protection. Refer to the Intel® 430TX PCIset Design Guide for sample layout topologies. • IDE Interface Two standard IDE interfaces are provided by the PIIX4. One IDE interface (primary) is included in this design. The primary IDE controller is connected as described in the TX Chipset design Guide. The secondary IDE controller is not used on the board. Hence all inputs to the secondary IDE controller are pulled to the inactive state with a 10 KΩ resistor. All outputs and bidirectional pins are left floating. A Hard Drive Active LED circuit is connected to the HD_ACT# signal of the primary IDE connector. If the secondary IDE controller is to be used, an OR-gate between the HD_ACT1# and the HD_ACT2# should be used to drive the LED circuit. Proper operation of the IDE circuit depends on the total length of the IDE bus. The total signal length of the IDE drivers to the end of the IDE cables should not exceed 18". Therefore, the PIIX4 should be located as close as possible to the IDE connectors to allow the IDE cable to be as long as possible. When the distance between the PIIX4 and the ATA connectors exceeds four inches the series termination resistors should be placed within one inch of the PIIX4. Designs that place the PIIX4 within four inches of the ATA connectors can place the series

20 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

resistors anywhere along the trace. The capacitance of each pin of the IDE connector on the host should be below 25 pF when the cables are disconnected from the host. • Clocks Refer to the Intel® 430TX PCIset Design Guide for layout topologies. • General Purpose Input and Output Pins 15 general purpose inputs and 15 general purpose outputs are provided on the board. A table of the pins and sharing information is below:

Table 3. General Purpose Input and Output Pins

GPO Pin Muxed With GPI Pin Muxed With

GPO0 1 None GPI1 2 None GPO8 3 None GPI2 4 REQA# GPO9 5 GNTA# GPI3 6 REQB# GPO10 7 GNTB# GPI4 8 REQC# GPO11 9 GNTC# GPI5 10 APICREQ# GPO12 11 APICACK# GPI7 12 None GPO15 13 APICCS# GPI13 14 None GPO21 15 SUS_STAT2# GPI14 16 None GPO24 17 RTCCS# GPI15 18 None GPO25 19 RTCALE GPI16 20 None GPO26 21 KBCCS# GPI17 22 None GPO27 23 None GPI18 24 None GPO28 25 None GPI19 26 None GPO29 27 IRQ9OUT# GPI20 28 None GPO30 29 None GPI21 30 None NOTE: 1. All GPIO pins in the sample design are always available. Pins that are multiplexed with other signals are not used for their alternate function and are therefore always available for GPIO.

6.1.5 Cache

The level two (L2) cache concept developed from the need to have data and instructions available to the processor locally. With the Intel386 processor running at 25 MHz, there is enough time to allow for a code fetch and data to arrive from system DRAM for the processor to use before a stall occurs. With the advent of faster processors, the need for L2 cache has become even greater. Now the processor is fast enough that without cache, the processor core can stall while waiting for code and data to arrive from the system DRAM. While the processor is stalled waiting for instructions, it cannot perform other tasks.

Intel's dual 8-Kbyte (non-MMX-enhanced) with 2-way set associativity or dual 16-Kbyte (MMX- enhanced) with 4-way set associativity level one (L1) caches on the Pentium processor(s), with the addition of a 512-Kbyte L2 cache system, greatly lessens bus utilization and increases the overall throughput of the system. The baseboard has been designed with 512 Kbyte of fast static RAM cache available. The devices are (part number: KM732V696T-13 manufactured by Samsung Electronic Company) supplied in a 100-pin Thin Quad Flatpack-leaded (TQFP) surface package

Application Note 21 Embedded Pentium® Processor-Based POS Terminal Sample Design

mount. The devices are Synchronous Pipelined Burst SRAM architecture. The I/O is 2.5 V while

VCC is 3.3 VDC. The cycle time is 7.8 ns and the array is 64 K x 32 K. This architecture allows easy interface to the 440TX chipset without the need for level shifters.

6.2 Video

The Chips and Technologies 69000 HiQVideo Accelerator with integrated memory is used in this design. The 69000 solution integrates 2 Mbyte SDRAM for use in frame buffering. This memory supports up to an 83 MHz clock, allowing a high memory bandwidth.

This part supports a variety of outputs, including monochrome, color Single Panel, Single-Drive (SS), Dual-Panel, Dual-Drive (DD), and standard / high resolution, passive STN and active matrix TFT/MIM LCD, as well as EL panels and can be customized.

6.2.1 Chips and Technologies 69000 HiQVideo Accelerator with Integrated Memory

The CHIPS 69000 is a portable graphics accelerator that integrates high performance memory technology for the graphics frame buffer. Based on the HiQVideo graphics accelerator core, the 69000 combines a flat panel controller capabilities with low-power, high performance integrated memory.

6.2.2 High Performance Integrated Memory

The 69000 incorporates 2Mbyte of proprietary integrated SDRAM for the graphics/video frame buffer. The integrated SDRAM memory can support up to 83 MHz operation, increasing the available memory bandwidth for the graphics subsystem.

6.2.3 HiQColor Technology

The 69000 integrates Chips and Technologies HiQColor technology based on the CHIPS proprietary Temporal Modulated Energy Distribution (TMED) algorithm, HiQColor technology is a process that allows the display of 16.7 million true colors of STN panels without using Frame Rate Control (FRC) or dithering. TMED also reduces the need for the panel tuning associated with current FRC-based algorithms. The TMED algorithm eliminates all of the flaws (such as shimmer, Mach banding, and other motion artifacts) normally associated with dithering and FRC.

6.2.4 Versatile Panel Support

The HiQVideo family supports a wide variety of monochrome and color single-panel, single-drive (SS) and dual-panel, dual drive (DD), standard and high-resolution, passive STN, and active matrix TFT/MIM LCD, and EL panels. With HiQColor technology, up to 256 gray scales are supported on passive STN LCDs. Up to 16.7 million different colors can be displayed on passive STN LCDs and on 24-bit active matrix LCDs.

The 69000 offers a variety of programmable features to optimize display quality. Vertical centering and stretching are provided for handling modes with less than 480 lines on 480-line panels. Horizontal and vertical stretching capabilities are also available for both text and graphics modes for optimal display of VGA text and graphics modes on 800x600, 1024x768 and 1280x1024 panels.

22 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

6.2.5 Television NTSC/PAL Flicker Free Output

The 69000 uses a flicker reduction process which makes text of all fonts and sizes readable by reducing the flicker and jumping lines on the display. The 69000 uses a line buffer and digital filters to average adjacent vertical lines for odd/even display. The chip also uses both horizontal and vertical interpolation to make both graphics and text appear smooth on a standard television. This process reduces the effect of flicker on NTSC displays.

6.2.5.1 Design Note

The Chips and Technologies 69000 HiQVideo Accelerator provides VGA and LCD output on the board. Using the Analog Devices AD725 RGB to NTSC/Pal Encoder, the board also provides TV- out capability.

The 69000 is PCI device number 2 (IDSEL connected to AD13 through a 220 Ω resistor) and uses PCI interrupt INTA#.

On the board a RGB monitor is always populated. Therefore when a TV Encoder like the AD725 is added, the RGB signals must be buffered. This is accomplished by a AD8073 video amplifier with high input impedances on each color signal. They are configured for a gain of two, which is normalized by the divide by two termination scheme used for the RGB monitor. However, since the RGB signals shift to ground during horizontal sync period, the AD8073 require –5 V supply.

The board provides an interface to LCD screens with up to 36-bit color. 8-bit monochrome to 24- bit color LCD panels are supported by Panel Connector 1. 36-bit LCD panels are supported using both Panel Connector 1 and Panel Connector 2.

All Panel interface signals from the graphics controller are 3.3 V. Level-shifting buffers should be added between the outputs from the graphics controller and the inputs of a 5.0 V flat panel if the 69000's VOL and VOH do not meet the requirements for the panel's VIL and VIH. The signals involved include pins P0-P35, SHFCLK, LP, FLM and M. The included schematics do NOT include these level shifters. The design assumes 3.3 V panels.

To ensure full compatibility with older CRT displays, 3.3 V to 5.0 V level-shifting buffers are added between the 69000's HSYNC and VSYNC outputs and the display's HSYNC and VSYNC inputs.

Power and ground signals to the 69000 are as specified in the CHIPS 69000 HiQVideo Accelerator with Integrated Memory datasheet. Refer to Table 2 for the URL. Table 4 lists all power and ground requirements, and their implementation on the board.

Application Note 23 Embedded Pentium® Processor-Based POS Terminal Sample Design

Table 4. Power and Ground Requirements

Pin Name Description Requirement Implementation

DACVCC should be isolated Isolated from all other VCCs Analog power for the from all other VCCs and DACVCC through ferrite beads with internal RAMDAC should not be greater than filtering caps CORVCC DACGND should be Analog ground for the common with digital ground DACGND Tied to analog GND internal RAMDAC but must be tightly coupled to DACVCC Analog power for the MCKVCC must be at the Coupled to MCKGND MCKVCC internal memory clock same voltage level as through RC network synthesizer (MCLK) CORVCC Analog ground for the MCKVCC/MCKGND pair Tied to digital GND through MCKGND internal memory clock must be INDIVIDUALLY ferrite bead synthesizer (MCLK) decoupled Analog power pins for the DCKVCC must be at the Coupled to DCKGND DCKVCC internal dot clock same voltage level as through RC network synthesizer (DCLK) CORVCC Analog ground pins for the DCKVCC/DCKGND pair Tied to digital GND through DCKGND internal dot clock must be INDIVIDUALLY ferrite bead synthesizer (DCLK) decoupled GND Digital ground Tied to digital GND Digital power for the CORVCC graphics controller internal logic (a.k.a. the “core” VCC) Tied to 3.3 V plane with MEMGND Embedded memory ground filtering caps RGND Internal reference GND Should be tied to GND Tied to digital GND TIed to 3.3 V plane with IOVCC I/O power filtering caps Power for embedded Tied to 3.3 V plane with MEMVCC memory filtering caps

Proper layout of the 69000 is important to getting optimal performance.

The power plane that is attached to the core power supply should be as wide as practical for high current carrying capacity, and low inductance.

Decoupling capacitors should ideally be placed as close as possible to the 69000. This means that the best decoupling will occur if the capacitors are placed directly underneath the component. If a single sided board is required and capacitors cannot be placed underneath the component then decoupling is recommended at the corners of the 69000. Placing the capacitors at the corners minimizes decoupling trace lengths from the BGA package, reducing EMI.

Avoid placing audio components near a switching power supply.

Digital signals should be isolated from analog circuitry as much as possible to keep digital and analog currents from crossing. Ground currents from digital signals are noisy and should be isolated from the audio signals. Do not run dynamic digital signals such as clock, address or data lines in or close to the analog area.

24 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

All analog circuitry should be placed as close to I/O connectors as possible and should be isolated to as small an area as possible. Analog components and circuitry should reside over a separate ground and power plane with a gap between digital and analog planes made as wide as possible (25–50 mils is the acceptable minimum, 100 mils is ideal). The two plane pairs should be separated by a 2–3 mm gap. This means using at least a four layer board with ground and power planes forming an internal high capacitive, sandwich. This creates an effective series resistance (ESR) and effective series inductance (ESL) bypass capacitor.

Analog signals should reside over, or be referenced to, the analog ground plane as much as possible. Vias should be kept to a minimum. All analog signal traces should be as wide as possible for lower impedance.

Internal power and ground planes should be solid with no traces routed on them. The analog power plane containing the voltage regulator should coincide with the analog ground plane as much as possible. Analog ground shielding should be used on the external layers, especially near a low level input (i.e., microphone).

The analog and digital planes should be connected at one point only through a 0 Ω resistor or a ferrite bead. This maintains the proper reference potential for each ground plane. On the board this should be placed as close as possible to the 69000. This allows analog and digital ground return currents from the 69000 to flow through the analog and digital ground plane respectively.

There should not be any digital or analog traces crossing the gap between the analog and digital planes.

IC leads should have pads and vias that go directly to the appropriate plane for power and ground.

A separate small digital partition should be used for the crystal oscillator. This partition serves to keep noise from coupling onto the analog signals.

For information on how to interface to LCD Panels for the 65550, 65554, 65555 and 69000 HiQVideo accelorator series, refer to their respective application notes. See Table 2 for the URL.

A jumper on VEESAFE has been added to allow VEESAFE to be driven by a scaled version of VDDSAFE (scaled by a 1 KΩ potentiometer) for newer panels that have a low voltage requirement for VEESAFE. It is important that the potentiometer be fed from VDDSAFE rather than some other voltage source so that the resulting VEESAFE will meet the same power sequencing requirements as the panel. The sequencing of VEESAFE will be the same for VDDSAFE. The current requirement for a low-voltage VEESAFE is intended to be 1 mA maximum. • Analog Devices AD725 RGB to NTSC/PAL Encoder with Luma Trap Port — The Analog Devices AD725 is a RGB to NTSC/PAL Encoder which may be populated on the board to add TV OUT capability. — RIN, BIN, and GIN are analog inputs that should be terminated by 75 Ω resistors to ground in close proximity to the IC. — The AD725 is a mixed signal part. It has separate pins for analog and digital +5 V and ground power supplies. Both the analog and digital ground pins should be tied to the ground plane by a short, low inductance path. Each power pin should have a bypass capacitor of 0.1 µF and a larger tantalum capacitor of 10 µF. — The outputs have a DC bias that must be AC-coupled for proper operation. This is done on the board by placing a 220 µF tantalum capacitor and 75 Ω resistor in a series on each output.

Application Note 25 Embedded Pentium® Processor-Based POS Terminal Sample Design

— On the board, a RGB monitor is always populated. Therefore, when a TV encoder like the AD725 is added, the RGB signals must be buffered. This is accomplished by an AD8073 video amplifier with high input impedances on each RGB signal. The signals are configured for a gain of two, which is normalized by the divide by two termination scheme used for the RGB monitor. However, since the RGB signals go to ground during horizontal synchronization, the AD8073 requires a –5 V supply. — A jumper is placed on pin 5 of the AD725. Placing a jumper on pins 1–2 enables the AD725. A jumper on pins 2–3 disables the AD725. — A jumper is also placed on pins 1 and 12. Placing a jumper on pins 1–2 enables NTSC, placing a jumper on 2–3 enables PAL. It is important that the oscillator circuit, placed on pin 3 of the AD725, also be changed when switching from NTSC to PAL (a 14.318180 MHz crystal is already placed for NTSC) the crystal must be changed from 14.318180 MHz to 17.734475 MHz for PAL. — Proper layout of the AD725 circuitry is required for optimal performance. — All passive components should be placed as close as possible to the AD725. — A “fence” should be formed around the analog signals. No digital signals should be routed under or above the analog power and ground planes. — The filter circuits for the video output signals (CMPS, LUMA and CRMA) should be placed as close as possible to the connector. Long lengths of closely-spaced parallel analog signals should be avoided. Wherever analog signals run in parallel, separated by less than 15 mils for longer than 250 mils, run a ground line between the video input traces of approximately 12 mils in width. — The three analog inputs (RIN, GIN, BIN) should be terminated by a 75 Ω to ground close to the respective pins. — Layout guidelines should be followed as in the HiQVideo 69000.

6.3 Audio

The audio solution on the board is AC ’97 Component Specification 1.0 compliant. It features an Ensoniq AudioPCI 97 ES1371 Digital Controller, and an Analog Devices AC ’97 SoundPort Codec AD1819 connected through the 5-wire AC ’97 link.

The AC ’97 audio architecture provides legacy support as well as a migration path to digital audio. Sound Blaster emulation is provided, as well as MIDI data interface. The AD1819 provides an analog front end for high performance audio, modem, and DSP applications.

6.3.1 AC ’97 Audio

AC ’97 defines a high quality two-chip audio architecture (AC ’97 digital controller and AC ’97 codec) advancing the migration to digital audio, while maintaining support for analog audio sources and analog interconnect for backwards compatibility. The two-chip audio solution comprising a digital audio controller, plus a high quality analog component that includes Digital- to-Analog Converters (DAC), Analog-to-Digital Converters (ADC) mixer and I/O. The architecture supports a wide range of high quality audio solutions, from a 2-channel mix of digital and analog audio, to multi-channel digital audio. The system is capable of achieving greater than 90 dB SNR performance.

26 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

6.3.2 Ensoniq AudioPCI 97 ES1371 Digital Controller

The Ensoniq AudioPCI 97 ES1371 Digital Controller supports simultaneous stereo audio, and host-based wave table music synthesis through the integration of an AC ’97 2.0-compatible link and a PCI interface, in addition to audio legacy compatibility. The controller includes digital AC- link converters, WDM digital mixing acceleration, and variable sample rate conversion.

The PCI interface handles up to two digital audio streams, modem and handset streams. The digital audio streams are sample-rate converted and mixed to a common rate before being transmitted over the AC ’97 2.2-compatible link to an AC ’97 codec.

The sample rates are completely independent from the incoming and outgoing streams. The controller includes a variable sample rate converter that allows instantaneous support for sample rates ranging from 7 KHz to 48 KHz, with a resolution of 1 Hz.

SoundBlaster emulation is provided through the combination of hardware digital mixing, software SoundBlaster trapping, and host generated wave table music synthesis.

The primary interface for communicating MIDI data to and from the host is the hardware MPU- 401 interface. The MPU-401 interface includes a built-in 64 byte FIFO for communication to the host bus.

6.3.2.1 Design Note

The ES1371 Digital Controller is PCI device number 16 (IDSEL connector to AD27 through a 220-Ω resistor). It is also PCI bus master #2 (connected to PCI bus master Pins REQ2# and GNT3#) and uses PCI interrupt INTB# on the board.

Note: The MIDI/JOYSTICK interface is not implemented on the board.

6.3.3 Analog Devices AC ’97 AD1819 SoundPort Codec

The AD1819 SoundPort codec is designed to meet all requirements of the Audio Codec, Component Specification, v1.03. The AD1819 supports multiple codec configurations (up to three per AC link), a DSP serial mode, variable sample rates, modem sample rates and filtering, and built-in Phat Stereo 3D enhancement.

The AD1819 is an analog front end for high performance audio, modem, or DSP applications.

The main architectural features of the AD1819 are the high quality analog mixer section, two channels of sigma-delta ADC conversion, two channels of sigma-delta DAC conversion and Data Direct Scrambling (D2s) rate generators. The AD1819's left channel ADC and DAC are compatible for modem applications supporting irrational sample rates and modem filtering requirements.

6.3.3.1 Design Note

The AD1819 codec is connected to the ES1371 through the 5-wire AC ’97 link. RESET# of the 5- wire AC ’97 link is connected to PCI RESET (RST#) on the board.

The board implements microphone, video, line, and CDROM inputs as well as line, mono and line level outputs. The AD1819 provides interfaces for PC beep, phone input, and auxiliary inputs that are not implemented on the board.

Application Note 27 Embedded Pentium® Processor-Based POS Terminal Sample Design

There are various filter pins on the AD1819. These pins are listed below with their implementation on the board.

Table 5. AD1819 Codec Filter Pins and Implementations

Pin Name TQFP I/O Description Board Implementation

Antialiasing Filter Capacitor - AFILT1 29 O 270 pF ceramic capacitor-to-analog ground ADC Right Channel Antialiasing Filter Capacitor - AFILT2 30 O 270 pF ceramic capacitor-to-analog ground ADC Left Channel AC-Coupling Filter Capacitor - FILT_R 31 O 1 µF tantalum capacitor-to-analog ground ADC Right Channel AC-Coupling Filter Capacitor - FILT_L 32 O 1 µF tantalum capacitor-to-analog ground ADC Left Channel 3D Phat Stereo Enhancement - RX3D 33 O 47 nF capacitor-to-analog ground Resistor CX3D 34 I 3d Phat Stereo Enhancement - 100 nF capacitor connected to RX3D

Note: Proper board layout of the AC ’97 Audio components is important to getting optimal performance. Avoid placing the audio components near a switching power supply.

To keep digital and analog signal currents from crossing, digital signals should be isolated from analog circuitry as much as possible. Ground currents from digital signals are noisy and should be isolated from the audio signals. Do not run dynamic digital signals such as clock, address or data lines in or around the analog area.

All analog circuitry should be placed as close to I/O connectors as possible and should be isolated to as small an area as possible. Analog components and circuitry should reside over a separate ground and power plane with a gap made as wide as possible (25–50 mil is decent and 100 mil is ideal) between digital and analog planes. The two plane pairs should be separated by a 2–3 mm gap. This means using at least a four-layer board with ground and power planes forming an internal high capacitive sandwich. This gives an effective low ESR and ESL bypass capacitor.

Analog signals should reside over, or be referenced to, the analog ground plane as much as possible. Vias should be kept to a minimum. All analog signal traces, especially VREFOUT and analog power lines on the AD1819, should be as wide as possible for lower impedance connections.

The analog and digital planes should be connected at one point only, through a 0-Ω resistor or a ferrite bead. This maintains the proper reference potential for each ground plane. On the board, this should be placed as close as possible to the AD1819 and its voltage regulator. This allows the AD1819’s analog and digital ground return currents to flow through the analog and digital ground plane respectively.

Note: There should not be any digital or analog traces crossing the gap between the analog and digital planes.

28 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

IC leads should have pads and vias that go directly to the appropriate plane for power and ground. A separate small digital partition should be used for the crystal oscillator. This partition serves to keep noise from coupling onto the analog signals.

6.4 SMSC FDC37B78x Ultra I/O

The Standard Microsystems Corporation (SMSC) FDC37B78x Ultra I/O provides keyboard, mouse, and floppy disk port and control on the board. It also provides two serial ports: COM1 is shared with the touch screen interface, and COM2 is shared with the infrared interface. The ultra I/ O resides on the ISA bus and provides twelve IRQ options with full 16-bit address decode.

The FDC37B78x Ultra I/O provides support for the ISA Plug-and-Play Standard, v1.0a. Through internal configuration registers, each of the FDC37B78x 's logical device's I/O address, DMA channel and IRQ channel may be programmed. There are 480 I/O address location options, 12 IRQ options or serial IRQ options, and four DMA channel options for each logical device.

6.4.1 Floppy Disk Controller (FDC)

The FDC provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation, and Data Rate Selection logic for an IBM PC XT/AT-compatible FDC. The true CMOS 765B core is 100% compatible with the IBM PC XT/AT in addition to providing data overflow and underflow protection. The FDC is also compatible with the 82077AA using SMSC's proprietary floppy disk controller core.

6.4.2 Serial Port Controller

The FDC37B78x incorporates two full function UARTs. They are compatible to the NS16450, the 16450 ACE registers, and the NS16C550A. The UARTs perform the necessary serial-to-parallel conversion on received characters and the parallel-to-serial conversion on transmitted characters. The data rates are programmable from 460.8 Kbaud to 50 baud. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. Each UART contains a programmable baud rate generator that is capable of dividing the input clock or crystal by any number in the range of 1 to 65535. The second UART supports IrDA 1.0, HP-SIR, ASK-IR, and Consumer IR infrared modes of operation.

6.4.3 Infrared Interface

Infrared support is included in the SMSC FDC37B78x Ultra I/O chip and includes Consumer IR and IrDA, v1.0 support. The interface provides a two-way wireless communications port. There are several IR implementations for the second UART in this chip (logical device 5), IrDA, Consumer Remote Control, and Amplitude Shift Keyed IR. The IR transmission can use the standard UART2 TXD2 and RXD2 pins, or optional IRTX and IRRX pins.

Serial communication baud rates up to 115.2 Kbps are provided for through IrDA, v1.0. The Amplitude Shift Keyed IR allows an asynchronous baud rate of up to 19.2 Kbaud.

6.4.3.1 Design Note

COM1 is shared with the touch screen. Three 3-pin jumpers are provided to switch from COM1 to touch screen and vice versa. Placing a jumper on pins 1–2 on all three jumpers enables the touch screen. Placing a jumper on pins 2–3 enables COM1.

Application Note 29 Embedded Pentium® Processor-Based POS Terminal Sample Design

COM2 is shared with the Infrared interface. IRTX2 and IRRX2 of the ultra I/O directly connect TXD and RXD of the TEMIC TFDU4100 Infrared Transceiver respectively. The functionality of this COM port must be switched in the BIOS. The board uses the FDC37B78x's alternate IRTX2 and IRRX2 pins, allowing BIOS to switch from COM2 to the Infrared interface.

6.4.4 Parallel Port Controller

The parallel port controller is compatible with the IBM PC XT/AT. It supports the optional PS/2- type bi-directional parallel port (SPP) mode, the Enhanced Parallel Port (EPP) mode, and the Extended Capabilities Port (ECP) mode.

6.4.5 Keyboard and Mouse

The universal keyboard controller uses an 8042 microcontroller processor core.

6.4.5.1 Design Note for Ultra I/O

Each power pin must be individually decoupled with a 0.1 µF capacitor. Since the real time clock on the ultra I/O is not used, VBAT must be tied to ground. If not grounded, this pin may float and confuse the internal circuitry that is trying to detect whether power is valid.

The ultra I/O provides a BIOS interface. This is not implemented on the board, therefore ROMCS# must be pulled high to disable the ROM buffers and avoid interference with the boot ROM.

The SYSOPT pin is latched on the falling edge of RESET_DRV or on VCC Power On Reset to determine the configuration register's base address. The SYSOPT pin is used to select the CONFIG PORT's I/O address at power-up. Once powered up, the configuration power base address can be changed through configuration registers. See Table 6 for SYSOPT settings. Table 6. SYSOPT Pin Settings

SYSOPT = 1 SYSOPT = 0 Port Name (10 KΩ pull-up resistor) (1 KΩ pull-down resistor) Board Setting

CONFIG PORT 0x03F0h 0x0370h INDEX PORT 0x03F0h 0x0370h DATA PORT INDEX PORT + 1 INDEX PORT + 1

Note: If using TTL RS232 drivers, use a 1 KΩ pull-down resistor. If using CMOS RS232 drivers, use 10 KΩ pull-down resistor. The board uses TTL drivers, therefore SYSOPT should be pulled down with a 10 KΩ pull-up resistor. Therefore, the CONFIG PORT and INDEX PORT for the FDC37B78x is located at 0x0370h after Reset.

The setting on SYSOPT must be different then SYSOPT on the SMSC FDC37C669 Super I/O in order for the two chips to configure at different addresses. On the board, FDC37C669 SYSOPT is pulled low with a 1-KΩ resistor. Therefore the FDC37C669 is located at 0x0370h in memory after reset. The two options are given in Table 7.

30 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

Table 7. SYSOPT Setting Options

Option FDC37B78x SYSOPT Pin FDC37C669 SYSOPT Pin

SYSOPT = 1 SYSOPT = 0 A (pulled HIGH with 10 KΩ resistor) (pulled LOW with 1 KΩ resistor) SYSOPT = 0 SYSOPT = 1 B (pulled LOW with 1 KΩ resistor) (pulled HIGH with 10 KΩ resistor)

6.4.6 Additional Serial Ports with SMSC 37C669 Super I/O

An additional Super I/O, SMSC 37C669 is used on the board to add two extra serial ports COM3 and COM4. The parallel, IDE, and floppy interfaces are not used on this design. This configuration was chosen over separate 16550's because of cost and board space considerations.

Note: Each power pin must be individually decoupled with 0.1 µF capacitors.

All inputs to unused devices (i.e., parallel, IDE and floppy) are pulled to their inactive state. The value of the pull-up/pull-down resistor is chosen to keep the inputs within 0.5 V of the supply rails in order to minimize current consumption. Each pin has 10 µA of current leakage.

The FDC37C669 provides 11 decoded address lines, AEN, plus one chip-select input. Since the FDC37C669 can only decode the lower 11 address bits and AEN, an OR-gate is used to decode addresses A11–A15. The output of the OR-gate is low when A11–A15 are low, therefore asserting the FDC37C669 chip select. This chip select, AEN, and 11-bit address decode provides the full 16- bit ISA decode necessary.

6.4.6.1 Design Note

At the trailing edge of a hardware reset, the SYSOPT input is latched to determine the configuration base address. Refer to Table 8 for SYSOPT settings.

Table 8. SYSOPT Settings

SYSOPT = 0 SYSOPT = 1 Port Name (1 KΩ pull-down resistor) (10 KΩ pull-up resistor)

INDEX Base I/O Address 0x03F0 0x0370

Note: If you are using TTL RS232 drivers, use a 1 KΩ pull-down resistor. If using CMOS RS232 drivers, use a 10 KΩ pull-down resistor. The board uses TTL drivers, therefore SYSOPT should be pulled

Application Note 31 Embedded Pentium® Processor-Based POS Terminal Sample Design

down with a 1 KΩ resistor or pulled up with a 10 KΩ resistor. SYSOPT is pulled low on the board, therefore the FD37C669 is located at 0x03F0h in memory after Reset.

The setting on SYSOPT must be different then SYSOPT on the FDC37B78x Ultra I/O in order for the two chips to configure at different addresses. The two options are listed in Table 9.

Table 9. SYSOPT Setting Options

Option FDC37B78x SYSOPT Pin FDC37C669 SYSOPT Pin

SYSOPT = 1 SYSOPT = 0 A (pulled HIGH with 10 KΩ resistor) (pulled LOW with 1 KΩ resistor) SYSOPT = 0 SYSOPT = 1 B (pulled LOW with 1 KΩ resistor) (pulled HIGH with 10 KΩ resistor) NOTE: 1. On the board, SYSOPT on the FDC37B78x is pulled HIGH and SYSOPT on the FDC37C669 is pulled LOW.

6.5 Tritech Microelectronics TR88L803 Touch Screen Controller

TriTech Microelectronics TR88L03 Touch Screen Controller is used to implement a touch screen solution. This is a fully integrated pen input processor with two multiplexed A/D input channels. The chip uses a serial interface, and there is no user configuration required.

The low-power TR88L803 contains all the circuitry required to interface the low cost 4- and 5-wire resistive digitizers to applications and provide pen-input capability. The TR88L803 uses 10-bit ADCs to resolve 1024 levels. When clocked at 4 MHz, the TR88L803 is designed to simplify pen interfacing by integrating all pen-input tasks required to present X, Y position data to the main application at 200 coordinate pairs per second. The TR88L803 provides standard asynchronous serial output or synchronous serial output. The TR88L803, with enhanced noise filtering, is ideally suited for operation in electrically noisy environments.

6.5.1 Design Note

The touch screen controller shares resources with COM1 on the board. To use either COM1 or the touch screen, the board must be jumpered correctly.

The TR88L803 is configured to use power from the serial port COM1. The Touch Screen circuit draws less than 10 mA from the serial port during Power On conditions. During IDLE/SLEEP mode, it draws less than 5 mA. A 3.3 V voltage regulator across the serial port Data Terminal Ready (DTR) and Ground (GND) pins generate a stable power source (digital VDD and analog VDD) from the 5 V to 12 V source found on DTR.

The TR88L803's serial data output is connected to the serial port TX pin through two general- purpose transistors. The transistors are properly biased to provide the necessary signal level swing for the TX pin. The negative signal level is derived with the RX pin of the serial port. RX is not used since data is unidirectional for the touch screen controller.

The touch screen controller provides two independent ADC input channels under the ADC multiplex mode. Control pin (MUX_SEL) multiplexes the internal ADC between serving the digitizer inputs (X+, X-, Y+, Y-) and the two independent ADC input channels. These channels are not implemented on the board, therefore ADC_1 and ADC_2 are tied to the analog ground through a 10-KΩ resistor and MUX_SEL is tied to ground.

32 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

The touch screen controller provides a 4-wire interface for the Dynapro touch screen.

Mixed signal layout guidelines should be followed as discussed in the LCD/Video and Audio sections. • LCD w/ Integrated Touch Screen: The touch screen controller provides a four-wire interface for the Dynapro touch screen. The LCD interface consists of two connectors: Flat Panel Connector 1 and Flat Panel Connector 2. The Flat Panel Connector 1 provides an interface to LCD screens with up to 24-bit color. For 36-bit color, both Flat Panel Connector 1 and Flat Panel Connector 2 must be used.

6.6 PCMCIA (Strataflash & PC Card) Socket

This reference design uses the Texas Instruments PCI1221 PC Card Controller, supporting both an external PCMCIA card socket as well as on-board Intel® StrataFlash™ memory. The controller operates on a 3.3 V core voltage and is PCI interface compatible with 3.3 V and 5.0 V PCI signaling environments. Supporting up to five general purpose I/Os, the controller is compliant with both the PCI Local Bus Specification, v2.1 and 1995 PC Card Standards. The Fujitsu Takamisawa Americas 565P068-G/J-4V socket is compatible with PCMCIA card type I, II, and III.

6.6.1 Texas Instruments PCI1221 PC Card (PCMCIA) Controller

The Texas Instruments PCI1221 is a PCI-to-PC card controller that supports two independent PC card sockets, compliant with the 1995 PC Card Standards. The 1995 PC Card Standards retain the 16-bit PC card specification defined in PCMCIA, v2.1, and defines the new 32-bit PC card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1221 supports any combination of 16-bit and CardBus PC cards in the two sockets and, as required, are powered at 5 V or 3.3 V.

The PCI1221 is compliant with the PCI Local Bus Specification, v2.1 and with the PCI Bus Power Management Interface Specification. The PCI1221 can act as either a PCI master or slave device with PCI bus mastering initiated during CardBus PC card bridging transactions.

6.6.1.1 Slot A: PCMCIA Socket with Texas Instruments TPS2206 PC Card Power-Interface Switch with Reset

Slot A of the PCI1221 is connected to a PCMCIA socket for PCMCIA cards on the board. The Texas Instruments TPS2206 provides voltage regulation, overcurrent and over-temperature protection for the PCMCIA socket. The TPS2206 also accommodates 3.3 V/5 V systems by first powering up the PCMCIA card with 5 V, then polling it to determine its 3.3 V compatibility.

As well as the above, the TPS2206 also provides a reset to the PCMCIA card. This reset is triggered by a PCI RESET (RST#) on the board.

6.6.1.2 Slot B: Intel StrataFlash Memory

Capitalizing on two-bit-per-cell technology, Intel StrataFlash memory products provide 2X the bits in 1X the space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory devices are the first to bring reliable, two-bit-per-cell storage technology to the flash market.

Intel StrataFlash memory benefits include, more density in less space, lowest cost-per-bit NOR devices, support for code and data storage, and easy migration to future devices.

Application Note 33 Embedded Pentium® Processor-Based POS Terminal Sample Design

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1221 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1221 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide high performance with sustained bursting. The PCI1221 can also be programmed to accept fast posted writes to improve system bus utilization.

General purpose inputs and outputs are provided to implement sideband functions. Many other features are designed into the PCI1221, such as socket activity LEDs.

A CMOS process is used to achieve low system power consumption while operating at PCI clock rates up to 33 MHz. Power consumption is further reduced by several low-power modes.

6.6.1.3 Design Note

The Texas Instruments PCI1221 is a PCI-to-PC card controller. The controller provides two PC card slots, Slot A is connected to a PCMCIA socket for PCMCIA cards on the board. Slot B of the PC card controller provides the interface to Intel StrataFlash memory.

The PCI1221 PC card controller is PCI bus master #3 (connected to PCI bus master pins REQ3# and GNT3#) on the board. It is also PCI device number 5 (IDSEL connected to AD16).

The PCI1221 provides the user with flexibility in determining the interrupt implementation. The interrupt mode is selected via bits [2:1] of the Device Control Register at PCI offset 92h. Other registers that must also be configured are described below. The interrupt implementations are listed in Table 10.

The board implements parallel IRQ and PCI interrupts. In this interrupt mode, the PCI1221 routes the legacy interrupts, IRQ[15:2], via the seven multifunction terminals MFUNC[6:0]. The parallel IRQ and PCI interrupt modes are selected by programming bits [2:1] of the Device Control Register at PCI offset 92h to a value of 01b. When this mode is selected, the multifunction terminals must be configured through the Multifunction Routing Register at PCI offset 8Ch.

Table 10. Interrupt Implementations

Interrupt Mode PCI Offset 92h Bits 2:1

Parallel PCI Interrupts Only 00 Parallel IRQ and PCI Interrupts 01 Serial IRQ and Parallel PCI Interrupts 10 Serial IRQ and PCI Interrupts 11

The PCI interrupts INTA# and INTB#, are available only on terminals MFUNC0 and MFUNC1 respectively. A maximum of five IRQ interrupts may be implemented through multifunction terminals MFUNC[6:2].

The multifunction terminals are connected on the board as listed in Table 11.

34 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

Table 11. Multifunction (MFUNC[6:0]) Board Connections

Terminal Pin Connection on Board

MFUNC0 INTC# MFUNC1 INTD# MFUNC2 IRQ4 MFUNC3 IRQ5 MFUNC4 IRQ9 MFUNC5 IRQ10 MFUNC6 IRQ15

6.7 ISA PCI Expansion Cards

There are two PCI expansion slots on this sample design, allowing for add-in card peripherals to enhance any design. There is also one ISA expansion slot in the design. With the variety of peripherals in this design that would ordinarily be implemented through an add-in card, two extra PCI slots and one extra ISA slot allows for functionality that has not been added.

6.7.1 Design Note

• ISA Bus/Expansion Slots As discussed on the Intel® 430TX PCIset Design Guide (order number 290613), pull-up and pull-down resistors should be placed as follows: —10 KΩ pull-ups on SD[15:0] and SA[19:0]. —1 KΩ pull-up on IOCHRDY and REFRESH#. —10 KΩ pull-up on IRQx (10 KΩ pull-up on IRQ8, MEMR#, MEMW#, IOR#, IOW#, LA[23:17], SMEMR#, SMEMW#, SBHE#, and BALE. —330 Ω on ZEROWS#, MASTER#, MEMCS16#, and IOCS16#. — 4.7 KΩ on IOCHK#. — 5.6 KΩ pull-down resistors on DRQx. • PCI Bus/Expansion Slots Per the Intel® 430TX PCIset Design Guide, place pull-up signal resistors on the following: — 2.7 KΩ pull-up resistors to 5 V on PIRQ[D:A]#, SDONE, SBO#, FRAME#, TRDY#, STOP#, IRDY#, DEVSEL#, PLOCK#, PERR#, SERR#, REQ64# and ACK64# and PAR —10 KΩ pull-ups to 3.3 V on GNT[3:0]#, PHLD# and PHLDA#. There are two PCI expansion slots on the board. Slot 0 is PCI device #17, Slot 1 is PCI device #18 (IDSEL connected to AD28 and AD29 through a 220 Ω resistor respectively). Each slot is connected to PCI bus master arbitration pins REQ# and GNT#. Slot 0 is connected to GNT0# and REQ0#, and Slot 1 is connected to GNT1# and REQ1#.

Note: For layout considerations when placing series resistors, refer to the Intel® 430TX PCIset Design Guide.

Application Note 35 Embedded Pentium® Processor-Based POS Terminal Sample Design

Interrupts on the board are configured as indicated in Table 12 to minimize interrupt latency.

Table 12. Board Interrupt Configurations

Device LCD / Video AC ’97 Audio PCMCIA† PCI Slot 0 PCI Slot 1 Interrupt Pin Controller

0 INTA# INTB# INTC# INTD# INTA# 1 X X INTD# INTA# INTB# 2 X X X INTB# INTC# 3 X X X INTC# INTD# † The PCMCIA controller also uses legacy ISA IRQs. Refer to the PCMCIA section on page 33 for more information.

Note: Refer to the PCI Local Bus Specification, v2.1, for routing guidelines (see Table 2).

6.8 Clocking

Improper layout of the clock lines on the board can cause cross-coupling with other signal lines. It is recommended that the clock line spacing (air gap) be at least two times the trace width of any surrounding traces. It is also strongly recommended that the clock spacing be at least four times the trace width of any strobe line.

6.8.1 Cypress Semiconductor CY2280

The CY2280 is a clock synthesizer/driver that outputs four processor clocks at 2.5 V. There are eight PCI clocks that run at one-half or one-third the processor clock frequency of 66.6 MHz and 100 MHz respectively. One of the PCI clocks is free-running. The CY2280 possesses power-down, processor stop, and PCI stop pins for power management control. The signals are synchronized on-chip and ensure glitch-free transitions on the outputs.

The CY2280 outputs are designed for low EMI emissions. For further information, please refer to the following URL: http://www.cypress.com/cypress/prodgate/timi/cy2280.htm.

6.8.2 Cypress Semiconductor CY2309

The CY2309 is a 3.3 V zero-delay buffer designed to distribute high speed clocks in PC systems and SDRAM modules. There are on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. All outputs have less than 200 ps of edge-to-edge jitter. The input-to-output propagation delay is guaranteed to be less than 350 ps, and the output-to-output skew is guaranteed to be less than 250 ps. For more information please refer to the following URL: http://www.cypress.com/cypress/prodgate/timi/cy2309.html.

6.8.3 Clocking for 430TX Chipset

The Intel 430TX chipset uses several techniques from the mobile and desktop markets to reduce power consumption and hence power dissipation in a Pentium processor-based embedded system.

In the MTXC there are three main states used in clocking. 1. Clock Stopped: CLKRUN# is being monitored for a restart, the clock is stopped.

36 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

2. Imminent Clock Stop: The system has indicated the clock is about to be halted utilising the CLKRUN# line. 3. Clock Running: The clock is running and the PCI system bus is operational.

The MTXC is a CLKRUN# master unit and behaves according to the protocols specified for a master control device. The PIIX4 companion device to the chipset controls system clocks and is the CLKRUN# central resource. In designing a system, the main system clock should originate from a master clock ocillator, and for the processor and MTXC, be from the same buffer driver output.

The signal paths must be setup to minimize clock skew and the resulting system instabilities. Trace length matching, along with proper terminations to minimize reflected energy, will result in better system performance and less overall noise that may possibly be affecting system reliability.

When the Intel 430TX chipset is used in a system application, the designer may elect to take advantage of the different clocking schemes and modes available to enhance system power and performance. There are five low power clocking modes available: 1. Chip standby: The MTXC processor and PCI busses are idle. 2. Dynamic stop clock: Assists the processor in transitioning in and out of clock stop from system run. 3. Powered On Suspend: All system phase locked loops (PLL) are shut down. The real time clock (RTC) and suspend clock (SUSCLK) are running. DRAM refresh is accomplished by using SUSCLK. 4. Suspend to Ram (STR): The processor and L2 cache are clocked off. RTC and SUSCLK are running. DRAM refreshes using SUSCLK 5. Suspend to Disk (STD): The processor and L2 cache, DRAM and PCI interface are clocked off.

Note: In clocking the main system the PCI bus clock is derived from the main processor clock and is one half the frequency of said clock.

6.8.4 Clocking for 440BX Chipset

As described in Section 6.8.3 above, except for SDRAM, the clock is synchronized with BXDCLKO and BXDCLKRD.

7.0 Design Considerations

There should be decoupling capacitors for every schematic page and one bulk capacitor for the entire design. This provides a short between power and ground for high frequency noise signals and reduces impedance. • If a part is removed from the design, the outputs can be left unconnected, but the inputs should be pulled either high or low through an appropriate resistor. • When changing jumper settings, first power down the board. • Trace widths on all power and ground signals should be ~10 mil.

Application Note 37 Embedded Pentium® Processor-Based POS Terminal Sample Design

A fence is a line routed out of a plane such that a given area is isolated from the rest of the plane except at a single point of contact, conceptually the “gate” in the fence. A fence will minimize noise originating from the digital signaling onto the analog signals. This provides higher quality video or audio. An example is shown in Figure 1. The heavy black line is the routed area. The width of the gate or opening can be up to 75% of the length of the integrated circuit or signals in question. The width of the routed fence should conform to the separation routing between power planes (i.e., 25 mils minimum). Figure 6. Fence Example

Routed “fence” Fenced area

Overlying Chip/Signals “gate”

Plane (e.g., VCC)

8.0 Windows CE

Windows CE can have the same look and feel as Microsoft Windows 98 or Windows NT. A variety of interfaces are supported for embedded applications. The hardware configuration for an embedded system can include the following peripherals: keyboard, mouse, touch screen, and so forth. It is often easier for users to deal with commands and keys that pertain to the desktop PC because they are familiar to dealing with them on their office or home desktop PC. A similar environment in the embedded product segment eliminates the need for retraining of personnel since they are already familiar with the look and feel of the system. Often times, it helps to be able to have little or no difference between the embedded and desktop device from a user interface perspective.

In Windows CE, the PC is used to prototype peripherals and develop device drivers; all development is done on the PC. If the target platform is also Intel Architecture, the large knowledge base for Intel Architecture can be utilized for hardware expertise, programmers, training materials, and sample code. Intel Architecture CISC is very efficient for all Windows operating systems. Since a lot of optimization effort has already been spent on the PC, reuse of PC developments can result in faster time-to-market. This is possible if the architecture of the Windows CE target is the same as the PC. The Windows CE Embedded Toolkit includes PC chipset and peripheral support, including basic VGA drivers and S3 accelerated drivers.

There are some differences between programming for the desktop and programming in Windows CE. Since Windows CE programs are required to have a small memory footprint, an important aspect of its programming is the need to manage with limited memory. Since memory usage must be minimized, having knowledge of memory allocations with Windows CE is important.

Embedded systems may stay powered-on for long periods of time. Programmers need to keep this in mind to ensure that the programs run flawlessly for many months at a time. Modifications must be made to the OEM Adaptation Layer. Since different solutions are possible for different applications, the varying need for applications can be met.

38 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

8.1 Windows CE for Embedded Applications

Windows CE is designed to be a multi-threaded, preemptive, multitasking operating system for platforms with limited resources. This is to say that multiple processes can be running simultaneously, each assigned a specific priority. Each process can have multiple threads. This allows a process to have more than one flow of execution running concurrently. Windows CE is designed as a modular operating system that can be customized to contain only the modules needed by the application. Refer to Table 2 for the URL to Microsoft’s on-line Embedded Toolkit (ETK).

8.2 Windows CE Environment

8.2.1 Kernel

The Windows CE kernel contains the core operating system functionality that must be present on all Windows CE-based platforms. It includes support for memory management, process management, exception handling, multitasking and multithreading.

The kernel is provided as the file Nk.lib. The OEM Adaptation Layer must be developed to create the platform-specific Nk.exe module. For an overview of the OEM Adaptation Layer, refer to Section 8.2.3.

The kernel is designed specifically for small, fast, embedded devices. The kernel supports only a single 4 Gbyte address space (a 2 Gbyte virtual address and a 2 Gbyte physical address range). 1 Gbyte of the 2 Gbyte virtual address space is divided into 33 slots, each of which has a size of 32 Mbytes. The kernel protects each process by assigning each to a unique open slot in memory. Within each slot, memory regions are allocated for the following: • 64 Kbytes of reserved space • Executable files, code, and data sections • Primary thread's stack, and the process's default heap • Dynamic-link libraries (DLLs) loaded from RAM • DLLs loaded from ROM

The kernel protects applications from accessing memory outside of their allocated slot by generating an exception. Applications can check for and handle such exceptions by using the “try and except” Windows CE functions. The system is limited to 32 processes, but the number of threads running in a process is limited only by the amount of available memory.

8.2.2 Modularity

Windows CE is built from a number of discrete modules, hence the size (footprint) of the operating system software can be controlled by selecting only the applicable modules. Several of these modules are also further divided into components. By selecting a minimum set of modules and components, the ROM and RAM requirements needed to support the end product can be minimized.

Refer to Understanding Modularity in Microsoft Windows CE. See to Table 2 for the URL.

Application Note 39 Embedded Pentium® Processor-Based POS Terminal Sample Design

8.2.3 OEM Adaptation Layer (OAL)

A developer can adapt Windows CE for a specific target platform by creating a thin layer of code that resides between the kernel and the target platform. To avoid confusion with the Windows NT Hardware Abstraction Layer (HAL), Windows CE refers to this interface as the OAL.

In addition to managing functions such as timing and power, the primary purpose of the OAL is to expose the target platform's hardware to the kernel. That is, each hardware interrupt request line (IRQ) is associated with one interrupt service routine (ISR). When interrupts are enabled and an interrupt occurs, the kernel calls the registered ISR for that interrupt. The ISR, the kernel mode portion of interrupt processing, is kept as short as possible. Its responsibility is primarily to direct the kernel to schedule and launch the appropriate interrupt service thread (IST). The IST, implemented in the device driver software module, gets or sends data and control codes to the hardware and acknowledges the device interrupt.

8.3 Windows CE Build Information

8.3.1 Getting Started

After installing all the necessary software (e.g., Visual C++, SDK, and ETK), get into the correct build environment for the project you are going to develop. Several are provided with Windows CE 2.10 (e.g., Maxall, Minshell). Windows CE 2.0 includes demos named DEMO1–DEMO7. After getting into the desired build environment, type “blddemo” to build the image for that project. This will place the image in the release directory. After building the image, load it into the target system using the Parallel Port Transfer Tool (PPSH) or the CE Shell Utility (CESH).

8.3.2 Building a Windows CE Operating System Configuration

The configurations included with the Windows CE Embedded Toolkit for Visual C++ contain all the modules and components needed to build different versions of a Windows CE operating system.

Included in the directory %_PUBLICROOT%\Common\Oak\Misc, a build batch file, called Blddemo.bat, automates the Build Tools required to generate the platform for your Windows CE operating system. For each configuration, a build batch file %_TGTPROJ%.bat, for example Minkern.bat, specifies the environment variables required for your Windows CE project. The following procedure describes how to configure your build environment and use Blddemo.bat to create the Windows CE operating system image for the operating system configuration.

To build a Windows CE operating system configuration: 1. If the configuration includes the Windows CE debug shell utility (CESH), invoke the Microsoft WinDbg debugging program shortcut for your platform (e.g., x86 Debugger). 2. Invoke the new command prompt build window shortcut that you created in Preparing to Build a Windows CE Operating System configuration. 3. As an optional step, modify your command prompt build window to add scroll bars. Scroll bars let you scroll back through the commands that the various batch files and tools execute. Click on the MS DOS icon in the top-left corner of the window, then click on Properties. Click on Layout and change the screen buffer size and height setting to 1000. This modification will give you a 1000-line screen buffer so you can see up to 1000 of the most recent lines in that command window. After clicking OK, select the Modify shortcut that started the window to make this change permanent.

40 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

4. Set any additional environment variables for the configuration build in your command prompt build window. For example, if you want to build the Windows CE kernel with remote debugging enabled, use the following command: set IMGNODEBUGGER= To compile a configuration so that debugging messages are enabled, set the environment variable WINCEDEBUG to debug using the following command: set WINCEDEBUG=debug For information on configuration-specific environment variables, see the corresponding description of the Windows CE operating system configuration in Section 8.3.2. 5. Enter the build batch file command to build the configuration: blddemo After the build batch file is done processing, the current directory should still be the %_WINCEROOT% directory. 6. Verify that the build batch file command completed successfully by checking whether the Nk.bin file exists in the directory %_FLATRELEASEDIR% (by default, \Wince210\Release). Nk.bin contains the binary image of the operating system for your selected platform.

8.3.3 Building a New Project

This section provides a tutorial that describes how to build the Windows CE operating system image based on the Maxall configuration. In this section, you will: • Create a new platform directory • Create a new project directory • Create a new command prompt build window • Build the Windows CE operating system image for your new project

This tutorial assumes that you have installed the Embedded Development Kit in the default directory established by the setup program.

8.3.3.1 Create a New Platform Directory

To create a new platform directory, copy the Wince210\Platform\Cepc directory and all of its contents, including the subdirectories and their contents, into a new platform directory. The platform name should be no more than eight characters in length.

From a Command Prompt window, enter the following commands to copy the \Cepc directory from its default location and create \MyPlat, your new platform directory: cd \Wince210\Platform xcopy Cepc MyPlat /E /V /I

8.3.3.2 Create a New Project Directory

The Windows CE Embedded Toolkit for Visual C++ 5.0 (Embedded Toolkit) contains typical configurations of the Windows CE operating system. Use the Maxall configuration as the template for your MyProj build. 1. From a Command Prompt window, enter the following commands to copy the \Maxall directory (including all subdirectories and contents) into a new project directory named \MyProj. The project name should be no more than eight characters in length: cd \Wince210\Public xcopy Maxall MyProj /E /V /I

Application Note 41 Embedded Pentium® Processor-Based POS Terminal Sample Design

2. Rename the \MyProj\Maxall.bat file. The name of this batch file should always match the name of your project directory. Enter the following commands to rename the project batch file: cd \Wince210\Public\MyProj rename MAXALL.BAT MYPROJ.BAT

8.3.3.3 Create a New Command Prompt Build Window

The Embedded Toolkit includes a collection of shortcuts for the Minshell configuration. Each shortcut opens a command prompt build window specific for a supported processor. Use the x86 Minshell command prompt build window shortcut as a template for your command prompt build window shortcut. Your project and hardware development platform directories must first be created before you launch this shortcut. 1. In the Windows CE Embedded Development Kit program group, select the x86 Minshell shortcut. 2. Make a copy of the shortcut and rename it “x86 MyProj”. 3. In the tab shortcut for the icon's properties, modify the target command line parameters that follow the Wince.bat command. These modifications are case sensitive. Wince.bat For your build, the last part of the command line (starting with Wince.bat) must read as follows: Wince.bat x86 I486 CE MYPROJ MYPLAT 4. Click OK to save the modified shortcut.

8.3.3.4 Build the Windows CE Operating System Image for a New Project

1. Invoke the x86 Build MyProj shortcut that you have previously created. 2. Enter the following command to build a complete version of Windows CE: blddemo After Blddemo.bat has finished processing, the current directory should still be the \Wince210 directory. 3. Be sure the build completed successfully by verifying that the Windows CE operating system image, called Nk.bin, exists in the \Wince210\Release directory. The build process sets this directory using the environment variable %_FLATRELEASEDIR%. If Nk.bin does not exist, then the build of the Windows CE operating system image was not completed successfully. Before rebuilding, refer to Preparing Your Development Workstation for Subsequent Projects in the Windows CE Embedded Toolkit. If Nk.bin exists, the Windows CE operating system image for MyProj was built successfully, and you can now run this image on your PC-based hardware development platform.

8.3.3.5 Adding Files or Applications to the Windows CE Operating System Image

1. Copy the file or application to the \Wince210\Public\\Oak\Files directory. 2. Edit the project.bib file in the same directory. Add a reference to the end of the file to include the files/app formatted:

42 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

filename.ext $(_FLATRELEASEDIR)\filename.ext S 3. Build the image by calling the blddemo utility.

Note: The filename.ext should be replaced with the name of your file or application. The S signals the image builder to make the file a system file. Other switches are H (hidden) and U (uncompressed), and can be used in combinations (e.g., SH = hidden system file).

9.0 Windows CE Device Drivers

Device drivers are programs that provide an interface between the operating system software and platform hardware. In previous versions of Microsoft's operating system, these device drivers are implemented as special system executable files that run at the same privilege level as the operating system kernel. On Windows CE, device drivers are implemented as DLLs and run at the same privilege level as the user code.

9.1 Dynamic Link Libraries (DLLs)

DLLs are software function libraries just like their predecessor the static library. When a static library is linked to a program, the library functions used by the program are copied into the final executable image. This increases the size of the program. When a program is linked with a DLL, the library functions used by the program are not copied into the final executable image; only a function “stub” is copied. This function stub serves to identify the DLL and the function within the DLL that is being called upon. The actual DLL code is loaded into a separate memory space and the link between the program and the library function is created by the operating system when the function call is made. In addition, multiple programs can use DLLs simultaneously, reducing the memory requirements of each program.

9.2 Windows CE Device Driver Model

Windows CE has two types of device drivers as viewed from a software perspective: built-in and installable. Built-in drivers are typically for hardware that is native to the Windows CE target platform and are linked directly with the operating system image at build time. Some examples of this include keyboard, touch screen panel, battery, notification LED, PC card adapter, and audio hardware. Installable drivers are typically for hardware that can be added to the platform. This type of driver is loaded by the operating system and exists as a stand-alone DLL. Some examples of this include modems, printers, digital cameras and PCMCIA cards. In either case, the terms built-in and installable relate to whether or not a particular device driver is linked directly with the operating system image or loaded at run time as a stand-alone DLL.

For Windows CE drivers, Microsoft provides a layer of source code known as the Model Device Driver (MDD) component. The MDD component defines the interface to the operating system for a given type of device driver and is common to all platforms that use that type of device. The MDD also defines the interface to the platform-specific driver code. This platform-specific driver code is referred to as the Platform Device Driver (PDD) component. The PDD component implements the interface to the hardware device. These two layers are compiled, then linked together to form the complete driver DLL.

Application Note 43 Embedded Pentium® Processor-Based POS Terminal Sample Design

Whether or not a given type of device driver is built-in or installable is pre-determined by the MDD/OS interface defined by Microsoft for that type of device. For built-in drivers, Microsoft has defined a set of custom MDD/OS interfaces. For installable drivers, Microsoft has defined a set of common MDD/OS interfaces.

Note: Windows CE device drivers implementation is not required as MDD and PDD components. They may be implemented as a single, monolithic entity providing that the MDD/OS interface, as defined by Microsoft for a given device, is used. See Figure 2. Figure 7. Device Driver Architecture

GWE Subsystem Device Manager

MDD Layer Monolithic MDD Layer (Audio, touch, (PC card, Monolithic keyboard) Driver Serial) (display, Driver battery, LED PDD Layer PDD Layer

HARDWARE

A6176-01

9.3 Interaction with Application Software

Installable device drivers are viewed as a special file in the file system by the application software. The interface exposed to the application corresponds to the standard Win32 file I/O functions such as OpenFile, ReadFile, DeviceIOControl, and others. The file system recognizes filenames as being special devices when they consist of exactly three uppercase letters, a single digit, and a colon ( : ). An example of this would be “COM1:”, which references the first serial port available on the platform.

Built-in device drivers are accessed by application software using API calls that Microsoft has implemented in the Windows CE operating system for each device.

9.4 Incorporating Device Drivers

To include drivers in the Windows CE image, first take the compiled driver or file and place it in the following directory: %_WINCEROOT%\public\maxall\files

44 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

Note: Maxall can be changed to the name of your project directory.

Edit the project.bib file in the same directory to include your file(s) and run blddemo.

A serial cable is needed. Windebug window must be open. All debug messages will be displayed on the windebug screen. The image must be downloaded to test the target board.

Refer to Microsoft’s web site for information on new releases.

9.4.1 NE2000 ISA Network Interface Cards (NIC)

First, install the card on the embedded Pentium processor target board running Windows CE (WinCE 2.1 ETK). Along with plugging in the NIC, the following configurations must be made to ensure that the card is recognized.

The following files need to be modified prior to building a Windows CE image: 1. Registry entries in the wince.c file need to be modified. Set the CEPC_NE2000_PCI variable to enable registry entries 2. To set up the registry correctly, modify the platform.reg file. In WinCE210\platform\cepc\files\platform.reg If PCI, change the bus type to 1 3. Find the following path and verify the keys: Hkey_local_machine\comm\NE20001\Parms 4. Make sure that PCI enumeration is functional. In Public\common\misc\wince.bat Set CEPC_NE2000_PCI=1 Now the build will include the NE2000 driver 5. Build the driver. Add NE2000 drivers to platform\cepc\drivers directory Use build -c to build your image For PCI devices, add PCI enumeration In the wince210\public\common\oak\drivers\ceddk\test\pcienum Use build -c to build your image 6. Debug In the Wince.bat file, set the following environment variables to build in debug mode: Wincedebug = debug imgnodebugger =

9.4.1.1 NE2000 NIC Configuration

When the card is connected, run pcienum.exe. Grab the I/O address after changing wince.c Build again in the common area. 1. On the target board, press the Ctrl+Esc keys to run a program. If PCI, run pcienum.exe. 2. Run registry: NE20001 In the wince210\platform\CEPC\Files\platform.reg file make the following changes:

Application Note 45 Embedded Pentium® Processor-Based POS Terminal Sample Design

a. Change Iobaseaddress = 00240 b. Change Interruptnumber = 05 3. In the wince.c file, make the following changes. This should be in the NE2000 directory. a. Change the interrupt number from 10 to 5 b. Change bustype to 1 if ISA c. Change Iobaseaddress to 576 d. Type “build -c” 4. Before completing a build, delete the release directory and the maxall.bif file found in platform\CEPC\MAXALL.Bif. a. Use blddemo to build the image b. When the image is downloaded, use the ping application can be used to test the card.

9.4.2 ACTiSYS IR 2000B

To configure the ACTiSYS IR 2000B component: 1. Disable port 2 in the BIOS 2. Set the environment variable to use nscfir.dll instead of irsir.dll 3. Add the following to the Maxall.bat file or to the batch file that is used: set IMGNSCFIR=1 4. To set up the registry correctly, modify the platform.reg file 5. Find the following path and verify the following keys: [HKEY_LOCAL_MACHINE\Comm\NscIrda1\Parms] “BoardType”=dword:0 “DongleType”=dword:4 “ConfigBase”=dword:398

Note: The above keys are important keys, however other keys should also be checked for compatibility with your system (e.g., Bus Number, and IRQ).

9.4.3 Audio

The card used in the sample design is the Creative Ensoniq AudioPCI card. Alternately this configuration is valid for equivalent parts on the board, namely the Ensoniq ES1371 and an AC ’97 codec. The following steps are required to configure the digital controller. 1. The following driver files need to be included in the build: wavepdd.cpp wavepdd.h ensoniq.h 2. Edit the following source files: a. Makefile b. Make a directory in %_WINCEROOT%\platform\cepc\drivers for the driver

46 Application Note Embedded Pentium® Processor-Based POS Terminal Sample Design

— Give it a name, we called it “ES1371WaveDev” — Copy files into directory — Edit file %_WINCEROOT%\platform\cepc\drivers\dirs to include this directory. Remove references to the WaveDev in “dirs” file c. Run “blddemo” from %_WINCEROOT% 3. Set up configurations in VC++ to compile for Intel Architecture Load Application Check the Configuration list dialogue box for the desired configuration. a. Under “Build” menu, select “Configurations..” b. Click on Add button c. Pick a matching configuration from “Copy Settings from...” — For debug select “Win32 (WCE xxxx) Debug” — For release select “Win32 (WCE xxxx) Release” (xxxx signifies don't care) d. Pick a platform — Choose WCE x86 to compile for target — Choose WCE x86em to compile for emulator e. Click on OK f. Click on Close

Application Note 47 Embedded Pentium® Processor-Based POS Terminal Sample Design

Appendix A. Schematics

A.1 POS Terminal Baseboard Schematics

Schematics are provided for the following items: • Embedded Processor Assembly Connector • SDRAM DIMM socket • Clocks • ISA/PCI pullups • PCI slots 0 and 1 • 69000 part 1 and 2 • AC ’97 Audio part 1 and 2 • PCI1221 • StrataFlash • PIIX4 part 1 and 2 • IDE connector • USB connectors • Ultra I/O • ISA connector • COMx, DB25, floppy • Touch screen controller • Super I/O (extra serial ports) • BIOS • AXT power connector • Unused gates

48 Application Note A B C D E

J1A J1B J1C

A1 B1 C1 D1 E1 F1 A2 B2 C2 D2 E2 F2 SBA5 AD_STBB V3_3 G_AD31 SBA7 GND 4 A3 B3 C3 D3 E3 F3 4 A4 G_AD25 G_AD24 B4 C4 SBA6 SBA4 D4 E4 SBA0 G_REQ# F4 A5 G_AD30 GND B5 C5 G_AD26 G_AD27 D5 E5 V3_3 ST0 F5 RBF# G_AD29 G_AD4 G_AD6 G_AD8 G_GNT# A6 B6 C6 D6 E6 F6 GND V3_3 G_AD3 G_AD5 G_C/BE0# G_AD13 A7 B7 C7 D7 E7 F7 3 MD0 V3_3 G_AD1 MD1 3 G_AD2 AD_STBA CLKRUN# 13 GND G_AD12 A8 B8 C8 D8 E8 F8 3 MD2 MD0 MD1 MD33 3 3 MD3 GND CLKRUN# MD32 3 G_AD7 G_AD10 A9 B9 C9 D9 E9 F9 MD2 MD33 MD4 3 3 MD37 MD3 MD32 MD35 3 G_AD0 G_AD11 A10 B10 C10 D10 E10 F10 3 MD36 GND MD4 MD38 3 3 MD40 MD37 MD35 MD6 3 3 MD34 V3_3 G_AD9 A11 B11 C11 D11 E11 F11 3 MD7 MD36 MD38 MD42 3 MD40 MD6 MD39 3 3 MD5 MD34 GND AD0 6,7,9,11,13 A12 B12 C12 D12 E12 F12 MD7 MD42 MD11 3 3 MD44 GND MD39 MD10 3 3 MD8 MD5 AD0 MECC1 3 A13 B13 C13 D13 E13 F13 3 MD41 V3_3 MD19 MD45 3 3 MD15 MD44 MD18 3 MD9 MD16 MECC1 -SERR 5,6,7,9,11,13 A14 B14 C14 D14 E14 F14 3 MD43 MD41 MD45 MD14 3 MD23 GND MD13 3 3 MD12 MD17 SERR# AD16 6,7,9,11,13 A15 B15 C15 D15 E15 F15 MD43 MD22 MECC0 3 3 MECC5 V3_3 MD21 MD47 3 3 MD46 MD20 AD16 A16 B16 C16 D16 E16 F16 3 MECC4 GND MECC0 3 DQMA0 MECC5 MD47 MD46 V3_3 AD19 6,7,9,11,13 V3_3 A17 MECC4 GND B17 C17 DQMA0 V3_3 D17 DQMA1 3 E17 GND AD23 F17 AD23 6,7,9,11,13 A18 B18 C18 D18 E18 F18 3 CS_B1# CSB5# CSB4# CSB2# DQMA2 DQMA5 3 3 CS_A0# DQMB1 AD19 AD27 6,7,9,11,13 A19 B19 C19 D19 E19 F19 3 SCASA# CSB1# SCASB# DQMB5 DQMA5 CSA0# AD27 -PCIRST 6,7,9,10,11,13 A20 B20 C20 D20 E20 F20 SCASA# V3_3 WE_A# 3 CSA4# CSA3# 3 MAA1 CSB3# PCI_RST# A21 GND WEA# B21 DQMA4 3 C21 V3_3 MAB1# D21 E21 MAA1 GND F21 CS_B0# 3 A22 B22 C22 D22 R1 E22 F22 3 CS_A1# SRASB# DQMA4 MAB0# Reserved8 MAB3# CSB0# -IRDY 5,6,7,9,11,13 A23 CSA1# CSA2# B23 C23 MAB2# WEB# D23 10k E23 V3_3 IRDY# F23 3 SRASA# -PGNT3 5,11 1 A24 SRASA# CSA5# B24 C24 V3_3 GND D24 E24 GND GNT3# F24 TP 3 MAA0 RSV8 MAA3 3 -PGNT1 5,6 A25 Reserved0 GND B25 C25 MAA0 MAA3 D25 E25 MAB6# GNT1# F25 3 MAA4 MAA2 3 A26 MAA4 MAA2 B26 C26 MAB5# MAB9# D26 E26 MAB7# GND F26 3 MAA8 TP1 A27 MAA8 MAB4# B27 C27 Reserved4 GND D27 E27 MAB10 GND F27 3 MAA12 MAA5 3 4 MAB#12 MAA9 3 MAA6 3 A28 MAA12 MAA5 B28 C28 MAB12# MAA9 D28 MAB#9 E28 GND MAA6 F28 MAB8# GND 3 MAA11 MAA11 CKE0 CKE0 3 4 BXDCLKO DCLKO MAA7 MAA7 3 A29 B29 RSV4 C29 D29 E29 F29 MD25 3 A30 GND MAB11# B30 C30 CKE3 CKE4 D30 E30 V3_3 MD25 F30 MAA10 3 3 DQMA3 MD60 3 A31 MAB13# Reserved2 B31 C31 Reserved5 MAA10 D31 E31 DQMA3 MD60 F31 3 CKE1 MAA13 3 3 DQMA2 DQMA6 3 A32 CKE1 MAA13 B32 C32 DQMA1 GND D32 E32 V3_3 DQMA6 F32 BxFBCLK 4 5,14 SLP# 1 A33 CKE5 CKE2 B33 RSV2 RSV5 C33 Reserved6 DCLKWR D33 E33 SLP# V3_3 F33 TP NMI 5,14 MECC2 3 A34 Reserved1 Reserved3 B34 C34 V3_3 NMI D34 E34 GND MECC2 F34 14 ZZ INIT 5,14 DQMA7 3 A35 V3_3 GND B35 RSV6 C35 L2_ZZ INIT# D35 E35 V3_3 DQMA7 F35 3,5,14 SMBCLK INTR 5,145,14 FERR# MECC6 3 TP2 A36 V3_3 V3_3 B36 RSV3 C36 SM_CLK INTR D36 E36 FERR# MECC6 F36 SUS_STAT1# 14 3,5,14 SMBDATA 5,14 IGNNE# MECC3 3 A37 V3_3 SUS_STAT1# B37 C37 SM_DATA GND D37 E37 IGNNE# MECC3 F37 SUSCLK 14 5,14 A20M# A38 V3_3 SUS_CLK B38 C38 GND V3_3 D38 E38 A20M# GND F38 GND V3_3 Reserved7 PIC_CLK 5,14 STPCLK# STPCLK# SMI# SMI# 14 A39 B39 C39 D39 E39 F39 V3_3 WSC# PICD1 PICD0 23 DBRESET DB_RST CPU_RST CPURST 5,14 A40 B40 C40 D40 E40 F40 3 4,14 CONFIG1 CPU_TYPE GND RSV7 V3_3 GND V3_3 V5_0 3 950554-00x 950554-00x 950554-00x

1 TP 1 TP3 TP RSV2 1 TP TP4 RSV8 TP5 RSV3 1 TP TP6 RSV4 1 TP TP7 RSV5 1 TP TP8 RSV6 1 TP TP9 RSV7 GFBCLK J1D J1E Note: Distance from HCKL4 to GCLKIN must be G1 H1 J1 K1 3.0" longer than from GCKOUT to AGP Connector G2 H2 J2 K2 G3 ST1 PIPE# H3 J3 SBA3 GND K3 G4 ST2 SBA1 H4 J4 SBA2 GCLKIN K4 G5 SB_STB GND H5 J5 G_C/BE3# GCLKO K5 G6 G_STOP# G_AD16 H6 J6 G_AD20 G_AD23 K6 G_PAR G_AD18 G_AD17 GND G7 H7 1 J7 K7 G_AD15 V3_3 TP G_C/BE2# G_AD22 G8 H8 J8 K8 GND G_C/BE1# G_FRAME# G_AD21 G9 H9 TP10 RSV9 J9 K9 G_AD14 G_TRDY# G_IRDY# G_AD19 G10 H10 1 J10 K10 6,7,9,11,13 AD4 V3_3 G_DEVSEL# TP 6,7,9,11,13 AD3 V3_3 G_AD28 AD1 6,7,9,11,13 G11 H11 J11 K11 C/BE0# AD4 GND AD2 6,7,9,11,13 AD3 AD1 AD5 6,7,9,11,13 G12 H12 TP11 RSV10 J12 K12 2 6,7,9,11,13 AD10 C/BE0# AD2 AD6 6,7,9,11,13 GND AD5 AD9 6,7,9,11,13 2 G13 H13 J13 K13 6,7,9,11,13 AD13 AD10 AD6 AD7 6,7,9,11,13 GND AD9 AD11 6,7,9,11,13 G14 H14 J14 K14 5,6,7,9,11,13 PAR AD13 AD7 6,7,9,11,13 AD8 GND AD11 AD14 6,7,9,11,13 G15 H15 J15 K15 5,6,7,9,11,13 -TRDY PAR GND AD15 6,7,9,11,13 6,7,9,11,13 AD12 AD8 AD14 -PLOCK 5,6 G16 H16 1 J16 K16 TRDY# AD15 -STOP 5,6,7,9,11,13 TP 6,7,9,11,13 -C/BE1 AD12 PLOCK# AD18 6,7,9,11,13 G17 H17 J17 K17 6,7,9,11,13 AD30 V5_0 STOP# AD17 6,7,9,11,13 RSV12 5,6,7,9,11,13 -DEVSEL C/BE1# AD18 AD21 6,7,9,11,13 G18 H18 TP12 J18 K18 6,7,9,11,13 AD22 AD30 AD17 AD24 6,7,9,11,13 DEVSEL# AD21 PCICLK7 4 G19 H19 1 J19 K19 AD22 AD24 TP 6,7,9,11,13 -C/BE2 V5_0 PCLK G20 H20 J20 K20 5,13 -PHOLD V5_0 Reserved11 RSV13 C/BE2# V5_0 AD25 6,7,9,11,13 G21 H21 TP13 J21 K21 5,6,7,9,11,13 -FRAME PHOLD# GND 6,7,9,11,13 AD26 V5_0 AD25 -PREQ0 5,6,13 G22 H22 1 J22 K22 FRAME# V5_0 -C/BE3 6,7,9,11,13 TP 6,7,9,11,13 AD28 AD26 REQ0# G23 V5_0 C/BE3# H23 J23 AD28 V5_0 K23 AD20 6,7,9,11,13 TP14 RSV14 6,7,9,11,13 AD29 MD59 3 G24 GND AD20 H24 AD31 6,7,9,11,13 J24 AD29 MD59 K24 MD54 3 G25 Reserved9 AD31 H25 J25 Reserved13 MD54 K25 5,9 -PGNT2RSV9 5,6,13 -PREQ1RSV13 G26 GNT2# V5_0 H26 J26 REQ1# Reserved16 K26 5 -PGNT4 -PREQ2 5,9,13 5,11,13 -PREQ3 RSV16 MD24 3 G27 GNT4# REQ2# H27 J27 REQ3# MD24 K27 5,13 -PHOLDA -PGNT0 5,6 5 -PREQ4 MD23 3 G28 PHLDA# GNT0# H28 1 J28 REQ4# MD15 K28 TP MD55 3 G29 GND V3_3 H29 RSV16 RSV14 J29 Reserved14 MD55 K29 Reserved10 Reserved12 TP15 GND MD56 MD56 3 RSV10G30 H30 RSV12 MD26 3 J30 K30 MD63 3 G31 V3_3 MD26 H31 J31 V3_3 MD63 K31 3 MD57 MD58 3 3 MD51 MD31 3 G32 MD57 MD58 H32 J32 MD51 MD31 K32 3 MECC7 MD50 3 3 MD52 G33 MECC7 MD50 H33 J33 MD52 GND K33 3 MD48 MD18 3 3 MD19 CPUCLK0 4 G34 MD48 MD10 H34 J34 MD11 HCLK0 K34 3 MD16 3 MD53 G35 MD8 GND H35 J35 MD53 GND K35 3 MD17 MD21 3 3 MD22 CPUCLK1 4 G36 MD9 MD13 H36 J36 MD14 HCLK1 K36 3 MD49 MD20 3 G37 MD49 MD12 H37 J37 V3_3 GND K37 3 MD27 MD28 3 3 MD62 CPUCLK2 4 G38 MD27 MD28 H38 J38 MD62 HCLK2 K38 3 MD29 MD61 3 3 MD30 G39 MD29 MD61 H39 J39 MD30 GND K39 V3_3 VR_PWRGD CPUPWROK 23 V5_0 HCLK3 G40 H40 J40 K40 V5_0 V5_0 V5_0 V5_0 950554-00x 950554-00x

1 1

Title CPU Connector

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 224of A B C D E A B C D E

V3_3

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 47uF 47uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF

4 4

Socket 0

2 MECC[7:0]

2 MAA[13:0]

2 MD[63:0]

J2 A01 B85 A02 B86 A03 GND GND B87 A04 DQ0 DQ32 B88 MD0 A05 DQ1 DQ33 B89 MD32 MD1 A06 DQ2 DQ34 B90 MD33 3 MD2 A07 DQ3 DQ35 B91 MD34 3 MD3 A08 V3_3 V3_3 B92 MD35 A09 DQ4 DQ36 B93 MD4 A10 DQ5 DQ37 B94 MD36 MD5 MD37 DQ6 DQ38DQ39 MD6 DQ7 MD38 MD7 MD39 A11 B95 A12 DQ40 B96 A13 DQ8 GND B97 MD8 MD40 A14 GND DQ41 B98 DQ9 MD9 A15 DQ42 B99 MD41 DQ10 DQ43 MD10 A16 B100 MD42 DQ11 DQ44 MD11 A17 B101 MD43 A18 DQ12 DQ45 B102 MD12 DQ13 MD44 MD13 A19 V3_3 B103 MD45 A20 V3_3 DQ46 B104 DQ14 MD14 A21 DQ47 B105 MD46 A22 DQ15 CB4 B106 MD15 CB0 MD47 A23 CB5 B107 MECC0 CB1 MECC4 A24 GND B108 MECC1 GND MECC5 A25 NC B109 NC A26 NC B110 NC V3_3 A27 B111 2 WE_A# V3_3 SCASA# 2 A28 /CAS B112 2 DQMA0 WE0DQMB0 DQMB4 DQMA4 2 A29 B113 2 DQMA1 DQMB1 DQMB5 DQMA5 2 A30 B114 2 CS_A0# /S0 /S1 CS_A1# 2 A31 DU /RAS B115 SRASA# 2 A32 GND GND B116 A33 A0 A1 B117 A34 B118 MAA0 A2 A3 MAA1 A35 A4 A5 B119 MAA2 MAA3 A36 A6 A7 B120 MAA4 MAA5 A37 A8 A9 B121 MAA6 A38 B122 MAA7 MAA8 A10(AP) BA0 MAA9 A39 BA1 A11 B123 MAA10 A40 B124 MAA11 MAA12 V3_3 V3_3 MAA13

2 2 A41 CK1 B125 SDCLK1 4 A42 V3_3 A12 B126 4 SDCLK0 A43 CK0 GND B127 MAA12 A44 GND CKE0 B128 CKE0 2 A45 DU /S3 B129 2 CS_B0# CS_B1# 2 A46 /S2 DQMB6 B130 2 DQMA2 DQMA6 2 A47 DQMB2 DQMB7 B131 2 DQMA3 DQMA7 2 A48 DQBM3 A13 B132 A49 DU V3_3 B133 A50 V3_3 NC B134 A51 NC NC B135 A52 NC CB6 B136 R2 CB2 CB7 MECC2 A53 B137 MECC6 0 V3_3 A54 CB3 GND B138 MECC3 GND MECC7 A55 DQ48 B139 DQ16 A56 B140 R3 MD16 DQ17 DQ49 MD48 A57 B141 MD17 DQ18 DQ50 MD49 0 MD18 A58 DQ19 DQ51 B142 MD50 MD19 A59 V3_3 V3_3 B143 MD51 A60 DQ20 DQ52 B144 MD20 A61 NC NC B145 MD52 A62 VREF (NC) DU B146 A63 B147 2 CKE1 CKE1 REGE A64 GND GND B148 A65 DQ21 DQ53 B149 MD21 A66 DQ22 DQ54 B150 MD53 MD22 A67 DQ23 DQ55 B151 MD54 MD23 A68 GND GND B152 MD55 A69 DQ24 DQ56 B153 MD24 A70 DQ25 DQ57 B154 MD56 MD25 A71 DQ26 DQ58 B155 MD57 MD26 A72 DQ27 DQ59 B156 MD58 MD27 A73 V3_3 V3_3 B157 MD59 A74 DQ28 DQ60 B158 MD28 MD60 A75 DQ29 DQ61 B159 MD29 MD61 A76 DQ30 DQ62 B160 MD30 MD62 A77 DQ31 DQ63 B161 MD31 MD63 1 A78 GND GND B162 1 A79 CK2 CK3 B163 4 SDCLK2 SDCLK3 4 A80 NC NC B164 A81 WP SA0 B165 A82 SDA SA1 B166 2,5,14 SMBDATA A83 SCL SA2 B167 2,5,14 SMBCLK A84 V3_3SDRAM DIMMV3_3 B168 Slave address 10100000b

Title DIMM0

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 324of A B C D E A B C D E

TP16

V2.5 TP V3_3

1 V5_0 U1

2 3 Out In 4 R4 OutTab 124 C11 V2.5 C12 1% 0.1uF C13 C14 C15 C16 C17 C18 C19 C20 C20 C20 C20 C21 C22 C23 100uF 10uF 4 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF .1uF .1uF .1uF 0.01uF 0.01uF 4 47uF 0.01uF 1 Adj/GND

R5 LT117 124 1% V3_3

Note: R4 and R5 should be placed as close as possible to U1

R6 8 7 6 5 8 7 6 5 RP1 RP2 2.7K 10K 10K 1 2 3 4 1 2 3 4 37 41 46 Stuff only to enable U2 15 9 21 48 19 33 stopping of clocks 40 R7 33 CPUCLK0 CPUCLK0 2 AVDD AVDD 39 R8 33 CPUCLK1 CPUCLK1 2

VDDPCI VDDPCI 36 R9 33 VDDREF VDDUSB VDDCPU VDDCPU CPUCLK2 2 VDDAPIC CPUCLK2 35CPUCLKR_0 R10 33 CPUCLK3 R11 0 30 CPUCLKR_1 14 CPU_STOP# CPU_STOP# R12 0 31 7CPUCLKR_2 R13 33 14 PCI_STOP# PCI_STOP# PCICLK_F PCICLKF 14 R14 0 29 8CPUCLKR_3 R15 33 CPUCLK3 PCICLK1 6 14 SUSA# PWR_DWN# PCI_CLK1 R16 33 PCI_CLK2 10 PCICLKF_R PCICLK2 6 PCI_CLK3 11 27 13PCICLKR_1 R17 33 SEL0 PCI_CLK4 PCICLK4 11 PCICLKR_2 R18 33 26 SEL1 PCI_CLK5 14 PCICLK5 7 R19 10k 25 16 R20 33 2 MAB#12 SEL100 PCI_CLK6 PCICLK6 9 3 28 CY2280 17PCICLKR_4 R21 33 3

1 1 SEL_SS# PCI_CLK7 PCICLKR_5 PCICLK7 2 PCICLKR_6 J3 J4 USBCLK0 22 R22 33 PCICLKR_7 USBCLK0 14 JUMP2 HDR2 42 RESERVED USBCLK1 23 USBCLKR_0 2 2 1 R23 33 REF0 REF0 18,21 2 R24 33 REF1 REF1 17 4 XTALIN 47 R25 33 REF2 REFR_0 REF2 14 5 XTALOUT REFR_1 APIC0 45REFR_2 APIC1 44 Keep crystal close to clock and Y1 VSS VSS VSS VSS caps close to crystal. All lead VSS 1 2 VSS VSS VSS VSS VSS lengths should be equal. 14.318MHz 32 34 38 43 3 6 12 18 20 24

USE WIDE TRACES ON CLOCKS C24 C25 10pf 10pf This circuit is only used for TX/Pentium Designs. Note only two DIMMS are supported.

This circuit is only used for BX/PentiumII Designs. Note V3_3 two DIMMS are supported.

2 2 C33 C34 C35 C36 C37 C38 C39 0.01uF 0.01uF 0.01uF 0.01uF 15uF 15uF 15uF

These caps can be tuned to These caps can be tuned change delay through to buffer. change delay through C40 C41 buffer. 10pF 10pF U4 1 16 2 BXDCLKO R33 0 2 Ref CLKOUT 15 R27 0 C40 C41 2 BxFBCLK SDCLK0 3 3 CLKA1 CLKA4 14SDCLKR0 R28 0 10pF 10pF CLKA2 CLKA3 SDCLK1 3 U4 4 13SDCLKR1 5 VDD VDD 12 1 16 6 GND GND 11 R29 0 CPUCLK3 2 Ref CLKOUT 15 CLKB1 CLKB4 SDCLK2 3 7 10SDCLKR2 R30 0 3 CLKA1 CLKA4 14 SDCLKR0 CLKB2 CLKB3 SDCLK3 3 8 9SDCLKR3 4 CLKA2 CLKA3 13 SDCLKR1 S2 S1 5 VDD VDD 12 6 GND GND 11 Zero Delay Buffer 7 CLKB1 CLKB4 10 SDCLKR2 CLKB2 CLKB3 8 9 SDCLKR3 S2 S1

Zero Delay Buffer V5_0

14 U5D U5A

9 8 1 2 CONFIG1 2,14 CONFIG1 CONFIG1# 7 74HCT14 74HCT14

1 1

Title Clocks

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 424of A B C D E A B C D E

ISA Pullups PCI Pullups

V5_0

V5_0 13,17,18,21 SD[15:0] C20 C20 RP3 .1uF 10uF 1 8 RP4 2 7 1 8 6,7 -PERR 3 6 2 7 4 2,6,7,9,11,13 -SERR 4 4 5 2,6,7,9,11,13 PAR 3 6 SD0 4 5 SD1 10K 2,6,7,9,11,13 -FRAME SD2 RP5 2.7K SD3 1 8 RP6 2 7 1 8 2,6,7,9,11,13 -IRDY 3 6 2 7 2,6,7,9,11,13 -TRDY 4 5 3 6 2,6,7,9,11,13 -DEVSEL SD4 4 5 SD5 10K 2,6,7,9,11,13 -STOP SD6 RP7 2.7K SD7 1 8 2 7 3 6 RP8 4 5 1 8 SD8 6,7,14 PIRQA# 2 7 SD9 6,9,14 PIRQB# 10K 3 6 SD10 6,11,14 PIRQC# RP9 4 5 SD11 6,11,14 PIRQD# 1 8 2 7 2.7K 3 6 SD12 4 5 SD13 RP10 10K 1 8 SD14 2,6,13 -PREQ0 2 7 SD15 2,6,13 -PREQ1 3 6 2,9,13 -PREQ2 4 5 2,11,13 -PREQ3 10K

RP11 1 8 6 SDONE 2 7 6 -SBO 3 6 6 REQ64# 4 5 6 ACK64# RP12 2.7K 13,17,18,21,22 SA[19:0] 3 1 8 3 2 7 R34 2.7K 3 6 2,6 -PLOCK SA0 4 5 R35 2.7K SA1 2 -PREQ4 SA2 10K SA3 RP13 1 8 2 7 V3_3 SA4 3 6 SA5 4 5 SA6 10K R36 10K SA7 2,13 -PHOLD RP14 R37 10K 2,13 -PHOLDA 1 8 2 7 SA8 3 6 4 5 R38 10K SA9 2 -PGNT4 SA10 SA11 10K RP15 RP16 1 8 2,11 -PGNT3 1 8 2 7 2,6 -PGNT0 2 7 3 6 2,6 -PGNT1 SA12 3 6 4 5 2,9 -PGNT2 SA13 4 5 SA14 10K SA15 10K RP17 1 8 2 7 SA16 3 6 SA17 4 5 V2.5 SA18 SA19 10K RP18 1 8 2 7 LA17 2 3 6 2 LA18 4 5 LA19 R39 1K LA20 10K 2,14 INIT R40 1K 2,14 CPURST RP19 1 8 RP20 2 7 1 8 RP21 LA21 13,18,22 MEMW# 3 6 2 7 1 8 LA22 13,17,18,21 IOW# 2,14 A20M# 4 5 3 6 2 7 13,18 LA[23:17] LA23 13,18,22 MEMR# 4 5 3 6 13,17,18,21 IOR# 10K 4 5 10K 2,14 IGNNE# RP22 2.7K 1 8 13,18 REFRESH# 2 7 RP23 18 MASTER16# RP24 3 6 1 8 13,17,18 IOCHRDY 2,14 NMI 1 8 4 5 2 7 14,17 IRQ1 13,18 ZEROWS# 2,14 INTR 2 7 3 6 14,17,18,21 IRQ3 2,14 FERR# 3 6 1K 4 5 11,14,17,18,21 IRQ4 2,14 STPCLK# 4 5 V3_3 11,14,17,18,21 IRQ5 2.7K Note IRQ8 Pull-up 10K RP25 is on PIIX4 page RP26 1 8 RP27 13,18 IOCS16# 1 8 2 7 1 8 14,17,18,21 IRQ6 13,18 MEMCS16# 2,14 SLP# 2 7 3 6 2 7 14,17,18,21 IRQ7 13,18 IOCHK# 3 6 4 5 3 6 11,14,18 IRQ9 2,3,14 SMBDATA 4 5 4 5 11,14,17,18,21 IRQ10 1K 2,3,14 SMBCLK 10K 2.7K RP28 RP29 1 8 1 8 14,18,21 IRQ11 13,18 SMEMW# 2 7 2 7 14,17,18 IRQ12 13,18 SMEMR# 3 6 3 6 14,15,17,18 IRQ14 13,18 SBHE# 4 5 4 5 11,14,17,18 IRQ15 13,18 BALE 10K 10K RP30 1 8 14,17,18 DRQ0 1 2 7 1 14,17,18 DRQ1 3 6 14,17,18 DRQ2 4 5 14,17,18 DRQ3 5.6K RP31 1 8 14,18 DRQ5 2 7 14,18 DRQ6 3 6 14,18 DRQ7 4 5

5.6K Title ISA/PCI Pullups

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 524of A B C D E A B C D E

J8/J9 V5_0: A5, A8, A10, A16, A59, A61, A62 | A1, A3, A4 B5, B6, B19, B22, B59, B61, B62

J8/J9 V3_3: A21, A27, A33, A39 A45, A53 V5_0 B25, B31, B36, B41, B43, B54

J8/J9 NC: A9, A11, A14, A19 R41 R42 R43 B10, B14 4.7K 4.7K 4.7K 4 4 J8/J9 GND: A12, A13, A18, A24, A30, A35, A37, A42, A48, A56 B3, B12, B13, B15, B17, B28, B34, B38, B46, B49, PCI_TDI PCI_TMS PCI_TCLK B57|B2 R44 J8/J9 +12V: A2 PCI_TRST 4.7K -12V: B1

V5_0 V3_3 V5_0 V3_3

C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 10uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 10uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 10uF 0.1uF 0.1uF

AD[31:0]

2,7,9,11,13 AD[31:0]

3 3 2,7,9,11,13 -C/BE[3:0]

-C/BE[3:0]

J5 J6 B1 A1 B1 A1 -12V PCI_TRST -12V PCI_TCLK B2 A2 B2 A2 B3 TCK +12V A3 B3 TCK +12V A3 GND TRST PCI_TMS GND TRST PCI_TRST B4 TMS A4 B4 TMS A4 TDO PCI_TDI PCI_TCLK TDO B5 TDI A5 B5 TDI A5 V5_0 V5_0 V5_0 V5_0 PCI_TMS B6 A6 B6 A6 V5_0 INTA PIRQD# 5,11,14 V5_0 INTA PCI_TDI B7 A7 B7 A7 5,7,14 PIRQA# INTB PIRQB# 5,9,14 INTB B8 A8 B8 A8 5,11,14 PIRQC# INTD INTC INTD INTC PIRQA# B9 A9 B9 A9 NC PIRQB# NC PIRQC# B10 V5_0 A10 B10 V5_0 A10 PRSNT1 V5_0 PIRQD# PRSNT1 V5_0 B11 NC A11 B11 NC A11 NC NC C60 B12 PRSNT2 A12 C61 C62 B12 PRSNT2 A12 GND GND 0.01uF B13 GND A13 0.01uF 0.01uF B13 GND A13 GND GND C63 GND GND B14 NC A14 B14 NC A14 0.01uF B15 NC A15 B15 NC A15 RST -PCIRST 2,7,9,10,11,13 RST B16 GND A16 B16 GND A16 V5_0 4 PCICLK2 V5_0 B17 CLK A17 B17 CLK A17 -PCIRST 4 PCICLK1 GNT -PGNT0 2,5 GNT -PGNT1 2,5 B18 GND A18 B18 GND A18 2,5,13 -PREQ0 GND 2,5,13 -PREQ1 GND PCICLK1 B19 REQ NC A19 B19 REQ NC A19 B20 AD[30] A20 B20 AD[30] A20 V5_0AD[31] AD[31]V5_0 B21 V3_3 A21 B21 V3_3 A21 AD[29] AD[29] AD31 B22 A22 AD30 AD28 AD31 B22 A22 AD30 AD29 GND AD[28] GND AD[28] AD29 B23 A23 R45 AD29 B23 A23 R46 AD[27] AD[26] AD[27] AD[26] B24 A24 AD28 B24 A24 AD28 AD[25] GND 220 AD[25] GND 220 AD27 B25 A25 AD26 AD27 B25 A25 AD26 V3_3 AD[24] V3_3 AD[24] AD25 B26 A26 AD25 B26 A26 C/BE3 IDSEL C/BE3 IDSEL -C/BE3 B27 A27 AD24 -C/BE3 B27 A27 AD24 V3_3 PCIA2 V3_3 PCIB2 B28 AD[23] AD[22] A28 B28 AD[23] AD[22] A28 AD23 B29 GND A29 AD23 B29 GND A29 AD[21] AD[20] AD[21] AD[20] B30 A30 AD22 B30 A30 AD22 AD[19] GND AD[19] GND AD21 B31 A31 AD20 AD21 B31 A31 AD20 2 V3_3 AD[18] V3_3 AD[18] 2 AD19 B32 A32 AD19 B32 A32 AD[17] AD[16] AD18 AD[17] AD[16] AD18 B33 A33 B33 A33 AD17 C/BE2 V3_3 AD16 AD17 C/BE2 V3_3 AD16 B34 A34 B34 A34 -C/BE2 FRAME -FRAME 2,5,7,9,11,13 -C/BE2 FRAME B35 A35 B35 A35 2,5,7,9,11,13 -IRDY GND GND -FRAME B36 GND A36 B36 GND A36 IRDYV3_3 -TRDY 2,5,7,9,11,13 -IRDY V3_3IRDY B37 TRDYGND A37 B37 TRDYGND A37 2,5,7,9,11,13 -DEVSEL GNDDEVSEL DEVSELGND -TRDY B38 STOP A38 B38 STOP A38 LOCK -STOP 2,5,7,9,11,13 -DEVSEL LOCK B39 V3_3 A39 B39 V3_3 A39 2,5 -PLOCK PERR PERR -STOP B40 SDONE A40 B40 SDONE A40 5,7 -PERR V3_3 SDONE 5 -PLOCK V3_3 B41 SBO A41 B41 SBO A41 2,5,7,9,11,13 -SERR -SBO 5 -PERR SDONE B42 GND A42 B42 GND A42 SERR PAR 2,5,7,9,11,13 -SERR SERR -SBO B43 PAR A43 B43 PAR A43 V3_3 V3_3 PAR B44 AD[15] A44 B44 AD[15] A44 -C/BE1 C/BE1 -C/BE1 C/BE1 B45 AD[14] V3_3 A45 AD15 B45 AD[14] V3_3 A45 AD15 B46 GND A46 B46 GND A46 AD14 AD[13] AD14 AD[13] B47 AD[12] A47 B47 AD[12] A47 AD[11] AD13 AD[11] AD13 AD12 B48 A48 AD11 AD12 B48 A48 AD11 GNDAD[10] GND AD[10]GND GND AD10 B49 AD[09] A49 AD10 B49 AD[09] A49 AD9 AD9 AD[08] AD[08] B52 C/BE0 A52 B52 C/BE0 A52 AD8 B53 AD[07] V3_3 A53 AD8 B53 AD[07] V3_3 A53 AD[06] AD[06] AD7 B54 V3_3 A54 AD7 B54 V3_3 A54 AD[04] AD[04] B55 AD[05] A55 AD6 B55 AD[05] A55 AD6 AD5 B56 AD[03] GND A56 AD4 AD5 B56 AD[03] GND A56 AD4 AD3 B57 GND AD[02] A57 AD3 B57 GND AD[02] A57 B58 AD[00] A58 AD2 B58 AD[00] A58 AD2 AD[01] AD[01] AD1 B59 ACK64 A59 AD0 AD1 B59 ACK64 A59 AD0 V5_0 V5_0 B60 V5_0 A60 B60 V5_0 A60 5 ACK64# V5_0 REQ64 REQ64# 5 ACK64# V5_0 REQ64 REQ64# B61 V5_0 A61 B61 V5_0 A61 B62 A62 B62 A62 V5_0 V5_0 PCI Conn PCI Conn

-C/BE0 -C/BE0 PCI SLOT 1 1 PCI SLOT 0 1

Title PCI Slots 0 & 1

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 624of A B C D E A B C D E

V3_3

DCKVCC MCKVCC DACVCCU6 U5 B3 C4 D5 D9 W12 H4 N4 U8 U13 W1 D13 H17 N17 A1 B5 C2 C5 D3 D4 D8 Y20 V3_3 PLACE THESE CAPS CLOSE TO POWER PINS (CORVCC, IOVCC, MEMVCC)

C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 IOVCC IOVCC IOVCC IOVCC IOVCC DACVCC DCKVCC DCKVCC MCKVCC CORVCC CORVCC MEMVCC MEMVCC MEMVCC

2,6,9,11,13 AD[31:0] RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED P[23:0] 8 0.1uF tant. 0.1uF tant. 0.1uF tant. 0.1uF tant. 0.1uF tant. 0.1uF tant. 0.1uF tant. 0.1uF tant. 0.1uF tant. 0.1uF tant. U2 W6 4 AD0 P0 4 T3 V7 AD1 P1 R4 Y6 AD2 P2 T2 W7 AD0 AD3 P3 P0 U1 AD4 P4 V8 AD1 R3 Y7 P1 AD2 AD5 P5 P2 T1 AD6 P6 W8 V3_3 AD3 R2 U9 P3 AD4 AD7 P7 P4 FB1 R1 AD8 P8 V9 1 2 1/4 W AD5 P2 Y8 P5 12 AD6 AD9 P9 P6 10 R47 N3 AD10 P10 W9 BLM41A800S C74 C75 C76 AD7 P1 Y9 P7 AD8 AD11 P11 P8 N2 AD12 P12 V10 0.1uF 47uF tant. DCKVCC0.1uF AD9 P9 AD10 M4 AD13 P13 W10 P10 AD11 M3 AD14 P14 Y10 P11 N1 AD15 P15 U10 2 AD12 P12 AD13 AD13 J1 AD16 P16 U11 P13 DCKGNDFB2 AD14 J2 AD17 P17 Y11 P14 AD15 H1 AD18 P18 W11 P15 AD16 J3 AD19 P19 V11 P16 12 BLM41A800S AD17 J4 AD20 P20 Y12 P17 AD18 H2 AD21 LCD INTERFACE P21 Y13 P18

1 THE 69000 IS R48 AD19 G1 AD22 P22 V12 P19 PCI DEVICE #3 220 AD20 H3 AD23 P23 U12 P20 1/4 W AD24 P24 FB3 AD21 G3 W13 P21 P[35:24] 8 1 2 F2 AD25 PCI SIGNALS P25 Y14 12 AD22 P22 10 R49 AD23 E1 AD26 P26 V13 P23 BLM41A800S C77 C78 C79 AD24 F3 AD27 P27 W14 P24 MCKVCC AD25 D1 AD28 P28 Y15 P25 0.1uF 47uF tant. 0.1uF AD26 E2 AD29 P29 V14 P26 AD27 F4 AD30 P30 W15 P27 2 AD28 E3 AD31 P31 Y16 P28 2,6,9,11,13 -C/BE[3:0] FB4 AD29 P3 C/BE0# P32 V15 P29 MCKGND AD30 M2 C/BE1# P33 Y17 P30 C/BE2# P34 AD31 K3 W16 P31

12 C/BE3# P35 BLM41A800S -C/BE0 F1 U15 P32 -C/BE1 SHFCLK P33 IDSEL FLM Y5 SHFCLK 8

1 -C/BE2 P34 G2 RESET# LP/CL1/DE/BLANK# W5 FLM 8 3 -C/BE3 C1 Y4 P35 3 2,6,9,10,11,13 -PCIRST BUSCLK M/DE/BLANK# LP 8 D2 V6 4 PCICLK5 PAR ENAVDD M8 FB5 M1 V5 2,5,6,9,11,13 PAR FRAME# ENAVEE ENAVDD 8 1 2 K2 W4 12 2,5,6,9,11,13 -FRAME IRDY# ENABKL K1 U6 2,5,6,9,11,13 -IRDY TRDY# ENABKL 8 C80 BLM41A800S C81 C82 C83 K4 DACVCC 2,5,6,9,11,13 -TRDY STOP# VREF L1 V16 2,5,6,9,11,13 -STOP DEVSEL# HREF .1uF FB6 0.1uF 22uF tant. 0.1uF L4 W17 2,5,6,9,11,13 -DEVSEL PERR# VCLK 1 2 L2 Y18 12 5,6 -PERR SERR# PCLK/VCLKOUT L3 V17 2,5,6,9,11,13 -SERR INT# VP0 BLM41A800S A4 VP1 R18 5,6,14 PIRQA# VP2 U20 W3 VP3 T19 8 BLUE V4 BLUE VIDEO INTERFACE VP4 R17 8 GREEN V3_3 Y3 GREEN VP5 T18 8 RED CRT INTERFACE U3 RED VP6 U19 8 HSYNC/CSYNC V2 HSYNC/CSYNC VP7 V20 8 VSYNC V3 VSYNC VP8 T17 8 DDCDATA C84 C85 C86 C87 C88 C89 C90 U4 DDC DATA/GPIO2 VP9 U18 8 DDCCLK DDCCFG0 CLK/GPIO3 VP10 V19 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 22uF tant. D18 CFG1 VP11 W20 C19 CFG2 VP12 W19 B20 CFG3 VP13 U17 C18 CFG4 VP14 V18 V5_0 A20 CFG5 VP15 Y19 FB7 U7 R50 B19 CFG6 W18 1 2 8 5 A19 CFG7 12 +5VDC OUT +12V 1 4 B18 CFG8 A10 O/E GND CFG9 NC C91 C92 BLM41A800S C93 C94 100 C17 A11 CFG10 NC R51 20k 14.31818MHz Osc D16 A18 CFG11 NC 0.1uF 0.1uF 47uF tant. 0.1uF V3_3 B10 B11 CFG12 NC C95 C96 C10 B17 CFG13 NC A9 CFG14 NC C11 0.1uF 22uF tant. B9 CFG15 NC C16 R52 A8 NC C20 C9 NC D10 11k NC D11 E4 STNDBY# NC D19 2 C97 1% 2 C3 REFCLK/MCLKIN NC D20 R53 560 W2 RSET NC E17 V5_0 R54 A12 E18 DACVCC TMD1 MISC SIGNALS NC 0.1uF tant. D17 TMD0 NC E19 ACTIVITY LED D1 D6 GPIO7 NC E20 2MEG U16 F17 LED GPIO4 NC C98 C99 C100 C101 C102 C103 C104 C105 B1 MCLKIN NC F18 U8A U8B U8C R55 150 B2 DCLKIN NC F19 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 22uF tant. 22uF tant. C106 Y2 V1 GPIO0/ACTI NC F20 2 1 1 2 3 4 5 6 R56 100 T4 GPIO1/32KHzRMD0 NC G18 RMD1 NC G19 22pF 32.768KHz B8 RMD2 NC G20 74ACT04 74ACT04 74ACT04 RMD0 A7 RMD3 NC H18 RMD1 C8 RMD4 NC H19 RMD2 B7 RMD5 NC H20 V5_0 AVCC RMD3 A6 RMD6 NC J17 RMD4 C7 RMD7 NC J18 FB8 RMD5 B6 RMA0 NC J19 1 2 U9 RMD6 A5 RMA1 NC J20 12 11 10RMD7 D15 RMA2 NC K17 RMA3 NC C107 BLM41A800S C108 C109 RMD0 12 D0 A0 9 B16 BIOS ROM INTERFACE K18 RMD1 13 D1 A1 8 A17 RMA4 NC K19 0.1uF 0.1uF 22uF tant. RMD2 15 D2 A2 7 C15 RMA5 NC K20 NC RMD3 16 D3 A3 6 A16 RMA6 L17 RMA7 NC RMD4 17 D4 A4 5 B15 L18 RMA8 NC RMD5 18 D5 A5 4 C14 M17 RMA9 NC RMD6 19 D6 A6 3 A15 M18 RMA10 NC RMD7 D7 A7 25 B14 M19 A8 RMA11 NC FB9 24 C13 RMA12 NC M20 1 2 A9 21 A14 T20 12 A10 RMA13 NC 23 B13 RMA14 NC R20 BLM41A800S A11 2 D12 R19 A12 RMA15 NC 26 C12 RMA16 NC P20 FB10 A13 27 A13 P19 A14 RMA17 NC 1 2 V3_3 1 B12 P18 12 A15 69000 NC BIOS EXPANSION ROM L19 NC N20 BLM41A800S 28 20 L20 N19 VCC CE ROMOE#/MCLKOUT NC 1 22 C6 N18 1 OE FB11 C110 27512 1 2 12 0.1uF tant. BLM41A800S RGND RGND RGND RGND RGND MEMGND MEMGND MEMGND J10 J9 U7 U14 P4 G4 D7 Y1 M12 M11 M10 M9 P17 G17 D14 B4 A3 A2 Y2 L12 L11 L10 L9 K12 K11 K10 K9 J12 J11 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND DCKGND DCKGND MCKGND DACGND

DCKGND Title MCKGND 69000 Part 1

Size Document Number Rev C LCD/CRT Controller A

Date:Thursday, October 22, 1998 Sheet 724of A B C D E A B C D E PANEL CONNECTOR J7 USED TO CONTROL 1 7 P[23:0] 14V5_0 U10A FB12 1 2 15 13 VOLTAGE TO 12 BLM41A800S 11 FLAT PANEL 2 3 R57 FB13 1 2 FB14 16 15 13 10 12 1 2 BLM41A800S 11 8 V5_0 7 VSYNC 12 7 74HCT125 FB15 1 2 18 16 10 7 JP1 P0 12 SHFCLKC 33 C111 V5_0 BLM41A800S 8 5 FLMC BLM41A800S V5_0 V5_0 1 2 FB16 19 18 7 4 3 P1 12 LPC 2 470pF BLM41A800S 5 3 DE 1 P2 FB17 1 2 21 19 4 2 MC 12 AVCC AVCC F1 BLM41A800S 3 1 ENABKLC V3_3 14V5_0 4 U10B P3 1 2 FB18 22 21 2 HEADER 3 R58 R59 12 BLM41A800S 1 VEESAFE 5 6 R60 FB19 D2 D4 P4 FB20 1 2 24 22 +12VSAFE 12 1 2 15k 15k 3AMP BLM41A800S VDDSAFE 7 HSYNC/CSYNC 12 24 7 74HCT125 1N4148 1N4148 U11 P5 1 2 FB22 25 4 12 4 33 C112 1 2 FB21 BLM41A800S 7 DDCCLK 12 25 BLM41A800S BLM41A800S 15 P6 FB23 1 2 27 15 12 470pF 14 BLM41A800S 14 27 13 P7 1 2 FB24 28 13 12 BLM41A800S 12 12 28 FB25 CRT CONNECTORP8 FB26 1 2 11 11 1 2 30 7 DDCDATA 12BLM41A800S BLM41A800S 12 D3 D5 10 10 30 C114 C115 9 P9 1 2 FB27 31 9 12 1N4148 1N4148 8 BLM41A800S 8 P10 31 V5_0 470pF 470pF 7 FB28 1 2 33 7 12 6 BLM41A800S 6 P11 33 C113 5 5 1 2 FB29 34 12 BLM41A800S 4 4 P12 34 0.1uF 3 3 FB30 1 2 36 U12A AD8073 BLM41A800S 12 2 2 P13 36 5 R61 1 1 2 FB31 37 1 12 +IN 7 BLM41A800S 37 6 OUT P14 6 -5V FB33 1 2 39 6 9 -IN 12 AVCC AVCC AVCC CON15 P15 BLM41A800S 39 9 12 R62 1k R63 C116 75 1 2 FB35 40 12 14 12 BLM41A800S 40 14 17 1k P16 0.1uF D2 D4 D6 FB37 1 2 42 17 20 12 P17 BLM41A800S 42 20 23 1N4148 1N4148 1N4148 1 2 FB38 43 23 26 12 U12B AD8073 2 1 FB32 BLM41A800S 43 26 29 7 BLUE 2 1 P18 12 R64 BLM41A800S FB39 1 2 45 29 32 7 GREEN +IN 12 14 2 1 FB34 P19 BLM41A800S 45 32 35 7 RED OUT 2 1 13 BLM41A800S 1 2 FB40 46 35 38 -IN 12 2 1 FB36 P20 BLM41A800S 46 38 41 2 1 41 R66 R67 R68 R65 1k R69 75 BLM41A800S FB41 1 2 48 44 12 D3 D5 D7 C117 C118 C119 P21 BLM41A800S 48 44 47 1k 75 75 75 1 2 FB42 49 47 50 1N4148 1N4148 1N4148 47pF 47pF 47pF P22 12 BLM41A800S 49 50 CON50 U12C AD8073 P23 10 R70 +IN 8 OUT 3 9 3 -IN R71 1k R72 75 1k

FB43 1 2 7 ENABKL BLM41A800S 12 MC R73 DE 1 2 FB44 7 M ENABKL ENABKLC 12 BLM41A800S 0 R74 0 FB45 M 1 2 7 LP BLM41A800S 12 FB46 LP 1 2 LPC 7 FLM 12 BLM41A800S FLM FB47 1 2 FLMC 7 SHFCLK BLM41A800S 12 SHFCLK SHFCLKC U13 JP1 F2

3 2 1 HEADER 3

+12V V5_0 V3_3 C1243AMP C125 +12VSAFE 10uF tant. .1uF 1 8 S1 D1 2 7 G1 D1 V5_0 V5_0 R75 3 6 S2 D2 4 5 F3 50k G2 D2

C120 C121 C122 C123 Si9953DY C126 C1273AMP VDDSAFE Q1 10uF tant. 0.1uF 0.1uF 10uF tant. 7 ENABKL 10k R76 2N3904 10uF tant. 0.1uF R82 ENABKL 1K RPOT V5_0 1/4W

V5_0 J8 JP1 VEESAFE 2 U14 2 1-2 ENABLE TV OUT RCA JACK 50k R79 1 14 4 2-3 DISABLE TV OUT AD725 Q2 2 7 ENAVDD 10k R81 2N3904 3 ENAVDD PANEL CONNECTOR 2 C128 0.1Uf C129220uF tant. R78 75 APOS 5 DPOS TV OUT (36-Bit) HEADER 3 CE 10 C130 0.1uF 8 CMPS 7 BLUE 7 BIN J9 7 GREEN C131 0.1uF 6 GIN C132220uF tant. R80 75 7 7 RED SLD RIN 11 4 6 LUMA SLD 15 LUMA 3 5 7 VSYNC VSYNC GND SLD 16 2 GND 7 HSYNC/CSYNC HSYNC C133220uF tant. R82 75 J10 3 1 CRMA 4FSC 9 CRMA 1 STND 7 P[35:24] R83 12 SVIDEO FB48 1 2 2 YTRAP 12 P24 BLM41A800S 2 1 2 FB49 4 12 1MEG DGND AGND P25 BLM41A800S 4 14 14 FB50 1 2 6 C134 12 U8D U8E 13 2 P26 BLM41A800S 6 9 8 11 10 1 2 FB51 8 12 P27 BLM41A800S 8 7 74ACT04 R847 74ACT04 FB52 1 2 10 12 47pF P28 BLM41A800S 10 1 Y3 200 1 2 FB53 12 1 3 12 2 1 P29 BLM41A800S 12 3 5 FB54 1 2 14 5 7 12 14.318180MHz (NTSC) C135 P30 BLM41A800S 14 7 9 1 2 FB55 16 9 11 12 60pF P31 BLM41A800S 16 11 13 FB56 1 2 18 13 15 12 P32 BLM41A800S 18 15 17 1 2 FB57 20 17 19 P33 12 BLM41A800S 20 19 21 V5_0 FB58 1 2 22 21 23 P34 12 JP2 BLM41A800S 22 23 25 1 1-2 NTSC C1369pF L1 68uH FB59 25 1 P35 1 2 24 26 2-3 PAL 1 12 BLM41A800S 24 26 2 NOTE: FOR PAL 3 CRYSTAL MUST R85 47k D8 CON26 C137 ALSO BE CHANGED HEADER 3 18pF 1N4148 INSTALL FOR TV OUT CAPABILITY. IF POPULATED PLACE CLOSE TO CRT Title CIRCUIT 69000 Part 2

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 824of A B C D E A B C D E

4 4

C138 C139 C140 C141 C142 C143 C144 C145

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF V5_0

U15 12 25 37 50 62 74 85 100

79 VDD VDD VDD VDD VDD VDD VDD VDD 84 JYSTK0 PCICLK6 4 78 82 JYSTK1 CLK -PCIRST 2,6,7,10,11,13 77 JYSTK2 RST# 76 JYSTK3 46 AD[31:0] 2,6,7,11,13 73 JYSTK4 45 MIDI AD[0] 72 JYSTK5 AD[1] 44 71 JYSTK6 AD[2] 43 AD0 70 JYSTK7 AD[3] 41 AD1 68 MIDI_IN AD[4] 40 AD2 AD3 69 MIDI_OUT AD[5] 39 AD[6] 38 AD4 5-WIRE AC97 LINK' AD[7] 34 AD5 AD[8] 33 AD6 AD[9] 32 AD7 3 60 30 AD8 3 10 BIT_CLK BCLK AD[10] 59 29 AD9 10 SDATA_IN SDATA_IN AD[11] 58 SYNC AD[12] 28 AD10 10 SYNC 61 SDATA_OUT AC97 LINK AD[13] 27 AD11 10 SDATA_OUT AD[14] 24 AD12 2,6,7,10,11,13 ACRESET# -PCIRST 2,6,7,10,11,13 AD13 AD[15] 13 AD14 AD[16] 10 AD15 ES1371 AD[17] 9 AD16 AD[18] 8 AD[19] AD17 7 AD18 AD[20] 5 AD[21] AD19 4 AD20 PCI SIGNALS AD[22] 3 AD[23] AD21 AD27 98 AD22 THE ES1371 IS AD[24] 97 R86 PCI DEVICE #16 AD[25] AD23 96 AD24 220 AD[26] 94 AD[27] AD25 93 AD26 AD[28] 92 AD[29] AD27 91 AD28 AD[30] 89 AD[31] AD29 AD30 99 GPIO(3) C/BE[3]# AD31 56 GPIO(2) C/BE[2]# 14 -C/BE[3:0] 2,6,7,11,13 -C/BE3 55 GPIO(1) C/BE[1]# 23 54 GPIO(0) C/BE[0]# 35 -C/BE2 53 -C/BE1 22 -C/BE0 I2S_LCLKIN PAR PAR 2,5,6,7,11,13 52 I2S_BCLKIN FRAME# 15 -FRAME 2,5,6,7,11,13 49 I2S_SERIN TRDY# 18 -TRDY 2,5,6,7,11,13 48 IRDY# 16 -IRDY 2,5,6,7,11,13 20 STOP# -STOP 2,5,6,7,11,13 XTAL0_BUF IDSEL 2 63 19 10 XTAL0_BUF XTAL0 DEVSEL# -DEVSEL 2,5,6,7,11,13 66 XTALI 1k R87 65 REQ# 87 -PREQ2 2,5,13 GNT# 86 -PGNT2 2,5 2 2 1MEG R88 SERR# 21 -SERR 2,5,6,7,11,13 NC INTA# Y4 81 PIRQB# 5,6,14 1 2 88

24.576 MHz ES1371 GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD C146 C147 GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD 1 6 11 17 26 31 36 42 47 51 57 64 67 75 80 83 90 95 22pF 22pF

1 1

Title AC97 Audio Part 1

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 924of A B C D E A B C D E

AUXJP3 INPUTC175 4 3 1uF C176 2 1 AUX_R 1uF 1x4 AUX_L

4 4

CDROM AUDIO HEADER C177

H1 1uF 2mm 1 C178 pitch G 2 CD_L L 3 keyed G plug 4 1uF R C179 CD_GND HEADERCD 1uF CD_R MONO OUT JP4 C180

1 +12V U?? MC78M05CDT 2 1uF MONO_OUT 1 3 HEADER 2 Vin +5V

C163 C149 GND C149 C163

1uF tant. 0.1uF 2 0.1uF 1uF tant. FB65 V5_0 2 1 LINE LEVEL OUT 2 1 JP5 C181 3 HZ0805E601R 3 4 3 1uF C182 2 LNLVL_OUT_R 1 1uF 1x4 LNLVL_OUT_L C148 C149 V5_0 C150 C151 0.1uF 0.1uF

0.1uF 0.1uF R90 R91 38 1 9 U16 25 Do Not Install Do Not Install 5-WIRE AC97 LINK 12 6 AVdd1 AVdd2 DVdd1 DVdd2 BIT_CLK 9 C152 PC_BEEP BIT_CLK MICROPHONE 13 8 SDATA_IN 9 SDATA_IN 10 SYNC 9 C153 C154 PHONE_IN SYNC 0.0 R92 14 5 SDATA_OUT 9 J11 1uF 15 SDATA_OUT 11 0.0 R93 AUX_L ACRESET# 2,6,7,9,11,13 1 FB60 470pF NPO 1nF RESET# 0.0 R94 AUX_L AUX_R 2 1 2 37 40 12 AUX_R NC 1k R95 43 R96 R97 R98 MONO_OUT NC 3 HZ0805E601R MONO_OUT 16 44 NC Do Not Install Do Not Install Do Not Install R99 17 MICROPHONE VIDEO_L 2.21k VIDEO_R 21 22 MIC1 27 MIC1 28 MIC2 VREF C155 C156 C157 LINE INPUT VREFOUT 34 VREFOUT CX3D 33 10uF tant. .1uF 41 RX3D 0.1uF C158 J12 C159 C160 39 LNLVL_OUT_R AD1819A CS0 45 LNLVL_OUT_R 1 FB61 R100 LNLVL_OUT_L CS1 46 47nF 2 1 2 470p NPO 1nF NPO LNLVL_OUT_L 47 12 CHAIN_IN 47.5k CHAIN_CLK 48 3 HZ0805E601R C161 1uF 23 FB62 1k R101 2 LINE_IN_L 32 2 LINE INPUT 1 2 C162 1uF LINE_IN_L 24 FILT_L 31 12 1k R102 LINE_IN_R FILT_R 30 C163 C164 LINE_IN_R HZ0805E601R C165 C166 R103 AFILT2 29 AFILT1 C167 C168 1uF tant. 1uF tant. 470pF NPO 1nF NPO 47.5k 18 270pF NPO 270pF NPO CD_L LINE OUTPUT CD_L 19 20 CD_GND CD_GND CD_R CD_R C169 C170 R104 C171 J13 1nF NPO LINE_OUT_L XTL_IN 35 2 XTAL0_BUF 9 1 470pF NPOFB63 47.5k 1k R105 C172 LINE_OUT_L 2 1 2 1uF 36 LINE_OUT_R XTL_OUT 3 12 1k R106 LINE_OUT_R 3 HZ0805E601R 1uF AD1819A

FB64 AVss1 AVss2 DVss1 DVss2

LINE OUTPUT 1 2 26 42 4 7 12 HZ0805E601R R107 C173 FB65 C174 1 2 47.5k 1nF NPO 12 470pF NPO HZ0805E601R

ALL RESISTORS AND CAPACITORS ARE 1/8 W

SEE APPLICATION NOTE FOR LAYOUT GUIDELINES

1 1

Title AC97 Audio Part 2

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 10of 24 A B C D E A B C D E

PCMCIA_Socket 4 4 U17 A_A0 A_A1 A_A2 A_A3 A_A4 A_A5 A_A6 A_A7 A_A8 A_A9 A_A10 A_A11 A_A12 A_A13 A_A14 A_A15 A_A16 A_A17 A_A18 A_A19 A_A20 A_A21 A_A22 A_A23 A_A24 A_A25 A_D0 A_D1 A_D2 A_D3 A_D4 A_D5 A_D6 A_D7 A_D8 A_D9 A_D10 A_D11 A_D12 A_D13 A_D14 A_D15 A_BVD1(STSCHG#/RI#) A_BVD2(SPKR#) A_CD1# A_CD2# A_CE1# A_CE2# A_INPACK# A_IORD# A_IOWR# A_OE# A_READY(REQ#) A_REG# A_RESET A_WAIT# A_WE# A_WP(IOIS16#) A_VS1# A_VS2# GND GND GND GND Vcc Vcc Vpp2 Vpp1 2 3 4 5 6 64 65 66 37 38 39 40 41 63 62 36 67 7 42 60 44 45 9 16 61 58 59 15 33 43 57 68 1 34 35 51 17 52 18 29 28 27 26 25 24 23 22 12 11 8 10 21 13 14 20 19 46 47 48 49 50 53 54 55 56 30 31 32

C183 8 5 -PCIRST 2,6,7,9,10,13 0.1uF 11 AVPP LATCH 4 10 AVCC CLOCK 3 LATCH A_A0 A_A2 A_A3 A_A4 A_A5 A_A6 A_A7 A_A8 A_A9 A_D10 A_D11 A_D12 A_D13 A_D14 A_D15 A_A1 A_A10 A_A11 A_A12 A_A13 A_A14 A_A15 A_A16 A_A17 A_A18 A_A19 A_A20 A_A21 A_A22 A_A23 A_A24 A_A25 A_D0 A_D1 A_D2 A_D3 A_D4 A_D5 A_D6 A_D7 A_D8 A_D9 CLOCK A_CE1# A_CE2# A_IORD# A_IOWR# A_REG# A_RESET A_WAIT# 9 AVCC DATA A_CD1# A_CD2# A_OE# A_WE# A_VS1# A_VS2# AVCC 6 DATA V3_3 V5_0 +12V A_INPACK# C184 RESET A_READY(REQ#) A_WP(IOIS16#) 14 A_BVD2(SPKR#) 0.1uF 23 RESET# A_BVD1(STSCHG#/RI#) 22 BVPP 18 21 BVCC OC# 83 85 88 90 92 142 145 147 84 87 89 91 93 138 137 82 140 94 97 127 99 101 98 135 130 124 136 110 139 134 122 133 132 131 128 126 125 123 119 104 102 95 100 117 106 108 115 112 103 105 107 109 111 114 116 118 121 141 144 146 20 BVCC 15 C185 C186 BVCC 3.3V 16 1uF 0.1uF 3.3V 17 A_A0 A_A1 A_A2 A_A3 A_A4 A_A5 A_A6 A_A7 A_A8 A_A9 A_D0 A_D1 A_D2 A_D8 A_D9 A_D3 A_D4 A_D5 A_D6 A_D7 3.3V 1 A_A10 A_A11 A_A12 A_A13 A_A14 A_A15 A_A16 A_A17 A_A18 A_A19 A_A20 A_A21 A_A22 A_A23 A_A24 A_A25 A_D10 A_D11 A_D12 A_D13 A_D14 A_D15 A_OE# 4 PCICLK4 A_WE# 5V A_VS1# A_VS2# A_CE1# A_CE2# A_CD2# 180 A_CD1# 2 A_REG# A_WAIT# A_IORD#

2,6,7,9,10,13 -PCIRST A_RESET A_IOWR# 5V 166 PCLK 30 C187 C188 A_INPACK# 5V 24 1uF 0.1uF 2,6,7,9,13 AD[31:0] PRST# 12V 15 7 AD0 A_WP(IOIS16#) 12V A_BVD2(SPKR#)

14 A_READY(REQ#) AD1 12 12 GND AD0 11 AD2 67 AD3 B_A0 B_A[24:1] 12 AD1 10 A_BVD1(STSCHG#/RI#) 66 AD4 B_A1 AD2 9 65 B_A2 AD3 8 AD5 62 TI_TPS2206 AD6 PC CARD AD4 6 B_A3 60 B_A1 AD5 4 AD7 SLOT A B_A4 59 B_A2 U18 AD6 3 AD8 B_A5 57 B_A3 3 AD7 2 AD9 B_A6 54 B_A4 3 AD10 AD8 172 B_A7 39 B_A5 B_A8 AD9 208 36 B_A6 AD12AD11 AD10 206 29 B_A7 AD11 205 B_A9 34 B_A8 AD12 AD13 B_A10 B_A9 204 52 AD13 AD14 B_A10 191 B_A12B_A11 41 AD14 AD15 B_A13 B_A11 AD16 190 AD16 43 AD15 AD17 B_A14 B_A12 189 50 AD16 B_A13 188 AD18 B_A15 48 AD17 AD19 B_A16 B_A14 AD18 186 37 B_A15 U19 185 40 AD19 AD20 B_A18B_A17 B_A16 AD20 184 AD21 B_A19 42 B_A17 183 45 TI_PCI1221 AD21 AD22 PCI BUS B_A20 B_A18 R108 THE PCI1221 IS 179 47 AD22 AD24AD23 B_A21 B_A19 PCI DEVICE #5 165 49 220 AD23 AD25 B_A22 B_A20 AD24 177 B_A23 51 B_A21 176 AD26 53 AD25 AD27 B_A24 B_A22 AD26 174 B_A25 55 B_A23 AD28 AD27 173 B_A24 B_D[15:0] 12 171 AD29 76 AD28 B_D0 170 AD30 78 AD29 B_D1 AD30 AD31 80 B_D0 2,6,7,9,13 -C/BE[3:0] B_D2 AD31 5 C/BEO# PC CARD B_D317 B_D1 203 B_D419 B_D2 C/BE1# B_D5 -C/BE0 192 C/BE2# SLOT B 21 B_D3 -C/BE1 162 24 B_D4 -C/BE2 C/BE3# (FLASH) B_D6 26 B_D5 -C/BE3 202 B_D7 77 B_D6 2,5,6,7,9,13 PAR PAR B_D8 197 79 B_D7 2,5,6,7,9,13 -DEVSEL B_D9 V5_0 193 FRAME#DEVSEL# 81 B_D8 2,5,6,7,9,13 -FRAME B_D10B_D11 168 18 B_D9 2,5 -PGNT3 GNT# B_D12 182 20 B_D10 IDSEL 195 23 B_D11 V5_0 2,5,6,7,9,13 -IRDY IRDY# B_D13 199 25 B_D12 PERR# B_D14 169 27 B_D13 2,5,13 -PREQ3 REQ# B_D15 200 B_D14 2,5,6,7,9,13 -SERR SERR# B_BVD1(STSCHG#/RI#) 198 72 B_D15 2 2,5,6,7,9,13 -STOP STOP# B_BVD2(SPKR#) B_BVD1(STSCHG#/RI#) 2 196 71 2,5,6,7,9,13 -TRDY TRDY# B_CD1# B_BVD2(SPKR#) B_CD2# 16 154 74 5,6,14 PIRQC# MFUNC0 B_CD1# 155 28 5,6,14 PIRQD# MFUNC1 B_CE1# B_CD2# B_CE1# 12 157 30 5,14,17,18,21 IRQ4 MFUNC2 B_CE2# B_CE1# B_CE2# 12 V3_3 158 B_INPACK# 61 B_INPACK# 5,14,17,18,21 IRQ5 MFUNC3 B_CE2# 159 33 5,14,18 IRQ9 MFUNC4 B_IORD# V3_3 160 35 1K R109 5,14,17,18,21 IRQ10 MFUNC5 161 B_READY(IREQ#)B_IOWR# 32 5,14,17,18 IRQ15 MFUNC6 B_OE# B_OE# R109 43K 163 69 B_READY(IREQ#) RI_OUT#/PME# B_REG# B_OE# R109 43K 156 63 SUSPEND# B_RESET 149 B_WAIT# 58 SPKROUT B_WAIT# B_WE# 70 LATCH 150 B_WP(IOIS16#) 46 CLOCK LATCH B_WE# 151 73 B_WE# DATA CLOCK B_VS1# 152 DATA B_WP(IOIS16#) B_VS2# 68 56 R110 1K Vcc Vcc Vcc Vccb Vccp Vccp GND GND GND GND GND GND GND GND GND Vcc Vcc Vcc Vcc Vcc Vcci Vcc Vcca GND GND Vcc 187 201 120 38 148 178 1 13 22 44 75 96 129 153 167 181 194 207 7 31 64 86 113 143 164 175

C184 C189 C190 C191 C192 C193 C194 C184 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1uF

1 1

V3_3 V5_0

Title PCI1221

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 11of 24 A B C D E A B C D E

4 4

V5_0 V5_0

C195 C196 C197 0.1uF 47uF 0.1uF

U20 U21 A5 A2 J4 A5 A2 J4 28FXX0J5 28FXX0J5

11 B_A[24:1] B_D[15:0] 11 G8 H8 G8 H8 A0 D0 A0 D0 VPEN VCCq D7 VPEN VCCq G6 D7 G6 A1 D1 A1 D1 D8 H6 D8 H6 A2 D2 B_D[7:0] B_A[23:1] A2 D2 B_A1 D6 A3 D3 B_D0G5 B_A1 D6 A3 D3 G5 B_D8 B_A2 B8 A4 D4 B_D1H4 B_A2 B8 A4 D4 H4 B_D9 B_A3 C8 A5 D5 B_D2J3 B_A3 C8 A5 D5 J3 B_D10 B_A4 C7 A6 D6 B_D3G3 B_A4 C7 A6 D6 G3 B_D11 B_A5 B7 A7 D7 B_D4F3 B_A5 B7 A7 D7 F3 B_D12 B_A6 C6 A8 D8 B_D5G7 B_A6 C6 A8 D8 G7 B_D13 B_A7 B6 A9 D9 B_D6H7 B_A7 B6 A9 D9 H7 B_D14 B_A8A6 A10 D10 B_D7J6 B_A8 A6 A10 D10 J6 B_D15 B_A9 B5 A11 D11 H5 B_A9 B5 A11 D11 H5 B_A10 B4 A12 D12 G4 B_A10 B4 A12 D12 G4 B_A11 C4 A13 D13 H3 B_A11 C4 A13 D13 H3 B_A12 A3 A14 D14 H2 B_A12 A3 A14 D14 H2 B_A13 B3 A15 D15 G2 B_A13 B3 A15 D15 G2 B_A14 C3 A16 B_A14 C3 A16 3 B_A15 B2 A17 V5_0 B_A15 B2 A17 3 B_A16 D3 A18 A4 B_A16 D3 A18 A4 V5_0 CE0 CE0 B_A17 B1 A19 CE1 D2 V5_0 B_A17 B1 A19 CE1 D2 B_A18 C1 A20 CE2 F8 B_A18 C1 A20 CE2 F8 B_A19 C2 A21 B_A19 C2 A21 CEH# B_A20 B_A20 D1 A22 BYTE# F6 R111 D1 A22 BYTE# F6 B_A21 B_A21 WE# F1 WE# F1 B_A22 WE# 1K B_A22 1 H1 STS OE# G1 1 H1 STS OE# G1 B_A23 TP OE# B_A23 TP TP17 RP# C5 TP18 RP# C5 B_WE# B_WE# B_OE# B_OE# RP# RP# GNDGND VCC GNDGND VCC A7 J5 A7 J5 B_A24 B_CE2# 11 B_CE2# 11 B_CE1# B_CE1# V5_0 B_A24 V5_0

C198 C199 0.1uF 0.1uF

U22 U23 A5 A2 J4 A5 A2 J4 28FXX0J5 28FXX0J5

G8 H8 G8 H8 B_A[23:1] A0 D0 B_D[7:0] B_A[23:1] A0 D0 B_D[15:8] VPEN VCCq D7 VPEN VCCq G6 D7 G6 A1 D1 A1 D1 B_A1 D8 B_D0H6 B_A1 D8 H6 B_D8 A2 D2 A2 D2 B_A2 D6 B_D1G5 B_A2 D6 G5 B_D9 2 A3 D3 A3 D3 2 B_A3 B8 B_D2H4 B_A3 B8 H4 B_D10 B_A4 A4 D4 B_D3 B_A4 A4 D4 B_D11 C8 J3 C8 J3 B_A5 A5 D5 B_D4 B_A5 A5 D5 B_D12 C7 G3 C7 G3 B_A6 A6 D6 B_D5 B_A6 A6 D6 B_D13 B7 F3 B7 F3 B_A7 A7 D7 B_D6 B_A7 A7 D7 B_D14 B_A8 C6 A8 D8 B_D7G7 B_A8 C6 A8 D8 G7 B_D15 B_A9 B6 A9 D9 H7 B_A9 B6 A9 D9 H7 B_A10 A6 A10 D10 J6 B_A10 A6 A10 D10 J6 B_A11 B5 A11 D11 H5 B_A11 B5 A11 D11 H5 B_A12 B4 A12 D12 G4 B_A12 B4 A12 D12 G4 B_A13 C4 A13 D13 H3 B_A13 C4 A13 D13 H3 B_A14 A3 A14 D14 H2 B_A14 A3 A14 D14 H2 B_A15 B3 A15 D15 G2 B_A15 B3 A15 D15 G2 B_A16 C3 A16 B_A16 C3 A16 B_A17 B2 A17 B_A17 B2 A17 D3 A18 A4 D3 A18 A4 B_A18 CE0 B_A18 CE0 B_A19 B1 A19 CE1 D2 B_A19 B1 A19 CE1 D2 B_A20 C1 A20 CE2 F8 B_A20 C1 A20 CE2 F8 B_A21 C2 A21 B_A21 C2 A21 B_A22 D1 A22 BYTE# F6 B_A22 D1 A22 BYTE# F6 B_A23 WE# F1 B_A23 WE# F1 1 H1 STS OE# G1 B_WE# 1 H1 STS OE# G1 B_WE# TP TP TP19 RP# C5 B_OE# TP20 RP# C5 B_OE# RP# RP# GNDGND VCC GNDGND VCC A7 J5 A7 J5

1 1

Title StrataFlash

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 12of 24 A B C D E A B C D E

2,6,7,9,11 AD[31:0] U24A

B10 E15 A10 B15 D9 D14 C9AD0 SDD0 C14 AD0 B9AD1 SDD1 A14 AD1 A9AD2 SDD2 C13 AD2 D8AD3 SDD3 A13 AD3 4 E8AD4 SDD4 C12 4 AD4 B8AD5 SDD5 D12 AD5 A8AD6 SDD6 B13 AD6 D7AD7 SDD7 D13 U5B AD7 C7AD8 IDE SDD8 B14 AD8 B7AD9 SDD9 E14 3 4 SIGNALS RSTDRV# 15 AD9 A7AD10 SDD10 A15 AD10 D6AD11 SDD11 C15 AD11 E6AD12 SDD12 D15 74HCT14 AD12 E4AD13 SDD13 RSTDRV AD13 C4AD14 SDD14 C18 AD14 B4AD15 SDD15 H16 AD15 PDCS3# 15 A4AD16 B18 AD16 D3AD17 DS3S# H17 AD17 AD18 PCI DS3P# PDCS1# 15 AD18 AD18 E3 C3AD19 DS1S# AD19 SIGNALS SA[19:0] 5,17,18,21,22 B3AD20 DS1P# U11 AD20 AD21 E2 T11 AD21 AD22 C2 W11 AD22 AD23 SA0 B2 Y11 AD23 AD24 SA1 SA0 AD24 A2AD25 SA2 T10 SA1 AD25 D1AD26 SA3 W10 SA2 R112 AD26 E1AD27 SA4 U9 SA3 220 AD27 C1AD28 SA5 V9 SA4 AD28 B1AD29 SA6 Y9 SA5 AD29 AD30 SA7 T8 SA6 W8 2,6,7,9,11 -C/BE[3:0] AD30 AD31 SA8 SA7 AD31 C8 SA9 U7 SA8 C6 PIIX4 SA10 V7 SA9 D4C/BE#0 SA11 Y7 SA10 -C/BE0 D2C/BE#1 SA12 V6 SA11 -C/BE1 C/BE#2 SA13 Y6 SA12 PIIX4 is PCI -C/BE2 C/BE#3 SA14 T5 SA13 -C/BE3 C10 W5 SA14 2 CLKRUN# SA15 device #7 E5 SA16 U4 SA15 2,5,6,7,9,11 -DEVSEL A5CLOCKRUN# SA17 V4 SA16 2,5,6,7,9,11 -FRAME XD[7:0] 22 A3DEVSEL# SA18 SA17 B5FRAME# SA19 SA18 2,5,6,7,9,11 -IRDY SD[15:0] 5,17,18,21 3 B6IDSEL SA19 U25 3 2,5,6,7,9,11 PAR A1IRDY# V3 2 18 2,6,7,9,10,11 -PCIRST B12PAR W3 3 A1 B1 17 2,5 -PHOLD A12PCIRST# SD0 U2 4 A2 B2 16 2,5 -PHOLDA A6PHOLD# SD1 T2 SD0 SD0 5 A3 B3 15 XD0 2,5,6,7,9,11 -SERR SD1 SD1 XD1 D5PHOLDA# SD2 W2 6 A4 B4 14 2,5,6,7,9,11 -STOP SD2 SD2 XD2 C5SERR# SD3 Y2 7 A5 B5 13 2,5,6,7,9,11 -TRDY SD3 SD3 XD3 STOP# SD4 T1 8 A6 B6 12 SD4 SD4 A7 B7 XD4 E10TRDY# ISA/EIO SD5 V1 9 11 2,5,6 -PREQ0 SD5 SD5 A8 B8 XD5 A11 SD6 W16 2,5,6 -PREQ1 SIGNALS SD6 SD6 XD6 B11REQ0# SD7 T16 19 2,5,9 -PREQ2 SD7 SD7 14 XOE# G XD7 C11REQ1# SD8 Y17 1 2,5,11 -PREQ3 REQ2# SD9 SD8 14 XDIR# DIR V17 REQ3# SD10 SD9 Y18 74ALS245 15 PDD[15:0] SD11 SD10 F20 W18 SD12 SD11 E18PDD0 SD13 Y19 SD12 PDD0 E20PDD1 SD14 W19 SD13 D18 PDD1 PDD2 SD15 SD14 LA[23:17] 5,18 PDD2 D20PDD3 Y15 SD15 PDD3 C20PDD4 GPO1/LA17 T14 PDD4 B20PDD5 GPO2/LA18 W14 LA17 PDD5 A20PDD6 GPO3/LA19 U13 LA18 PDD6 A19PDD7 GPO4/LA20 V13 LA19 PDD7 B19PDD8 GPO5/LA21 Y13 LA20 PDD8 C19PDD9 GPO6/LA22 T12 LA21 PDD9 D19PDD10 GPO7/LA23 LA22 PDD10 D17PDD11 LA23 PDD11 E19 Y12 PDD12 MEMCS16# 5,18 PDD12 E17PDD13 MEMCS16# V15 MEMR# 5,18,22 PDD13 F19PDD14 MEMR# U15 PDD14 MEMW# 5,18,22 PDD15 MEMW# W4 SMEMR# 5,18 V5_0 PDD15 SMEMR# U3 SMEMW# 5,18 SMEMW# C17 T7 SYSCLK 18 B17SDA0 SYSCLK U10 BALE 5,18 R114 SDA1 GPO0/BALE A18 Y1 IOCHK# 5,18 G19SDA2 IDE GPI0/IOCHK# 15 PDDACK# 10k A17PDDACK# W7 2 SIGNALS REFRESH# 5,18 2 F18SDDACK# REFRESH# V12 15 PDREQ PDREQ# IOCS16# IOCS16# 5,18 A16 Y3 ZEROWS# 5,18 F17SDREQ# ZEROWS# 15 PDIOR# R113 F16PDIOR# W12 15 PDIOW# PDIOW# SBHE# SBHE# 5,18 10k G20 W1 15 PIORDY PIORDY RSTDRV RSTDRV 17,18,21 C16 Y5 IOR# 5,17,18,21 B16SDIOR# IOR# T4 SDIOW# IOW# IOW# 5,17,18,21 D16 T3 IOCHRDY 5,17,18 G16SIORDY IOCHRDY Y4 15 PDA0 PDA0 AEN AEN 17,18,21 G18 15 PDA1 PDA1 G17 15 PDA2 PDA2PIIX4E

1 1

Title PIIX4 Part 1

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 13of 24 A B C D E A B C D E

V3_3

V3.3SUS

V3.3SUS V3_3

C200 C201 C202 C203 C204 C205 C206 C207 C208 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

RP32 10K 1 8 4 2 7 4 3 6 4 5 U24B R15 R6 F15 E11 F6 T6 P15 R7 G6 F14 F5 E16 E12 E9 K5 N16 R16 VCC VCC VCC VCC VCC GPI7 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP THERM#

U14 VCCSUS VCCSUS LID 17,18 DACK0# VCCSUSB V3_3 W6 EXTSMI# 17,18 DACK1# Y10 RP33 10K 17,18 DACK2# V5DACK0# 1 8 17,18 DACK3# T15DACK1# F1 2 7 18 DACK5# USBP1+ 16 V16DACK2# H2 3 6 18 DACK6# USBP1- 16 W17DACK3# G2 4 5 18 DACK7# USBP0+ 16 SMBALERT# DACK5# USB USBP1+ H3 1 2 3 4 USBP0- 16 TEST# W15DACK6# USBP1- J1 5,17,18 DRQ0 SIGNALS OC0# 16 CONFIG2 RP34 U6DACK7# USBP0+ J2 5,17,18 DRQ1 OC1# 16 IRQ#8 V2 USBP0- 10K 5,17,18 DRQ2 U5DREQ0 OC0# V20 5,17,18 DRQ3 Y16DREQ1 OC1# W20 U26A 5,18 DRQ5 SUSA# 4 U16DREQ2 V19 5,18 DRQ6 DREQ3 EXTSMI# 8 7 6 5 U17 U18 1 2 5,18 DRQ7 DREQ5 SUSA# EXTSMI# PWRON# 23 DREQ6 GPO15/SUSB# M1 DREQ7 GPO16/SUSC# GPO15 N2 R1 74HCT14D POWER CPU_STOP# 4 P3REQA#/GPI2 R2 PCI_STOP# 4 GPI2 N1REQB#/GPI3 MGMT. GPO17/CPU_STP# K16 ZZ 2 P2 T17 GPI3 REQC#/GPI4 GPO18/PCI_STP# SUS_STAT1# 2 GPI4 P4GNTA#/GPO9 GPO19/ZZ T18 GPI5 GPO9 GNTB#/GPO10 GPO20/SUS_STAT1# H19 GPO10 V10 U19 17,18,21 TC GNTC#/GPO11 GPO21/SUS_STAT2# GPO11 J17 M17 GPO21 DMA/IRQ GPI8/HCT# RSMRST# 23 H18TC GPI9/BATLOW# U20 THERM# PWRBTN# 23 K18APICACK#/GPO12 SIGNALS RSMRST# P16 BATLOW# GPO12 T20 APICCS#/GPO13 PWRBT# SMBDATA 2,3,5 V3.3SUS H20APICREQ#/GP15 GPI10/LID R19 SMBCLK 2,3,5 J20 N17 LID 5,17 IRQ1 SMBDATA T9 P18 5,17,18,21 IRQ3 IRQ0/GP014 SMBCLK W9 5,11,17,18,21 IRQ4 IRQ1 GPI11/SMBALERT# R115 U8IRQ3 GPI12/RI#A SMBALERT# 5,11,17,18,21 IRQ5 3 V8IRQ4 GPI12 3 10k 5,17,18,21 IRQ6 Y8IRQ5 V5_0 5,17,18,21 IRQ7 Y20IRQ6 U1IRQ7 5,11,18 IRQ9 U12IRQ8/GPI6 V3.3SUS V3_3 5,11,17,18,21 IRQ10 W13IRQ9 R116 5,18,21 IRQ11 T13IRQ10 PIIX4 V3_3 5,17,18 IRQ12 1K D9 V14IRQ11 5,15,17,18 IRQ14 2 Y14IRQ12 Bat541% V3_3 5,11,17,18 IRQ15 IRQ14 J19IRQ15 J16 1 3 V3_3 V3.3SUS R3 8 7 6 5 5,6,7 PIRQA# R4SERIRG/GPI7 VREF RP35 5,6,9 PIRQB# GPI7 P5PIRQA# C209 5,6,11 PIRQC# 10K G1PIRQB# 0.1uF 5,6,11 PIRQD# PIRQC# 8 7 6 5 PIRQD# K20 RP36 2,5 SLP# M19 1 2 3 4 2,5 CPURST SLP# 10K K19 2,5 FERR# CPURST 8 7 6 5 L17 P19 2,5 IGNNE# FERR# L18 L2 RP37 2,5 INIT IGNNE# GPI1 L19 J3 1 2 3 4 2,5 INTR INIT GPI13 GPI1 10K P1 CPU L5 GPI13 17 KBDA20GATE INTR GPI14 L20 K3 GPI14 2,5 NMI A20GATE# INTERFACE GPI15 P20 K4 GPI15 2 SMI# NMI GPI16 J18 H1 GPI16 1 2 3 4 2,5 STPCLK# SMI# GPI17 N20 H4 GPI17 17 KBDRST# STPCLK# GPI18 M20 H5 GPI18 2,5 A20M# RCIN# GPI19 M18 G3 GPI19 23 PWROK A20M# GPI20 K17 GPI20 23 SPKR PWROK GPI21 V18SPKR GPI21 CPU Module must drive R17 SYSTEM GPI12 2,4 CONFIG1 TEST# CONFIG1l to indicate TEST# R18CONFIG1 BATLOW# processor type. CONFIG2 CONFIG2 3.3V = PentiumII M4 0V = Pentium 13 XOE# M3XOE#/GPO23 13 XDIR# M2XDIR#/GPO22 G4 2 22 BIOSCS# GPO0 2 L1BIOSCS# X-BUS T19 K2RTCALE/GPO25 GPO8 G5 GPO25 K1RTCCS#/GPO24 GPO27 F2 GPO24 Keep crystal close to PIIX4 and KBCCS#/GPO26 GPO28 F3 GPO26 caps close to crystal C211 GPO29/IRQ9Out F4 R20 GPO30 N19RTCX2 Trace lengths should be equal 2 RTCX1 10pF L16 Y5 VBAT J4 N/C P17 N18 32.768KHz 2 SUSCLK SUSCLK N/C GPIO HEADER USE WIDE TRACES ON CLOCKS C212 L3 N3 4 USBCLK0 48Mhz N/C 1 M16 JP6 N/C V11 M5 4 REF2 OSC N/C 12 D11 R5 10pF 4 PCICLKF PCICLK N/C GPO0 34 GPI1 GPO8 GPI2 VSS - D10,E7,E13,J[9:12] 56 GPO9 78 GPI3 K[9:12],L[9:12],M[9:12] MCCS# N4 GPO10 910 GPI4 GPO11 GPI5 VSSUSB J5 11 12 PCS0# L4 GPO12 13 14 GPI7 PCS1# N5 GPO15 15 16 GPI13 V3.3SUS GPO21 17 18 GPI14 GPO24 19 20 GPI15 GPO25 21 22 GPI16 GPO26 23 24 GPI17 3 VSS VSS VSS VSS VSS VSSUSB VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS GPO27 25 26 GPI18 GPO28 GPI19 D10 PIIX4E 27 28 2 Bat54 D10 E7 E13 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 J5 GPO29 29 30 GPI20 GPO30 GPI21 HEADER 15X2 1

1-2 Normal Operation

2 2-3 Clear CMOS

1 3 1 J14 1 1

D11 Bat54 2 JUMP3 1

C213 3 BT1 0.1uF BATTERY

2 R117 1K

Title PIIX4 Part 2

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 14of 24 A B C D E A B C D E

Primary IDE Connector

13 PDD[15:0]

RP38 33 JP7 R118 IDERSTP#R1 8 RP39 33 4 12 10k 4 2 7 1 8 PDD7 34 R119 3 6 2 7 56 8.2K 4 5 3 6 PDD7 78 910 4 5 PDD6 1 8 RP41 33 PDD8 PDD5 11 12 PDD9 2 7 13 14 1 8 PDD4 3 6 2 7 PDD10 15 16 PDD11 4 5 17 18 3 6 RP42 33PDD3 RP40 33 4 5 PDD2 19 20 PDD12 1 8 13 PDREQ 21 22 2 PDD17 PDD13 13 PDIOW# PDD0 23 24 PDD14 3 6 13 PDIOR# 25 26 PDD15 4 5 13 PDDACK# PDREQR 27 28 PDIOW#R 29 30 R120 RP43 33 PDIOR#R 31 32 1 8 13 PDA1 PDIORDYR 33 34 CSEL 470 2 7 35 36 13 PDA0 PDDACK#R 3 6 37 38 13 PDCS1# PDIRQR 4 5 PDA1R 39 40 13 RSTDRV# V5_0 PDA0R HEADER 20X2 PDA2R PDCS1#R PDCS3#R IDERSTP#R

R121 220

V5_0 2 1 R122 IN 10k D12 NC LGS260-DO HD Active LED 3 OUT 3 3

2 2

V5_0

R123 1K

RP44 47 1 8 13 PIORDY 2 PDIORDYR7 5,14,17,18 IRQ14 3 PDIRQR6 13 PDA2 4 PDA2R5 13 PDCS3# PDCS3#R

1 1

Title IDE Connector

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 15of 24 A B C D E A B C D E

USBVFIL1 USBVFIL2R124 R125 10K 10K V5_0

4 14 OC1# 14 OC0# 4 R126 R127 C214 15K C215 15K SMD250-002 F4 F5 SMD250002 0.01UF 0.01UF Poly-Fuse Poly-Fuse

Poly fuses should be in range of 1.5A to 5A

USBVFIL1 2 2 USBVFIL2 FB66 FB67 BLM41A800S BLM41A800S

8Ohm/100MHz/500mA 12 12 8Ohm/100MHz/500mA Place these caps within 1 inch

of USB Connector stack 1 1

C216 C217 C218 100uF 0.1uF 0.01uF C219 C220 C221 100uF 0.1uF 0.01uF

Place AsR128 Close as27 Possible to PIIX4 PCB Trace 45 Ohm Matched, Routed Together 14 USBP0- Stripline width 0.015 (1 oz) 44.88/45.45 Z1_VCC Z0_VCC Ohm R129 27 Z0- 14 USBP0+ 3 J15 3 Z0+ R130 R131 BOTTOM of Stacked USB Connector C222 C223 15K 15K 1 47pF 47pF 2 VCC0 9 3 D0- GND 10 4 D0+ GND GND0

Z0_GND 1 TOP of Stacked USB Connector

1 FB68 5 6 VCC1 11 BLM41A800S D1- GND 7 12

2 D1+ GND 8 GND1 2

USB Stack

PCB Trace 45 Ohm Matched, Routed Together Place As Close as Possible to PIIX4 Stripline width 0.015 (1 oz) 44.88/45.45 Ohm R132 27 14 USBP1- Z1- R133 27 14 USBP1+ Z1+

R134 R135 C224 C225 15K 15K 2 47pF 47pF 2

Z1_GND 1

1 FB69 BLM41A800S 2 2

NOTE 1: USB differential traces route together (Z0- & Z0+) and (Z1- & Z1+). Must be 45 Ohm Matched Stripline width 0.015 (for 1 oz)->44.88/45.45 Ohm. NOTE 2: Protect differential traces w/ guard traces or double space to any other signal. NOTE 3: Place ferrites at connector.

NOTE 4: Poly-fuse min 1.5A max 5A.

1 1

Title USB Connectors

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 16of 24 A B C D E A B C D E

V5_0

C226 C227 C228 C229 0.1uF 0.1uF 0.1uF 0.1uF

U27 62 93 121 69 65 19 20 21 5,13,18,21 SD[15:0] VTR VCC VCC VCC

44 VBAT 4 45 16 -RDATA 19 4 46 SD0 11 POWERON

PME#/IRQ9 -WGATE 19 47 SD1SD2 BUTTON_IN RDATA# 10 SD0 SD3 WGATE# -WDATA 19 49 12 -SIDE1 19 SD1 SD4 WDATA# 50 8 -DIR 19 SD2 51 SD5 HDSEL# 9 -STEP 19 SD3 SD6 DIR# 52 17 -DSKCHG 19 SD4 SD7 Floppy STEP# 5 5,13,18,21,22 SA[19:0] SD5 DSKCHG# -DRVSA 19 23 6 -DRVSB 19 SD6 24 DS0#DS1# 3 SD7 SA0 -MOTEA 19 25 4 -MOTEB 19 26 SA1 MTR0#MTR1 15 SA0 -WPT 19 27 SA2 14 SA1 SA4 -TRK0 19 28 SA3 WRTPRT# 13 V5_0 SA2 SA5 -INDEX 19 29 TRK0# 1 SA3 SA6 HDEN 19 30 INDEX# 2 R153 SA4 SA7 DRVDEN0 DRATE0 19 31 SA5 SA8 ISA/Host DRVDEN1 PULLING UP SYSOPT 32 112 SA6 SA9 RXD1 RXD0 20 CONFIGURES 78x TO 370h 33 113 SA7 SA10 TXD0 20 10K 34 115 SA8 RTS0# 19 35 TXD1 116 SA9 SA11 RTS1#/SYSOP CTS0# 19 36 117 SA10 SA12 CTS1# DTR0# 20 37 114 SA11 SA13 Uarts DTR1# DSR0# 19 SA12 38 SA14 DSR1# 119 DCD0# 19 SA13 SA15 DCD1# 118 RI0# 19 43 123 13,18,21 AEN SA14 AEN RI1# RXD1 19 64 124 5,13,18 IOCHRDY SA15 IOCHRDY RXD2/IRRX TXD1 19 53 126 13,18,21 RSTDRV RESET_DRV TXD2/IRTX RTS1# 19 40 127 5,11,14,18 IRQ15 RTS2# CTS1# 19 39 128 5,14,15,18 IRQ14 SER/IRQ15 CTS2# DTR1# 19 55 125 5,14,18 DRQ0 PCI_CLK/IRQ14/GP50 DTR2# DSR1# 19 57 122 5,14,18 DRQ1 DRQ0 DSR2# DCD1# 19 59 120 5,14,18 DRQ2 DRQ1 DCD2# RI1# 19 61 DRQ2 RI2# 5,14,18 DRQ3 DRQ3 54 DACK0# 14,18 DACK0# 56 14,18 DACK1# 58 DACK1# 96 14,18 DACK2# PDR0 19 60 DACK2# 97 14,18 DACK3# PD0 PDR1 19 3 63 DACK3# 98 3 14,18,21 TC PD1 PDR2 19 41 TC PD2 99 5,13,18,21 IOR# PDR3 19 42 IOR# PD3 100 5,13,18,21 IOW# IOW# PDR4 19 PD4 101 PDR5 19 PD5 102 PD6 PDR6 19 22 CLOCK14 Parallel 103 4 REF1 PD7 PDR7 19 66 95 SLCTIN# -SLCTRIN 19 68 XTL1 94 PINIT# -INIT 19 18 XTL2CLK32OUT 110 ALF# -ALF 19 111 STROBE# -STROBE 19 107 BUSY -BUSY 19 IR TRANSCEIVER 108 ACK# -ACK 19 70 106 PE PE 19 71 KDAT 105 SLCT SLCT 19 72 KCLK 109 V5_0 ERROR# -ERR 19 73 MDAT 75 MCLK 14 KBDRST# KBDRST# 76 14 KBDA20GATE A20M 77 83 GP10 78 R138 R139 5,14 IRQ1 IRQ1 GP11 U28 84 79 5,14,18,21 IRQ3 IRQ3 GP12 85 80 14 47 5,11,14,18,21 IRQ4 IRQ4 GP13 V5_0 86 81 4 1 5,11,14,18,21 IRQ5 IRQ5 GP14 87 82 3 Rxd IRED Anode 2 5,14,18,21 IRQ6 IRQ6 GP15 88 IRRX2 5 Txd IRED Cathode 6 5,14,18,21 IRQ7 IRQ7 NC Vcc1/SD 89 IRTX2 Alternate IR pins 7 8 C230 C231 IRQ8 SC GND R140 90 allow switch between 5,11,14,18,21 IRQ10 IRQ10 91 IRQ11/ROMCS# COM2 and Infrared Mode .1uF 4.7uF tant. 92 5,14,18 IRQ12 IRQ12 to be configured in 10K BIOS TFDU4100-TR3 This disables the ROM buffers. FDC37B78X BIOS needs to enable and VSS VSS VSS VSS configure IRQs AVSS 67 7 48 74 104

PULL romCs# high so as not to interfere with boot rom! 2 2 V5_0

V5_0

F6 SMD250-002 2 8 7 6 5 RP45 FB70 4.7k BLM41A800S 12 1 1 2 3 4

J16 FB71 1 2 T1 12 T2 KBDATA BLM41A800S T3 NC FB72 T4 GND 1 2 T5 KB_VCC 12 T6 KB_CLK TOP BLM41A800S NC 13 GND 14 GND 15 GND 16 GND 17 FB73 GND 1 2 B1 12 MDATA 1 B2 1 NC BLM41A800S B3 GND FB74 B4 M_VCC BOTTOM 1 2 B5 12 M_CLK B6 NC BLM41A800S PS2 STACK

C232 C233 C234 C235 C236 C237 470pF 470pF 470pF 470pF 470pF 0.1uF Title Super I/O

Size Document Number Rev C {Doc} A

Date:Monday, November 30, 1998 Sheet 17of 24 A B C D E A B C D E

ISA Slots

-5V -12V +12V V5_0 4 4

C238 C239 C240 C241 C242 C243 C244 C245 C246 C247 10uF 0.1uF 10uF 0.1uF 10uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF Note Cap Direction Note Cap Direction

5,13,17,21,22 SA[19:0]

5,13,17,21 SD[15:0]SA[19:0]

SD[15:0] 5,13 LA[23:17]

LA[23:17]

+12V -12V -5V

J17 B01 A01 IOCHK# 5,13 B02 A02 13,17,21 RSTDRV GNDRSTDRVIOCHCK SD7 3 B03 A03 3 V5_0 SD6 B04 A04 5,11,14 IRQ9 IRQ9 SD5 SD7 B05 -5V A05 B06 SD4 A06 SD6 5,14,17 DRQ2 DRQ2 SD3 B07 A07 SD5 -12V SD2 SD4 B08 A08 5,13 ZEROWS# 0WS SD3 B09 SD1 A09 +12V SD2 B10 SD0 A10 GND IOCHRDY 5,13,17 SD1 B11 IOCHRDY A11 5,13 SMEMW# SMEMW AEN AEN 13,17,21 SD0 B12 A12 5,13 SMEMR# SA19 B13 A13 5,13,17,21 IOW# IOWSMEMR SA18 B14 A14 5,13,17,21 IOR# SA19 B15 A15 14,17 DACK3# IORDACK3 SA18 B16 SA17 A16 5,14,17 DRQ3 DRQ3 SA17 B17 SA16 A17 14,17 DACK1# DACK1 SA14SA15 SA16 B18 A18 5,14,17 DRQ1 DRQ1 SA13 SA15 B19 A19 5,13 REFRESH# REFRESH SA12 SA14 B20 A20 13 SYSCLK CLK SA11 SA13 B21 A21 5,14,17,21 IRQ7 IRQ7 SA10 SA12 B22 A22 5,14,17,21 IRQ6 IRQ6 SA9 SA11 B23 A23 5,11,14,17,21 IRQ5 IRQ5 SA8 SA10 B24 A24 5,11,14,17,21 IRQ4 IRQ4 SA7 SA9 B25 A25 SA8 5,14,17,21 IRQ3 IRQ3 SA6 B26 A26 SA7 14,17 DACK2# DACK2 SA5 B27 TC A27 SA6 14,17,21 TC SA4 B28 A28 SA5 5,13 BALE BALE SA3 SA4 B29 V5_0 SA2 A29 SA3 B30 OSC SA1 A30 4,21 REF0 SA2 B31 GND SA0 A31 SA1 SA0

D01 MCS16 C01 5,13 MEMCS16# SBHELA23 SBHE# 5,13 D02 IOCS16 C02 5,13 IOCS16# LA22 D03 C03 5,11,14,17,21 IRQ10 LA21 D04 IRQ10 C04 LA23 5,14,21 IRQ11 D05 IRQ11 LA20 C05 LA22 5,14,17 IRQ12 D06 IRQ12 C06 LA21 2 5,11,14,17 IRQ15 LA19 2 D07 IRQ15 C07 LA20 5,14,15,17 IRQ14 LA17LA18 LA19 D08 IRQ14 C08 14,17 DACK0# LA18 D09 DRQ0DACK0 C09 5,14,17 DRQ0 MEMR MEMR# 5,13,22 LA17 D10 DACK5 C10 14 DACK5# MEMW MEMW# 5,13,22 D11 DRQ5 SD8 C11 5,14 DRQ5 D12 DACK6 SD9 C12 14 DACK6# SD8 D13 DRQ6 SD10 C13 5,14 DRQ6 SD11 SD9 D14 DACK7 C14 14 DACK7# SD12 SD10 D15 DRQ7 C15 5,14 DRQ7 V5_0 SD13 SD11 D16 C16 SD12 D17 MASTER C17 5 MASTER16# SD14 SD13 D18 GND C18 ISA Conn A SD15 SD14 SD15

J17/J18 V5_0: B03, B29, B31, D16 J17/J18 GND: B01, B10, D18

J17/J18: +12V B09 -12V B07 -5V B05

1 1

Title ISA Connector

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 18of 24 A B C D E A B C D E

V5_0

-12V +12V V5_0 -12V +12V V5_0 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 RP46 RP47 RP48 RP49 R141 4.7K 4.7K 4.7K 4.7K 4 COM1/COM2 4.7K 4 C248 C249 C250 C251 C252 C253 4 1 2 3 4 1 2 3 4 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1 2 3 4 1 2 3 PARALLEL +12V R142 17 -SLCTRIN U29 22 20 1 -PSLCTIN 19 V5_0 +12V 2 17 DCD0# 18 RY1 RA1 3 C254 17 DSR0# 17 RY2 RA2 4 220pF 20 RXD0_J -PPINIT 16 RY3 RA3 5 17 RTS0# SP_DCD0 J18 15 DA1 DY1 6 20 TXD0_J SP_DSR0 14 DA2 DY2 7 17 CTS0# RY4 RA4SP_RXD0 13 8 5 20 DTR0#_J SP_RTS0 12 DA3 DY3 9 9 5 COM1 17 RI0# SP_TXD0 11 RY5 RA5 10 4 9 C255 GND -12VSP_CTS0 8 4 220pF SP_DTR0 8 -PPERR GD75232SOPSP_RI0 3 C256 C257 C258 C259 7 3 470pF 470pF 470pF 470pF 2 7 2 6 6 -12V 1 1 C264 C260 C261 C262 C263 220pF -PALF 470pF 470pF 470pF 470pF

14 14 18 18 COM2 13 13 +12V 17 17 RP50 C265 12 1 8 220pF -PSTROBE 12 17 -INIT 16 2 7 16 17 -ERR U30 11 3 6 11 17 -ALF 20 1 15 -INIT 4 5 15 17 -STROBE 19 V5_0 +12V 2 10 -ERR 17 DCD1# 10 3 18 RY1 RA1 3 -ALF 22 3 17 DSR1# 17 RY2 RA2 4 -STROBE C266 17 RXD1 SERIAL STACK 16 RY3 RA3SP_DCD15 220pF PPDR0 17 RTS1# 15 DA1 DY1SP_DSR16 17 TXD1 14 DA2 DY2SP_RXD17 17 CTS1# RY4 RA4SP_RTS1 13 8 17 DTR1# SP_TXD1 12 DA3 DY3 9 17 RI1# RY5 RA5SP_CTS1 11 10 GND -12VSP_DTR1 C267 SP_RI1 PPDR1 GD75232SOP 220pF C268 C269 C270 C271 470pF 470pF 470pF 470pF

-12V RP51 C272 C273 C274 C275 1 8 C276 17 PDR0 PPDR2 470pF 470pF 470pF 470pF 2 7 220pF 17 PDR1 3 6 17 PDR2 PDR0 4 5 17 PDR3 PDR1 PDR2 PDR3 33

C277 PPDR3 220pF 26 27

1 14 C278 PPDR4 2 220pF 15 V5_0 3 16 4 RP52 17 1 8 5 17 PDR4 2 7 18 17 PDR5 PDR4 3 6 C279 PPDR5 6 2 17 PDR6 2 PDR5 4 5 220pF 19 4 3 2 1 17 PDR7 PDR6 7 PDR7 RP53 FLOPPY 33 20 R143 1K 8 1K 21 PPDR6 9 C280 22

5 6 7 8 220pF 10 23 11 24 12 PPDR7 25 C281 13 220pF JP8 J19 17 -DSKCHG 34 33 RP54 DB25 17 -SIDE1 32 31 1 8 17 -RDATA 17 -ACK 30 29 -ACK 2 7 -PPACK 17 -WPT 17 -BUSY 28 27 -BUSY 3 6 C282 17 -TRK0 17 PE 26 25 PE 4 5 220pF 17 -WGATE 24 23 17 SLCTSLCT 17 -WDATA 22 21 22 17 -STEP 20 19 17 -DIR 18 17 17 -MOTEB 16 15 -PPBUSY 17 -DRVSA 14 13 C283 17 -DRVSB 12 11 220pF 17 -MOTEA 10 9 17 -INDEX 8 7 Pin 5 is the Key 17 DRATE0 6 5 4 3 17 HDEN 2 1 PPE C284 220pF

1 1

FLOPPY HEADER 17X2 PPSLCT C285 220pF

Title COMx, DB25, Floppy

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 19of 24 A B C D E A B C D E

4 4

Vcc1 R144 U31 1 3 IN OUT C287 100 + C286 GND + 1uF tant. C288 Vcc1

2 1uF tant. 0.1 uF J20 CON4 C289 R145

MIC5201-3.3BS + 1 2 3 4

1uF tant. 100K

3 3

THESE JUMPERS ARE USED TO SWITCH BETWEEN COM1 AND TOUCH U32 Vcc1 SCREEN. PLACE A JUMPER ON 1-2 FOR TOUCH SCREEN 2-3 FOR COM1 1 16 R146 AVD Y- J21

1 JUMP3 2 15 VREF Y+ Y6 2 DTR0# 17 3 14 1 2 0 ohm ADC_1 X- DTR0#_J 19 4 ADC_2 X+ 13 1.8432 MHz 3 C290 0.1 uF C291 C292 5 VDD AVS 12 J22 C293 22 pF 22 pF

1 JUMP3 + 6 TXD PD_RST 11 2 TXD0 17 1uF tant. 7 VSS MUX_SEL 10 TXD0_J 19 8 XTALIN XTAL_OUT 9 3

TR88L803 J23

R147 1 JUMP3 2 RXD0 17

RXD0_J 19

10K 3

2 R148 C294 2

R149

10K 1uF tant. 10K R150 Q3 C295 PN2222 10K Vcc1 Q4 PN2222 0.1 uF R151 R152 820 10K

1 1

Title Touch Screen Controller

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 20of 24 A B C D E A B C D E

V5_0

nRDATA RP55 nDSKCHG 1 8 nWRTPRT 2 7 nACK nTRK00 3 6 69DACKA nERROR nINDEX 4 5 69BUSY 69DACKB 69IRRX2 69PE 69DACKC 10K SLCT 4 4 IRQIN

V5_0

C296 C297 PLACE CLOSE TO VCC PINS 0.1uF 0.1uF PWROK5 22,23

U33 15 72 58 5,13,17,18 SD[15:0] 48 1

D0 VCC VCC DRVDEN0 49 18 5,13,17,18,22 SA[19:0] D1 DRVDEN1 50 2 D2 nMTR0 SD0 51 D3 nMTR1 5 SD1 53 D4 nDS1 4 SD2 54 D5 nDS0 3 SD3 55 D6 nDIR 7 C298 C299 C300 C301 V5_0 SD4 56 D7 PWRGD/nGAMECS nSTEP 8 470pF 470pF 470pF 470pF SD5 nWDATA 9 SD6 SA0 28 A0 nWGATE 10 SD7 SA1 29 11

14 A1 nHDSEL U34 SA2 SA12 SA15 SA14 SA11 SA13 30 A2 nINDEX 12 SA3 31 A3 nTRK00 13 C302 C303 C304 C305 8 SA4 32 A4 nWRTPRT 14 470pF 470pF 470pF 470pF

VCC 2C J24 6 2 SA5 33 A5 nRDATA 16nINDEX 9 1Y 2B 1 SA6 34 17nTRK00 U35 +12V 2Y 2A A6 nDSKCHG 3 5 SA7 41 nWRTPRT 20 1 5 3 1C A7 11 4 SA8 42 A8 nRI1 84nRDATA 19 V5_0 +12V 2 9 5 3A 1B SA9 nDSKCHG RY1 RA1 9 12 3B 1A 3 43 A9 nDTR1 83 18 3 4 13 SA10 97 A10 nCTS1 82 17 RY2 RA2 4 8 4 3C RY3 RA3 8 3Y 10 27 nCS TXD1 79 16 5 3 nRTS1 81 15 DA1 DY1 6 7 3 COM3 GND 44 RXD1 78 14 DA2 DY2 7 2 7 5,13,17,18 IOR# 74HC4075D 45 nDSR1 80 13 RY4 RA4 8 6 2 5,13,17,18 IOW# nIOR DA3 DY3 6 7 46 nDCD1 85 12 9 1 13,17,18 AEN nIOW 1 35 11 RY5 RA5 10 14,17,18 TC AEN GND -12V 57 RESET 13,17,18 RSTDRV TC 21 GD75232SOP -12V 52 DRQ_A U36 +12V 99 DRQ_B 20 1 14 ADDRESS nRI2 V5_0 +12V 14 22 DRQ_C 86 19 2 18 18 36 nDAK_A nDTR2 93 18 RY1 RA1 3 13 DECODE nCTS2 RY2 RA2 13 69DACKA 96 nDAK_B 92 17 4 17 17 COM4 19 IRQ_AnDAK_C TXD2/IRTX 89 16 RY3 RA3 5 12 5,14,17,18 IRQ3 69DACKB DRV2/nADRX/IRQ_B nRTS2/SYSOPT 12 94 91 15 DA1 DY1 6 16 5,11,14,17,18 IRQ4 69DACKC IRQ_C RXD2/IRRX 16 37 88 14 DA2 DY2 7 11 5,11,14,17,18 IRQ5 IRQ_D nDSR2 11 38 90 13 RY4 RA4 8 15 5,14,17,18 IRQ6 IRQ_E nDCD2 15 39 87 12 DA3 DY3 9 10 5,14,17,18 IRQ7 IRQ_F RY5 RA5 10 40 11 10 5,11,14,17,18 IRQ10 nIDEEN/IRQ_H nSLCTIN GND -12V 24 73 5,14,18 IRQ11 nINIT GD75232SOP SERIAL STACK IRQIN nERROR 74 -12V 23 NHDCS0/IRRX2 nAUTOFD 75 PULLING DOWN SYSOPT 25 nHDCS1/IRTX2 nSTROBE 76 C306 C307 C308 C309 CONFIGURES 669 TO 3F0h 470pF 470pF 470pF 470pF IRQIN 26 ICLK SLCT 77nERROR 69IRRX2 20 59 R154 4,18 REF0 PE 98 60 NC BUSY 1K nACK 61SLCT PD0 6269PE C310 C311 C312 C313 PD1 6369BUSY 470pF 470pF 470pF 470pF PD2 64nACK PD3 65 PD4 66 PD5 68 2 PD6 69 2 PD7 70 IOCHRDY 71 100

FDC37C669 GND GND GND GND 6 47 67 95

1 1

THIS SUPER I/O IS USED SOLELY TO ADD SERIAL PORTS TO THE PRINCE BOARD.

Title Serial Ports

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 21of 24 A B C D E A B C D E

4 4

V5_0 +12V J25 1x3 1 3

5,13,17,18,21 SA[19:0] 2 C314 0.1uF

3 3 U37 XD[7:0] 13 21 20 A0 25 19 A1 DQ0 26 SA0 18 A2 DQ1 27 SA1 XD0 17 A3 DQ2 28 SA2 XD1 16 A4 DQ3 32 SA3 XD2 15 A5 DQ4 33 SA4 XD3 14 A6 DQ5 34 SA5 A7 DQ6 XD4 SA6 8 35 XD5 7 A8 DQ7 V5_0 SA7 A9 XD6 36 11 SA8 A10 VPP XD7 6 SA9 A11 5 31 SA10 A12 VCC SA11 4 A13 VCC 30 SA12 3 39 C315 A14 GND 0.1uF SA13 2 A15 GND 23 SA14 1 A16 SA15 40 A17 SA16 SA17 NC 12 9 13 5,13,18 MEMW# WE# NC 24 37 5,13,18 MEMR# OE# NC 22 38 14 BIOSCS# CE# NC 10 RP#

C316 28F002BC 0.1uF

+12V 2 2 2 1 3 PWROK5 21,23

J26 HDR3

1 1

Title BIOS

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 22of 24 A B C D E A B C D E

Power Indicators

V5_0 V3_3

-12V Place at ATX Connector R155 R156 220 124 C317 C318 C319 0.1uF 100uF 100uF

Note Cap Direction

4 1 2 1 2 4 Place at ATX Connector +12V IN IN

D13 NC D14 NC LGS260-DO LGS260-DO J27 C320 C321 C322 C323 C324 11 1 0.1uF 100uF OUT 470pF OUT 470pF V3_3 V3_3 100uF 12 2 -12V V3_3

13 3 3 3 GND GND 14 PS_ON V5_0 4 15 GND GND 5 16 6

2 GND V5_0 17 GND GND 7 1 3 18 8 V5_0 14 PWRON# -5V PW_OK 19 V5_0 5VSB 9 J28 20 V5_0 +12V 10 Note: Add screen marking for V5_0 LED, V3_3 LED 5VSB JUMP3 ATX POW CONN V5_0 14 U38A Open Collector -5V 1 2 2 DBRESET Place at ATX Connector R157 7 R158 4.7K 74ACT05 10K

C325 C326 C327 0.1uF 100uF 100uF S1

Note Cap Direction RESET SWITCH C328 C329 10uF 0.01uF V3.3SUS

3 V5_0 3

R159 Place at ATX Connector 10K U39A U5C 14 U38B 14 U40A PS_OK 1 3 5 6 3 4 1 2 Place at ATX Connector Place at ATX Connector PWROK 14 2 2 CPUPWROK V3_3 V5_0 5VSB 7 7 74ALS00 74HCT14 74ACT05 74LCT14

PWROK5 21,22 C330 C331 C332 C333 C334 C335 C334 0.1uF 100uF 100uF 0.1uF 100uF 100uF 100uF PS_OK = OR of PW_OK,-DBRESET,RESET SWITCH V3.3SUS

V3.3SUS

14 U40B S2 3 4 PWRBTN# 14 POWER SWITCH 7 R160 74LCT14 TP21 V3.3SUS 10K C336 TP 0.1uF V3.3SUS 1

U41 U40C 14 U40D 14 R161 V5_0 6 5 8 9 2 3 2 14 RSMRST# Out In 2 4 OutTab 7 7 2.7K 74LCT14 74LCT14 C337 C338 C339 C339 10uF 47uF 10uF 10uF J12 1 Adj/GND V5_0 1 LT117-3.3 1

2 2

3 1 3 TP JP10 1 TP22 2 3 AMP173981-3 14 SPKR 4 1x4 SPEAKER HEADER

1 NOTE 1: Locate Fan Header next to Processor Assembly 1 Note 2: Connect V5_0 feed for analog supplies AVDD1 and CLKAVDD1 at one point only on PCB Note 3: Place power connector decoupling at ATX connector NOTE 4: Note direction of caps on -12V, -5V supplies.

Title AXT Power Connector

Size Document Number Rev C {Doc} A

Date:Thursday, October 22, 1998 Sheet 23of 24 A B C D E A B C D E

V5_0

4 4 V5_0 14 U5E

11 10

7 U8F 74HCT14 14

13 12 14 U5F Make these connections Cutable7 13 12

10 74ACT04 14 7 74HCT14 9 8 Make these connections Cutable 7

U10C 74HCT125

14 13

12 11

Make these connections Cutable7 V3.3SUS U10D 74HCT125

3 14 U40E 3

11 10

7 74LCT14

14 U40F V5_0 14 U38C V5_0 13 12 5 6 U39B 7 4 7 Make these connections Cutable74LCT14 6 74ACT05 5 14 U38D 74ALS00 9 8 14 U39C 9 7 8 74ACT05 10 7 74ALS00 14 U38E

11 10 5VSB 14 U39D 12 7 74ACT05 Make these connections Cutable 11 13 7 74ALS00 14 U38F C333 14 U26B 0.1uF Make these connections13 Cutable 12 3 4 7 7 74ACT05 74HCT14D 2 2

14 U26C

5 6

7 74HCT14D

14 U26D

9 8

7 74HCT14D

U26E

11 10

74HCT14D

U26F

13 12 Make these connections Cutable 74HCT14D

1 1

Title Unused Gates

Size Document Number Rev C {Doc} A

Date:Tuesday, August 25, 1998 Sheet 24of 24 A B C D E