AMD64 Architecture Programmer's Manual, Volume 2

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AMD64 Technology AMD64 Architecture Programmer’s Manual Volume 2: System Programming Publication No. Revision Date 24593 3.21 March 2012 Advanced Micro Devices AMD64 Technology 24593—Rev. 3.21—March 2012 © 2002 – 2012 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. The information contained herein may be of a preliminary or advance nature and is subject to change without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other appli- cations intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD arrow logo, AMD Athlon, and AMD Opteron, and combinations thereof, AMD Virtualization and 3DNow! are trademarks, and AMD-K6 is a registered trademark of Advanced Micro Devices, Inc. MMX is a trademark and Pentium is a registered trademark of Intel Corporation. HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 24593—Rev. 3.21—March 2012 AMD64 Technology Contents Contents . iii Figures. xvii Tables . xxv Revision History. xxix Preface. xxxiii About This Book. xxxiii Audience . xxxiii Organization . xxxiii Conventions and Definitions . xxxiv Notational Conventions . xxxv Definitions . xxxvi Registers . xli Endian Order . xliv Related Documents. xliv 1 System-Programming Overview . .1 1.1 Memory Model . 1 Memory Addressing . 2 Memory Organization . 3 Canonical Address Form . .4 1.2 Memory Management . 5 Segmentation . 5 Paging . 7 Mixing Segmentation and Paging . 8 Real Addressing. 10 1.3 Operating Modes . 11 Long Mode. 12 64-Bit Mode. 13 Compatibility Mode. 13 Legacy Modes . 14 System Management Mode (SMM) . 15 1.4 System Registers . 15 1.5 System-Data Structures . 17 1.6 Interrupts . 19 1.7 Additional System-Programming Facilities . 20 Hardware Multitasking . .20 Machine Check . 21 Software Debugging . 21 Performance Monitoring . .22 2 x86 and AMD64 Architecture Differences . .23 2.1 Operating Modes . 23 Long Mode. 23 Contents iii AMD64 Technology 24593—Rev. 3.21—March 2012 Legacy Mode . 23 System-Management Mode. 24 2.2 Memory Model . 24 Memory Addressing . .24 Page Translation . 25 Segmentation . 26 2.3 Protection Checks . 27 2.4 Registers . 28 General-Purpose Registers. .28 YMM/XMM Registers . 28 Flags Register . 28 Instruction Pointer . ..

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