AMD64 Architecture Programmer's Manual, Volume 3, General
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AMD64 Technology AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions Publication No. Revision Date 24594 3.10 February 2005 Advanced Micro Devices © 2002, 2003, 2004, 2005 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular pur- pose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD arrow logo, and combinations thereof, and 3DNow! are trademarks, and AMD-K6 and AMD Athlon are registered trade- marks of Advanced Micro Devices, Inc. MMX is a trademark and Pentium is a registered trademark of Intel Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 24594 Rev. 3.10 February 2005 AMD64 Technology Contents Figures ix Tables xi Revision History xiii Preface xv About This Book . xv Audience . xv Contact Information. xv Organization . xv Definitions. xvi Related Documents . xxvii 1 Instruction Formats 1 1.1 Instruction Byte Order . 1 1.2 Instruction Prefixes. 3 Summary of Legacy Prefixes . 3 Operand-Size Override Prefix . 5 Address-Size Override Prefix . 6 Segment-Override Prefixes . 9 Lock Prefix . 10 Repeat Prefixes . 10 REX Prefixes . 14 1.3 Opcode . 20 1.4 ModRM and SIB Bytes . 20 1.5 Displacement Bytes. 22 1.6 Immediate Bytes . 23 1.7 RIP-Relative Addressing . 23 Encoding. 24 REX Prefix and RIP-Relative Addressing. 24 Address-Size Prefix and RIP-Relative Addressing. 25 2 Instruction Overview 27 2.1 Instruction Subsets . 27 2.2 Reference-Page Format . 28 2.3 Summary of Registers and Data Types . 30 General-Purpose Instructions. 30 System Instructions. 33 128-Bit Media Instructions . 35 64-Bit Media Instructions . 38 x87 Floating-Point Instructions . 40 2.4 Summary of Exceptions . 41 2.5 Notation . 43 Contents iii AMD64 Technology 24594 Rev. 3.10 February 2005 Mnemonic Syntax . 43 Opcode Syntax . 46 Pseudocode Definitions . 49 3 General-Purpose Instruction Reference 59 AAA . 61 AAD . 62 AAM . 63 AAS . 64 ADC. 65 ADD . 67 AND . 69 BOUND . 72 BSF . 74 BSR . 76 BSWAP . 78 BT . 79 BTC . 81 BTR . 83 BTS . 85 CALL (Near). 87 CALL (Far) . 89 CBW . 96 CWDE . 96 CDQE . 96 CWD . 97 CDQ. 97 CQO. 97 CLC . 98 CLD . 99 CLFLUSH. 100 CMC . 102 CMOVcc . 103 CMP . 107 CMPS . 110 CMPSB . 110 CMPSW. 110 CMPSD . 110 CMPSQ . 110 CMPXCHG . 113 CMPXCHG8B. 115 CMPXCHG16B. 115 CPUID. 117 DAA. 136 DAS . 137 DEC. 138 DIV . 140 ENTER . ..