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CLC031A SMPTE 292M/259M Digital Video Deserializer / Descrambler

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CLC031A SMPTE 292M/259M Digital Video Deserializer / Descrambler Data FIFOs CLC031A SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary September 2004 CLC031A SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs General Description The CLC031A’s internal circuitry is powered from +2.5 Volts and the I/O circuitry from a +3.3 Volt supply. Power dissipa- The CLC031A SMPTE 292M / 259M Digital Video tion is typically 850mW. The device is packaged in a 64-pin Deserializer/Descrambler with Video and Ancillary Data TQFP. FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial component video data, to 20-bit parallel data with a synchro- Features nized parallel word-rate clock. It also deserializes and de- n SDTV/HDTV serial digital video standard compliant codes SMPTE 259M, 270Mbps, 360Mbps and n Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps SMPTE 344M (proposed) 540Mbps serial component video and 1.485 Gbps serial video data rates with data, to 10-bit parallel data. Functions performed by the auto-detection CLC031A include: clock/data recovery from the serial data, n LSB de-dithering option serial-to-parallel data conversion, SMPTE standard data de- n Uses low-cost 27MHz crystal or clock oscillator coding, NRZI-to-NRZ conversion, parallel data clock genera- reference tion, word framing, CRC and EDH data checking and han- n Fast VCO lock time: < 500 µs at 1.485 Gbps dling, Ancillary Data extraction and automatic video format n Built-in self-test (BIST) and video test pattern generator determination. The parallel video output features a variable- (TPG)* depth FIFO which can be adjusted to delay the output data n Automatic EDH/CRC word and flag processing up to 4 parallel data clock periods. Ancillary Data may be selectively extracted from the parallel data through the use n Ancillary Data FIFO with extensive packet handling of masking and control bits in the configuration and control options registers and stored in the on-chip FIFO. Reverse LSB dith- n Adjustable, 4-deep parallel output video data FIFO ering is also implemented. n Flexible control and configuration I/O port The unique multi-functional I/O port of the CLC031A pro- n LVCMOS compatible control inputs and clock and data vides external access to functions and data stored in the outputs configuration and control registers. This feature allows the n LVDS and ECL-compatible, differential, serial inputs designer greater flexibility in tailoring the CLC031A to the n 3.3V I/O power supply and 2.5V logic power supply desired application. The CLC031A is auto-configured to a operation default operating condition at power-on or after a reset com- n Low power: typically 850mW mand. Separate power pins for the PLL, deserializer and n 64-pin TQFP package other functional circuits improve power supply rejection and n Commercial temperature range 0˚C to +70˚C noise performance. * Patent applications made or pending. The CLC031A has a unique Built-In Self-Test (BIST) and video Test Pattern Generator (TPG). The BIST enables com- prehensive testing of the device by the user. The BIST uses Applications the TPG as input data and includes SD and HD component n SDTV/HDTV serial-to-parallel digital video interfaces for: video test patterns, reference black, PLL and EQ pathologi- — Video editing equipment cals and a 75% saturation, 8 vertical colour bar pattern, for — VTRs all implemented rasters. The colour bar pattern has optional — Standards converters transition coding at changes in the chroma and luma bar — Digital video routers and switchers data. The TPG data is output via the parallel data port. — Digital video processing and editing equipment The CLC030, SMPTE 292M / 259M Digital Video Serializer — Video test pattern generators and digital video test with Ancillary Data FIFO and Integrated Cable Driver, is the equipment ideal complement to the CLC031A. — Video signal generators Ordering Information Order Number Package Type NS Package Number CLC031AVEC 64-Pin TQFP VEC-64A © 2004 National Semiconductor Corporation DS200201 www.national.com Typical Application CLC031A 20020101 www.national.com 2 CLC031A Block Diagram 20020102 3 www.national.com Connection Diagram CLC031A 20020103 64-Pin TQFP Order Number CLC031AVEC See NS Package Number VEC-64A www.national.com 4 CLC031A Absolute Maximum Ratings (Note 1) CMOS Input Current (single input): It is anticipated that this device will not be offered in Vi=VSSIO −0.15V: −5 mA a military qualified version. If Military/Aerospace speci- Vi=V +0.15V: +5 mA fied devices are required, please contact the National DDIO Semiconductor Sales Office / Distributors for availability CMOS Output Source/Sink Current: ±6mA and specifications. IBB Output Current: +300 µA CMOS I/O Supply Voltage IREF Output Current: +300 µA (VDDIO–VSSIO): 4.0V SDI Input Voltage VSSSI −0.15V to SDI Supply Voltage (Vi): VDDSI +0.15V (VDDSI–VSSSI): 4.0V Package Thermal Resistance θ Digital Logic Supply Voltage JA @ 0 LFM Airflow 40.1˚C/W θ (VDDD–VSSD): 3.0V JA @ 500 LFM Airflow 24.5˚C/W θ PLL Supply Voltage JC 5.23˚C/W (VDDPLL–VSSPLL): 3.0V Storage Temp. Range: −65˚C to +150˚C CMOS Input Voltage VSSIO −0.15V to Junction Temperature: +150˚C (Vi): VDDIO +0.15V Lead Temperature (Soldering 4 CMOS Output Voltage VSSIO −0.15V to Sec): +260˚C (Vo): VDDIO +0.15V ESD Rating (HBM): 6.0 kV ESD Rating (MM): 400 V Recommended Operating Conditions Symbol Parameter Conditions Reference Min Typ Max Units V CMOS I/O Supply Voltage V −V DDIO DDIO SSIO 3.150 3.300 3.450 V VDDSD SDI Supply Voltage VDDSI−VSSSI Digital Logic Supply V V –V DDD Voltage DDD SSD 2.375 2.500 2.625 V VDDPLL PLL Supply Voltage VDDPLL–VSSPLL Operating Free Air T 0 +70 ˚C A Temperature Required Input Conditions (Note 9) Symbol Parameter Conditions Reference Min Typ Max Units VIN Input Voltage Range All LVCMOS VSSIO VDDIO V tr,tf Rise Time, Fall Time 10%–90%Inputs 1.0 1.5 3.0 ns SMPTE 259M, Level C 270 SMPTE 259M, Level D 360 BRSDI Serial Input Data Rate SMPTE 344MSDI, SDI 540 MBPS SMPTE 292M 1,483 SMPTE 292M 1,485 V V V Common Mode Voltage V = 125 mV SSSI DDSI V CM(SDI) IN P-P +1.0V −0.05V V SDI Serial Input Voltage, IN(SDI) 125 800 880 mV Single-ended P-P V SDI Serial Input Voltage, IN(SDI) SDI, SDI 125 800 880 mV Differential P-P 20%–80%, SMPTE 259M 0.4 1.0 1.5 ns Data Rates t ,t Rise Time, Fall Time r f 20%–80%, SMPTE 292M 270 ps Data Rates 5 www.national.com Required Input Conditions (Continued) Symbol Parameter Conditions Reference Min Typ Max Units CLC031A Ancillary / Control Data f V MHz ACLK Clock Frequency CLK DCACLK Duty Cycle, Ancillary Clock 45 50 55 % ACLK Ancillary / Control Clock tr,tf and Data Rise Time, Fall 10%–90% 1.0 1.5 3.0 ns Time Setup Time, ADN to ACLK tS or ION to ACLK Rising 3.0 1.5 ns Edge Control Data Input or ION,ADN,ACLK Hold Time, Rising Edge I/O Bus Input Timing Diagram tH ACLK to ADN or ACLK to 3.0 1.5 ns ION Bias Supply Reference R Tolerance 1% 4.75k Ω REF Resistor f External Clock Frequency Ext Clk −100 +100 EXT CLK 27.0 MHz fXTAL Crystal Frequency Figure 6 XTALo, XTALi ppm ppm DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter Conditions Reference Min Typ Max Units V Input Voltage High Level 2.0 V IH DDIO V VIL Input Voltage Low LevelAll LVCMOS VSSIO 0.8 I Input Current High Level V =V (Note 8)Inputs +85 +150 IH IH DDIO µA IIL Input Current Low Level VIL =VSSIO −1 −20 VOH Output Voltage High Level IOH =−2mA 2.4 2.7 VDDIO V V V Output Voltage Low Level I =+2mA V SSIO SSIO OL OL SSIO +0.3 +0.5V All LVCMOS I =−2mA V V V Minimum Dynamic V OH Outputs DDIO OHV OH (Note 6) −0.5 I =+2mA V V Maximum Dynamic V OL SSIO OLP OL (Note 6) +0.4 VSDI Serial Data Input Voltage 125 800 880 mVP-P ISDI Serial Data Input Current SDI, SDI ±1 ±10 µA VTH Input Thereshold Over VCM range <100 mV Bias Supply Output I R = 8.66kΩ 1% −220 −188 BB Current BB µA Ω IREF Reference Output Current RREF = 4.75k 1% −290 −262 Power Supply Current, 270MBPS Data Rate 38.0 45.0 IDD (3.3V) VDDIO,VDDSI mA 3.3V Supply, Total 1,485MBPS Data Rate 47.0 50.0 Power Supply Current, 270MBPS Data Rate 80 120 IDD (2.5V) VDDD,VDDPLL mA 2.5V Supply, Total 1,485MBPS Data Rate 220 340 www.national.com 6 CLC031A AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). Symbol Parameter Conditions Reference Min Typ Max Units Serial Video Data Inputs SMPTE 259M, Level C 270 SMPTE 259M, Level D 360 BRSDI Serial Input Data Rate SMPTE 344M 540 MBPS SMPTE 292M 1,483 SMPTE 292MSDI, SDI 1,485 20%–80%, SMPTE 259M 0.4 1.0 1.5 pns Data Rates t ,t Rise Time, Fall Time r f 20%–80%, SMPTE 292M 270 ps Data Rates Parallel Video Data Outputs SMPTE 259M, 270MBPS 27.0 SMPTE 267M, 360MBPS 36.0 Video Output Clock f SMPTE 344M, 540M V 54.0 MHz VCLK Frequency BPS CLK SMPTE 292M, 1,483MBPS 74.176 SMPTE 292M, 1,485MBPS 74.25 Propagation Delay, Video V to DV t 50%–50% CLK N 0.5 2.0 ns pd Clock to Video Data Valid Timing Diagram DCV Duty Cycle, Video Clock VCLK 50±5% 27MHz 2.0 Video Data Output Clock 36MHz 1.4 t V ns JIT Jitter 54MHzCLK 1.0 P-P 74.25MHz 0.5 Parallel Ancillary / Control Data Inputs, Multi-function Parallel Bus Inputs Ancillary / Control Data f V MHz ACLK Clock Frequency CLK A Duty Cycle, Ancillary Data ANC Data clock CLK DC 45 50 55 % A Clock (Note 7) Output Rise Time, Fall t ,t 10%–90% 1.0 1.5 3.0 r f Time Setup Time, AD to A t N CLK IO ,AD ,A 3.0 1.5 S or IO to A Rising Edge N N CLK ns N CLK Control Data Input or I/O Timing Diagram Hold Time, Rising Edge Bus Input tH ACLK to ADN or ACLK to 3.0 1.5 ION Parallel Ancillary / Control Data Outputs Propagation Delay, Clock t 8.5 pd to Control Data A to AD 50%–50% CLK N ns Propagation Delay, Clock Timing Diagram t 11.5 pd to Ancillary Data Multi-function Parallel I/O Bus IO0–IO7 t ,t Rise Time, Fall Time 10%–90% 1.0 1.5 3.0 ns r f Timing Diagram PLL/CDR, Format Detect SD Rates (Note 5) 0.32 1.0 t Lock Detect Time LOCK HD Rates (Note 5) 0.26 1.0 ms tFORMAT Format Detect Time All Rates 20 Note 1: “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed.
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