JTAG/IEEE 1149.1 Design Considerations

JTAG/IEEE 1149.1 Design Considerations Application Report 1996 Advanced System Logic Products Printed in U.S.A. SCTA029 1196–CP JTAG/IEEE 1149.1 Design Considerations Data Book 1996 Advanced System Logic Products Printed in U.S.A. SCTA029 1196–CP Application Report JTAG/IEEE 1149.1 Design Considerations SCTA029 1 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright 1996, Texas Instruments Incorporated 2 Contents Title Page Introduction . 1 Is JTAG Right for You? . 2 Boundary-Scan Training . 4 Determining Where to Place Boundary-Scan Devices. 5 Available Literature on TI’s JTAG Boundary-Scan Logic Products. 6 Acknowledgment . 6 Appendix A – Basics of Boundary Scan . 7 Appendix B – Boundary-Scan Success Stories. 11 List of Illustrations Figure Title Page 1 Physical Access Problem in PCB Designs. 1 2 Life-Cycle Costs of Typical Product. 3 3 Boundary-Scan Cell . 7 4 Pinout of TI’s SN74BCT8244 . 7 5 TAP-Controller State Diagram . 8 6 Scan Path Connecting Two Boundary-Scan Devices. 9 List of Tables Table Title Page 1 Comparative Test-Cost Model . 2 2 Performance Comparison, JTAG Transceiver Functions. 5 iii iv Introduction The JTAG/IEEE 1149.1 test standard is becoming widely accepted as a way to overcome the problems created by surface-mount packages, double-sided boards, and multichip modules (see Figure 1), all of which result in a loss of physical access to signals on the board. By providing a means to test printed-circuit boards and modules that might otherwise be untestable, the time and cost required to develop a product and bring it to market can be reduced significantly. (see Appendix A for a brief overview of the 1149.1 standard.) Yesterday Today Tomorrow? Figure 1. Physical-Access Problem in PCB Designs The conversion to boundary scan has been readily accepted by many who realize that traditional test methods are not effective in dealing with the issues of decreasing physical access. Their products are such that faults not detected in the factory can be costly to isolate and repair if they surface after they are in the field. These customers see boundary scan as the only solution and have realized cost as well as time-to-market savings, in addition to providing a more reliable product to their customers. There are others who view boundary scan more skeptically and are uncertain of the ultimate benefits. To help illustrate the potential savings of boundary scan, Table 1 provides a comparative test cost model for an application from the professional product division of Philips Electronics, which involved including boundary scan in their ASICs. Though it doesn’t specifically address boundary-scan logic, the benefits to test program generation, testers, fixture costs, etc. apply. The reader may use this table as a guide to determine the comparative cost savings for his application. In place of the implementation costs for ASICs, you can substitute additional material costs associated with boundary-scan bus interface devices over their nonscan counterparts. In addition to costs savings, there are the benefits of decreased time to market, improved product quality, reduced customer downtime, etc. 1 Table 1. Comparative Test-Cost Model BOUNDARY SCAN NON BOUNDARY SCAN Implementation cost (BSR) 200k boards/year, $600k None 12 ASICs per PCB, 1% of $25 ASIC Test program generation 50 hours/tyhours/typpee= = $75k 300 hours/tyhours/typpee= = $450k 30 PCB types/year @ $50/hour Diagnostics 10 min. pperer rerepairpair = 10k hourshours = 2 min. per repair = 2k hours = $50k 70% yield of 200k PCBs = 60k PCBs $250k to be repaired @ $25/hour Number of testers ppllusus diagnostic time and retest ppllusus diagnostic time and retest 200k PCBs/year, test time 3 min./PCB = 10k hrs; = 15k hours = 3 testers = 23k hours = 5 testers 3 shifts/tester yields 5k hrs/year/tester Tester costs $75k $500k Investment = cost of ownership 33%/year $75k $830k Fixture costs @ $5k = $150k @ $15k = $450k 30 fixtures Labor cost 15k hours 23k hours @ $25/hour $375k $575k Yearly total $1325k $2555k (from: Boundary-Scan Test, A Practical Approach by Harry Bleeker, Peter van den Eijnden, and Frans de Jong, 1993) Implementing boundary scan into a design requires a different mindset due to the different hardware, software, and test equipment needs versus traditional test methods, Designers are often uncertain as to exactly how they should begin, what issues must be considered, and what pitfalls await. The purpose of this report is to touch on some of the issues designers should consider when designing with off-the-shelf boundary-scan logic components. Is JTAG Right for You? As noted in the introduction, one of the first decisions you will face is whether using boundary scan is of benefit to you. The designer is faced with many issues that must be addressed when implementing boundary scan into a design, versus a design with standard components. A key concern is the fact that boundary-scan devices generally are priced slightly higher than their non-JTAG counterparts. However, as shown in Table 1, there are many situations where the additional material cost of implementing boundary scan is offset by a reduction in life-cycle costs. Figure 2 provides two views of product life-cycle costs. The lower curve represents actual dollars spent. The upper curve illustrates that development decisions commit funds that other process steps must spend. By the time engineering “releases” a product to manufacturing, 85% of the project’s total costs are committed. These costs are driven by decisions made during the design phase and can only be reduced if they are considered early in the design phase. Both of the above examples illustrate that the goal of boundary scan is to reduce the product’s life-cycle cost, even though board or system material costs may increase. The life-cycle cost reduction is achieved by enabling faults to be easily identified and isolated, reducing test development and execution time. Further cost reduction is achieved by reducing or eliminating the need for expensive test fixtures and equipment. 2 Conception Validation Development Production Operation Support Dollars Committed Hidden Costs Dollars Spent (from ”Controlling Life-Cycle Costs Through Concurrent Engineering”, Addendum to the ATE and Instrumentation Proceedings, Miller Freeman Expositions, 1992) Figure 2. Life-Cycle Costs of Typical Product The use of boundary scan can also have a positive impact on time to market, resulting in a maximization of profit potential. These benefits are discussed in greater detail throughout this document. To make an accurate assessment of the benefits of boundary scan, representatives of all of the disciplines involved in the product’s development must discuss their respective problem areas. Only then can a solution be reached that truly addresses the total product life-cycle cost. Several factors can be analyzed to determine the impact of boundary scan on your application: Boundary Scan Can Reduce PCB Debug Time By providing access to device I/O without probes, boundary scan allows you to quickly identify and isolate defects to the device and, often, the pin level. Boards that previously may have taken weeks to debug can now be tested in a matter of days or even hours. Additionally, faults that may not have been detected during board test can now be found, preventing faults from surfacing during final test when the costs of finding and repairing the failure are magnified. Boundary-Scan Components Help Reduce Test Program Development Time Because tests can be performed independent of device functionality, costly in-circuit test models do not have to be developed. Instead, the user can obtain boundary-scan description language files (BSDL) from the silicon vendor. These files describe how boundary scan has been implemented within the part so tools can understand how to communicate with it. Another key feature of boundary scan is that tests performed at the device level can be rerun at the PCB and system level, reducing or eliminating the need to develop new tests or generate new test vectors.

Load more