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Dft) for Embedded Board Test

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Dft) for Embedded Board Test Design for Test (DfT) for Embedded Board Test Foresighted Board Level Design for Optimal Testability and Coverage Content 1. Design for Test - Embedded Board Test .................................................................................................. 5 1.1 Why Design for Test? ......................................................................................................................... 5 1.2 Why should you care about Embedded Board Test? ..................................................................... 5 1.3 Embedded Board Test Elements ....................................................................................................... 7 2. Chip Level DfT .............................................................................................................................................. 9 2.1 Insert IEEE 1149.1 functionality into ASICs .................................................................................... 9 2.2 Insert BIST functionality into ASICs ................................................................................................. 9 3. Board Level DfT – Main ICs ...................................................................................................................... 10 3.1 Select IEEE 1149.1 compliant ICs, if possible or necessary ........................................................ 10 3.2 Request accurate BSDL files from IC manufacturers ................................................................... 11 3.3 Verify standard compliance of the BSDL files ............................................................................... 11 3.4 Check BSDL files for compliance conditions and design warnings ............................................. 11 3.5 Check BSDL files for BIST capabilities ............................................................................................ 11 3.6 IEEE 1532 – Advantages over SVF or JAM/STAPL ....................................................................... 11 3.7 Place Board-Logic Functionality into FPGAs .................................................................................. 12 3.8 Watch the watchdog!........................................................................................................................ 12 3.9 Design for testability is team work ................................................................................................. 12 4. Scan Chains & Debug Ports ...................................................................................................................... 13 4.1 Test/Debug Port design – be consistent ........................................................................................ 13 4.2 Test/Debug Port layout and placement ......................................................................................... 13 4.3 Ensure proper TAP pin connections ................................................................................................ 13 4.4 Use pull-resistors to set compliance pins, boot pins or test control pins .................................. 14 4.5 Mind the PCB layout of test bus signals ......................................................................................... 14 4.6 Optimize test bus signal terminations ............................................................................................ 14 4.7 Maximum scan chain device number ............................................................................................. 16 4.8 Scan chain voltage levels ................................................................................................................. 17 4.9 Help test engineers in quickly locating scan chain errors ........................................................... 17 4.10 BScan ICs that power other BScan ICs & EXTEST ....................................................................... 17 4.11 Testing of assemblies of multiple boards ...................................................................................... 17 4.12 Allow to bypass ICs that are not mounted or not compliant ...................................................... 18 4.13 FPGA configuration and Boundary Scan ........................................................................................ 18 4.14 FPGA Concatenation ......................................................................................................................... 19 4.15 FPGA/CPLD test designs ................................................................................................................... 19 4.16 When to place devices in a separate scan chain? ........................................................................ 18 5. Non-Boundary Scan Signals and Devices ............................................................................................... 20 5.1 Provide access to control signals .................................................................................................... 20 5.2 Provide means to disable non-Boundary Scan ICs completely ................................................... 20 5.3 Make logic clusters controllable, whenever possible .................................................................... 21 5.4 Spare pins – BScan vs. GPIO vs. analogue… ................................................................................ 21 5.5 Access to all signals of memory ICs ............................................................................................... 21 6. Programming .............................................................................................................................................. 22 6.1 Access to programmable non-Boundary Scan ICs........................................................................ 22 6.2 Enhance programming speed with direct access to Write Enable pin ....................................... 22 6.3 TCK frequency impact ...................................................................................................................... 23 6.4 On-chip Flash memory ..................................................................................................................... 23 7. Extending Boundary Scan Test Coverage ............................................................................................... 24 7.1 Utilizing Boundary Scan throughout the product life cycle ......................................................... 24 7.2 Utilize test modes in non-Boundary Scan ICs (e.g. NAND-Tree) ............................................... 24 7.3 Test of analogue circuitry ................................................................................................................ 25 7.4 Test of optical components .............................................................................................................. 26 7.5 Test of switches ................................................................................................................................. 26 7.6 Clock signal verification .................................................................................................................... 27 7.7 Clock signal measurement ............................................................................................................... 27 7.8 Improving coverage using I/O tests ............................................................................................... 28 7.9 Improving coverage using at-speed tests (VarioTAP® and VarioCORE®) ................................. 28 7.10 Improving coverage by combining various test methodologies ................................................. 29 7.11 System test – Scan Router ICs ........................................................................................................ 31 8. Select an Embedded Board Test System ................................................................................................ 32 8.1 Software ............................................................................................................................................. 32 8.2 Hardware ............................................................................................................................................ 33 8.3 Licensing ............................................................................................................................................. 33 9. Glossary ....................................................................................................................................................... 34 10. Figures ..................................................................................................................................................... 36 1. Design for Test - Embedded Board Test 1.1 Why Design for Test? Many of today’s products contain quite complex components for information collection, processing and exchange. Besides, many of those components come in packages whose tens or hundreds of pins are either very narrow pitch or not even visible anymore. For many products, quality is an issue, not only for cost reasons but also for customer satisfaction; losing a reputation might be costly at the end or even lead to bankruptcy of a company. And a good product quality can be assured by good testing and that includes some preparations, known as Design for Test or DfT. But how much cost for test is good for a product? On the other side, how much cost will arise from not testing? The test efforts are different for every individual product
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