SEMIDRIVER Medium Power Double IGBT Driver
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No warranty or guarantee expressed or implied is made regarding Typical Applications delivery, performance or suitability. + -9#*./ : - * ;# 2+ $ )%% * + $% <: 1) .#* # -#*.%* %- %#$# % .%*%* 2) $*+ - = & > 3) # % *% .%* %* %- * ,# 2/ " * ""? % -+@ A 4) . % 2 # 6 && B? -% + .#*3 2 A 5) 7 " = C 8D3 "" = A & $;? -+@ C 6) ;.%/ ,#? % # 2 1 26-06-2006 MHW © by SEMIKRON Block diagramm SKHI 23 Fig. 1 The numbers refer to the description on page B14 – 45, section B. Fig. 2 Dimensions (in mm) and connections of the SKHI 23 2 26-06-2006 by SEMIKRON SEMIDRIVERTM SKHI 23/12 the 5 V level due to possible disturbances emitted by SEMIDRIVERTM SKHI 23/17 the power side. c) An INTERLOCK circuit prevents the two IGBTs of the Medium Power Double IGBT Driver half bridge to switch-on at the same time, and a “deadtime” can be adjusted by putting additional Overview resistors between pins J3 and K3 (RTD1) and pins J4 and K4 (RTD2). Therefore it will be possible to reduce The new intelligent double IGBT driver, SKHI 23 the deadtimet tTD (see also table 3). respectively SKHI 23/17 is a standard driver for all power The interlocking may also be inhibit by solder bridging IGBTs in the market. between pins J5 and K5 to obtain two independent drivers. SKHI 23/12 drives all IGBTs with VCE up to 1200 V. SKHI 23/17 drives all IGBTs with VCE up to 1700 V. To protect d) The ERROR MEMORY blocks the transmission of all the driver against moisture and dust it is coated with turn-on signals to the IGBT if either a short circuit or varnish. The adaption of the drivers to the application has malfunction of Vs is detected, a signal is sent to the been improved by using pins to changing several external control board through an open collector parameters and functions. The connections to the IGBTs transistor. It is preset to “high-logic” but can be set to can be made by using only one MOLEX connector with “low-logic” (ERROR). 12 pins or by using 2 separate connectors with 5 pins for each IGBT. e) The Vs MONITOR ensures that Vs actual is not below 13 V. The high power outputs capability was designed to switch high current double or single modules (or paralleled f) With a FERRITE TRANSFORMER the information IGBTs). The output buffers have been improved to make between primary and secondary may flow in both it possible to switch up to 200 A IGBT modules at directions and high levels of dv/dt and isolation are frequencies up to 20 kHz. obtained. A new function has been added to the short circuit g) A high frequency DC/DC CONVERTER avoids the protection circuitry (Soft Turn Off), this automatically requirement of external isolated power supplies to increases the IGBT turn off time and hence reduces the obtain the necessary gate voltage. An isolated ferrite DC voltage overshoot enabling the use of higher DC-bus transformer in half-bridge configuration supplies the voltages. This means an increase in the final output necessary power to the gate of the IGBT. With this power. feature, we can use the same power supply used in the external control circuit, even if we are using more Integrated DC/DC converters with high galvanic isolation than one SKHI 23, e.g. in three-phase configurations. (4 kV) ensures that the user is protected from the high voltage (secondary side). h) Short circuit protection is provided by measuring the collector-emitter voltage with a V MONITORING The power supply for the driver may be the same as used CE in the control board (0/+15 V) without the requirement of circuit. An additional circuit detects the short circuit isolation. All information that is transmitted between input after a delay (adjusted with RCE (this value can only be and output uses ferrite transformers, resulting in high dv/ reduced) and CCE (this value can only be increased) dt immunity (75 kV/µs). and decreases the turn off speed (adjusted by Rgoff-SC) of the IGBT. SOFT TURN-OFF under fault conditions The driver input stages are connected directly to the is necessary as it reduces the voltage overshoot and control board output and due to different control board allows for a faster turn off during normal operation. operating voltages, the input circuit includes a user voltage level selector (+15 V or +5 V). In the following only i) The OUTPUT BUFFER is responsible for providing the the designation SKHI 23 is used. This is valid for both correct current to the gate of the IGBT. If these signals driver versions. Any unique features will be marked as do not have sufficient power, the IGBT will not switch properly, and additional losses or even the destruction SKHI 23/12 (VCE = 1200 V) or SKHI 23/17 (VCE = 1700 V) respectively. of the IGBT may occur. According to the application (switching frequency and gate charge of the IGBT) the A. Features and Configuration of the Driver equivalent value of Rgon and the Rgoff must be matched to the optimum value. This can be done by putting a) A short description is given below. For detailed additional parallel resistors Rgon, Rgoff with those information, please refer to section B. The following is already on the board. If only one IGBT is to be used, valid for both channels (TOP and BOTTOM) unless (instead of paralleled IGBTs) only one cable could be specified. connected between driver and gate by solder bridging between the pins J12 and K12 (TOP) as well as b) The SKHI 23 has an INPUT LEVEL SELECTOR between J19 and K19 (Bottom). circuit for two different levels. It is preset for CMOS (15 V) level, but can be changed by the user to j) Fig. 1 shows a simplified block diagram of the SKHI 23 HCMOS (5 V) level by solder bridging between pins J1 driver. Some preliminary remarks will help the and K1. For long input cables, we do not recommend understanding: © by SEMIKRON 26-06-2006 3 • Stabilised +15 V must be present between pins X1.8,9 The following overview is showing the input treshold (Vs) and X1.10,11 (⊥); an input signal (ON or OFF voltages command to the IGBTs) from the control system is supplied to pins X1.2 and X1.4 (Vin) where HIGH=ON and LOW=OFF. The pin X1.1 can be used as a shield VIT+ (High) min typ max for the input signals. 15 V 9,5 V 11,0 V 12,5 V • Pin X2.5 on TOP (and X3.5 on BOT) at secondary side is normally connected to the collector of the IGBTs to 5 V 1,8 V 2,0 V 2,4 V monitor VCE, but for initial tests without connecting the IGBT it must be connected to pin X2.1 on TOP (and VIT- (Low) min typ max X3.1 on BOT) to avoid ERROR signal and enable the output signals to be measured. 15 V 3,6 V 4,2 V 4,8 V • The RESET is performed when both input Vin signals 5 V 1,8 V 0,65 V 0,8 V are zero (TOP = BOT = LOW). • To monitor the ERROR signal in “high-logic”, a pull-up resistor must be provided between pin X1.3 and Vs. • Table 1 (see page B 14–46) shows the factory adjustment and the different possible adjustments of the pins.