Past, Present, and Future of SPARC64 Processors
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Past, Present, and Future of SPARC64 Processors Takumi Maruyama Tsuyoshi Motokurumada Kuniki Morita Naozumi Aoki SPARC64 is the name of the series of SPARC-V9 architecture processors that Fujitsu has developed. The development of the first SPARC64 started in the 1990s, and the development of the latest generation is actively ongoing as of 2011. The processor frequency of the first SPARC64 was as little as 118 MHz and it had only 20 million transistors, while the processor frequency of the latest SPARC64 VIIIfx is 2 GHz and it has more than 700 million transistors. This paper describes the history of the SPARC64 processor development, and the enhanced points of each generation. 1. Introduction enhanced points of each generation. SPARC64 is the name of the series of SPARC-V9 architecture processors that 2. SPARC64, SPARC64 II Fujitsu has developed. The development of the SPARC64 processor has its origin in first SPARC64 started in the 1990s, and the SPARC641) developed by HAL Computer Systems development of the latest generation is actively (hereafter HAL), the then local subsidiary of ongoing as of 2011 (Figure 1). Fujitsu in the United States. This processor In the first half of the 1990s, various RISC adopted some cutting-edge technologies at the processors emerged besides SPARC. However, time of its shipment including the out-of-order only SPARC and POWER have survived to date superscalar method. However, more importantly, among RISC processor architectures in the high- this model has established the SPARC-V9 end processor segment. Some processors were instruction set architecture.2) superseded in terms of performance and some SPARC architecture is maintained by an could not survive in the market despite their independent non-profit organization called highly acclaimed technical advancement. Both SPARC International. While consultations SPARC and POWER have been developed not and decisions on SPARC-V9 were made by a by processor specialist vendors but by server board called the Architecture Committee in this vendors engaged in processor development. This organization, most of the committee members fact suggests that the excellence of a processor joined from HAL. is not determined by its performance alone but Compared with SPARC-V8, SPARC-V9 is by how it performs in combination with various characterized by expanded features that are components such as a system and OS that essential requirements for server processors such constitute a server. as having a larger address space by adopting a This paper describes the history of the 64-bit architecture, an availability to address SPARC64 processor development, and the multi-processors and enhanced reliability. 130 FUJITSU Sci. Tech. J., Vol. 47, No. 2, pp. 130–135 (April 2011) T. Maruyama et al.: Past, Present, and Future of SPARC64 Processors HPC CMOS Cu 45 nm Extended instruction for HPC (HPC-ACE) SPARC64 VIIIfx Tr=600 M SPARC64 CMOS Cu 65 nm VISIMPACT processor Tr=540 M CMOS Cu SPARC64 90 nm UNIX Multi-core and multi-thread Tr=400 M VII CMOS Cu SPARC64 Secondary cache on Die 90 nm VI Tr=190 M GS21 CMOS Cu SPARC64 1600 Non-Blocking cache 130 nm V + Technology Out-of-order execution SPARC64 Super-Scalar V High-Performance Tr=46 M GS21 Mainframe 900 Tr=30 M CMOS Cu Single-chip CPU CMOS Al 180 nm GS21 Tr=500 M 250 nm / 220 nm 600 CMOS Cu GS8900 90 nm Store Ahead Tr=10 M GS8800B Tr=190 M Branch History CMOS Al GS8800 CMOS Cu SPARC64 130 nm Prefetch 350 nm GP Tr=30 M Cache ECC GS8600 CMOS Cu Register and ALU Parity 180 nm / 150 nm SPARC64 Instruction Retry II Cache Dynamic Degradation SPARC64 : Technology generation Technology RC, RT and History High-Reliability 1996 1998 2000 2004 2008– –1995 –1997 –1999 –2003 –2007 VISIMPACT: Virtual single processor by integrated multi-core parallel architecture Figure 1 Development history of Fujitsu’s processors. Although SPARC64 and SPARC64 II were (0.15 μm CMOS) was developed by Fujitsu.3) used as processors for workstations instead of for SPARC64 GP adopted a single-chip configuration servers, it can be said that SPARC-V9 instruction while following the tradition of the basic pipeline set architecture established a foundation for configuration of SPARC64. Further, by adding using SPARC processors as servers. enhanced features such as a large-capacity SPARC64 was developed by using 0.4 μm external secondary cache and multi-processor complementary metal oxide semiconductors function, its capabilities as a processor for servers (CMOS) based on a frequency of 118 MHz. The were reinforced. Thanks to a duplicate design model adopted a multi-chip module (MCM) and a single-error correction mechanism based configuration, where one CPU core chip, four on parity or error checking and correction (ECC) cache chips and one MMU chip are integrated on for the cache and bus interface, a higher level of the same substrate. Acceleration of processing reliability was achieved in comparison with those speed up to 161 MHz was achieved in SPARC64 II in other UNIX processors at that time. by using 0.35 μm CMOS. SPARC64 GP was used as a processor for GRANPOWER and PRIMEPOWER, 3. SPARC64 GP Fujitsu’s UNIX servers. In its application The early type of SPARC64 GP (0.24 μm in PRIMEPOWER 2000, the world’s highest CMOS) was developed by HAL and its late type performance (7800 users) was achieved in the FUJITSU Sci. Tech. J., Vol. 47, No. 2 (April 2011) 131 T. Maruyama et al.: Past, Present, and Future of SPARC64 Processors 2-Tier SAP-SD Benchmark test at that time. Its increased frequency by increasing the steps of frequency was accelerated from the initial 250 the pipeline. With regard to hardware, Fujitsu MHz to 810 MHz in the end. made efforts to improve performance based on out-of-order execution of memory access, while 4. Mainframe maintaining an appearance that the processing In the beginning of the 1990s, Fujitsu is executed based on the memory access order changed its focus of development from established by SPARC-V9 in terms of software. conventional emitter-coupled logic (ECL) to LSI Technologies developed for mainframe CPUs using CMOS. In 1995, the GS Series, a novel were used also for this purpose. mainframe series characterized by all models In the development of SPARC64 V, an integrating CMOS, was announced. innovative performance evaluation model In GS8600, the first product of the GS series, was developed in a joint effort with Fujitsu features such as a two-level cache system, branch Laboratories, and a detailed configuration was history, store ahead and pre-fetch mechanism determined based on the results of performance were introduced. In GS8800B (2.5 generation evaluation against typical benchmarks such as model), a drastic change to the CPU control Standard Performance Evaluation Corporation method was made, from the lock step pipeline (SPEC) and Transaction Processing Performance method to the out-of-order superscalar method, Council Benchmark C (TPC-C). Further, to further improve performance. Thereafter, in highly reliable features conventionally adopted GS8900, a totally novel design was introduced in mainframes such as CPU hardware retry, to the cache component to achieve a more complete rescue of SRAM single-bit error and sophisticated CPU based on the superscalar history function were introduced, for the first method. The pipeline for CPUs, developed for time, to CPUs for UNIX. this GS8900, served as the basis of SPARC64 V, Moreover, to enhance the OS portability which will be explained in the next section. between Fujitsu’s SPARC64 Series and the UltraSPARC Series developed by Sun 5. SPARC64 V Microsystems, a new specification called The early models of SPARC64 V were joint programmer’s specification (JPS) was developed by using 130 nm CMOS, while late developed.7),8) SPARC64 V and later processors models used 90 nm CMOS.4),5) The frequency was adopted instruction set architectures compliant accelerated from the initial 1.35 GHz to 2.16 GHz with SPARC-V9 and JPS. in the final stage. SPARC64 V was used as a processor for A new pipeline was introduced to SPARC64 PRIMEPOWER, one of Fujitsu’s UNIX servers. V so that its basic structure would be identical PRIMEPOWER 2500 achieved the world’s with those of the CPU pipeline for mainframes.6) highest performance (21 000 users) in 2-Tier While both of SPARC64 GP and SPARC64 V are SAP-SD Benchmark tests at that time. four instruction issue, out-of-order superscalar processors, their micro-architectures are 6. SPARC64 VI significantly different from each other. SPARC64 VI is an extended series based on The main focus in designing the SPARC64 SPARC64 V, developed as a processor for SPARC GP was to increase the number of instructions Enterprise—a common UNIX server for Fujitsu to be executed per cycle by reducing the pipeline and Sun Microsystems. This series used Fujitsu’s steps. Meanwhile, with regard to SPARC64 V, the 90 nm CMOS and had a maximum frequency of aim was to produce a structure that could handle 2.4 GHz. 132 FUJITSU Sci. Tech. J., Vol. 47, No. 2 (April 2011) T. Maruyama et al.: Past, Present, and Future of SPARC64 Processors In SPARC64 VI, a configuration was adopted 8. SPARC64 VIIIfx where two cores on the basis of SPARC64 V were SPARC64 VIIIfx was developed as a built-in chips and the two threads were executed processor for supercomputers. This model was in each core.9) This multi-thread configuration adopted in the Next-Generation Super Computer was realized by using a method called vertical (nicknamed “K computer”) developed within multi-threading (VMT), to switch from one thread the framework of the Ministry of Education, to another using an event as a trigger.