DOCSLIB.ORG

Installation and Upgrade General Checklist Report

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Installation and Upgrade General Checklist Report VeritasTM Services and Operations Readiness Tools Installation and Upgrade Checklist Report for InfoScale Storage 7.3.1, Solaris 11, SPARC Index Back to top Important Notes Components for InfoScale System requirements Product features Product documentation Patches for InfoScale Storage and Platform Platform configuration Host bus adapter (HBA) parameters and switch parameters Operations Manager Array Support Libraries (ASLs) Additional tasks to consider Important Notes Back to top Note: You have not selected the latest product version. Consider installing or upgrading to the latest version; otherwise, you may encounter issues that have already been fixed. To run a new report for the latest product version, select it from the Veritas product drop-down list. Array Support Libraries (ASLs) When installing Veritas products, please be aware that ASLs updates are not included in the patches update bundle. Please go to the Array Support Libraries (ASLs) to get the latest updates for your disk arrays. Components for InfoScale Back to top The InfoScale product you selected contains the following component(s). Dynamic Multi-Pathing Storage Foundation Storage Foundation Cluster File System Get more introduction of Veritas InfoScale. System requirements Back to top Required CPU number and memory: Required number of CPUs Required memory SF or SFHA N/A 2GB SFCFS or SFCFSHA 2 2GB 1 of 11 VeritasTM Services and Operations Readiness Tools Required disk space: Partitions Minimum space required Maximum space required Recommended space /opt 99 MB 1051 MB 134 MB /root 1 MB 30 MB 1 MB /usr 3 MB 237 MB 3 MB /var 1 MB 1 MB 1 MB Supported architectures: SPARC M5 series [1] SPARC M6 series [1] SPARC M7 series [1][2] SPARC S7 series [1] SPARC T3 series [1] SPARC T4 series [1] SPARC T5 series [1] SPARC T7 series [1][2] SPARC T8 series [1][2] SPARC64 X+ series [1] SPARC64 XII series [1] SPARC64-V series SPARC64-VI series SPARC64-VII/VII+ series SPARC64-X series [1] UltraSPARC II series UltraSPARC III series UltraSPARC IV series UltraSPARC T1 series [1] UltraSPARC T2/T2+ series [1] 1. Oracle VM Server for SPARC supported. See the following TechNote: http://www.veritas.com/docs/DOC5860. 2. eUSB device is not supported. Related documentation Multi-core multi-thread processor SPARC64 Series Oracle's SPARC T3 SPARC T3 Processor Overview SPARC T4 Processor Data Sheet UltraSPARC - III CPU Module Installation Guide UltraSPARC IIs CPU Module Installation Guide UltraSPARC Processors 2 of 11 VeritasTM Services and Operations Readiness Tools Product features Back to top The features in the list are enabled in this release. Feature InfoScale Storage 1-256 TB File System ALUA and Generic ALUA Array Support Alert for SG Freeze/Unfreeze with time counter CFS Multi-transaction server Cluster File System Cluster Volume Manager Compression Concurrent I/O Data management application programming interface (DMAPI) Deduplication Device names consistent across cluster nodes Device names using Array Volume IDs Direct I/O Dirty region logging Dynamic LUN expansion Dynamic Multi-pathing Dynamic Multi-pathing - Intelligent pathing for EMC VPLEX Enclosure based naming FSS performance enhancements Fault tolerant file system File Change Log File system migration from EXT4 to VxFS File system snapshots File system storage checkpoints Flashsnap: Disk group split & join Flashsnap: Fast resynchronization Full size instant snapshots Hardware assisted copy Heartbeats: LLT over UDP Heartbeats: Low-priority Heartbeats:Dedicated Private Network connections Hot-relocation Import cloned LUN Improved VVR network bandwidth utilization for TCP protocol 3 of 11 VeritasTM Services and Operations Readiness Tools Keyless licensing Live migration from Oracle ASM Single Instance to VxFS Mount lock NFSv4 support Named data streams NetApp C-Dot Array Support Online coordinator disk replacement Online file system defragmentation Online file system grow & shrink Online relay out Online volume grow & shrink Operations Manager Oracle Disk Manager (ODM) and Cached ODM (CODM) Partitioned directories Portable Data Containers (formerly known as Cross-Platform Data Sharing (CDS)) Puppet support Quality of Service (QoS) for applications Quick I/O (QIO) and Cached QIO (CQIO) Remote mirrors for campus clusters Replicator option (formerly Volume Replicator) SCSI-3 based I/O fencing SCSI3-PGR Fencing with Coordinator Disks SSD device exploitation Security Exceptions for VIOM Site awareness with remote mirrors SmartAssist - SmartIO analysis & enablement tool SmartIO - Volume Manager and File System Read Caching SmartIO - Write Back Caching (ALL DLV's ) SmartMove SmartTier (formerly Dynamic Storage Tiering) Space-optimized instant snapshot Split-mirror snapshot Sub-cluster support Support for NVMe devices for non-intel cards Support for native 4k sector size storage devices Thin storage reclamation Thin storage reclamation using UNMAP Third Party Certificate Support 4 of 11 VeritasTM Services and Operations Readiness Tools User & group quotas VIOM API for service group management (Online/Offline/Switch) iSCSI device support Database storage checkpoints & rollback Oracle only FlashSnap: Database Oracle only SmartTier for Oracle (formerly Database DST) Oracle only Product documentation Back to top Product guides Veritas InfoScale Solutions Guide - English Veritas InfoScale Replication Administrator's Guide - English Veritas InfoScale Disaster Recovery Implementation Guide - English Veritas InfoScale Troubleshooting Guide - English InfoScale Solutions Guides Veritas InfoScale Solutions SmartIO for Solid-State Drives Solutions Guide - English Veritas InfoScale Virtualization Guide - English Veritas InfoScale Storage and Availability Management for Oracle Databases - English Veritas InfoScale What's New In This Release - English Release Notes Veritas InfoScale Release Notes - English Veritas InfoScale Updates, Patches, and Late Breaking News (LBN) - English Storage Foundation Configuration and Upgrade Guide - English Storage Foundation Guides Storage Foundation Administrator's Guide - English Veritas File System Programmer's Reference Guide - English Veritas InfoScale Installation Guide - English Installation Guide Veritas InfoScale Chef Deployment Guide - English Dynamic Multi-Pathing Guide Dynamic Multi-Pathing Administrator's Guide - English 5 of 11 VeritasTM Services and Operations Readiness Tools Getting Started Veritas InfoScale Getting Started Guide - English Legal Notice Veritas InfoScale Third-Party Software License Agreements - English Manual pages Manual Pages Veritas InfoScale Storage Manual Pages - English Compatibility lists Veritas InfoScale Hardware Compatibility List - AIX, Linux, Solaris - English Compatibility Lists Veritas InfoScale Software Compatibility List - Solaris - English Patches for InfoScale Storage and Platform Back to top Product (recommended) Patch Date Size cpi-Patch-7.3.1.2100 2021-08-30 37.61 KB dbed-sol11_spa...atch-7.3.1.1100 2020-01-23 75.95 MB vcs-sol11_sparc-Patch-7.3.1.1100 2019-11-05 100.18 MB infoscale-sol11...-Patch-7.3.1.200 2019-06-24 85.74 MB infoscale-sol11...-Patch-7.3.1.100 2019-02-28 88.44 MB vcsag-sol11_sp...Patch-7.3.1.100 2018-09-10 4.86 MB vcs-sol11_sparc-Patch-7.3.1.100 2018-09-10 99.59 MB cpi-Patch-7.3.1.200 2018-05-23 4.93 KB Platform (required) No patches required. Platform configuration Back to top Supported platform version. Last updated on 2021-01-01 Product versionPlatform version7.3.111.4, 11.3, 11.2, 11.1 Related documentation Oracle Solaris 11 Operating System Overview 6 of 11 VeritasTM Services and Operations Readiness Tools Host bus adapter (HBA) parameters and switch parameters Back to top Unless otherwise stated, the specified Veritas product supports all HBAs (except iSCSI HBAs) and fibre channel switches supported by the platform and storage array manufacturers listed in the hardware compatibility list (HCL). For more details, click the link to the HCL. Operations Manager Back to top Veritas InfoScale Operations Manager gives you a single, centralized management console for the InfoScale products. You can use it to monitor, visualize, and manage storage and cluster resources, and generate reports about these components in the Management Server domain.It can also help administrators centrally manage diverse data center environments. This section lists the documents for Veritas InfoScale Operations Manager 7.4.2. Documentation Array Support Libraries (ASLs) Back to top Array family (model) Documentation Libraries Dell EMC EqualLogic PS3000 series libvxeqlogic (embedded in the package VRTSaslapm) See TechNote Dell EMC EqualLogic PS4000 series libvxeqlogic (embedded in the package VRTSaslapm) See TechNote Dell EMC EqualLogic PS6000 series libvxeqlogic (embedded in the package VRTSaslapm) See TechNote Dell EMC SC Series libvxcompellent (embedded in the package VRTSaslapm) See TechNote Dell EMC Symmetrix DMX series with libvxemc (embedded in the package VRTSaslapm) See TechNote PowerPath Dell EMC Symmetrix DMX series libvxemc (embedded in the package VRTSaslapm) See TechNote Dell EMC Symmetrix VMAX series libvxemc (embedded in the package VRTSaslapm) See TechNote Dell EMC Symmetrix VMAX series libvxemc (embedded in the package VRTSaslapm) See TechNote with PowerPath Dell EMC Unity series libvxCLARiiON (embedded in the package VRTSaslapm) See TechNote Dell EMC VMAX3/VMAX All Flash libvxemc (embedded in the package VRTSaslapm) See TechNote Family series with PowerPath Dell EMC VMAX3/VMAX All Flash libvxemc (embedded in the package VRTSaslapm) See TechNote
Load more

Recommended publications
  • Arm Arhitektura Napreduje – No Postoje Izazovi
    ARM ARHITEKTURA NAPREDUJE – NO POSTOJE IZAZOVI SAŽETAK Procesori ARM ISA arhitekture ne koriste se više "samo" za mobitele i tablete, nego i za serverska računala (pa i superračunala), te laptop / desktop računala. I Apple je kod Macintosh računala prešao sa Intel arhitekture na ARM arhitekturu. Veliki izazov kod tog prelaska bio je - kako omogućiti da se programski kod pisan za Intelovu ISA arhitekturu, izvršava na procesoru M1 koji ima ARM arhitekturu. Općenito, želja je da se programi pisani za jednu ISA arhitekturu mogu sa što manje napora izvršavati na računalima koja imaju drugačiju ISA arhitekturu. Problem je u tome što različite ISA arhitekture mogu imati dosta različite memorijske modele. ABSTRACT ARM ISA processors are no longer used "only" for mobile phones and tablets, but also for server computers (even supercomputers) and laptops / desktops. Apple has also switched from Intel to ARM on Macintosh computers. The big challenge in that transition was - how to enable program code written for Intel's ISA architecture to run on an M1 processor that has an ARM architecture. In general, the desire is that programs written for one ISA architecture can be executed with as little effort as possible on computers that have a different ISA architecture. The problem is that different ISA architectures can have quite different memory models. 1. UVOD Procesori ARM ISA arhitekture ne koriste se više "samo" za mobitele i tablete, nego i za serverska računala (pa i superračunala), te laptop/desktop računala. Koriste se i u industriji, u proizvodnim procesima, a i kao ugradbeni čipovi u ostale proizvode, npr. za ugradnju u IOT uređaje i u vozila (posebno autonomna vozila).
    [Show full text]
  • Fujitsu's Vision for High Performance Computing
    FujitsuFujitsu’’ss VisionVision forfor HighHigh PerformancePerformance ComputingComputing October 26, 2004 Yuji Oinaga Fujitsu Ltd. 1 CONTENTSCONTENTS HPC Policy and Concept Current HPC Platform HPC2500 IA-Cluster Major HPC customers Road Map Toward Peta-Scale Computing 2 FUJITSUFUJITSU HPCHPC PolicyPolicy ~ Developing & Providing Top Level Supercomputer ~ - High Computational Power - High Speed Interconnect - Reliability/Availability - Leading Edge Semiconductor Technology - Highly Reliable, HPC Featured Operating System & Middleware - Sophisticated Compilers and Development Tools 3 HistoryHistory ofof HPCHPC PlatformPlatform PRIMEPOWER HPC2500 VPP5000 Vector Parallel VPP300/700 IA32/IPF Cluster PRIMEPOWER VPP500 2000 Vector VP2000 AP3000 VP Series AP1000 F230-75APU Scalar 1980 1985 1990 1995 2000 2005 4 ConceptConcept ofof FujitsuFujitsu HPCHPC ProvideProvide thethe best/fastestbest/fastest platformplatform forfor eacheach applications.applications. -Scalar SMP : PRIMEPOWER, New Linux SMP -IA Cluster : PRIMERGY Cluster ProvideProvide thethe highhigh speedspeed interconnect.interconnect. -Crossbar : High Speed Optical Interconnect -Multi-Stage : Infiniband ProvideProvide HighHigh Operability/UsabilityOperability/Usability -Enhancement of Operability/Usability : Extended Partitioning, Dynamic Reconfiguration -Cluster Middleware : Total Cluster Control System ( Parallelnavi ) Shared Rapid File System ( SRFS ) 5 FujitsuFujitsu’’ss CurrentCurrent HPCHPC PlatformPlatform ~ Fujitsu is a leading edge company in HPC field ~ SPARC/Solaris
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • Microprocessor
    MICROPROCESSOR www.MPRonline.com THE REPORTINSIDER’S GUIDE TO MICROPROCESSOR HARDWARE FUJITSU’S SPARC64 V IS REAL DEAL Fujitsu’s design differs from HAL’s version; faster than US III By Kevin Krewell {10/21/02-01} At Microprocessor Forum 2002, Fujitsu stepped forward to carry the banner for the fastest SPARC processor, surpassing Sun’s fastest UltraSPARC III on clock frequency and SPEC performance. In fact, at 1.35GHz, the Fujitsu processor has the highest clock frequency of any 64-bit server processor now in production. This by a Fujitsu acquisition, HAL Computer. At Micro- clock-speed advantage—plus large on-chip processor Forum 1999, Mike Shebanow, then vice caches; a fast system-crossbar switch; and a four- president and CTO of the HAL Computer Divi- issue, out-of-order core—translates into good sion of Fujitsu, proposed a complex and very wide SPEC benchmark performance for Fujitsu’s superscalar version of the SPARC64 V processor, SPARC64 V processor. The SPARC64 V is an evo- with an instruction trace cache, superspeculation, lutionary step in Fujitsu’s SPARC processor line and split L2 cache (see MPR 11/15/99-01,“Hal instead of the more-radical approach proposed three Makes Sparcs Fly”). Mike’s innovative chip never made years ago by HAL Computer at Microprocessor Forum it to market, but the trace-cache idea became a mainstream 1999. This latest version of Fujitsu’s SPARC processor fam- processor feature, shipping in Intel’s Pentium 4 microarchi- ily, revealed by Fujitsu’s director of Development Depart- tecture. The Pentium 4 also paralleled another of Mike’s ment (Processor Development Division) Aiichiro Inoue, is based on an enhanced version of the previous SPARC64 GP processor core, with larger caches and advanced semicon- L1I$ Decode & FP (16) L1D$ L2$ 128KB I-buffer Issue (4) SP (10) 128KB 2MB ductor process technology.
    [Show full text]
  • Guía Sobre Tiflotecnología Y Tecnología De Apoyo Para Uso
    Guía sobre Tiflotecnología y Tecnología de Apoyo para uso educativo (Última actualización: febrero 2016) Guía sobre Tiflotecnología y Tecnología de Apoyo para uso educativo ÍNDICE INTRODUCCIÓN ..................................................................................................................................... 6 CONOCIMIENTOS BÁSICOS .................................................................................................................. 11 DEFINICIONES.................................................................................................................................... 11 HARDWARE ....................................................................................................................................... 14 SOFTWARE ........................................................................................................................................ 18 OTROS DISPOSITIVOS ........................................................................................................................ 19 SISTEMA OPERATIVO (VERSIONES) WINDOWS, OS X, IOS, ANDROID, WINDOWS MOBILE, LINUX ........ 22 WINDOWS ......................................................................................................................................... 23 OS X ................................................................................................................................................... 25 LINUX ...............................................................................................................................................
    [Show full text]
  • PAP Advanced Computer Architectures 1 ISA Development History
    Advanced Computer Architectures History and Future Czech Technical University in Prague, Faculty of Electrical Engineering Slides authors: Michal Štepanovský, update Pavel Píša B4M35PAP Advanced Computer Architectures 1 ISA development history 1936 Alan Turing: On computable numbers, with an application to 1939 Bombe: the Entscheidungsproblem designed to crack 1937: Howard Aiken: Concept of Enigma Automatic Sequence Controlled 1941 Konrad Zuse: Calculator – ASCC. Z3 – the world first 1945 John von Neumann: First functional Turing Draft of a Report on the EDVAC. complete computer, New idea: Stored-program program controlled computer. Previous computers 1944 Harvard Mark I required to physically modified to 1944 Colossus for given task. Remark: stored- 1946 ENIAC program idea appeared even 1947 Transistor earlier in 1943 year – ENIAC 1948 Manchester development: J. P. Eckert a J. Baby – the first stored- Mauchly program computer 1949 EDSAC – Computers of that era are single accumulator equipped by accumulator (one 1953 EDSAC, register) for arithmetic and logic Manchester Mark I, operations which is fixed IBM 700 series: single accumulator destination and one of source + index register operands. 2 B4M35PAP Advanced Computer Architectures 2 ISA development history 1954 John Backus: FORTRAN (FOrmula TRANslator) language There is a significant separation of the programming model from 1958: JohnMcCarthy: LSP (LISt implementation !!! Processing) language 1961 B5000: Computer designed and 1960 ALGOL (ALGOrithmic Language) optimized for ALGOL 60
    [Show full text]
  • Sparc64 V/Vi の高性能，高信頼技術
    2006 年 10 月 31 日 サイエンティフック・システム研究会 科学技術計算分科会 2006 年度会合資料 SPARC64 V/VI の高性能，高信頼技術 富士通株式会社 サーバシステム事業本部 井上 愛一郎 [email protected] [アブストラクト] 富士通は黎明期である 1950 年代からコンピュータハードウェアの開発に一貫して取り組んできた．この長い 開発の歴史の中で，富士通では信頼性を常にテーマとして掲げると同時に，最先端の高性能技術を開発して きた． これらの高性能と高信頼の技術を盛り込んだメインフレームの CPU をベースにして，2000 年から SPARC64 V の開発に着手して，これを 2003 年から出荷した． そして 2004 年には，これを 90nm の最先端半導体に焼き なおした二世代目の SPARC64 V＋を出荷し，高性能と高信頼によって大変好評を頂いている． また，これに続くプロセサとして，デュアルコア化，コアのエンハンス，フロントサイドバスを高スループットの Jupiter バスとするなど，マイクロアーキを刷新した SPARC64 VI の出荷が間近となっている．本稿では，ここに 至る開発の歴史を概観しながら，高性能と高信頼に関わる技術を紹介し，あわせて，将来に向けた方向性を示 していきたい． [キーワード] SPARC64，高性能，高信頼，デュアルコア，最先端半導体，開発の歴史 1. はじめに 半導体の集積度の低い時代において，１チップに CPU を収める要件は，マイクロプロセサ開発の大きな制 約であった．一方，同時代に，メインフレームやサーバ用の CPU 開発に求められた第一の要件は，高性能と信 頼性の追及である．この時代のマイクロプロセサとメインフレームの CPU とは，機能に大きな隔たりがあった． テクノロジの進歩でチップの集積度が上がるに伴い，徐々に，高性能化のための複雑な機能が，マイクロプ ロセサに実装されていった．やがてチップをまたぐ信号授受のコストが，性能のボトルネックになるに至り，全て のコンピュータの CPU は 1 チップで作られるようになった．そして，この１チップ化が，かつてのマイクロプロセサ を起源とする CPU と，メインフレームを起源とする CPU の競合状態を生んだ．その中で，多くの人が性能差以 外に，大きな意味を持たないかのように受け止めている．どの CPU も，本当に，違いがなくなってしまったのだ ろうか？ 半導体の集積度向上はなおも続き，チップあたりのトランジスタ数は CPU 1 個分を超過し，それが大容量キ ャッシュの内蔵に繋がった．現在は，複数 CPU を 1 チップに収め，さらにシステム機能も CPU チップに取り込む 流れにある．その一方で，向上した周波数や微細化は消費電力を増大させ，電力量削減と熱冷却が，現在の 1 大きな課題である．そのなかで，システムのありかたまでを含む検討，すなわち，従来どおり性能向上を追求し ていくのか，何によって高性能を実現していくのか，社会の重要なインフラに求められる要件を現在注目されて いる機能で満たしていけるのか，などに対する解が求められている．これから数年間はメインフレームやサー バ用の CPU にとっては，試練の連続であろうことは想像に難くない． 一旦世にでた製品は，開発当初は先進的で優れたものであっても，やがて寿命がくる．しかし，製品のなか にある技術は，注目の多寡があるものの，それは市場の要求や時代のテクノロジとの組み合わせなどに左右 されており，寿命という概念のあてはまらないものである．技術は，必然性との出会いで注目をあび，あるいは，
    [Show full text]
  • Domain Time II Configuration Settings Using the Utilities About Settings (.Reg) Files on This Page
    Domain Time II Domain Time II Documentation Version 5.2 These pages contain the documentation for the current version of Domain Time II (v 5.2). The information is current as of 1 Aug 2021. Note: the online version of this documentation is always current. Please refer to our website for up-to-date information. NOTE: For easier navigation, turn on Bookmarks (View -> Show/Hide -> Navigation Panes -> Bookmarks) Installing Domain Time II System Requirements Planning Recommended Configurations Public Time Servers Regulatory Compliance FINRA CAT NMS PLAN 21 CFR Part 11 EU MiFID II Upgrades 4.x to 5.x Considerations Setup Command-line Options Network Rollout Active Directory Policies DHCP Server Options Auto-Manage Windows Firewall Configuring the Domain Time II Components Domain Time II Server Domain Time II Client for Windows Domain Time II Client for Linux (DTLinux) Domain Time II Manager Domain Time II Monitor Service Domain Time II Update Server Domain Time II Other Managment Tools Domain Time II Audit Server Windows Time Agent Copyright © 1995-2021 Greyware Automation Products, Inc. All Rights Reserved All Trademarks mentioned are the properties of their respective owners. Domain Time II System Requirements Version 5.2 This page explains the recommended versions and basic system requirements for using Domain Time II. Recommended versions This table shows the recommended version for use on the indicated operating systems. Note: Older versions may be available for compatibility on the indicated platforms, however support and documentation are provided only for the current release version (v5.2). Many of the older versions will run on other operating systems than the ones shown here, however, the indicated version provides the best performance for the operating system listed.
    [Show full text]
  • Architektura Procesorů Ultrasparc
    Architektura procesorů UltraSPARC Pokročilé architektury počítačů Prosinec 2009 Pavel Juška, jus011 OBSAH 1. Architektura procesorů SPARC........................................................................................................3 1.1 Charakteristika...........................................................................................................................4 1.2 Historie.......................................................................................................................................4 1.3 Specifikace.................................................................................................................................6 1.4 Operační systémy.......................................................................................................................7 1.5 Superpočítače.............................................................................................................................7 2. Zdroje...............................................................................................................................................8 1. ARCHITEKTURA PROCESORŮ SPARC SPARC (Scalable Processor Architecture) je architektura procesorů založená na RISC instrukční sadě, kterou vyvinula firma Sun Microsystems a byla představena v roce 1986. SPARC je registrovaná ochranná známka společnosti SPARC International, Inc, což je organizace založená v roce 1989 na podporu architektury SPARC, která zároveň provádí testování v rámci dodržování standardů. Implementace původní 32-bitové
    [Show full text]
  • SPARC64 V Microprocessor Provides Foundation for PRIMEPOWER Performance and Reliability Leadership
    SPARC64 V Microprocessor Provides Foundation for PRIMEPOWER Performance and Reliability Leadership September 2002 A D.H. Brown Associates, Inc. White Paper Prepared for Fujitsu This document is copyrighted ã by D.H. Brown Associates, Inc. (DHBA) and is protected by U.S. and international copyright laws and conventions. This document may not be copied, reproduced, stored in a retrieval system, transmitted in any form, posted on a public or private website or bulletin board, or sublicensed to a third party without the written consent of DHBA. No copyright may be obscured or removed from the paper. D.H. Brown Associates, Inc. and DHBA are trademarks of D.H. Brown Associates, Inc. All trademarks and registered marks of products and companies referred to in this paper are protected. This document was developed on the basis of information and sources believed to be reliable. This document is to be used “as is.” DHBA makes no guarantees or representations regarding, and shall have no liability for the accuracy of, data, subject matter, quality, or timeliness of the content. The data contained in this document are subject to change. DHBA accepts no responsibility to inform the reader of changes in the data. In addition, DHBA may change its view of the products, services, and companies described in this document. DHBA accepts no responsibility for decisions made on the basis of information contained herein, nor from the reader’s attempts to duplicate performance results or other outcomes. Nor can the paper be used to predict future values or performance levels. This document may not be used to create an endorsement for products and services discussed in the paper or for other products and services offered by the vendors discussed.
    [Show full text]
  • SPARC64™ VI Extensions
    SPARC64™ VI Extensions Fujitsu Limited Release 1.3, 27 Mar. 2007 Fujitsu Limited 4-1-1 Kamikodanaka Nakahara-ku, Kawasaki, 211-8588 Japan Copyright© 2006 Fujitsu Limited, 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki, 211-8588, Japan. All rights reserved. This product and related documentation are protected by copyright and distributed under licenses restricting their use, copying, distribution, and decompilation. No part of this product or related documentation may be reproduced in any form by any means without prior written authorization of Fujitsu Limited and its licensors, if any. The product(s) described in this book may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS SPARC64™ is a registered trademark of SPARC International, Inc., licensed exclusively to Fujitsu Limited. UNIX is a registered trademark of The Open Group in the United States and other countries. Sun, Sun Microsystems, the Sun logo, Solaris, and all Solaris-related trademarks and logos are registered trademarks of Sun Microsystems, Inc. Fujitsu and the Fujitsu logo are trademarks of Fujitsu Limited. This publication is provided “as is” without warranty of any kind, either express or implied, including, but not limited to, the implied warranties of merchantability, fitness for a particular purpose, or noninfringement. This publication could include technical inaccuracies or typographical errors. changes are periodically added to the information herein; these changes will be incorporated in new editions of the publication. hal computer systems, inc. may make improvements and/or changes in the product(s) and/or the program(s) described in this publication at any time. Contents 1.
    [Show full text]
  • PAP) Computer Microarchitecture Architect Architecture (‘50S-’80S Gates/Register-Transfer Level (RTL) (‘90S - ???) ) Circuits Reliability, Devices Power, … Physics
    Advanced Computer Architectures 01 Introduction Czech Technical University in Prague, Faculty of Electrical Engineering Slides authors: Michal Štepanovský, Pavel Píša Ver.2.00 Abstraction Layers in Modern Systems Application Algorithm Programming Language Parallel computing, Original Our Operating System/Virtual Machine security, … domain focus in of the Instruction Set Architecture (ISA) Domain of ACA recent computer (B4M35PAP) computer Microarchitecture architect architecture (‘50s-’80s Gates/Register-Transfer Level (RTL) (‘90s - ???) ) Circuits Reliability, Devices power, … Physics Reference: John Kubiatowicz: EECS 252 Graduate Computer Architecture, Lecture 1. University of California, Berkeley B4M35PAP Advanced Computer Architectures 2 Instruction Architecture and Their Implementation Software ISA Architecture Hardware Organization of HW • Two different processors can implement exactly the same ISA, but internal structure (micro-architecture) of these processors can vary significantly (different pipelines, etc.) • Organization – view from the top (memory subsystem, buses, control unit,…) • Hardware – view from the bottom (logic circuits, technology, …) B4M35PAP Advanced Computer Architectures 3 What is it? First Transistor First integrated circuit (IC) (Bell Labs) – Dec. 23, 1947 Jack Kilby's original IC (Texas Instruments) - 1958 B4M35PAP Advanced Computer Architectures 4 Technology constantly on the move! • Num of transistors not limiting factor • Currently billions transistors/chip • (Xilinx Versal VP1802 ~ 92⋅109) • Problems:
    [Show full text]