A Low-Power Receiver for Simultaneous Electrocardiogram and Respiratory Rate Detection

A LOW-POWER RECEIVER FOR SIMULTANEOUS ELECTROCARDIOGRAM AND RESPIRATORY RATE DETECTION

JIFU LIANG

Submitted in partial fulﬁllment of the requirements

For the degree of Master of Science

Department of Electrical Engineering and Computer Science

CASE WESTERN RESERVE UNIVERSITY

August, 2016 A Low-Power Receiver for Simultaneous Electrocardiogram and

Respiratory Rate Detection

Case Western Reserve University Case School of Graduate Studies

We hereby approve the thesis1 of

JIFU LIANG

for the degree of

Master of Science

Dr. Soumyajit Mandal

Committee Chair, Adviser July 1st, 2016 Department of Electrical Engineering and Computer Science

Dr. Pedram Mohseni

Committee Member July 1st, 2016 Department of Electrical Engineering and Computer Science

Dr. Dominique Durand

Committee Member July 1st, 2016 Department of Biomedical Engineering

1We certify that written approval has been obtained for any proprietary material contained therein. I would like to dedicate this thesis to my advisor, Dr. Soumyajit Mandal, for his endless guidance of my research. I would also dedicate this thesis to my parents, Yanjun Liang and Jinju Lu, for their support of my study in America. I would also dedicate this thesis to my girlfriend, Shuyue Li, for her encouragement of my study at CWRU. Table of Contents

List of Tables vi

List of Figures vii

Acknowledgements xiii

Abstract xiv

Chapter 1. Introduction1

Motivation1

Research Goals2

Literature Review3

Structure of the Thesis 13

Chapter 2. First Chip Design 14

Impedance Pneumography 14

Block Diagram 16

Clock Generator Block 18

Controlled Injected Current Block and Mixer 20

Preampliﬁer Block 21

Wide-linear Range OTA and Filters 24

Second Gain Stage for Amplifying RR signal 29

Chapter 3. Measurement Result of First Chip 32

Programmable Injected Current Block and Mixer 34

iv ECG Ampliﬁer 35

RR Measurement 40

Chapter 4. Second Chip Design 43

Fully Differential Wide-linear-range OTA 43

Fully Differential Filters 45

Fully Differential Preampliﬁer Block 47

Digital Block 52

Second Gain Stage for Amplifying RR signal 57

Layout 60

Chapter 5. Conclusions 63

Appendix A. PCB for testing the AFE 66

Appendix. Complete References 68

v List of Tables

3.1 Comparison table with the state of the art 34

vi List of Figures

1.1 Conceptual view of a wireless biopotential measurement system

integrated into a chest band. The three patch electrodes are denoted

RA, LA, and REF,respectively.3

1.2 One of the most frequently used topology of bioelectric ampliﬁer1.6

1.3 (a) Typology of MOS pseudo resistor. (b) Basic structure of switched

capacitor.7

1.4 Schematic of ECG ampliﬁer in reference2.8

1.5 Schematic of ECG ampliﬁer presented by Wen et al.3. 10

1.6 Schematic of ECG ampliﬁer presented by Burke and Gleeson4. 11

2.1 Simpliﬁed structure of the respiration circuit when RA and LA

electrodes are used. 15

2.2 Detected respiratory rate signal after ﬁltering with a fourth-order

LPF with cutoff frequency of 2 Hz. A commercial AFE (ADS1298R)

when the volunteer took deep breath. 16

2.3 Simpliﬁed block diagram of the integrated front-end receiver. 17

2.4 Typical spectra of the ECG, modulated RR, and baseband RR signals

before the HPF, before the quadrature modulator, and after the

modulator. 19

2.5 Clock generator circuit used to generate 0◦, 90◦, 180◦, and 270◦ clocks. 19

vii 2.6 Simulation result of the clock generator block. clk1 and clk2 have 90◦

phase shift. 20

2.7 Programmable current mirrors and double balanced mixer used for

generating I AC . The amplitude of I AC can be programmed over a 1:16

range (4 bits) by the switches φ1-φ4. 21

2.8 Schematic of the low-noise ECG ampliﬁer. 22

2.9 Schematic of the OTA used four times in the preampliﬁer. 23

2.10 Simulation results of (a) the AC response of the preampliﬁer. (b) the

output of the preampliﬁer when an input of 2 mV 100 Hz sinusoid

wave is used. (c) the output of the ECG path when an input of 2 mV

100 Hz sinusoid wave is used. 25

2.11 (a) First-order G C LPF topology. (b) First-order G C HPF m − m − topology. 25

2.12 Basic single-stage ﬁve transistor OTA with NMOS input transistors. 26

2.13 The wide-linear-range OTA used several times in the AFE. 27

2.14 Schematic of the BPF and second gain stage used to process each

demodulated RR signal component. The capacitors C1 and C2

are 400 pF off-chip capacitors, while C3 and C4 are 2 pF on-chip

capacitors. 29

2.15 Simulation results of (a) the AC response of the BPF after demodulator.

(b) the I component of RR at the output of mixer if a 1 µV RR signal is

applied at the input of the preampliﬁer. (c) the ﬁnal output of RR path

if a 1 µV RR signal is applied at the input of the preampliﬁer. 31

viii 3.1 Die photograph of the fabricated AFE, which has an active area of

1050 µm 600 µm. Major blocks are labeled. 32 × 3.2 The PCB used to test the ﬁrst chip. 33

3.3 The measured transistor I-V curve used to set the 200 nA off-chip bias

current. This curve was measured by using a Keithley source meter. 34

3.4 Circuit used to test the programmable injected current block and the

mixer. A ﬁxed resistor (100 kΩ) was placed between LA and RA. 35

3.5 (a) Square voltage waveforms across the RA and LA with different

injected currents when a 100 kΩ resistor was used between RA and

LA. (b) Measured positive and negative currents as a function of the

digital code. 36

3.6 (a) Differential frequency response of both the ECG ampliﬁer and the

following LPF. (b) Common-mode frequency response of both the

ECG ampliﬁer and the following LPF without utilizing driven-ground

circuit. 36

3.7 (a) Output noise of the both the ECG ampliﬁer and the following LPF.

(b) Input noise of the both the ECG ampliﬁer and the following LPF. 37

3.8 (a) Output of the ECG path when high-frequency clock is disabled.

The input signal is a 2 mV, 10 Hz sinusoid wave. (b) Output of the ECG

path to the sum of a 1.5 mV, 10 Hz sinusoid (simulating ECG) and a

1.4 mV, 100 Hz square wave (simulating RR carrier). 38

3.9 Detected ECG signal after baseline removal and ﬁltering with a

fourth-order LPF (f 50 Hz). 39 c =

ix 3.10 The DC voltage at the output of the ECG path shifted from 0.3 V to

2.4 V in around 900 seconds. 40

3.11 (a) Body model used to generate ECG-like and RR-like signals. (b)

Simulation result of the modulated RR-like signal when 100 nA 1 kHz

AC currents are fed to LA and RA. (c) The FFT result of the transient

signal generated by the body model. 41

3.12 Input triangle wave used to modulate the impedance between RA and

LA at 0.5 Hz, and measured I and Q RR outputs after ﬁltering with a

fourth-order Butterworth LPf with cutoff frequency of 5 Hz. 42

4.1 (a) Fully differential version of wide-linear-range OTA. (b) Differential-

difference OTA used in CMFB. (c) Fully differential OTA stage. 45

4.2 (a) A single stage of fully differential OTA in the preampliﬁer. (b) Bode

plot of the fully differential OTA stage. 46

4.3 (a) Fully differential LPF.(b) Fully differential HPF. 47

4.4 The AC simulation results of (a) HPF with cutoff frequency of 1 kHz to

remove ECG signal in RR path. (b) LPF with cutoff frequency of 5 Hz

to remove high-frequency RR carrier signal in RR path. 3 nF off-chip

capacitor is used. 47

4.5 Circuit of fully differential preampliﬁer. 49

4.6 Modiﬁed switched capacitor topology. 51

4.7 Equivalent circuits of the modiﬁed switched capacitor topology in

two phases. (a) Equivalent circuit when clk1 is on and clk2 is off. (b)

Equivalent circuit when clk1 is off and clk2 is on. 51

x 4.8 Transient simulation result at the output of the preampliﬁer when

a 2 mV 100 Hz sinusoid wave simulating ECG signal and a 10 kHz

square wave simulating RR carrier signal are used at the input of the

circuit. 52

4.9 Digital blocks in the AFE. 53

4.10 Frequency response of the ﬁrst-order LPF by using switched capacitor. 54

4.11 Programmable counter. 55

4.12 Two-phase non-overlapping clocks generator block. 55

4.13 (a) Programmable bus used to set digital inputs. (b) Timing diagram

of SPI. 56

4.14 Simulation results of the circuits generating clocks used in the mixer

for modulation and demodulation. (a) The 38 kHz input square wave

simulating the off-chip clock. (b) The ﬁrst output clock with one

fourth of the frequency of the input wave. (c) The second output clock

with one fourth of the frequency of the input wave and 90 ◦ phase

shift. 57

4.15 Simulation results of the circuits generating clocks used in the

switched capacitor. (a) The ﬁrst output clock. (b) The second output

clock. (c) 2 ns delay between the two non-overlapping output clocks. 58

4.16 Second gain stage for amplifying RR signal. 58

4.17 Open-loop Bode plot of the op-amp stage. 59

4.18 Closed-loop Bode plot of the op-amp stage. 60

xi 4.19 Transient simulation result at the output of I branch in RR path

(I I ). The frequency of RR signal is chosen as 5 Hz to increase the + − − simulation speed. 60

4.20 Layout of the second chip. 62

A.1 Schematic of the PCB board. 66

A.2 Layout of the PCB board. 67

xii Acknowledgements 0.1 Acknowledgements

I would especially like to thank my mentor, research advisor, Dr. Soumyajit Mandal, for his endless support of my research during my M.S. study. I would never accomplish this project without his guidance. Not only has he taught me much knowledge about IC design, but also he has assisted me to adapt to the study at CWRU.

Thanks to my parents, Yanjun Liang and Jinju Lu, for their continuously support of my study in America. Thank you for providing me an opportunity to study abroad. You will always be my beloved parents.

To my girlfriend, Shuyue Li, who keeps giving me encouragement during my study at CWRU. Although we are studying at different universities, but your support makes me a better student and a better man.

I would also dedicate to my M.S. committee members, Dr. Pedram Mohseni and Dr.

Dominique Durand. Thank you for your advice and help on my thesis.

I am very grateful to Yingying Wang, for your enduring help on my chip design.

Thank you for being patient and answering all my questions.

I would also thank many of the students and staffs at CWRU. Thanks to Dr. Steve

Majerus for your instruction in the lab. Thanks to my partner in this project, Shixiong

Li, who helped me design my ﬁrst chip. Thanks to another partner in this project, Gre- gory Hessler, who helped me to study the method to transmit data by using RFduino board. Thanks to my friend, Ali Nikoofard, who helped me test my ﬁrst chip. Thanks to my friends, Cheng Chen and Xinyao Tang, for all the happy and tough time we spent together.

Last but not least, thanks to all the people who helped me ﬁnish this thesis.

xiii Abstract

A Low-Power Receiver for Simultaneous Electrocardiogram and Respiratory Rate Detection

Abstract

JIFU LIANG

0.2 Abstract

Electrocardiogram (ECG) and respiratory rate (RR) signals are useful for doctors to diagnose heart and respiratory diseases. This work is to design a low-power analog front- end (AFE) for simultaneously detecting both ECG and RR signals. In this projectïijNˇ two chips have been designed on the OnSemi 0.5 µm CMOS process, and the first one has been tested. For the first chip, both simulation and measurement results prove the functionality of it. The circuit draws 6.2 µA from a 3 V power supply. The gain for the ECG and RR signals are 40 dB and 70 dB, respectively. To modify the defects found during the measurement of the first chip, a fully differential AFE with more gain in RR path is designed. The circuit draws 14 µA from a 3 V power supply, and the simulation results verify the functionality. The AFE can be further used in a wearable biopotential system for measuring both ECG and RR signals.

xiv 1

1 Introduction

1.1 Motivation

Heart disease is the leading cause of death in the United States. According to the Amer-

ican Heart Association (AHA), an estimated 85.6 million American adults (more than

one-third of the total population) have one or more types of cardiovascular diseases

(CVDs). Heart disease happens on someone in the United States every 43 seconds,

killing more than 375,000 people a year. Based on the fact that many people are suf-

fering from CVDs, a large amount of money is spent on their healthcare. In 2011, it cost

207.3 billion for direct heart disease, 48.6 billion for hypertension, 33 billion for stroke

and 27.7 for other CVDs5. Consequently, monitoring heart activity has gained consid-

erable attention. It has been known that Electrocardiogram (ECG) shows the heart elec-

trical activity, and it contains much information related to heart rate and rhythm which

can be helpful for doctors to diagnose heart disease. So many different kinds of ECG

monitors have been produced and utilized6.

Respiratory rate (RR) is deﬁned as the number of breaths a person has in one minute.

It is very useful for doctors to diagnose pneumonia and many other respiratory dis-

eases7. High respiratory rate has also been observed on a large proportion of cardiac

arrest patients8,9. Based on the study from Health Grades in 2011, 20% of postoperative Introduction 2

respiratory failures resulted in death10. However, monitoring RR has not gained much attention compared to other vital signs11. RR is also not recorded in many hospitals, even when respiratory condition is the primary problem for patients12,13. One main reason is that there are not enough reliable RR monitoring systems14.

Wearable health-monitoring systems have drawn much interests in recent years15.

From the study of Trans-European Network Home-Care Management Systems (TEN-

HMS), home telemonitoring systems get better feedback from patients. For home telemonitoring patients, it costs 26% fewer days in hospital, leading to a 10% cost savings.

Survival rate is also substantially better for home telemonitoring patients16. Wearable systems not only have those advantages, but also fulﬁll the need for monitoring patients over a long period of time. A distinct example is ECG monitoring. It is desirable that

ECG can be monitored over several weeks or months, and wearable monitoring systems are more suitable compared to the normal ambulatory systems in this case17. But chal-

lenges for wearable monitoring systems exist, and one main problem is the considera-

tion of power consumption.

1.2 Research Goals

In this project, the goal is to design an integrated low-power analog front-end (AFE) for

simultaneously detecting ECG and RR signals. We assume that there are three electrodes

connecting to the body, including right arm (RA), left arm (LA), and reference electrode

(REF). The impedance pneumography (IP) method18,19, which will be described in the

second chapter in detail, is utilized to detect RR signal. Both ECG and RR are measured

between RA and LA chest electrodes. A driven-ground circuit using the REF electrode is

also utilized to boost common-mode rejection ratio (CMRR). Introduction 3

This chip could be ultimately used in a wearable biopotential measurement system, which can continuously wirelessly monitor heart activity and respiratory condition. Fig. 1.1 shows the desired chest band, including all the three electrodes, AFE, ADC, antennas, and batteries. All the raw data is processed by an AFE and then digitized by an ADC. After that, the digitized signals are buffered and then wirelessly transmitted to a Simband or a mobile phone. The Simband can be programmed so that users can have good interface with it, and users can also directly read the data collected from the chest band. Another advantage of using Simband is that it reduces power consumption by allowing the chest band to transmit data to a local unit over short distance (i.e., by cre- ating a so-called body area network20). In this case, it is easy for people to wear this user-friendly monitoring system for long time.

Figure 1.1. Conceptual view of a wireless biopotential measurement system integrated into a chest band. The three patch electrodes are denoted RA, LA, and REF,respectively.

1.3 Literature Review

Wet electrodes, dry electrodes and non-contact electrodes are widely used to collect electro-physiology signals in biopotential systems. The difference between these three electrodes is discussed in this section. Also, monitoring ECG has gained much attention, Introduction 4

and there have been many different kinds of ECG monitors in the market6. Several re- searchers have integrated AFEs with ADCs and digital processors (to extract heart rate, etc.) into complete systems-on-chips (SoCs)2,21,22, but in this section the literature review is limited to analog front-ends since the focus of this thesis is on the AFE. Some of the ECG measuring circuits have the active ground circuit but some don’t. The difference between them is discussed in the following content. In addition, the amplitudes of physiological signals are in the order of tens of µV to tens of mV and the frequency varies from DC to a few kHz23. Typically, the frequency of ECG signal is from 1 Hz to

100 Hz and the amplitude of it varies from 0.5 mV to 4 mV24, while the RR signal has a typical bandwidth of 0.5 Hz. Since the frequencies of the ECG and RR signals are rather low, ﬁlters with very low corner frequency are always needed. It is easy to implement

ﬁlters with low cut-off frequencies by using off-chip capacitors and resistors. But either switched capacitor resistors25 or MOS pseudo resistors1,26 are required for on-chip im- plementations.

1.3.1 Electrodes

Electrodes are an important part of physiology monitoring systems. And the three kinds of most common electrodes are wet electrodes, dry electrodes and non-contact electrodes. Wet electrodes like Ag/AgCl electrodes are widely used in bioelectric applications currently27. The advantages of Ag/AgCl electrodes is obvious that they are simple, disposable and easy to be used28. And the most important advantage of Ag/AgCl electrodes is the low impedance29. But the electrolytic gel has to be applied, which may cause allergic reactions28. And they can not be used for long time because of the dehy- dration30. Also, short circuiting may happen since the gel can smear31. But for the dry electrodes, these problems do not exist since the gel is not applied. However, since there Introduction 5

is no adhesion between the dry electrodes and the body, electrodes may shift when the body moves30. Compared to wet electrodes and dry electrodes, non-contact electrodes do not have an ohmic connection to the skin. No preparation is needed if non-contact electrodes are utilized. The non-contact electrodes are insensitive to skin conditions, so they are very suitable for wearable monitoring systems since they can be embedded within a comfortable layers of fabric32. But the input impedance of the AFE should be high so that it can extract the signal from non-contact electrodes29. And any motion of the non-contact electrodes with respect to the skin may generate artifact.

1.3.2 Ampliﬁers Using Two Electrodes

It is very appealing that bioelectric ampliﬁers only uses two electrodes because only minimal number of contacts are utilized to collect signals. It also saves power since the active-ground circuit is not utilized. However, without driven-ground circuit, the electric potential of the human body can not be controlled. It is necessary to eliminate DC component and very low-frequency signals prior to amplifying biopotentials because of electrode offset voltages, motion artifacts, and so on. Therefore, AC-coupled ampliﬁers are often used to remove DC component and very low-frequency signals. There is one basic topology as shown in Fig. 1.2 which is commonly used in many biomedical ampli-

ﬁers with only two electrodes1. The mid-band gain is set by the ratio of capacitors in the feedback loop. The bandwidth is approximately gm/(AmCL), where gm is the transconductance of the OTA and Am is the mid-band gain. The low-frequency cutoff is set by the effective resistance of the pseudo resistor and the capacitor in parallel with it. How- ever, some circuits use pseudo resistor to work as large resistors1,33–35, while some other circuits use switched capacitor resistors to behave as large resistors36. Introduction 6

C1 V1 Vo V2 CL C1 C2

Figure 1.2. One of the most frequently used topology of bioelectric ampliﬁer1.

For the MOS pseudo resistor in Fig. 1.2, it behaves as a resistor-like device, which has

a monotonic I-V relationship1,26. To simply understand the device, it contains a pair of

diodes in parallel with different polarity. Therefore, the current increases exponentially with voltage across them. With negative VGS, the device acts like a diode-connected

PMOS device. With positive VGS, the device acts like a diode-connected bipolar device.

High resistance exists when the voltage across the device is small, so two pseudo resis-

tors are commonly used in series as shown in Fig. 1.2 so that the distortion for large

signals can be reduced.

The switched capacitor is a discrete-time system that can also be used to replace the

large resistor. The basic structure of switched capacitor resistor is shown in Fig. 1.3(b). Introduction 7

ϕ1 and ϕ2 are nonoverlapping two-phase clocks with the period of T . The average current i1 is T T 1 Z 1 Z 2 i1 i1(t)dt i1(t)dt (1.1) = T 0 = T 0 dq1(t) i1(t) (1.2) = dt From the equation (1.1) and (1.2), we can get

Z T T 1 2 dq1(t) C VC ( 2 ) C VC (0) C V1 C V2 i1 dt · − · · − · (1.3) = T 0 dt = T ≈ T

From the continuous time perspective, we also know

V1 V2 i1 − (1.4) = R where R is the effective resistance of the circuit. By comparing the equation (1.3) and

(1.4), we can get the following conclusion that

T R (1.5) = C

The structure of switched capacitor can be modiﬁed and different equivalent resistance can be obtained, which may be different from the equation (1.5). But all of them share the same idea that a charge q is transferred from the input to the output in each clock cycle.

i1 ɸ1 ɸ2

P+ P+ N+ + + + V V N-well 1 Vc C 2 P-sub

Figure 1.3. (a) Typology of MOS pseudo resistor. (b) Basic structure of switched capacitor. Introduction 8

Liang et al. present a system of portable ECG monitoring system based on Bluetooth connectivity to a mobile phone2. In his system, ECG signal is collected by the dry skin electrodes, and then amplified, filtered, and analog-digital converted. After that, the digital data is sent to a mobile phone through Bluetooth. In his core monitoring circuit, a preamplifier and a band-pass filter are designed in his AFE. A commercial microcontroller with a built-in ADC is also included. The schematic of preamplifier is shown in

Fig. 1.4.

Vt R2=1MΩ

C1=20pf C2=0.1pf R1=100kΩ C3=12pf Vip Vo Vin

C1=20pf C2=0.1pf R1=100kΩ

Ω Ω

R C Vt Vcm

Figure 1.4. Schematic of ECG ampliﬁer in reference2.

In this preampliﬁer, two stages of ampliﬁcation are utilized. The gain of each stage is set by the ratio of two capacitors or two resistors in negative feedback. Besides, the

PMOS transistors in the feedback loop work as pseudo resistors. The pseudo resistor and the capacitor in parallel with it form the high-pass pole. The PMOS transistors are biased in subthreshold region, and the equivalent resistance is set by Vt . As the author

9 14 states, the equivalent resistance changes from 10 Ω to 10 Ω if Vt changes from 0.8 V to

1.6 V,resulting the pole changing from around 10 mHz to several hundred Hz. Measured Introduction 9

result shows that the passband is from around 0.01 Hz to 100 Hz, and the input referred noise is around 2.3 µVr ms. But in this preampliﬁer, there is a disadvantage that several resistors are used in the ampliﬁer which produce noise. The thermal noise in a resistor is described by the following equation.

v2 4kT R∆f (1.6) n = where k is Boltzmann’s constant in joules per Kelvin, T is the temperature in Kelvin, and

R is the resistor value in Ohms.

For the ampliﬁers without driven-ground circuit, there are several advantages. For example, the circuit takes less area and it may have less power consumption. But the disadvantage is obvious that the AC common-mode voltage can not be reduced. Al- though AC coupled ampliﬁer can be used to remove the DC component of the common mode signal, the power-line interference still needs to be removed. However, for wearable monitoring systems, the AC interference is a smaller problem since the short leads are utilized.

1.3.3 Ampliﬁers Using Reference Electrodes

Now the ampliﬁers with driven-ground circuit is discussed. The goal of the driven- ground circuit is to reduce the common-mode signal by using negative feedback37. Three electrodes are widely used in the ampliﬁers with active ground circuit, including two electrodes measuring electric signals and one electrode working as reference electrode.

The reduction of the common-mode voltage is related to the gain of the driven-ground circuit. Thus, a relatively high gain is desired in the driven-ground circuit. However, a high gain feedback loop may lead instability. Also in the driven-ground circuit, buffers may be needed to drive the body impedance. Introduction 10

Wen et al. provide another full custom AFE for long-time ECG monitoring3. The circuit contains the instrumentation amplifier, filters, second amplifying stage, driven- ground circuit, power management circuit, and leadoff monitoring circuit. The schematic of the ECG amplifier is shown in Fig. 1.5. The bandwidth varies from 0.5 Hz to 100 Hz with mid-band gain of 51 dB. The CMRR is 75 dB and input referred noise is 12 µV.

LA Buffer

R1 R2 R3 Cr R0 Rr R4 RL Buffer Vcm Out RL R0

R1 R2

R3 RA Buffer

Figure 1.5. Schematic of ECG ampliﬁer presented by Wen et al.3.

In this preampliﬁer, the inputs of two buffers are connected to both RA and LA elec-

trodes. By doing this, it can increase the equivalent input impedance of the ampliﬁer.

For each stage of the instrumentation ampliﬁer, the gain is set by the ratio of resistors

in the feedback loop. Also, the driven-leg circuit is utilized to increase the CMRR. The

common mode voltage Vcm is sensed by the two resistors R0. Sensed Vcm is buffered, inverted, ampliﬁed, and then fed back to the body. By increasing the gain of the ampliﬁer in the drive-leg circuit, we can increase the CMRR.

Another ECG ampliﬁer design incorporating driven-ground circuit is presented by

Burke and Gleeson4. Since this ampliﬁer is constructed on a matrix board, there are no Introduction 11

constraints of resistors and capacitors with large values. The ampliﬁer draws 9 µA from a 3.3 V power supply. The bandwidth of the ampliﬁer is from 0.05 Hz to 1.9 kHz with the gain of 43 dB. The CMRR is 55 dB without active ground circuit, and it increases to 88 dB if driven-ground circuit is used.

VCC

C1 R6 V1 R1 R10 R11 R7 R2 R4 R8 C2 R9 C4 R5 R3 Vo R5 C2 C3 C4 R2 R4 R7 R8 R1 R10 R11 V2 C1 R6 C6

R14 C5 VCC Vref R15 C7 R13 R12

Figure 1.6. Schematic of ECG ampliﬁer presented by Burke and Gleeson4.

The amplifier has three stages. The first stage is AC coupled by using C1, causing attenuation of DC offset and low-frequency input signals. R1 provides patient protection by limiting the current coming from the electrodes, and R6 with R3 set up the DC bias voltage for the op-amps. R2 defines the input impedance of the amplifier to meet CMRR requirements in the presence of inevitable electrode impedance mismatch. The second stage is also a differential stage with DC coupled at the input. R9 and C3 set the DC

gain to unity. Since the input capacitance of the op-amp generates a zero, C2 is used Introduction 12

here to define the zero more reliably. The third stage is a simple DC coupled stage with resistors in the negative feedback. Besides all the three stages, the reference circuit is used to increase the CMRR. R7 detects the common-mode voltage. Then, it is inverted, amplified, and sent to the reference electrode. More information of this amplifier can be found in reference4.

By using driven-ground circuit, the common-mode voltage including the DC value and the powerline interference can be greatly reduced. This explains why in this project the driven-leg circuit is used in AFE.

1.3.4 Summary of Bioelectric Ampliﬁers

From the overview of the research field, to design a good preamplifier, several conditions should be satisfied.

The ﬁrst one is noise. A high-quality ampliﬁer should have very low equivalent input noise since the amplitude of ECG signal and other bioelectric signals are rather small.

For example, the amplitude of ECG signal varies from 0.5 mV to 4 mV24. To reduce the

noise, several methods like increasing the bias current for the ampliﬁer can be utilized.

The second constraint is common-mode rejection ratio (CMRR). The CMRR should

be good enough to decrease the power-line interference so that the power-line inter-

ference is not able to have effect on the measurement of ECG signal. For a body-worn

device, 20 dB CMRR is needed since there is not a big common-mode voltage38. But for

a device not entirely worn on the body, at least 80 dB CMRR is needed.

The third constraint is low high-pass ﬁlter corner frequency to allow low-frequency

signal components (as low as 0.1 Hz for ECG) to be ampliﬁed. It is easy to implement

off-chip large capacitors or resistors to get a low cutoff frequency. However, switched Introduction 13

capacitor or MOS pseudo resistor can also be integrated in the chip if the designer wants to reduce the size of the monitoring system.

The fourth condition is power consumption. Power consumption should be as low as possible so that monitoring systems can work for a longer period of time without changing batteries. This is also good when a bioelectric signal needs to be monitored for long periods of time to detect transient and infrequent symptoms (such as missing or irregular heartbeats) that can be used by doctors for diagnosis. Another advantage of systems with low power consumption is that the weight of the devices is light since smaller batteries can be used for a given operating lifetime.

1.4 Structure of the Thesis

In this project, two AFE chips have been designed. This thesis is divided into the following parts. In Chapter 2, the design of the ﬁrst chip is introduced in detail. In Chapter

3, the measurement result of the ﬁrst chip is presented. In Chapter 4, the design of the second chip is introduced in detail. And Chapter 5 contains the conclusion. 14

2 First Chip Design

In this chapter, the ﬁrst AFE chip design is presented in detail. ECG signal is collected directly by two conventional contact electrodes RA and LA. To detect RR, impedance pneumography (IP) method, which will be described later, is used so that the low-frequency

RR signal is modulated on a high-frequency carrier signal. The low-noise preamplifier in the AFE amplifies both the ECG and modulated RR signals. After the preamplifier,

LPFs are used to remove modulated RR signal in ECG path. In RR path, HPFs are used to remove ECG. Then, the mixer is utilized to extract the RR signal, and the following BPF is used to remove high-frequency carrier and low-frequency noise. Since the amplitude of RR is small, there is another gain stage for further ampliﬁcation of the RR signal.

2.1 Impedance Pneumography

Impedance pneumography method is widely used to measure respiratory rate. Fig. 2.1 shows the simpliﬁed structure of the respiration circuit when RA and LA electrodes are used. During respiration, the thorax can be treated as two impedance components: a constant baseline impedance (Z 2Z ) and a varying impedance (∆Z )18,19,39. bod y + electr ode

For the relatively constant term, the value of Zbod y is around 500 Ω based on the study

18 from Grenvik et al , and Zelectr ode is related to the kind of electrodes used (around First Chip Design 15

2 kΩ impedance for a standard patch electrode). For the varying term caused by respiration, there are two reasons causing the change of the electrical resistance. Firstly, the chest expands (contracts) during respiration, causing the length of the conductance paths increasing (decreasing), which increases (decreases) the impedance of the thorax.

Secondly, the gas volume of the chest increases (decreases), causing the conductivity decreasing (increasing) because the conductivity of gas is not as good as the one of tissue, which increases (decreases) the impedance of the thorax. Taken together, ∆Z increases when the chest expands and ∆Z decreases while the chest contracts. Typically,

∆Z varies from 0.1 Ω to 1 Ω19.

IAC

ZElectrode ZElectrode

Zbody ΔZ Body

Figure 2.1. Simpliﬁed structure of the respiration circuit when RA and LA electrodes are used.

If a high-frequency AC current is injected into a body through the two electrodes, a varying voltage is then generated across the electrodes. The AC current behaves as the carrier signal, and it is amplitude-modulated by the low-frequency respiratory signal. In the following circuit, the low-frequency RR signal is extracted and the carrier signal is ﬁltered. Fig. 2.2 shows the detected respiratory rate signal after ﬁltering with a fourth-order LPF with cutoff frequency of 2 Hz. A commercial AFE (ADS1298R) designed by Texas Instruments, which utilizes impedance pneumography method to measure RR First Chip Design 16

signal, is used here when the volunteer took deep breath. From Fig. 2.2, it can be estimated that the frequency of detected RR signal is around 0.25 Hz. In addition, since the gain of this AFE is set to 6 and the injected current is around 30 µA, the estimated varying impedance ∆Z in thorax is around 1.2 Ω. In this design, the impedance pneumography method mentioned above is used to detect RR signal. Another method to measure RR signal is to extract it directly from ECG signal40. Studies have shown that

ECG signal is modulated because of the respiration. So ECG-derived respiratory activity measurement is a method to derive RR signal from modulated ECG by using some signal processing algorithms.

0.6 0.5 0.4 0.3 0.2 Voltage (mV) 0.1 0 4 6 8 10 12 14 16 18 20 Time (s)

Figure 2.2. Detected respiratory rate signal after ﬁltering with a fourth- order LPF with cutoff frequency of 2 Hz. A commercial AFE (ADS1298R) designed by Texas Instruments is used here to measure RR signal when the volunteer took deep breath.

2.2 Block Diagram

A simpliﬁed block diagram of the integrated AFE is shown in Fig. 2.3. The amplitude of ECG signal varies from 0.5 mV to 4 mV24. For RR, ∆Z typically varies from 0.1 Ω

to 1 Ω19. The AHA recommends that the safe limit current is 10 µA41. In this project,

the maximum injected current is 1.6 µA, which causes the maximum amplitude of RR First Chip Design 17

signal to be 1.6 µA x 1 Ω = 1.6 µV.Since the quantization step size, i.e., least signiﬁcant bit

(LSB), of a moderate-resolution (8-10bits) low-power analog-to-digital converter (ADC) is typically 0.5 - 5 mV,the AFE should provide at least 20 dB gain for ECG signal and 70 dB gain for RR signal to ensure that output SNR is not affected by the ADC’s quantization noise.

Q-Path Chip

Off-chip 10kHz RR Q-branch Clk 20kHz Clk VCC I-Path RR I-branch

Modulation Pre-amp Left Arm (LA) Right Arm (RA) ECG signal

VCM Left Leg (LL) VREF

Figure 2.3. Simpliﬁed block diagram of the integrated front-end receiver.

To collect ECG signal, two electrodes (LA and RA) are used to make a differential voltage measurement. To collect RR signal, a high-frequency AC current of known amplitude is injected into the tissue through the two electrodes as mentioned before. The

AC current is the carrier signal which is amplitude-modulated by the RR signal, and the differential voltage is generated across two electrodes since ∆Z changes during respira-

tion. The modulation frequency of the AC current is set to 10 kHz which is much larger

than the frequency of the ECG signal so that there is little interference between ECG and

modulated RR signals. First Chip Design 18

After collecting both of the signals, a low-noise preampliﬁer is used to amplify both

ECG and RR signals. In the ampliﬁer, the active ground circuit is utilized to increase

CMRR, and the third electrode (LL) is used as reference electrode here.

After the preamplifier, in order to get ECG signal, LPFs are needed to remove the modulated RR signal. To get RR signal, HPFs are utilized first so that the ECG signal is at- tenuated. A quadrature demodulator is then employed, and both the real and imaginary components of RR signal are extracted. At the output of the demodulator, band-pass filters (BPFs) are used to remove the high-frequency carrier signal and the RR signal is selected. The resulting spectra is shown in Fig. 2.4. Since the amplitude of RR signal is small and the gain of the preamplifier is not enough, to ensure that the signal can be digitized without adding significant quantization noise, there is another gain stage for further amplification of the RR signal.

2.3 Clock Generator Block

In this design, since the RR signal needs to be modulated and demodulated, four clocks are needed to be fed into the mixers, including 0◦, 90◦, 180◦, and 270◦ clocks. An easy

method to generate these four clocks is shown in Fig. 2.5 if an off-chip clock is utilized.

D-ﬂip-ﬂop is used to divide the frequency of the input signal by two, and an inverter fol-

lowed by the D-ﬂip-ﬂop is able to generate a clock with 90◦ phase shift. The simulation

result of the clock generator block is shown in Fig. 2.6. It’s shown that clk1 and clk2 have

90◦ phase shift, and the frequency of them is half of the frequency of off-chip clock.

Clocks are only needed when user wants to monitor RR signal. The NAND gate can

disable the clocks when user only wants to monitor ECG signal so that clock feedthrough

has no inﬂuence on the measurement of the ECG signal. First Chip Design 19

-700 Hz Signal +700 Hz LO ECG

LOerror

f -fModulated-RR 0 fModulated-RR -10 kHz Signal 10 kHz LO

LOerror ECG f -fModulated-RR 0 fModulated-RR -10 kHz Signal 10 kHz -0.1 Hz 0.1 Hz -0.65 Hz 0.65 Hz

f -fModulated-RR -f f fModulated-RR -10 kHz RR RR 10 kHz -20 kHz -0.5 Hz 0.5 Hz 20 kHz

Figure 2.4. Typical spectra of the ECG, modulated RR, and baseband RR signals before the HPF, before the quadrature modulator, and after the modulator.

DS SET Q 1x 3x 9x 9x clk1_ba

clk clk_in R CLR Q clk1 NAND enable DS SET Q 1x 3x 9x 9x clk2_ba 1x clk R CLR Q clk2

Figure 2.5. Clock generator circuit used to generate 0◦, 90◦, 180◦, and 270◦ clocks. First Chip Design 20

3 offchip clock 2 1

Voltage (V) 0 0 0.2 0.4 0.6 0.8 1 Time (ms) 3 clk1 2 1

Voltage (V) 0 0 0.2 0.4 0.6 0.8 1 Time (ms) 3 clk2 2 1

0Voltage (V) 0 0.2 0.4 0.6 0.8 1 Time (ms)

Figure 2.6. Simulation result of the clock generator block. clk1 and clk2 have 90◦ phase shift.

2.4 Controlled Injected Current Block and Mixer

Since the varying impedance term of thorax ∆Z is hard to predict, the amplitude of AC

current should be able to be controlled. The preampliﬁer has a limited linear range of

around 7.5 mV and a ﬁxed amount of input-referred noise of 8.1 µVr ms over a bandwidth of 300 Hz. Therefore, the SNR will be poor if the modulated RR is small, while the

circuit will saturate and generate inter-modulation distortion between the ECG and RR

signals if the modulated RR signal is too large. To control the injected current in this

design, two programmable binary-weighted 4-bit current mirrors are used to generate

controllable injected current. As Fig. 2.7 shows, the minimum injected current is 100 nA.

If all the switches are closed, the maximum injected current should be 1.6 µA, which is

still smaller than the AHA-recommended safe limit current of 10 µA. Because of the four switches, the injected current is able to vary from 100 nA to 1.6 µA in steps of 100 nA. In this case, the user is able to change the injected current if ∆Z changes. First Chip Design 21

VCC I I 2I 4I 8I

100 Clk nA ɸ1 ɸ2 ɸ3 ɸ4 RA Ipmos-out

Clk 100 Inmos-out

nA ɸ1 ɸ2 ɸ3 ɸ4 LA

I I 2I 4I 8I Clk

Figure 2.7. Programmable current mirrors and double balanced mixer used for generating I AC . The amplitude of I AC can be programmed over a 1:16 range (4 bits) by the switches φ1-φ4.

Besides the programmable current mirrors, a passive double-balanced mixer is used here. The output of the two current mirrors are connected to the RF port of the mixer, and the high frequency clock signal which is set to 10 kHz here is fed to the LO port.

The outputs of the mixer are connected to the RA and LA electrodes. Thus, the AC current is injected into the body through the electrodes and the AC current is amplitude- modulated by the low-frequency RR signal.

2.5 Preampliﬁer Block

The main preamplifier as shown in Fig 2.8 is a modified version of the circuit described in42,43. This low-noise amplifier is utilized to amplify both the ECG and RR signals.

Three electrodes are included in the ampliﬁer. RA electrode and LA electrode are connected to the inputs of the ampliﬁer (Vin and Vin ), and the reference electrode is con- + − nected to the output of the common-mode feedback circuit (Vcm f b).

The amplifier is a two-stage instrumentation amplifier. For each stage in the amplifier, a single-stage operational transconductance amplifier (OTA) is used, which is First Chip Design 22

A Vin+ Vref A

A sense Vout VCM A

Vin- V DD A

A = Vref Vcmfb

Figure 2.8. Schematic of the low-noise ECG amplifier. biased in sub-threshold mode to reduce power consumption. The schematic of the OTA is shown in Fig 2.9. In the OTA, the input differential signals are fed to PMOS devices since the flicker noise in this process is significantly lower (about 5x) for PMOS devices.

Also, by increasing W/L, the transistors are driven into sub-threshold mode.

For the instrumentation amplifier, the mid-band gain of each stage is set to 10 by choosing the ratio of capacitors in the feedback loop. Therefore, the total gain of the amplifier is 100 (40 dB). Compared to some standard instrumentation amplifiers, capacitors instead of resistors are utilized in the feedback loop to set up the gain. That is because resistors contribute noise and the matching property of resistors is poor. How- ever, using capacitors can not provide the DC voltage levels for the OTA. To overcome this problem, the MOS pseudo resistors described earlier are used so that DC current is able to flow. These pseudo resistors act as very large resistors for small signals, shown as the "A" block in Fig 2.8. To reduce the distortion of large signals, two pseudo resistors First Chip Design 23

are placed in series. Thus, the DC gain is set to 1 by using these pseudo resistors, while the AC gain is set by the capacitors in parallel with the pseudo resistors.

VCC VB

V+ V- OUT

Figure 2.9. Schematic of the OTA used four times in the preampliﬁer.

Besides, a common-mode feedback path is included in the ampliﬁer to remove common- mode signal, such as the powerline interference. The reference electrode, usually placed on the leg, is connected to the output of the driven-ground circuit denoted as Vcm f b in

Fig. 2.8. The common-mode voltage is sensed in the first stage of the instrumentation amplifier. And the OTA in the common-mode feedback amplifies the difference between the sensed common-mode voltage and the reference voltage which is set to 0.75 V in this design. Since the output impedance of the feedback is in series with the impedance of the reference electrode, it is necessary to reduce the output impedance of the circuit so that the electrode with an impedance of around 2 kΩ can be driven. Therefore, a super- buffer circuit is utilized to lower the output impedance. First Chip Design 24

1 For the standard source follower, the output impedance is Ro . However, gm g = + mb for this super-buffer circuit, the negative feedback through the additional PMOS re-

duces the impedance by a factor of about gm2ro1, resulting the output impedance of

1 1 Ro . Therefore, a typical electrode with an impedance of around 2 kΩ gm g gm2ro1 = + mb can be driven effectively. Another thing that needs to be mentioned is that the open

circuit voltage gains of both standard buffer and super buffer do not have much differ-

ence. The gain of the standard source follower is vo gm ro , while the gain of the v 1 (gm g )ro i = + + mb vo gm1ro1 super-buffer circuit is 1 . Thus, if gm2ro2 1, both voltage gains vi 1 (gm1 gmb1)ro1 = + + + gm2ro2 À are approximately equal to 1, and the super source follower has little effect on the open circuit voltage gain. The detail description of the super source follower is in44.

Fig. 2.10 shows the simulation result of the ECG path. The mid-band gain is around

40 dB as shown in Fig. 2.10(a). If a 2 mV 100 Hz sinusoid wave and a 10 kHz carrier signal are applied, both of them get ampliﬁed as shown in Fig. 2.10(b). Fig. 2.10(c) shows the output of the ECG path, and it is clear to see that the high-frequency carrier is reduced by the LPFs. From Fig. 2.10(c), it can be estimated that the gain in ECG path is around

40 dB, which is in the agreement with the design value.

2.6 Wide-linear Range OTA and Filters

This AFE is designed to monitor ECG and RR simultaneously. Therefore, LPFs are needed to remove high-frequency modulated RR signal in ECG path, and both HPFs and LPFs are needed to remove ECG as well as high-frequency carrier in RR path. First-order

G C LPF and HPF topologies, as shown in Fig. 2.11(a) and (b), are used several times m − First Chip Design 25

0 Gain (dB) -20

-40 10-2 100 102 104 106 Frequency (Hz)

0.8 0.8

0.6 0.6 Voltage (V)

Voltage (V) 0.4 0.4

ECG Amp output ECG output 0.2 0.2 024681012 024681012 Time (ms) Time (ms)

Figure 2.10. Simulation results of (a) the AC response of the preamplifier. (b) the output of the preamplifier when an input of 2 mV 100 Hz sinusoid wave is used. (c) the output of the ECG path when an input of 2 mV 100 Hz sinusoid wave is used. in the AFE. The cutoff frequency of the filter shown in Fig. 2.11 is

1 Gm fcuto f f (2.1) = 2πRC = 2πC

Vin Vout C

Vin Gm Vout m C G

Vref

Figure 2.11. (a) First-order G C LPF topology. (b) First-order G C m − m − HPF topology. First Chip Design 26

VCC

i+ i+ Out iout V+ V- Vs i- VB iB

Figure 2.12. Basic single-stage ﬁve transistor OTA with NMOS input transistors.

For the OTA in the filters, considering the basic five-transistor OTA in Fig. 2.12 first.

Assuming the input pair of transistors operates in the sub-threshold region, we have

κs v vs +− i I0e ϕt (2.2) + =

κs v vs −− i I0e ϕt (2.3) − =

i i iB (2.4) + + − =

i i iout (2.5) + − − = 1 κs (2.6) = 1 γ 2pϕ0 VSB + + p 2εsi qNA γ (2.7) = Cox where ϕ kT is the thermal voltage which has a typical value of 26 mV at the tempera- t = q ture of 300K; ε is the dielectric constant of Silicon; and NA is the dopant atom density.

From equation (2.2)-(2.5), we can get the conclusion that

µ ¶ κs(v v ) iout iB tanh + − − (2.8) = 2ϕt First Chip Design 27

and we deﬁne the linear range as the slope of iout at the origin, i.e., when v v 0: + − − =

2ϕt VL (2.9) = κs

If ks=0.7 and ϕt =26 mV, then the linear range of the basic ﬁve-transistor OTA VL is

around 75 mV, which is not sufficient to filter the amplified ECG signal (typical ampli-

tude = 100-200 mV). To overcome this, the OTA used in the AFE is a modiﬁed version

of the wide-linear-range OTA (WLR OTA) presented in45, as shown in Fig. 2.13. In this

design, source degeneration and bump linearization techniques are used to increase the

linear range, similar to the circuit in45. However, the circuit here uses gate terminals as inputs instead of well terminals so that the layout is simpliﬁed. In this case, the cost is the reduced linear range, but it is still sufﬁcient for this application.

VCC VCC

M3 M4 VCC VB

Iout M5 M6 M9 M10 V- V+ M11 M7 M8 M1 M2 M12

Figure 2.13. The wide-linear-range OTA used several times in the AFE.

The source degeneration method is a common technique to increase the linear range.

It was ﬁrst used in vacuum-tube design46, and it was then used in bipolar design as emitter degeneration47. By using source degeneration, the current ﬂowing a transistor First Chip Design 28

is converted to a voltage through a resistor, and that voltage is then fed back to the source of the transistor. In this case, the current is decreased. The linear range increases by a factor of approximately 2 by using source degeneration method.

The bump linearization is a technique to linearize a hyperbolic tangent function48.

In a bump differential pair, there is a central arm including two transistors in series. The current ﬂowing through these two bump transistors is a bump-shaped function of the differential voltage. The current in the outer arm (I) is the usual hyperbolic tangent function of the differential voltages (V). However, the bump transistors steal current near the origin of the I-V curve. If ω is the ratio of the W/L of the bump transistors and the W/L of the transistors in the outer arm, we can get the following equation

sinhx iout (2.10) = β coshx + where ω β 1 (2.11) = + 2 κ(v v ) x + − − (2.12) = ϕt The optimal value of β is 2, in the following sense. If we Taylor expand the equation

(2.10) at β=2, it can be found that no cubic distortion term exists.

sinhx x x5 x7 (2.13) 2 coshx = 3 − 540 + 4536 + · · · + As a comparison, the cubic distortion exists when β=0.

x x x3 x5 tanh (2.14) 2 = 2 − 24 + 240 + · · ·

The bump linearization increases the linear range by a factor of around 1.5, and it does not contribute noise. Therefore, by using both the source degeneration and bump linearization techniques, the linear range is increased by a factor of 2 1.5 3, setting × = First Chip Design 29

the VL to around 270 mV, which is enough to ﬁlter out the ampliﬁed ECG and RR signals.

In the ECG path, two ﬁrst-order G C LPFs with cutoff frequency of 1 kHz are used to m − reduce the high-frequency modulated RR signal in ECG path. In RR path, four ﬁrst-order

HPFs with cutoff frequency of 700 Hz are ﬁrst used to reduce the ECG signal before the

demodulator.

2.7 Second Gain Stage for Amplifying RR signal

After the demodulator, both the I and Q components of RR signal are extracted. But

the amplitude of the RR signal is still small, as analyzed below. Considering the varying

impedance term of the thorax ∆Z is 1 Ω19 and the injected AC current is the maximum

current of 1.6 µA. The preampliﬁer can provide 40 dB gain, however there is 4 dB conver-

sion loss because of the mixer. Thus, after the demodulator, the amplitude of RR signal

is around 100 µV, which is hard to directly be digitized with a moderate-resolution ADC,

or displayed on an oscilloscope or other monitoring devices. To overcome this problem,

another gain stage is used and the circuit is shown in Fig. 2.14.

I+ RR C1 C3 Gm1

1 I-branch Ibias

Vref 2

I- 2 Gm

C2 C4 Ibias Vref LPF (0.65 Hz) HPF (0.1 Hz) Second gain stage

Figure 2.14. Schematic of the BPF and second gain stage used to process each demodulated RR signal component. The capacitors C1 and C2 are 400 pF off-chip capacitors, while C3 and C4 are 2 pF on-chip capacitors. First Chip Design 30

The signals coming from the output of the demodulator, including both the I (Q ) + + and I (Q ) components, are passed through pseudo-differential BPFs. The upper side- − − band, the high-frequency carrier, DC offset, and low-frequency noise are removed. In

the BPF, two ﬁrst order G C LPFs, in which the WLR OTA described earlier is used, m − are utilized in each path of I (Q ) and I (Q ). The -3 dB frequency of the LPFs is set + + − − to 0.65 Hz, which contains the fundamental frequency of RR signal (a typical bandwidth of 0.5 Hz). Also, since the corner frequency of the LPF is relatively low, 400 pF off-chip capacitors are used here while the bias current of OTAs is kept at a reasonable value

(1 nA). The HPF is a simple CR circuit, in which adaptive element is used to behave as a big resistor. The -3 dB frequency of the HPF is set to 0.1 Hz. Also, by using this HPF, the DC voltage of the input of the OTA can be set to the reference voltage. However, the disadvantage of using a pseudo resistor in the ﬁlter is that its effective resistance is process-dependent because of threshold voltage variations, which makes the cutoff frequency also process-dependent.

The circuit following the BPF is the second gain stage for amplifying the RR signal.

The OTAs used here are still the WLR OTA described earlier. This stage also performs the differential to single-ended conversion. The relationship between the output signal and the input signal is described by the following equation.

Vout Gm1 I bi as1 (2.15) (V V ) = G = I in1 − in2 m2 bi as2 From the equation (2.15), it is easy to set the gain of this stage by choosing the ratio of two bias currents. Here a current ratio of 50 (34 dB) is set. By doing this, the total gain for RR signal is around 40 4 34 70 dB. And the -4 dB term comes from the loss of the − + = mixer. First Chip Design 31

Fig. 2.15 shows the simulation results of RR path. The AC response of the second

RR gain stage is presented in Fig. 2.15(a). If a 1 µV RR signal is applied at the input of the preampliﬁer, the output signals of the demodulator in I branch are presented in

Fig. 2.15(b). The ﬁnal outputs of RR path, including both the I and Q components, are presented in Fig. 2.15(c). From Fig. 2.15(c), it can be estimated that the gain in RR path is around 72 dB, which is in good agreement with the theoretical design value.

-10

-20 Voltage (dB)

-30 LPF (0.65 Hz) HPF (0.1 Hz) -40 10-3 10-2 10-1 100 101 102 Freq (Hz) 3

0.85 I+ 2 I- 1 0.8 0

0.75 -1 Voltage (V) Voltage (mV) -2 I branch output 0.7 Q branch output -3 0 0.2 0.4 0.6 0.8 1 0 0.5 1 1.5 2 Time (ms) Time (sec)

Figure 2.15. Simulation results of (a) the AC response of the BPF after demodulator. (b) the I component of RR at the output of mixer if a 1 µV RR signal is applied at the input of the preamplifier. (c) the final output of RR path if a 1 µV RR signal is applied at the input of the preamplifier. 32

3 Measurement Result of First Chip

In this chapter, the measurement of the ﬁrst chip is discussed. The chip was fabricated in the OnSemi 0.5 µm CMOS process through the MOSIS Educational Program

(MEP). The die photograph of the AFE is shown in Fig. 3.1, which includes the active area of 1050 µm 600 µm. ×

AFE Current mirror RR HPF Amp

LPF part ECG CLKdivider

Q-path RR Amp and LPF I-path RR Amp and LPF

Figure 3.1. Die photograph of the fabricated AFE, which has an active area of 1050 µm 600 µm. Major blocks are labeled. ×

To test the chip, a printed circuit board (PCB) was designed to set up the measurement environment. All off-chip capacitors for the ﬁlters were soldered on the board. Sig- nal generators were used to provide a sinusoid wave (simulating ECG) and a square wave

(simulating high-frequency RR carrier). These signals were fed into the chip through the Measurement Result of First Chip 33

Figure 3.2. The PCB used to test the ﬁrst chip.

BNC connectors on the PCB. For off-chip bias currents, Keithley source meters were used to source the desired current and measure the corresponding voltages. Then, po- tentiometers were used to provide the voltages corresponding to the desired currents. In this case, it is then only necessary to provide voltages instead of off-chip bias currents.

Speciﬁcally, by using source meters, the current could be swept so that an I-V curve of the on-chip bias transistor could be obtained. It was easy to ﬁnd the corresponding voltages of the desired off-chip bias current by using the measured I-V curve. The I-V curve used to set a 200 nA off-chip bias current is shown in Fig. 3.3. More information about the schematic and the layout of the PCB board can be found in the appendix.

The AFE drew 6.2 µA from a single 3 V power supply. Table 3.1 compares our receiver with other reported ECG AFEs. It can be concluded that our AFE has lower power consumption, and our AFE can monitor both ECG and RR signals while others can only monitor ECG. For the future use of this AFE, it is easy to power this AFE by using two

1.5 V alkaline batteries or one 3 V lithium battery. Measurement Result of First Chip 34

1.6

1.4

1.2 Voltage (V) 1 I-V curve used to set 200 nA bias current 0.8 0 0.2 0.4 0.6 0.8 1.0 Current (uA)

Figure 3.3. The measured transistor I-V curve used to set the 200 nA off- chip bias current. This curve was measured by using a Keithley source meter.

Table 3.1. Comparison table with the state of the art

Parameters This work 20133 201249 20112 CMOS CMOS CMOS CMOS Technology 0.5 µm 0.18 µm 0.35 µm 0.35 µm Power Supply 3V 2.9-5.5V 2.0-3.5V 3.3V Current 6.2µA 190µA 170µA 725µA Gain (ECG) 40 dB 51 dB 40 dB 66.5 dB Note: This work monitors both ECG and RR signals, while the circuits in other reference only measure ECG.

3.1 Programmable Injected Current Block and Mixer

The first part tested was the programmable injected current block and the mixer. To test them, a fixed resistor (100 kΩ) was placed between LA and RA as shown in Fig. 3.4. By placing a fixed resistor here, there should be a square input voltage waveform across the

RA and LA. That is because the injected current goes through the ﬁxed resistor from RA to LA when Clk was high and from LA to RA when Clk was low.

The measurement result of the programmable current mirrors and mixer is shown in

Fig. 3.5. There are 4 bits in the programmable injected current block, so 16 square waveforms are included in Fig. 3.5(a) by changing the programmable bits. To further analyze Measurement Result of First Chip 35

VCC I I 2I 4I 8I

100 Clk nA ɸ1 ɸ2 ɸ3 ɸ4 RA Ipmos-out

Clk 100k 100 Inmos-out

nA ɸ1 ɸ2 ɸ3 ɸ4 LA

I I 2I 4I 8I Clk

Figure 3.4. Circuit used to test the programmable injected current block and the mixer. A ﬁxed resistor (100 kΩ) was placed between LA and RA.

the function of this block, the actual amount of injected current from the programmable

current mirrors were calculated. Fig. 3.5(b) shows the calculated positive and negative

currents from current mirrors as a function of the four-bits code. The actual currents

are larger than the theoretical values, and this is probably because the I-V curves used

to set the off-chip bias currents were not calibrated well. The injected current is depen-

dent on the off-chip bias current, therefore the actual injected current is different from

the design value when the off-chip bias current is not the theoretical value. In addition,

there is an offset I I which has an average value of 65 nA, which is relatively small | P − N | (less than 1 LSB = 100 nA).

3.2 ECG Ampliﬁer

The ECG ampliﬁer is the most important part in the AFE. And the measurement result

is presented here.

The differential frequency response of the ECG signal path (consisting of ECG am-

pliﬁer and LPF) is shown in Fig. 3.6(a). The measured upper cutoff frequency is around Measurement Result of First Chip 36

0.4 3 Positive 2.5 Negative 0.2 Offset

A) 2 μ 0 1.5

1 Voltage (V) Current ( -0.2 0.5

-0.4 0 0 0.02 0.04 0.06 0.08 0.1 12345678910111213141516 Time (sec) Digital code

Figure 3.5. (a) Square voltage waveforms across the RA and LA with different injected currents when a 100 kΩ resistor was used between RA and LA. (b) Measured positive and negative currents as a function of the digital code.

150 Hz, however, the theoretical value is 1 kHz. The reason for this is probably a different off-chip bias current was used so that the cutoff frequency of the LPF changed. Also, the mid-band gain is around 39.5 dB, which is in good agreement with the design value of 40 dB. Fig. 3.6(b) is the common-mode frequency response of the ECG path without utilizing driven-ground circuit. The average gain of common-mode signal in the band of

100 Hz is around 0.8 dB, resulting in the CMRR in ECG path of 39.5 dB - 0.8 dB = 38.7 dB without driven-ground circuit.

40 10

30 0

20 -10 10 -20 Gain (dB) Gain (dB) 0 -30 -10

-20 -40 0 1 2 3 100 101 102 103 104 10 10 10 10 Frequency (Hz) Frequency (Hz)

Figure 3.6. (a) Differential frequency response of both the ECG ampliﬁer and the following LPF.(b) Common-mode frequency response of both the ECG ampliﬁer and the following LPF without utilizing driven-ground circuit. Measurement Result of First Chip 37

The input and output noise measurement results of the both the ECG ampliﬁer and the following LPFs is shown in Fig. 3.7(a) and (b). From the result, it is easy to con- clude that the 1/f corner frequency is around 25 Hz. The thermal noise PSD is around

254 nV/Hz1/2, which is slightly larger than the simulation result of 162 nV/Hz1/2. The

minimum detectable signal is around 38 µV in the band of 1-150 Hz. Since the upper

cutoff frequency of the LPF is around 150 Hz, the thermal noise is ﬂat in the range of

25 Hz to 150 Hz but not ﬂat when frequency is higher than 150 Hz.

-4 10 10-4 Output noise Input noise

-6 /Hz) 10 2 10-5

10-8

-6 Noise (V 10 10-10 Noise (V/sqrt(Hz))

-12 10 10-7 0 1 2 3 0 1 2 3 10 10 Freq (Hz) 10 10 10 10 Freq (Hz) 10 10

Figure 3.7. (a) Output noise of the both the ECG ampliﬁer and the following LPF. (b) Input noise of the both the ECG ampliﬁer and the following LPF.

Fig. 3.8 proves that the preampliﬁer can amplify both the ECG and high-frequency carrier signals as expected. As described in the second chapter, the high-frequency clock can be disabled when user only wants to monitor ECG signal. Fig. 3.8(a) shows the output of the ECG path when clock was disabled. The input signal, a 2 mV, 10 Hz sinusoid wave generated from a signal generator, which simulated ECG signal, was ampliﬁed by around 40 dB as expected.

Fig. 3.8(b) shows the output of the ECG path when input signal was the sum of a

1.5 mV, 10 Hz sinusoid (simulating ECG) and a 1.4 mV, 100 Hz square wave (simulating Measurement Result of First Chip 38

RR carrier). Since the upper cutoff frequency of the ECG LPF is around 150 Hz as described earlier, a relatively low-frequency clock (100 Hz) was used here so that the ECG

LPF did not have effect on it. It is easy to see that both the ECG and the RR carrier signals got ampliﬁed by around 40 dB in good agreement with simulations.

0.2 ECG output 0.2 0.1

0 0 Voltage (V) -0.1 Voltage (V) -0.2 output signal -0.2 0 0.2 0.4 0.6 0.8 1 0 0.05 0.1 0.15 0.2 Time (s) Time (s)

Figure 3.8. (a) Output of the ECG path when high-frequency clock is disabled. The input signal is a 2 mV, 10 Hz sinusoid wave. (b) Output of the ECG path to the sum of a 1.5 mV, 10 Hz sinusoid (simulating ECG) and a 1.4 mV, 100 Hz square wave (simulating RR carrier).

Fig. 3.9 shows a real ECG signal detected from human body by using two standard patch electrodes which were placed on the right and left upper arms. The data presented has been ﬁltered with a fourth-order Butterworth LPF with cutoff frequency of

50 Hz. The frequency of R wave in the output ECG signal is around 1.3 Hz which is in good agreement with the frequency of the heart rate. But the amplitude of the output signal is smaller than what we expected. One possible reason is that the placement of the electrodes may not be optimal for measuring ECG signal.

Although the measurement results above have proven that the preampliﬁer can amplify both ECG and RR carrier signals as expected, there is a major problem that we found during the experiment. The DC voltage at the output of the ECG path shifted as time went by as shown in Fig. 3.10. Theoretically, the DC voltage at the output of the preampliﬁer should be equal to the reference voltage (0.75 V) which was provided from Measurement Result of First Chip 39

9 5

6 0

Voltage (mV) 012345 3 ECG signal 0 012345 Time (s)

Figure 3.9. Detected ECG signal after baseline removal and filtering with a fourth-order LPF (f 50 Hz). c = a external power supply. But every time the chip was turned on, the DC voltage at the output of the ECG path started to increase from around 0.3 V and finally saturated at around 2.4 V after approximately 900 seconds. To make the AFE work as expected, a suitable range for this DC voltage was concluded during the experiment, in which 40 dB gain could be obtained from this preamplifier. And this DC voltage range is from around

0.6 V to 1.5 V. In this case, the preampliﬁer could only work well for about 2 minutes.

The reason causing this problem is the leakage current in the adaptive element, which is a well-known problem with pseudo resistors50. In this AFE, NMOS transistors are used in the pseudo resistors. The body terminal of NMOS transistor has to be connected to ground because of the process of this chip. In this case, if we assume the source is the high-impedance node, connecting bulk to ground creates a non-zero reverse-bias voltage across the source to body junction diode, resulting in the leakage current in a pseudo resistor. Because of this leakage current, the DC voltage starts to change slowly when the leakage current ﬂowing through the adaptive element. It is possible to avoid this problem by using PMOS transistors instead of NMOS transistors to work as pseudo resistors because the body terminal of a PMOS transistor can be connected to the drain so that Measurement Result of First Chip 40

all diodes are zero biased. Another way to avoid this problem is to use switched capacitor resistors instead of pseudo resistors, but the cost is that the complexity of the circuit increases.

2.5

1.5

1 Voltage (V)

0.5 Output of ECG path 0 100 200 300 400 500 600 700 800 900 1000 Time (s)

Figure 3.10. The DC voltage at the output of the ECG path shifted from 0.3 V to 2.4 V in around 900 seconds.

3.3 RR Measurement

To test the functionality of the RR path, a body model as shown in Fig. 3.11(a) was used to generate both the ECG-like and RR-like signals at the same time. In the body model, the source V1 is a sinusoid wave behaved as ECG signal. By choosing the values of resistors and capacitors, the ECG-like signal can be fed to RA and LA. The source V2 is a 1 Hz triangle wave which is able to turn the discrete FETs on or off, so that the impedance between RA and LA is modulated by around 1%. Fig. 3.11(b) shows the transient simulation result of this body model. It is able to ﬁnd the modulated RR-like signal when a 100 nA 1 kHz AC current was used. Fig. 3.11(c) shows that the body model is able to generate the modulated RR signal (999 Hz and 1001 Hz). This body model was soldered on the PCB board. Measurement Result of First Chip 41

1.8 k 1.8 k F

μ 5.6 k LA

33 33 0.56 k V1 Vref V2

0.56 k F

μ 5.6 k RA 33 33 1.8 k 1.8 k ×10-3 2

-80 1.5

1 -100

0.5 -120 0 Voltage (V) -140 -0.5

-1 -160 20log(amplitude/1Volt) (dB) -1.5 997 998 999 1000 1001 1002 1003 012345 Time (s) Frequency (Hz)

Figure 3.11. (a) Body model used to generate ECG-like and RR-like signals. (b) Simulation result of the modulated RR-like signal when 100 nA 1 kHz AC currents are fed to LA and RA. (c) The FFT result of the transient signal generated by the body model.

Fig. 3.12 shows the measured I and Q components of RR signal after ﬁltering with a fourth-order Butterworth LPF with cutoff frequency of 5 Hz. The 0.5 Hz ramp wave was used to control the FETs on or off. The results prove the functionality of the RR path with a total gain of around 72 dB. Measurement Result of First Chip 42

6 Input ramp wave 4

2 Voltage (V) 0 024681012 Time (s) 0.04 0.03 I branch output 0.02 Q branch output 0.01 0 -0.01 -0.02 Voltage (V) -0.03 -0.04 024681012 Time (s)

Figure 3.12. Input triangle wave used to modulate the impedance between RA and LA at 0.5 Hz, and measured I and Q RR outputs after ﬁl- tering with a fourth-order Butterworth LPf with cutoff frequency of 5 Hz. 43

4 Second Chip Design

From the measurement results of the ﬁrst chip, several updates are needed. For the second chip, a fully differential AFE is designed to improve CMRR and reduce distortion. Also, more gain in RR path is needed since the amplitude of RR is small. Besides, it is necessary to get rid of the DC voltage shifting problem caused by the leakage current in the adaptive element. In addition, the driven-ground circuit needs to be updated because it did not work well during the experiment. Finally, four-terminal sensing method is utilized to detect respiratory rate. AC current is injected into body through a pair of electrodes while the signal is sensed by another pair of electrodes, resulting more accu- rate measurement of body impedance. The simulation result proves the functionality of the second AFE, which draws 14 µA from a 3 V power supply. The gain for ECG signal is

40 dB (46 dB if the preampliﬁer works in high gain mode) while the gain for RR signal is

82 dB (88 dB if the preampliﬁer works in high gain mode).

4.1 Fully Differential Wide-linear-range OTA

The second chip is a fully differential AFE. Therefore, a fully differential WLR OTA is needed. Fig. 4.1(a) is the fully differential version of the wide-linear-range OTA. For this fully differential OTA, a common-mode feedback (CMFB) must be used. In the feedback, Second Chip Design 44

the common-mode voltage is sensed and then compared with a suitable reference voltage. Then the circuit feeds back the correcting signal so that the output common-mode voltage is set to a desired value. Normally, two resistors are used to detect the common- mode voltage, and an OTA is used to compare the sensed common-mode voltage with a reference. However, in our chip, a differential-difference operational transconductance ampliﬁer (DDOTA)51, as shown in Fig. 4.1(b), is used to detect the common-mode voltage and compare it with a reference voltage. No passive component is used to detect the common-mode voltage here, which ensures that the CMFB circuit has high input impedance and does not load the main OTA (which would reduce its differential voltage gain). The stage of the fully differential OTA with the common-mode feedback is shown in Fig. 4.1(c). For the load capacitors C1 and C2, the CMFB half circuit only sees C1 as

52 the load capacitor while the differential half circuit sees C1+2C2 as the load capacitor .

Thus, the values of C1 and C2 can be adjusted to independently set the bandwidths of the differential and common-mode paths. We connect the output of the DDOTA (Vf b)

to the bias voltage node (VB ) so the negative common-mode feedback is generated. The

fully differential OTA stage in the preampliﬁer is shown in Fig. 4.2(a), and the gain is set

by the ratio of capacitors in the feedback loop. To set up the input DC voltage, a modiﬁed

switched capacitor resistors topology is used, which will be described in detail later.

To check the stability of this single stage of fully differential OTA in the preampliﬁer

shown in Fig. 4.2(a), the Bode plot is plotted as shown in Fig. 4.2(b). From the Bode plot,

it is clear to see that the phase margin is around 80 ◦ and the gain margin is around 12 dB, which proves the stability of the fully differential OTA. Second Chip Design 45

VCC VCC

M3 M4 VCC Vbias VB

out- M5 M6 out+ M9 M10 V- V+ M11 M7 M8 M1 M2 M12

VCC VCC

Vfb

1 Vpp Vpn Vnp Vnn C Ib ref C2 V C1

Figure 4.1. (a) Fully differential version of wide-linear-range OTA. (b) Differential-difference OTA used in CMFB. (c) Fully differential OTA stage.

4.2 Fully Differential Filters

In order to design fully differential ﬁlters, the fully differential OTA presented above is used. In ECG path, the LPFs are needed to remove high-frequency modulated RR signal.

In RR path, HPFs are needed to remove ECG signal before the demodulator. After the demodulator, LPFs with off-chip capacitors are needed to remove high-frequency RR carrier signal. Second Chip Design 46

Vref

cap

1 Switch

1pf 0.1pf 0.1pf Vin1 Vout1 0.1pf Vin2 Vout2

1pf 0.1pf 0.1pf

cap

2 Switch Vref 20

-20 Gain (dB)

-40 10-3 10-2 10-1 100 101 102 103 104 105 106 107 Frequency (Hz) 100

-100

Phase (degree) -200 10-3 10-2 10-1 100 101 102 103 104 105 106 107 Frequency (Hz)

Figure 4.2. (a) A single stage of fully differential OTA in the preampliﬁer. (b) Bode plot of the fully differential OTA stage.

Fig. 4.3 shows the filters by using the fully differential OTA. The LPF shown in Fig. 4.3(a) is the modified version of the second RR gain stage in the first chip. Fig. 4.3(b) is the stan-

C dard fully differential Gm C HPF.The time constant of the fully differential ﬁlters is − Gm

(if Gm1 is equal to Gm2 in the LPF). Fig. 4.4(a) shows the AC simulation result of the HPF with cutoff frequency of 1 kHz to remove ECG signal in RR path. Fig. 4.4(b) shows the AC simulation result of the LPF with cutoff frequency of 5 Hz to remove high-frequency RR carrier signal in RR path. To get this low cutoff frequency, 3 nF off-chip capacitor is used here. Second Chip Design 47

C C Gm1 C

1 C

bias

I I

Figure 4.3. (a) Fully differential LPF.(b) Fully differential HPF.

-20

-40

-60

Gain (dB) -80

-100

-120 10-2 100 102 104 106 Frequency (Hz) 0

-50

Gain (dB) -100

-150 10-4 10-2 100 102 104 106 108 Frequency (Hz)

Figure 4.4. The AC simulation results of (a) HPF with cutoff frequency of 1 kHz to remove ECG signal in RR path. (b) LPF with cutoff frequency of 5 Hz to remove high-frequency RR carrier signal in RR path. 3 nF off-chip capacitor is used.

4.3 Fully Differential Preampliﬁer Block

By using the fully differential OTA described above, a fully differential preampliﬁer is de-

signed as shown in Fig. 4.5. There are two stages in the preampliﬁer. In each stage, the Second Chip Design 48

OTA is AC coupled. The gain is set by the ratio of capacitors in the feedback loop. The gain of the ﬁrst stage is set to 10 while the gain of the second stage is programmable.

By turning the switches on and off, the gain can be set to 10 or 20 in the second stage.

In addition, the driven-ground circuit is updated. Two OTAs in unity feedback work as buffers to sense the common-mode voltage. Then, the sensed common-mode voltage will be compared to a reference voltage, and the difference of them is ampliﬁed by two gain stages. The ﬁrst gain stage in the driven-ground circuit includes two OTAs, with the one in unity feedback acting as a buffered resistor. The gain is set by the ratio of two bias currents. In order to ensure that Gm2 can work in linear range, Ibi as1 is a programmable bias current so that the gain of this stage can be controlled. In this design, the programmable gain varies from 1 to 8. The second gain stage includes an op-amp with resistors in the feedback loop. The gain is set by the ratio of two resistors, which is

10 (20 dB) in this case. Another reason that an op-amp is used here is that the output impedance of it is relatively high to drive the electrode impedance of around 2 kΩ.

To set up the DC voltage in the preamplifier, MOS pseudo resistors are generally used but the DC voltage shifting problem exists. Therefore, in order to create a large resistor to generate a low-frequency pole, switched capacitor instead of pseudo resistor is used here. Instead of the standard switched capacitor as described in the first chapter, a novel structure of switched capacitor shown in Fig. 4.6, which is described in53, is utilized to provide DC voltage for the amplifier. The idea to design this modified switched capacitor topology is the same as the standard switched capacitor. It works by moving charges into and out of capacitors when switches are on and off. The equivalent circuits in two phases are presented in Fig. 4.7, and the effective capacitances are 0.5C and 2.5C, respectively. Second Chip Design 49

Vref Vref

2 2

cap cap

1 1 Switch Switch 1pf

1pf 0.1pf 0.1pf 1pf 0.1pf 0.1pf Vin1 Vout1 0.1pf 0.1pf Vin2 Vout2 1pf 0.1pf 0.1pf 1pf 0.1pf 0.1pf

1pf

1 1

cap cap

2 2

Switch Switch Vref Vref

20k 200k Vref

Vref

Gm1 Vcmfb 1

Ibias 15pf

Gm Ibias

Vref

Figure 4.5. Circuit of fully differential preampliﬁer.

When clk2 is high, the effective capacitance is 0.5C as shown in Fig. 4.7(a), and the total charge q0 is

q (V V ) 0.5C (4.1) 0 = 1 − 2 × When clk2 becomes low and clk1 becomes high, the effective capacitance is 2.5C as shown in Fig. 4.7(b). Since the total charge in the switched capacitor keeps the same, the voltage Vclk1 becomes

(V1 V2) 0.5C Vclk1 − × (4.2) = 2.5C Second Chip Design 50

Thus, some charge transfers from the two capacitors in parallel to the two capacitors in series, and the amount of it is

q V 0.5C (4.3) 1 = clk1 ×

From equation (4.2) and (4.3), it can be concluded that

(V1 V2) 0.5C q1 − × 0.5C (V1 V2) 0.1C (4.4) = 2.5C × = − ×

The term q1 here is the charge that is transferred during one cycle. From the continuous time perspective, we also know that the rate of transfer of charge per unit time is

I q f (4.5) = × where f is the transfer rate.

Taking equation (4.4) and (4.5) together, we can get

I (V V ) 0.1C f (4.6) = 1 − 2 × ×

Therefore, for this modiﬁed switched capacitor topology as shown in Fig. 4.6, the equivalent resistance is

(V1 V2) 10 Req − (4.7) = I = f C × This equivalent resistance is 10 times larger than the standard switched capacitor topology when the same frequency and capacitor value are used. There are several reasons that this modiﬁed topology is needed. Since the frequencies of ECG and RR are low, a low cutoff frequency of around 0.1 Hz is needed, resulting in a big resistor of around

200 GΩ. By using switched capacitor, reducing the clock frequency or reducing the on- chip capacitor value can generate a larger resistor, as shown in equation (4.7). However, the minimum reliable on-chip capacitor value is around 50 fF.To get a cutoff frequency Second Chip Design 51

of 0.1 Hz, the equivalent resistance should be around 200 GΩ if a big on-chip capacitor of 10 pF is used. In this case, for the standard switched capacitor topology, if the capacitor in the switched capacitor is 50 fF, the clock frequency should be around 100 Hz, which is in the band of ECG signal. Therefore, this modiﬁed switched capacitor topology is needed. By using this new structure, we can set the capacitor value as 50 fF and the clock frequency as 1000 Hz, which is not in the band of ECG signal anymore.

clk2 clk1 clk2 V1 V2 clk1 C clk2C

clk1 clk2 clk2 clk1 C C

Figure 4.6. Modiﬁed switched capacitor topology.

V1 Vclk1 V2 C C C V1 V2 C C C

Figure 4.7. Equivalent circuits of the modiﬁed switched capacitor topology in two phases. (a) Equivalent circuit when clk1 is on and clk2 is off. (b) Equivalent circuit when clk1 is off and clk2 is on.

Fig. 4.8 shows the simulation result at the output of the preampliﬁer (V V ) out1 − out2 when a 2 mV 100 Hz sinusoid wave simulating ECG signal and a 10 kHz square wave simulating RR carrier signal are used at the input of the circuit. It can be seen that both the

ECG-like signal and the high-frequency carrier signal can be ampliﬁed by the preampli-

ﬁer. Second Chip Design 52

0.2 output of preamplifier

-0.2 Voltage (V) -0.4

-0.6 024681012 Time (ms)

Figure 4.8. Transient simulation result at the output of the preampliﬁer when a 2 mV 100 Hz sinusoid wave simulating ECG signal and a 10 kHz square wave simulating RR carrier signal are used at the input of the circuit.

4.4 Digital Block

Since the switched capacitor is used in the AFE, some digital circuits are needed to generate the clocks for switched capacitor. Fig. 4.9 shows the digital blocks in the AFE. The input frequency is chosen as 38 kHz. To generate clocks for the mixer to extract I component and Q component of RR signal, a D flip-flop and the same clock generator block described in the second chapter are used in the AFE. In this case, clock generator block has four outputs, and clk1 and clk2 have 90◦ phase shift. Since there is a D flip-flop in this branch, the frequency of clk1 and clk2 is 38 kHz/4=9.5 kHz, which is the frequency of RR carrier signal. Also, the enable function is still available in this block. If the user only wants to monitor ECG, the high-frequency RR carrier can be disabled.

The other branch of the digital circuit is used to generate the clocks for switched capacitor. A programmable frequency divider block and a nonoverlapping clock generator block are included. For the programmable frequency divider block as shown in

Fig. 4.11. Five D ﬂip-ﬂops are placed in series so that they behave like a counter. The

Q of each D ﬂip-ﬂop connects to the input of a XNOR gate, while the other input of the Second Chip Design 53

clk1 DS SET Q enable clock clk1_ba clk R CLR Q generator clk2 clk_in clk2_ba

Programmable clk1_sc nonoverlapping freq divider clk2_sc

Figure 4.9. Digital blocks in the AFE.

XNOR gate is the programmable bit. The programmable bits are set to the desired frequency divider ratio. The reason we need to use the programmable frequency divider is that the switched capacitor resistor is a discrete-time system. The switched capacitor resistor along with any load capacitance presented at its output acts as an RC LPF.

The frequency response is periodic, and the peaks exist at integer multiples of the clock frequency fSC . The frequency of signals should be midway between these peaks so the maximum attenuation can be obtained from the ﬁlter, as shown in Fig. 4.10. Therefore, we need to set the frequency of RR carrier (fRR ) signal to be an odd multiple of fSC /2,

i.e., f (2n 1)f /2, where n 0,1,2 . In this case, it is easy for users to adjust the RR = + SC = · ·· frequency divider ratio by using the programmable frequency divider circuit.

The way this block works is that the counter counts one by one until it is reset when it

counts the value of programmable bits. For example, if the programmable bits are 11000, which is 24 in decimal, the counter counts starting from 1. When the counter counts 24,

all the Q outputs of each D ﬂip-ﬂop are equal to the corresponding programmable bits, resulting the following NAND gate generating a high output. This output triggers all the

D flip-flops to reset. The problem of this block is that the delays in each path are not the same. Therefore, another D flip-flop clocked with the inverse of the input clock is used Chapter 9 – Section 1 (5/2/04) Page 9.1-20

Example 9.1-5 - Continued Second Chip DesignFrequency Response of the First-order, Switched Capacitor,54 Low Pass Circuit:

1 100

0.8 50 0.707 Arg[Hoo(ejωT)] 0.6 ω = 1/τ1 |Hoo(ejωT)| 0 0.4 Magnitude -50 0.2 Arg[H(j )] |H(j )| ω ω = 1/τ1 ω Phase Shift (Degrees) 0 -100 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 ω/ωc ω/ωc Fig. 9.1-12

Figure 4.10.Better Frequency results response would of be the obtained first-order if LPF fc > by 20kHz. using switched capacitor. following the output of the AND gate. This additional D flip-flop removes all the glitches at the output of the AND gate, and the output of this additional D flip-flop is used to reset the five D flip-flops in the counter. This reset signal does not have 50% duty cycle.

Thus, another D ﬂip-ﬂopCMOS Analog is usedCircuit toDesign divide the frequency by two, generating a 50% duty © P.E. Allen - 2004 cycle clock. Chapter 9 – Section 1 (5/2/04) Page 9.1-21

There are ﬁve programmable bits so the maximum frequency divider ratio is 32. The SUMMARY frequency of the output• Resistance clock is described emulation as is the replacement of continuous time resistors with switched capacitor approximations fin fout (4.8) - Parallel switched= r atio capacitor2 resistor emulation × The clocks of switched- Series capacitor switched should capacitor be two-phase resistor non-overlapping emulation clocks, so Series-parallel switched capacitor resistor emulation the non-overlapping- clocks generator circuit is needed. The circuit of this block is shown - Bilinear switched capacitor resistor emulation in Fig. 4.11. Several• inverters Time constant in series areaccuracy used so thatof switched a delay is generated.capacitor By circuits using the is proportional to the NOR gates and thesecapacitance inverters with ratio feedback, and the two clock output frequency clocks are non-overlapping • Analysis of switched capacitor circuits includes the following steps: and the delay between them comes from the delay generated by the inverters in series. 1.) Analyze the circuit in the time-domain during a selected phase period. Since many digital2.) inputs The are resulting needed for equations the digital are circuit, based in orderon q = to Cv save. some pins of the chip, the programmable3.) Analyze three-wirethe following serial phase bus circuit period is used, carrying as shown over in the initial conditions from the previous analysis. 4.) Identify the time-domain equation that relates the desired voltage variables. 5.) Convert this equation to the z-domain. 6.) Solve for the desired z-domain transfer function. 7.) Replace z by ejωT and examine the frequency response.

DS SET Q DS SET Q DS SET Q DS SET Q DS SET Q ratio5 clk_in clk clk clk clk clk R CLR Q R CLR Q R CLR Q R CLR Q R CLR Q ratio4 reset clk_out ratio3 DS SET Q AND DS SET Q clk R CLR Q clk ratio2 R CLR Q

ratio1

Figure 4.11. Programmable counter.

1x 1x 1x 1x 1x 1x 1x 3x 9x clk1_sc

1x 1x 1x 1x 3x 9x clk2_sc

Figure 4.12. Two-phase non-overlapping clocks generator block.

Fig. 4.13(a). Microcontroller can be used off-chip and some code can be written to transmit all the digital inputs by using Serial Peripheral Interface (SPI). The D ﬂip-ﬂops work as shift registers, and the latches are used to save the bits. When the enable signal is high, the latches retain their previous values to ensure that incorrect values are not passed into the circuit while the shift register is being programmed. The enable signal goes low after shift register programming is complete, thus the circuit loads the correct data values into the latches. The timing diagram for enable, clk, and data signals are shown in

Fig. 4.13(b).

To test the functionality of all the digital circuit in the AFE, the circuit shown in

Fig. 4.9 has been simulated. The following simulation results prove the functionality of all the digital blocks, as shown in Fig. 4.14 and Fig. 4.15. The input clock is a 38 kHz Second Chip Design 56

bit[1] bit[2] bit[n] bit[n+1]

Q Q Q Q

en en en en

DATA DATA DATA DATA

enable enable enable enable DATA DS SET Q DS SET Q DS SET Q DS SET Q clk clk clk clk clk R CLR Q clk R CLR Q clk R CLR Q clk R CLR Q

enable clk data

Figure 4.13. (a) Programmable bus used to set digital inputs. (b) Timing diagram of SPI.

square wave simulating the off-chip clock, as shown in Fig. 4.14(a). The Fig. 4.14(b) and

Fig. 4.14(c) are the outputs of two clocks with 90◦ phase shift, which are further used in the mixer for modulation and demodulation. It is clear to see that the frequencies of the two clocks in the Fig. 4.14(b) and Fig. 4.14(c) are same and one fourth of the frequency of the input clock shown in Fig. 4.14(a).

The other branch of the digital circuit shown in Fig. 4.9 is used to generate non- overlapping clocks for switched capacitor. The simulation results are in Fig. 4.15. Fig. 4.15(a) and Fig. 4.15(b) show the outputs of two non-overlapping clocks. In this simulation, the programmable frequency divider ratio is set to 19, therefore the frequency of the clocks in Fig. 4.15(a) and Fig. 4.15(b) is 1 kHz, which is in agreement with the theoretical value.

If these two clocks are zoomed in, it is clear to see that they are non-overlapping, as shown in Fig. 4.15(c). In the non-overlapping clock generator block as shown in Fig. 4.12, Second Chip Design 57

8 inverters are used in series in each branch, resulting a 2 ns delay between the two output clocks for switched capacitor, as shown in Fig. 4.15(c).

4 off-chip clk 2 Voltage 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Time (s) ×10-3 4 clk1 2

Voltage (V) 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Time (s) ×10-3 4 clk2 2

Voltage (V) 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Time (s) ×10-3

Figure 4.14. Simulation results of the circuits generating clocks used in the mixer for modulation and demodulation. (a) The 38 kHz input square wave simulating the off-chip clock. (b) The ﬁrst output clock with one fourth of the frequency of the input wave. (c) The second output clock with one fourth of the frequency of the input wave and 90 ◦ phase shift.

4.5 Second Gain Stage for Amplifying RR signal

As we described earlier, the amplitude of RR signal is really small. Therefore, another gain stage for amplifying RR signal is needed. The circuit shown in Fig. 4.16 contains three parts, including a HPF and two gain stages.

For the HPF, the modiﬁed switched capacitor described earlier is used. The theoretical equivalent resistance of the switched capacitor is 200 GΩ, resulting in the cutoff frequency of this HPF around 0.08 Hz. In order to amplify the extracted RR signal, there are two gain stages in this block. The ﬁrst gain stage includes an op-amp. The gain is set Second Chip Design 58

2 SC clk1

Voltage (V) 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Time (s) ×10-3 4 SC clk2 2

Voltage (V) 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Time (s) ×10-3 4

2 SC clk1 SC clk2

Voltage (V) 0 494.01 494.011 494.012 494.013 494.014 494.015 494.016 494.017 494.018 494.019 494.02 Time (us)

Figure 4.15. Simulation results of the circuits generating clocks used in the switched capacitor. (a) The ﬁrst output clock. (b) The second output clock. (c) 2 ns delay between the two non-overlapping output clocks.

Vref

cap 1 Switch 0.1pF 10pF 2pF Iin+ Iout+

2 Gm1

Iout- 1

Iin- cap 2pF 1 10pF Switch

0.1pF

1 Ibias

ref 1

V 2

cap

Switch

2 Switch ref V Ibias

HPF (0.08 Hz) Gain stage 1 Gain stage 2

Figure 4.16. Second gain stage for amplifying RR signal. by the ratio of the capacitors in the feedback loop, which is set to 20 in the design. To set up the input DC voltages, the same switched capacitors are used. The second gain stage is the fully differential version of the second RR gain stage used in the ﬁrst AFE, Second Chip Design 59

as described in the second chapter. The gain of this stage is set by the ratio of two bias currents, which is set to 10 in the design. In this case, the total gain of this block utilized to further amplify the RR signal is 20 10 200 (46 dB). × = In order to test the stability of the op-amp stage, the open-loop Bode plot is plotted as shown in Fig. 4.17. The phase margin is 65 ◦ and the gain margin is 18 dB, which is sufﬁcient for this application. Fig. 4.18 shows the simulated closed-loop Bode plot of the op-amp stage shown in Fig. 4.16. The phase margin is around 50 ◦ and the gain margin is around 5 dB. Fig. 4.19 shows the transient simulation result at the output of I branch in

RR path (I I ). In this simulation, the body model used in Section 3.3 is utilized here + − − to generate modulated RR signal. The frequency of RR signal is set to 5 Hz to increase the simulation speed, which is modulated on a 10 kHz carrier signal. At the output of the

I branch in RR path as shown in Fig. 4.19, it can be seen that the high-frequency carrier signal is removed by the ﬁlters in RR path and the 5 Hz RR signal is extracted.

100

0 Gain (dB)

-50 10-2 100 102 104 106 108 Frequency (Hz) 0

-100

-200

-300 Phase (degree) -400 10-2 100 102 104 106 108 Frequency (Hz)

Figure 4.17. Open-loop Bode plot of the op-amp stage. Second Chip Design 60

Gain (dB) 0

-10 10-2 100 102 104 106 108 Frequency (Hz) 100

-100 Phase (degree) -200 10-2 100 102 104 106 108 Frequency (Hz)

Figure 4.18. Closed-loop Bode plot of the op-amp stage.

0.5 I component of RR signal 0.4

0.3

0.2

0.1 Voltage (V)

-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Time (s)

Figure 4.19. Transient simulation result at the output of I branch in RR path (I I ). The frequency of RR signal is chosen as 5 Hz to increase + − − the simulation speed.

4.6 Layout

Good layout leads to good performance. In the design, several methods are utilized to make layout better.

For critical components like differential pairs and current mirrors, they should be laid out carefully. The ﬁrst technique is common-centroid layout. A common-centroid array should cancel systematic mismatches due to gradients. Also, making devices larger is another way to improve matching, while the trade-off is the increased layout area. Second Chip Design 61

It is also useful to use small transistors to create many ﬁngers so that transistors with large W/L can be achieved. Metal instead of poly should be used to interconnect gates if possible. In addition, guard rings are often utilized to reduce substrate coupling noise.

NMOS rings should be tied to ground while PMOS rings should be connected to the power supply. It is also very important to use as many contacts as possible to increase the conductance between two layers.

For passive components, poly-poly capacitors with the typical capacitance density of around 900 aF/µm2 and high resistance (Hi-Res) resistors with typical resistivity of around 1192 Ω/ are widely used in this AFE. To have better layout, both of them have ä common-centroid layouts to improve matching. Guard rings are also used to protect capacitors and resistors.

Fig. 4.20 shows the ﬁnal layout of the whole AFE. The active area is around 1050 µm

1050 µm, and the total area is around 1500 µm 1500 µm. × × Second Chip Design 62

Figure 4.20. Layout of the second chip. 63

5 Conclusions

This thesis has demonstrated two AFEs for simultaneous measurement of ECG and

RR signals. The ﬁrst chip has been fabricated on the OnSemi 0.5 µm CMOS process and it has been tested. Both simulation and measurement results prove the functionality of it. One conference paper emerged based on the results of the ﬁrst chip54. The second

AFE has been designed to correct the defects in the ﬁrst chip, and it will be submitted for fabrication on the same process. In this chapter, we will summarize the results of the main blocks in the AFEs and discuss the future work.

ECG Ampliﬁer: Two different preampliﬁers have been designed in each AFE. In the

first chip, the preamplifier used is a modified version of the amplifier presented in42,43.

Since the frequencies of bioelectrical signals are low (typical ECG bandwidth of 1 Hz to

100 Hz and RR bandwidth of 0.5 Hz)24, the MOS pseudo resistors are used to generate a low cutoff frequency. The driven-ground circuit is also utilized to boost the CMRR.

Measured results show that the 1/f corner frequency is around 25 Hz and the thermal noise PSD is around 254 nV/Hz1/2, which are in good agreement with simulations. The minimum detectable signal is around 38 µV in the band of 1-150 Hz. The mid-band gain is 40 dB as expected. Conclusions 64

However, certain design defects were found during the measurement. The DC voltage at the output of the amplifier shifted. This is because the leakage current exists in the pseudo resistor. To overcome this problem, another preamplifier is designed in the second AFE. For the second amplifier, switched capacitor is used to replace the MOS pseudo resistor so that the leakage current in the pseudo resistor does not have effect on the circuit. Another advantage of using switched capacitor resistors is that the effective resistance can be easily controlled by changing the clock frequency fed to switched capacitor. In this case, the high-pass cutoff frequency can be controlled during operation.

It is possible to control the effective resistance of pseudo resistor by changing the gate bias voltage23,55, but this method is much less straightforward. Also in this preampli-

ﬁer, the second gain stage has programmable gain. Besides, the driven-ground circuit is updated since we found the original driven-ground circuit did not work well. Source followers and on-chip resistors are used to detect the common-mode voltage. Two OTAs, with the one in unity feedback acting as a buffered resistor, are used to compare the sensed common-mode voltage with a reference voltage and amplify the difference between them. An op-amp in unity feedback is then used to act as a buffer so that the driven-ground circuit is able to drive the electrode impedance.

Second Gain Stage for RR:

In the ﬁrst AFE, the circuit uses two WLR OTAs, with the one in unity feedback be- having as a resistor. The gain is set by the ratio of two bias currents, which is set to 50

(34 dB) in the chip. However, it is not good to set the ratio of bias currents too high since the OTA in unity feedback may be saturated. The second chip is a fully differential AFE, and a fully differential version of the original RR gain stage is used. The gain is set to

10 (20 dB) which is more reasonable. To provide more gain in RR path, the circuit also Conclusions 65

uses an op-amp to amplify the RR signal. The gain of the op-amp stage is set by the ratio of capacitors in the feedback loop, which is set to 20 (26 dB) in the AFE, resulting the total RR gain of 40 dB+20 dB+26 dB-4 dB=82 dB. Here the -4 dB term comes from the conversion loss of the mixer.

Future Work: The ultimate goal of this thesis is to use the AFE designed in a wearable biopotential measurement system, which can continuously monitor high-quality ECG and respiratory condition. The chest band with three electrodes collects the signals. The

AFE designed can amplify the sensed signals and an ADC is also needed to digitize the ampliﬁed outputs. Digitized signals shall be buffered locally and transmitted to a wrist band or a personal computer through low-power Bluetooth.

The biopotential measurement system can be further used in several applications.

One application is to use the system to discriminate between the non-epileptic seizures and epileptic seizures56. This technique has been demonstrated on a limited number of patients at University Hospitals (UH) Case Medical Center (CMC) to identify psy- chogenic non-epileptic seizures (PNES). Appendix 66

Appendix A PCB for testing the AFE

This appendix presents the schematic and layout of the PCB board used to test the

ﬁrst AFE.

1 2 3 4

DCOD0Sub-Sub COB1 COP11 COB2 COP12 COB3 COP7 B1 P11 B2 P12 B3 P7 PID0Sub011 VNLVDDinDDin ANLAPVDDinPVDDin clk 9 PIB101 PIP1101 1 PIB201 PIP1201 1 PIB301 3 PIP703 PID0Sub09 RANLRA 2 PIP1102 2 PIP1202 2 2 PIP702 PID0Sub02 PIB10MH PIB20MH PIB30MH 10 17 1 PIP701 PID0Sub010 PID0Sub017 51K101-400A4 Header 2 51K101-400A4 Header 2 51K101-400A4 3 A COP8 PID0Sub03 A Header 3 RAB P8 PID0Sub01111 4 3 PIP803 PID0Sub04 GND GND GND NLLALA 12 2 PIP802 PID0Sub012 VDD APVDD 5 1 PIP801 COP9 PID0Sub05 PIC902 PIC1002 PIC1102 PIC1202 P9 PID0Sub01313 COC9C9 COC10C10 COC11C11 COC12C12 Header 3 LAB 6 3 PIP903 PID0Sub06 PIC901 CAP 1uPIC1001F 6CA.3VP 0 180005n(2F0 61.32)V 0805(2012) PIC1101 CAP 1uPIC1201F 6CA.3VP 0 180005n(2F0 61.32)V 0805(2012) NLLLLL 14 16 2 PIP902 PID0Sub014 PID0Sub016 PIJ901 PIJ1001 PIJ1101 7 1 PIP901 PID0Sub07 GND PID0Sub01515 COJ9J9 COJ10J10 COJ11J11 Header 3 LLB PID0Sub088 Socket Socket Socket GND GND 212612043

COP1P1 P2COP2 APVDD APVDD CHCOCH11 3 PIP103 3 PIP203 SC1 SC2 NLSC1SC1 1 40 NL200nA200nA PIP102 PIP202 PICH101 PICH1040 R1COR1 R2COR2 2 2 NLSC2 SC1 200nA COJ6J6 NLRAB PIP101 PIP201 SC2 PICH1022 PICH103939 LL 1PIR101 PIR1022 1PIR201 PIR2022 RAB 1 1 SC2 LL 2 NLSC3SC3 3 38 LA PIR502 B PICH103 SC3 LA PICH1038 B Header 3 Header 3 NLSC4SC4 4 37 RA PICH104 SC4 RA PICH1037 GND GND 5 36 ECGout PIJ601 COJ7J7 R5COR5 PICH105 5 ECGout PICH1036 2 PICH1066 PICH103535 Iout Socket PIJ701 PIc3102 PIR501 COP3 COP4 6 Iout COc31c31 1 P3 P4 PICH1077 PICH103434 5nA COC8C8 7 5nA 2 COTran1Tran1 APVDD APVDD 8 33 SocketCOC7C7 JCOJ2121 PIc3101 cap33u PIR702 1 3 PIP303 3 PIP403 PICH108 8 cap8 PICH1033 PIC801 PIC802 1 PITran101 D PIP302 SC3 PIP402 SC4 PICH1099 PICH103232 C6COC6 PIC701 PIC702 PIJ2101 PITran1022 2 2 9 cap7 CAP 1nF 6.3V 0805(2012) R7COR7 G PIP301 PIP401 PICH101010 PICH103131 C5COC5 PIC601 PIC602 PITran1033 1 1 10 cap6 CAP 1nF 6.3V 0805(2012) S PICH101111 PICH103030 PIC501 PIC502 COC4C4 Socket PIR701 11 cap5 1 2n7000 Header 3 Header 3 12 29 CAP 1nF 6COC3C3.3V 0805(2012) LNLLLBLB PICH1012 12 cap4 PICH1029 PIC401 PIC402 2 COTran2Tran2 GND COC13 GND 13 28 CAP 1nF 6COC2.3V 0805(2012) JCOJ2222 PIR802 3 PIJ2001 C13 PICH1013 13 cap3 PICH1028 C2 PIC301 PIC302 PITran203 S 14 27 COC1 CAP 1nF 6.3V 0805(2012) 2 PICH1014 14 cap2 PICH1027 C1 PIC201 PIC202 PIJ2201 G PITran202 GND 15 26 CAP 1nF 6.3V 0805G(2N0D12) R8COR8 1 JCOJ2020

PIC1302 PIC1301 PICH1015 PICH1026 PIC101 PIC102 2 PITran201 APGND cap1 CAP 1nF 6.3V 0805(2012) D APVDD PICH101616 PICH102525 Socket PIc3202 PIR801 Socket CAP 100nF 6.3V 0805(2012) NLPADFOL APVDD Gnda CAP 1nF 6.3V 0805(2012) COc32c32 1 2n7000 COC14C14 PADFOPICH1017L 17 PICH102424 Qout COC15C15 PADFOL Qout 2 GND VDD 18 23 NLVDDVDD PIc3201 cap33u PIR602 PIC1402 PIC1401 PICH1018 VDDD VDDA PICH1023 PIC1502 PIC1501 1 19 22 NLclkclk PIJ801 GND PICH1019 GNDD clk PICH1022 CAP 100nF 6.3V 0805(2012) NLCLK0enCLK_en 20 21 NL0075V0.75V CAP 100nF 6.3V 0805(2012) R6COR6 PICH1020 PICH1021 COR3 COR4 CLK_en 0.75v R3 R4 NLLAB GND GND JCOJ88 1PIR301 PIR3022 PIR601 1PIR401 PIR4022 LAB GND chip1 1 C Socket C COP10P10 APVDD 3 PIP1003 CLK_en 2 PIP1002 P1COP133 COU1U1 1 PIP1001 1 4 NLQoutQout 4 PIP1304 PIU101 SCLK AIN0 PIU104 Header 3 10 5 NLIoutIout 3 PIP1303 PIU1010 DIN AIN1 PIU105 GND 9 6 NLECGoutECGout 2 PIP1302 PIU109 DOUT/DRDY AIN2 PIU106 2 7 1 PIP1301 PIU102 CS AIN3 PIU107 COJ1J1 P5COP5 COJ2J2 P6COP6 COC24C24 Header 4 NLAPVDDAPVDD8 3 PIJ101 PIP501 1 PIJ201 PIP601 1 PIC2402 PIC2401 PIU108 VDD GND PIU103 200nA NL5nA5nA GND PIP502 2 PIP602 2 Socket Socket CAP 100nF 6.3V 08A0D5S1(201128)IDGST PIP503 3 PIP603 3 APVDD APVDD APVDD APVDD GND GND PIPot1033 COPot1Pot1 PIPot2033 COPot2Pot2 PIPot3033 PoCOPot3t3 Header 3 PIPot4033 PoCOPot4t4 Header 3 pot1 pot1 pot1 pot1 PIC1602 PIPot1011 0.75V PIC1802 PIPot2011 PADFOL PIC2002 PIPot3011 PIC2202 PIPot4011 COC16C16 PIC1702 C1COC188 PIC1902 COC20C20 PIC2102 COC22C22 PIC2302 PIC1601 CAP 10PIPot1020nF 6.3V 080COC175C1(27012) PIC1801 CAP 10PIPot2020nF 6.3V 080COC19C15(29012) PIC2001 CAP 10PIPot3020nF 6.3VC2COC21 01805(2012) PIC2201 CAP 10PIPot4020nF 6.3VC2COC23 03805(2012) 2 PIC1701 CAP 100nF 6.3V 0805(22 012) PIC1901 CAP 100nF 6.3V 0805(2012) 2 PIC2101 CAP 100nF 6.3V 0805(2012) 2 PIC2301 CAP 100nF 6.3V 0805(2012) Title D D GND GND GND GND GND GND GND GND Size Number Revision A4 Date: 2016/6/7 Sheet of File: C:\Users\..\chiptest1.SchDoc Drawn By: 1 2 3 4

Figure A.1. Schematic of the PCB board. Appendix 67

COJ9 COPot3 COP9 COP8 COP7 PAJ901 COJ1 PAJ101 PAC2102 COC21 COP5 PAPot302 PAC2101 COCH1 PAP901 PAP902 PAP903 PAP801 PAP802 PAP803 PAP701 PAP702 PAP703 PAD0Sub017 PAP501 PAP502 PAP503 PAPot301 COR4 PAR402 PAR202 COR2 COC20 PAPot303 PAR401 COR6 PAR601 PAR602 PAR501 PAR502 COR5 PAR201 PAD0Sub01 COR8 COR7 PAD0Sub09 PAC2001 PAC2002 COR3 PAD0Sub02 PAR801 PAR802 PAR701 PAR702 PAD0Sub010 PAR302 COR1 PAD0Sub03 COP1 PAP101 PAP102 PAP103 COTran2 COTran1 PAD0Sub011 PAR301 PAR102 COD0Sub PAD0Sub04 PACH101 PACH1040 PATran201 PATran202 PATran203 PATran103 PATran102 PATran101 PAR101 PAD0Sub012 PAD0Sub05 COP2 PAP201 PAP202 PAP203 PACH102 PACH1039 PAc3201 COc31 PAD0Sub013 COc32 PAJ2201 PAJ2001 COJ20 PAD0Sub06 PACH103 PACH1038 PAc3202 PAc3102 PAD0Sub014 COP3 PAP301 PAP302 PAP303 PACH104 PACH1037 COJ22 PAD0Sub07 PAJ201 PAc3101 PAD0Sub015 PACH105 PACH1036 COJ2 COPot4 PAD0Sub08 COC23 COP4 PAP401 PAP402 PAP403 PACH106 PACH1035 COP6 PAP603 PAP602 PAP601 PAPot402 PAJ1101 COJ11 PAC2302 COJ21 PACH107 PACH1034 PAPot401 COB1 PAC2301 PACH108 PACH1033 PAC801 PAC802 COC8 PAPot403 PAJ2101 PAD0Sub016 PACH109 PACH1032 PAC701 PAC702 COC7 PAC2202 PACH1010 PACH1031 PAC2201 COC22 PAB101 PAC601 PAC602 COC6 COC19 PACH1011 PACH1030 PAC1901 PAC1902 PACH1012 PACH1029 PAC501 PAC502 COC5 PAB10MH PACH1013 PACH1028 COJ6 COJ7 COJ8 PAC1301 PAC401 PAC402 COC4 COC10 COC9 PAC1302 PACH1014 PACH1027 PAJ601 PAJ701 PAJ801 PAP1101 PAC1002 PAC902 COC13 PACH1026 PAC301 PAC302 PAP1102 PAC1001 PAC901 PACH1015 COC3 COC2 COP11 PACH1016 PACH1025 PAC201 PAC202 COU1

PACH1017 PACH1024 PAU106 PAU105 PAU107 PAU104 COP13 COPot2 PAC101 PAC102 PAU108 PAU103 PAC1502 PAC1501 PAU109 PAU102 PAC1401 PACH1018 PACH1023 COC1 PAU1010 PAU101 PAPot202 PAPot201 PAPot203 PAP1304 PAC1801 PAC1802 PAC1402 PACH1019 PACH1022 COC14 COC15 PAP1303 COC18 PACH1020 PACH1021 PAC2401 PAC2402 PAP1302 COP12 COC24 COP10 PAP1301 PAP1201 COB3 PAP1003 PAB201 PAP1202 COPot1 COJ10 PAP1002 COC11 PAPot102 PAP1001 COC17 PAC1701 PAC1702 PAB301 PAJ1001 PAB20MH PAC1101 PAC1102 PAPot101 COB2 COC16 PAC1601 PAPot103 COC12 PAC1201 PAC1202 PAC1602 PAB30MH

Figure A.2. Layout of the PCB board. Bibliography 68

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