By Hossein Kassiri Bidhendi a Thesis Submitted in Conformity

MULTI-MODAL DENSELY-INTEGRATED CLOSED-LOOP NEUROSTIMULATORS FOR MONITORING AND TREATMENT OF NEUROLOGICAL DISORDERS

Hossein Kassiri Bidhendi

A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto

Abstract

Multi-Modal Densely-Integrated Closed-Loop Neurostimulators for Monitoring and Treatment of Neurological Disorders

Hossein Kassiri Bidhendi Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto 2016

This dissertation presents the design, implementation and validation of four multi- and single-die systems-on-chip (SoCs) for diagnostic and treatment of neurological disorders. The first prototype is a multi-die wireless device that is designed and implemented as the first step toward a fully-integrated wireless brain machine interface SoC. The device is sized at 2 × 2 × 0.7 cm3, weighs 6 grams, and is comprised of two mini- boards and a power receiver coil. It takes advantage of two previously-reported chips (one on each board) as the core components for neural recording and stimulation, and for wireless data/power communication, respectively. The system is validated in: (a) in vivo detection and control of epileptic seizures in rats with temporal lobe epilepsy, and (b) sleep-stage classification and triggering responsive stimulation for REM (rapid eye movement) sleep suppression. The second prototype is a 16 mm2 0.13 μm CMOS SoC. In this design, all the system-level functionalities of the above multi-die system (i.e. wireless data transmitters, wireless power receiver, signal processing unit for seizure detection, etc.) are integrated on a single die, and the AC-coupled recording channel is replaced with a chopper-stabilized digitally-assisted DC-coupled front-end. This is done by borrowing III circuit blocks of three previously-reported chips (1. wireless power and data 2. DC- coupled front-end and 3. stimulator, and digital backend) and combining them on the same die. Channel-to-channel gain mismatch among the 64 channels of this chip is removed by utilizing a multiplying ADC, included in each channel, in a digital calibration loop. The third prototype, which is the latest generation of responsive neurostimulator SoCs developed in our lab, features 64 correlated double-sampled Δ2Σ-based (a Δ stage and a ΔΣ stage) neural recording front-ends capable of recording brain signals with rail-to-rail DC offset variation. The mixed-signal design results in the channel area reduction by an order of magnitude (0.013 mm2 for amplifier+ADC+stimulator), and channel power consumption being linearly scalable with the input signal frequency bandwidth. Additionally, using a current-output-DAC that is placed in the feedback path of the Δ2Σ ADC, a mixed-mode analog-digital multiplication is performed in each channel. This yields a compact implementation of band-pass digital filters, as well as voltage gain scaling. The analog multiplication circuit is reused as a current-mode stimulator when the SoC is configured to perform neurostimulation. The chip occupies 6mm2 and is validated in vivo in epileptic seizure monitoring, detection, and abortion. The fourth prototype is a wireless 4-channel dual-mode arbitrary-waveform neurostimulator IC with 20 V voltage compliance. The system uses a load-aware adaptive supply voltage control, which results in up to 68.5% saving in power consumption. The 10 mm2 SoC is implemented in a 0.35μm HV-CMOS process. It is housed in a 2 × 2 × 0.7 cm3 multi-PCB device, that also provides wireless power and data/commands telemetry for the chip. This design is preceded by the design of a board-level high- voltage hybrid 16-channel electrical and 8-channel optogenetic stimulator, validated in vivo for both its electrical and optogenetic stimulation functionalities. IV

To Him who taught me to love

To my parents for their unconditional love V

Acknowledgements

First and foremost, I would like to thank Professor Roman Genov, my PhD advisor for his insight, guidance, and support throughout my doctoral studies. Coming from a pure electronic background, I had very limited knowledge on the field of biomedical electronics when I started my PhD. He patiently introduced me to the field, connected me with the right collaborators, and generously shared his vast knowledge on the field. During my work in Prof. Genov’s lab, I always felt that I have access to every resource required to implement my ideas. This included funding for fabrication of about a dozen silicon chips and PCBs, to access to world-class experts for consulting about and validating of my designs. Finally I would like to thank him for supporting me in scholarship applications, for giving me the opportunity to mentor undergraduate and graduate students, and for all the non-electronic life lessons I learned from him as my supervisor, and also as a friend.

I would also like to thank my defense committee: Prof. Gulak, Prof. Liscidini, Prof. Plataniotis, Prof. Ng, and my external examiner, Prof. Verma for reading my thesis and their feedback which helped improving this thesis.

During my 5 years in U of T, I was lucky to have Prof. Perez Velzquez, Prof. Carlen, and Prof. Valiante as collaborators to ask my neuroscience questions and for testing my prototypes in their labs. They generously offered me their knowledge, lab space, and equipment in Toronto Hospital for Sick Children and Toronto Western Hospital. I would like to thank them and their group members for their continuous help during the past 5 years. Speciﬁcally, I would like to thank Yana Adamchik, Michael Chang, and Wanida Nuwisait for their help with different animal experiments.

Over the past few years, there were a few people who contributed signiﬁcantly in my research which I am very grateful to. I would like to thank Amer Samarah for patiently VI answering my CAD questions, Karim Abdelhalim for introducing me to this project, and Arshya Feyzi for always being available to hear and criticize my circuit ideas. My special thanks goes to M. Tariqus Salam and Nima Soltani. Tariq was involved in all of the animal experiments I did over the past few years, and helped me more than anyone else to validate my designs. He was always available to answer my never- ending neuroscience questions, connected me to the right people in the hospital, and more importantly, has been a great friend. Nima has shared the 5-year journey with me almost from the ﬁrst day, we co-designed a chip together, had several long technical discussions which resulted in building our PhD ideas, and spent hundreds of hours in the lab helping each other in testing and validating our designs.

I would also like to acknowledge my U of T colleagues, who made my PhD the most memorable experience of my life. I would like to thank Farhad Ramezankhani, Enver G. Kilinc, Javid Musayev, Navid Sarhang Nejad, Behzad Dehlaghi Jadid, Saber Amini, Masumi Shibata, Hyunjoong Lee, Stefan Shopov, Konstantinos Vasilakopoulos, Sevil Zeynep Lulec, Aynaz Vatankhah, Samira Karimelahi, Alireza Sharif Bakhtiar, Kentaro Yamamoto, Derek Ho, Alireza Nilchi, Hamed Sadeghi, Amir Hejazi, Saeid Mojiri, and Mahdi Marsousi. I am also grateful to ECE staff members Jennifer Rodriguez, Jaro Pristupa, Darlene Gorzo, Jayne Leake, and Gaja Sanmugaratnam who helped me in different ways during the past 5 years.

I was fortunate to have the opportunity to mentor graduate and undergraduate students who also contributed into my research. I would like to thank Aditi Chemparathy, Yu Hu, Richard Gao, Chang Liu, Gairik Dutta, Shreedutt Hegde, Fadime Bekmambe- tova, Fred Chen, Behraz Vatankhahghadim, Kevin Gumba, Sana Tonekaboni, Peter Li and Alan Li.

My wife had to go through a lot of trouble so that I could ﬁnish this work. I am greatly indebted to her for all she has done. Finally, I would like to thank my parents VII and my sister for their unconditional support throughout the years and motivating me to ﬁnish. VIII

Contents

1 Introduction 1

1.1 Objective ...... 1

1.2 Implantable Brain Machine Interfaces ...... 3

1.2.1 System Overview ...... 3

1.2.2 System Design Requirements ...... 4

1.3 Large Form-Factor Neurostimulators ...... 6

1.3.1 Academic Designs ...... 6

1.3.2 Commercially-Available Neurostimulators ...... 7

1.4 Integrated Circuits for Wireless Responsive Neurostimulators ...... 12

1.4.1 Electrodes ...... 12

1.4.2 Recording Ampliﬁer ...... 16

1.4.3 Digital Backend ...... 21

1.4.4 Wireless Data and Power ...... 22

1.5 Electrical Current/Voltage and Optogenetic Stimulation ...... 24

1.5.1 Electrical High-Voltage Stimulators ...... 24

1.5.2 Optogenetic Stimulation ...... 28

1.6 Thesis Organization ...... 34

2 Implantable Wireless Mini-Board for Monitoring and Treatment of Neuro- IX

logical Disorders 41

2.1 Battery-less Modular Responsive Neurostimulator for Prediction and Abortion of Epileptic Seizures ...... 42

2.1.1 Introduction ...... 42

2.1.2 Methods and Material ...... 43

2.1.3 Results ...... 48

2.1.4 Safety ...... 50

2.1.5 Conclusion ...... 53

2.2 Electronic Sleep Stage Classiﬁers: A Survey and VLSI Design Method- ology ...... 56

2.2.1 Introduction ...... 56

2.2.2 Review of Sleep-Stage Monitoring Sensors ...... 58

2.2.3 Review of Sleep Classiﬁcation Algorithms ...... 62

2.2.4 Algorithm Comparative Study ...... 67

2.2.5 Electronic Implementation of Algorithm C ...... 74

2.2.6 Proposed Algorithm Results ...... 79

2.2.7 Conclusion ...... 81

3 Battery-Less Tri-Band-Radio Neuro-Monitor and Responsive Neuro-Stimulator IC for Diagnostics and Treatment of Neurological Disorders 83

3.1 Introduction ...... 83

3.2 Motivation ...... 84

3.3 System VLSI Architecture ...... 85

3.4 VLSI Circuit Implementation ...... 88

3.4.1 Neural Recording ...... 88

3.4.2 Wireless Transmitters ...... 96

3.4.3 Inductive Power and Command Telemetry ...... 97 X

3.5 Experimental Results ...... 99

3.5.1 Analog Front-end ...... 101

3.5.2 Wireless Transmitters ...... 104

3.5.3 Inductive Power and Command Telemetry ...... 107

3.6 Experimental Validation ...... 109

3.6.1 In-vivo Early Seizure Detection and Control ...... 109

3.6.2 Ofﬂine Early Seizure Detection in Humans ...... 111

3.6.3 Statistical Analysis ...... 112

3.7 Discussion ...... 114

3.7.1 Resource Utilization ...... 114

3.7.2 Comparison to the State of the Art ...... 116

3.7.3 In-vivo Results ...... 116

3.8 Conclusion ...... 118

4 64-channel Rail-to-Rail-Input Inductively-Powered Dual-Radio Closed-Loop Neurostimulator 120

4.1 Introduction ...... 120

4.2 Motivation ...... 123

4.3 Rail-to-Rail-Input Signal Aquisition ...... 124

4.3.1 Architecture Selection ...... 124

4.3.2 Quadrature Output ...... 126

4.3.3 Input Dynamic Range ...... 127

4.3.4 Differential Recording ...... 127

4.4 VLSI Circuit Implementation ...... 128

4.4.1 Neural Front-End ...... 128

4.4.2 Noise Analysis ...... 130

4.4.3 Closed-Loop Neurostimulation ...... 137 XI

4.4.4 In-Channel Multiplication ...... 139

4.4.5 Dual-Input-Mode Operation ...... 140

4.5 System VLSI Architecture ...... 143

4.5.1 Tone-Selection Filter ...... 143

4.5.2 Seizure Detection and Closed-Loop Stimulation ...... 144

4.6 Experimental Results ...... 145

4.6.1 Mixed-Signal Front-End ...... 147

4.6.2 Mixed-Signal FIR Filter and Digital Backend ...... 147

4.6.3 Wireless Radio, and Inductive Powering ...... 151

4.7 In Vivo Experiments ...... 152

4.7.1 In-vivo Early Seizure Detection and Control ...... 152

4.7.2 Ofﬂine Early Seizure Detection in Humans ...... 154

4.8 Discussion ...... 156

4.8.1 Resource Utilization ...... 156

4.8.2 Area and Power Scalability ...... 157

4.8.3 Comparison to the State of the Art ...... 157

4.9 Conclusion ...... 160

5 Power-Adaptive High-Voltage-Compliance Electrical and Optical Neurostim- ulators 162

5.1 Inductively Powered Arbitrary-Waveform Adaptive-Supply Electro-Optical Neurostimulator Mini-Board ...... 164

5.1.1 Introduction ...... 164

5.1.2 System Architecture ...... 165

5.1.3 Design Implementation ...... 167

5.1.4 Architecture of Digital System ...... 172

5.1.5 Electrode Design ...... 173 XII

5.1.6 Electrical Measurement Result ...... 175

5.1.7 In Vivo Experimental Results ...... 179

5.1.8 Conclusion ...... 182

5.2 A Battery-less Implantable High-VoltageArbitrary-Waveform Dual-Mode Neurostimulator IC with Load-Aware Current-Optimized Power Supply 184

5.2.1 Introduction ...... 184

5.2.2 Motivation ...... 185

5.2.3 System VLSI Architecture ...... 186

5.2.4 VLSI Circuit Implementation ...... 188

5.2.5 Experimental Results ...... 194

5.2.6 Discussion ...... 201

5.2.7 Conclusion ...... 204

6 Conclusions and Future Work 206

6.1 Contributions and Relevant Publications ...... 206

6.2 Future Work ...... 211

6.2.1 Improvements to SoCs ...... 211

6.2.2 Future In-Vivo Experiments ...... 212

A Supplementary Hardware Documentation 213

B Control Signals 216

C Sample Verilog codes 218

C.1 Sample code for the HV stimulator IC ...... 218

C.2 Sample code for the closed-loop neurostimulator IC ...... 220

C.3 Sample code for programming on-board DAC ...... 244 XIII

D MATLAB codes 247 D.1 MATLAB code for playing ofﬂine data ...... 247 D.2 Reading from USB controller ...... 248 XIV

List of Tables

1.1 State-of-the-art stand-alone neural recording and/or stimulation implantable devices .8

1.2 State-of-the-art commercial neural recording and/or stimulation systems ...... 13

1.3 State-of-the-art neural recording and/or stimulation SoCs ...... 23 1.4 State-of-the-art neurostimulator SoCs ...... 29 1.5 Summary of chapters ...... 40

2.1 State-of-the-art miniaturized neural recording and/or stimulation SoC-based systems .55 2.2 Summary of sensory methods for sleep stage monitoring ...... 62 2.3 Comparison with the existing software-based sleep classiﬁcation methods 75 2.4 Comparison with hardware-based sleep classiﬁcation devices ...... 82

3.1 Summary of the experimental results ...... 115

3.2 State-of-the-art neural recording and/or stimulation SoCs ...... 119

4.1 Comparison of Different Implementations for 64 64-tap FIR ﬁlters. . . . 144

4.2 Summary of the experimental results ...... 155

4.3 State-of-the-art neural recording and/or stimulation SoCs ...... 161

5.1 State-of-the-art neurostimulator SoCs ...... 205 XV

List of Figures

1.1 Block diagram of a wireless closed-loop neurostimulator. An envisioned implanting conﬁguration is also depicted...... 2

1.2 Simpliﬁed block diagram of the presented high-voltage miniaturized neurostimulator. An envisioned implanting conﬁguration is also depicted. 6

1.3 Recording, stimulation and inductive powering modules of the Triangle Biosystems implant...... 10

1.4 Medtronic’s Activa RC open-loop battery-powered neurostimulator. . . 10

1.5 St Jude brio open-loop battery-powered neurostimulator...... 11

1.6 Neuropace’s RNS responsive neurostimulator...... 12

1.7 Models of probe impedance. (a) For many analyses, the impedance of the signal probe can be modeled as a simple capacitor. (b) A more detailed model with components that are found by curve ﬁtting. (c) The most detailed model that is mostly used in controlled electrochemical experiments...... 14

1.8 Electrode impedance as a function of frequency for 1 cm2 Pt, Pt black, and TiN electrode materials [43] ...... 15

1.9 (a) Conventional ac-coupled, (b-d) analog-assisted DC-coupled, and (e- g) digitally-assisted DC-coupled neural ampliﬁers...... 18 XVI

1.10 Envisioned implantation conﬁguration of the wireless electro-optical neurostimulator and its three main components. Illustration done by M. T. Salam...... 31

1.11 Light-triggered ictal activity in an epileptic VGAT-ChR2 mice [111]. . . 33

1.12 Cyclic occurrences of slow wave sleep (SWS) and rapid eye movement (REM) sleep during a typical 9 hour sleep cycle...... 33

1.13 Thesis organization outline. All credits for collaborative efforts are given in section 1.6. and throughout this thesis and in all relevant ﬁgure captions...... 37

2.1 Block diagram of the wireless closed-loop neurostimulator microsystem implanted on a rat’s brain...... 43

2.2 (a) Simpliﬁed block diagram of the implantable inductively-powered closed-loop neurostimulator, (b) different components of the multi-PCB microsystem. (Wireless communication board and inductive coil were designed by N. Soltani. The inductive ﬂoor was designed by M. Aliroteh.) 44

2.3 Neural recording/stimulation mini-PCB (a) top and (b) bottom view. (c) Top view of the board showing the bond wires that connect the SoC’s pads to the pads on the board. (d) The micrograph of the neurostimulator SoC designed by K. Abdelhalim, ﬁrst reported in [2]...... 47

2.4 Experimentally-measured frequency spectrum of the recording front- end (top), the input-referred noise (middle), and spectrum of the FSK transmitter (bottom)...... 48

2.5 Experimentally measured results: (a) an example of an early seizure detection in the non-treatment group, and (b) an example of a seizure abortion in the treatment group of rats. (Animal experiments were done with the assistance of M.T. Salam.) ...... 54 XVII

2.6 Electronic sensors used for various methods of sleep stage classiﬁcation. 59

2.7 (a) Placement of different head sensors used for polysomnography (PSG). (b) Approximate average signal power in the δ (cortex) and θ (hippocampus) EEG bands, and the EMG band during different sleep stages. 61

2.8 A simpliﬁed block diagram of the VLSI (very-large-scale integration) sleep stage classiﬁer with an envisioned closed-loop neurostimulator for REM-sleep suppression...... 66

2.9 Algorithm A: Signal flow chart of the first sleep-stage classification algorithm originally reported in [152]...... 68

2.10 Algorithm B: Signal ﬂow chart of the second sleep-stage classiﬁcation algorithm originally reported in [154]...... 68

2.11 Algorithm C (proposed): Signal ﬂow chart of the sleep-stage classiﬁ- cation algorithm proposed here implemented in MATLAB. (Algorithm implementation and testing was done by A. Chemparathy)...... 69

2.12 A 15-minute sample simulation results of the three classiﬁcation algorithms implemented in MATLAB, with their corresponding average error compared to the hypnogram. Simulation results were acquired with A. Chemparathy’s assistance...... 73

2.13 Simpliﬁed hardware implementation of the small-scale VLSI-based sleep- stage classiﬁer...... 76

2.14 FPGA VLSI architecture implementation of the presented sleep-stage classiﬁcation algorithm. FPGA implementation and optimization were done with the assistance of A. Chemparathy and P. Li, respectively. . . 78

2.15 Effect of the averaging window size on the sensitivity, speciﬁcity and accuracy of the REM sleep detection...... 79 XVIII

2.16 Sample simulation results of the presented classiﬁcation algorithm implemented on an ACTEL FPGA, with the corresponding average error when compared to the hypnogram. Measurement results were acquired with A. Chemparathy’s assistance...... 80

3.1 A simpliﬁed functional diagram of the presented neurostimulator SoC and peripheral blocks...... 85

3.2 Two types of input DC offset removal circuits: (a) AC-coupled closed- loop architecture and (b) DC-coupled open-loop architecture...... 87

3.3 Simpliﬁed block diagram of the presented open-loop DC-coupled front- end with digital feedback and gain calibration. (The ﬁrst version of this front-end is presented in [48]) ...... 90

3.4 Simpliﬁed circuit diagram of the chopper-stabilized neural recording front-end [48], with digitally-assisted offset cancellation and digital gain-mismatch calibration (The ﬁrst version of this front-end is presented in [48]) ...... 92

3.5 Simpliﬁed block diagram of the multiplying ADC originally reported in [2], utilized for gain mismatch calibration (Q is quantization noise). . 95

3.6 Circuit schematic of the UWB transmitters with a tunable bandwidth originally reported in [166]. CTL controls the output pulse bandwidth by controlling the delay of each inverter cell...... 96

3.7 Simpliﬁed block diagram of the FSK transmitter operating at 916.4 MHz, originally reported in [13]...... 97

3.8 Simpliﬁed block diagram of the inductive powering system, and the command receiver, ﬁrst reported in [2]...... 99

3.9 Micrograph of the SoC with major blocks labeled...... 100

3.10 Floor plan of the neural recording/stimulation channel...... 100 XIX

3.11 Experimentally measured results for the analog front-end: (a) transfer characteristics spectrum of the recording front-end with digitally- adjustable high-pass pole, (b) power spectral density of the ADC with 130 Hz input at full scale, and (c) input-referred noise with and without chopper-stabilization...... 102

3.12 Experimentally measured (a) analog front-end CMRR and PSRR vs input DC offset, and (b) input-referred noise (integrated from 1 Hz to 1 kHz) vs input DC offset...... 103

3.13 Experimentally measured (a) voltage gain values for several channels before and after gain-mismatch calibration, and (b) histogram of gain value distribution before and after calibration...... 104

3.14 Experimentally measured (a) output spectrum of the pulse for the ﬁrst UWB transmitter (BAND1: 3.1-10.6 GHz), and (b) an example of a transmitted pulse train. The experimental measurements were performed by N. Soltani...... 105

3.15 Experimentally measured (a) output spectrum of the pulse for the second UWB transmitter(BAND2: <1 GHz), and (b) an example of a transmitted pulse train. The experimental measurements were performed by N. Soltani...... 106

3.16 Experimentally measured (a) spectrum of the FSK transmitter, and (b) an example of transmitted and received Manchester-encoded data at 1.2 Mbps using FSK modulation...... 106

3.17 Experimentally measured results for inductive link: (a) power transfer efﬁciency, and (b) output power versus magnetic ﬁeld. The experimental measurements were performed by N. Soltani...... 108 XX

3.18 Experimentally measured seizure detection and control results: (a) an example of seizure detection for the non-treatment group of rats, and (b) an example of a seizure abortion for the treatment group of rats. (Animal experiments were done with the assistance of M. T. Salam). . . 110

3.19 An example of ofﬂine early seizure detection in a human patient. Hu- man data were provided by M. T. Salam...... 112

3.20 (a) Statistical analysis for the in-vivo experiments. (b) Seizure detection sensitivity, speciﬁcity and seizure reduction rate of the epileptic rats in in-vivo experiments. Statistical analysis was done by M. T. Salam. . . . 113

3.21 Power breakdown of the integrated circuit operating in two modes: (a) with the UWB transmitters, and (b) with the FSK transmitter. (c) Area breakdown of the IC...... 117

4.1 (a) Phase synchrony index in different brain regions before, during and after an epileptic seizure [163]. (b) Block diagram of a wireless closed- loop neurostimulator. An envisioned implanting conﬁguration is also depicted...... 121

4.2 Incremental evolution of the block diagram of Δ2Σ-based neural recording channel with quadrature outputs and in-channel mixed-mode analog- digital multiplier, implemented using a current-mode multiplying DAC (IMDAC)...... 125

4.3 64 differential Δ2Σ-based neural recording channels...... 128

4.4 Simpliﬁed circuit diagram of the Δ2Σ-based neural recording front- end with correlated double-sampling, quadrature output and in-channel mixed-mode multiplication...... 129 XXI

4.5 Oversampling ratio versus the electrode impedance for (a) ECoG, and

(b) EEG bandwidth. The green area shows the OSR and RELEC values that satisfy both noise and input impedance requirements...... 135

4.6 Electrode impedance as a function of frequency for 1 mm2 Pt, Pt black, and TiN electrode materials [43] ...... 136

4.7 Time-multiplexed sampling of signal and reference electrodes for different channels...... 137

4.8 Circuit schematic of 8-bit current-DAC used for current-mode stimulation as well as in-channel multiplication (all the transistors are thick oxide)...... 138

4.9 Circuit schematic of the biasing circuit for the 8-bit current DAC (all the transistors are thick oxide)...... 138

4.10 (a) Simpliﬁed z-domain block diagram of the recording front-end with in-channel multiplier. (b) Transposed-form 64 tap FIR ﬁlter implemented using in-channel analog-digital multipliers...... 139

4.11 (a) Simpliﬁed block diagram of the presented dual-mode voltage-current recording neural ADC. (b) The neural ADC, when operating in voltage- recording mode. (c) The neural ADC, when operating in current-recording mode...... 141

4.12 A simpliﬁed functional diagram of the presented neurostimulator SoC and peripheral blocks...... 142

4.13 (a) Micrograph of the SoC with major blocks labeled. (b) Floor plan of the neural recording/stimulation channel...... 146 XXII

4.14 Experimentally measured results for the neurostimulator channel: (a) power spectral density of the neural ADC with 130 Hz input at full scale, (b) input-referred noise with and without correlated double sampling. (c) Neural stimulating current into a 1kΩ load for different pulse shapes and duty cycles...... 148

4.15 Experimentally measured neural front-end CMRR and PSRR vs input DC offset...... 148

4.16 Experimental test setup for CMRR measurements...... 149

4.17 (a) Frequency responses of the programmable FIR ﬁlter for different center frequencies, (b) An example of the FIR ﬁlter performance for a two-tone input (8Hz and 40Hz) and the FIR being programmed as a HPF with a pole at 20Hz...... 149

4.18 Experimentally measured (a) input multi-tone sinulsoidal signals (b) reconstructed output of the FIR band-pass ﬁlter programmed at 200Hz for both in-phase and quadrature signals, (c) quadrature output phase error with reference to ideal 90 degrees, (d) 8 bit phase output of the on-chip processor...... 150

4.19 Experimentally measured output spectrum of the pulse for the (a) delay- based UWB transmitter, and (b) VCO-based UWB transmitters. The experimental measurements were performed by N. Soltani...... 151

4.20 Experimentally measured seizure detection and control results: (a) an example of seizure detection for the ﬁrst experiment (no stimulation), and (b) an example of a seizure abortion for second experiment (detection+SoC- triggered stimulation). Animal experiments are done with the assistance of M. T. Salam ...... 153 XXIII

4.21 An example of ofﬂine early seizure detection in a human patient. Hu- man data were provided by M. T. Salam...... 156

4.22 Power breakdown of the integrated circuit operating in two modes: (a) with the delay-based UWB transmitter, and (b) with the VCO-based UWB transmitter. (c) Area breakdown of the IC...... 158

4.23 (a) Channel power scalability with the input signal frequency bandwidth, (b) Comparison between conventional ac-coupled and presented Δ2Σ-based channel area scalability with CMOS technology node. . . . 159

5.1 Simplified block diagram and physical view of the inductively-powered electro-optical stimulating system. The focus of this section of the chapter is on the high-voltage electro-optical neurostimulator mini-board. The stimulator board design, firmware development, and electrical testing is done with the assistance of F. Chen and B. Vatankhah. Wireless communication board and inductive coil were designed by N. Soltani. The inductive floor was designed by M. Aliroteh...... 166

5.2 Simpliﬁed block diagram of the power-adaptive high-voltage electro- optical stimulator board. The stimulator board design, ﬁrmware development, and electrical testing is done with the assistance of F. Chen and B. Vatankhah...... 168

5.3 Block-level architecture of the digital system implemented on the FPGA. 172

5.4 ECoG grid: (a) Layers of ECoG (not to scale), (b) fabricated ECoG electrode array, and (c) LEDs assembled within the dual-layer ECoG electrode array (opcog) and blue light passing through the opcog from LED 1. Electrode design and fabrication is done by M. T. Salam and Ch. Lucasius...... 174 XXIV

5.5 Four experimentally-measured arbitrary waveforms generated simultaneously by the neurostimulator for an nominal 1kΩ load...... 175

5.6 Experimentally-measured voltage waveforms of the adaptive supply and reference voltage. The system keeps the supply voltage at the optimum value for a 2mA stimulation current while load impedance varies. . . . 176

5.7 Comparing the power consumption of the system with adaptive supply to the case with the ﬁxed supply, for different electrode impedances. . . 176

5.8 Experimentally-measured (a) stimulation current, and (b) anodic and cathodic current amplitudes, for different values of the digitally-controlled potentiometer...... 177

5.9 (a) Microelectrode chronic implantation and (2) placement of LEDs assembled within a ﬂexible ECoG electrode array (opcog) through a craniotomy on the cortex (The procedure is done by Dr. M. Tariqus Salam). 178

5.10 Electrical stimulation of the hippocampus and icEEG recordings in the hippocampus, cortex and brainstem. The animal experiments are done with the assistance of M. T. Salam and F. Chen...... 180

5.11 A brief (30 ms) optical stimulation using LED1 and spatiotemporal propagation of neuronal excitation in a ChR2-expressing mouse. The animal experiments are done with the assistance of M. T. Salam and F. Chen...... 181

5.12 Four channel recordings of brain neural activity before, during and after 5s optogenetic stimulation in an epileptic animal, illustrating post- stimulation LVF ictal brain activity...... 182

5.13 Four channel recordings of brain neural activity before, during and after 20s optogenetic stimulation in an epileptic animal, illustrating post- stimulation LVF ictal brain activity...... 183 XXV

5.14 Four channel recordings of brain neural activity before, during and after 20s optogenetic stimulation in a control animal...... 183

5.15 Simpliﬁed block diagram of the presented high-voltage miniaturized neurostimulator. An envisioned implanting conﬁguration is also depicted.186

5.16 Block diagram of the miniaturized neurostimulator SoC. The HV neurostimulator IC is shown on the right and the block diagram of inductive power and data receiver board is shown on the left...... 187

5.17 Simpliﬁed circuit schematic of the load- and current-efﬁcient neurostimulator channels with the in-channel and backend digital controller, and switched-capacitor voltage divider. The chip design and layout is done with the assistance of Y. Hu and Ch. Liu, respectively...... 189

5.18 Simpliﬁed circuit schematic of the rail-to-rail opamp...... 190

5.19 Circuit schematic of the rail-to-rail clocked comparator...... 191

5.20 Circuit schematic of tri-stage logice level shifter connecting high voltage blocks to low-voltage digital controller...... 191

5.21 Circuit schematic of 8-bit current-DAC used for reference current generation...... 192

5.22 State diagram of the digital FSM controller used for supply voltage control...... 193

5.23 Components of the wireless implantable high-voltage neurostimulator device. The HV stimulator board design is done with the assistance of G. Dutta. Wireless communication board and inductive coil were designed by N. Soltani. The inductive ﬂoor was designed by M. Aliroteh.195 XXVI

5.24 Top and bottom view of the neurostimulator mini-PCB with the IC being directly wire-bonded on it. The HV stimulator board design is done with the assistance of G. Dutta. The chip design and layout is done with the assistance of Y. Hu and Ch. Liu, respectively...... 196 5.25 (a) The chip micro graph with major blocks labeled. (b) Floor plan of a neurostimulation channel. The chip design and layout is done with the assistance of Y. Hu and Ch. Liu, respectively...... 197 5.26 Experimentally measured stimulation current amplitude versus load impedance for 4 VCC examples...... 198 5.27 Experimentally measured differential and integrated nonlinearity of the 8-bit current DAC used for reference stimulation current generation. . . 199 5.28 Experimentally measured waveforms generated by the 4 stimulation channels, optimized for a different purpose...... 199 5.29 Electrode voltage, digital controller outputs and supply voltage when load impedance is varied...... 200 5.30 Experimentally measured energy saving for different stimulation current amplitudes and three examples of load impedance...... 202 5.31 Power and area breakdown of the integrated circuit...... 203

A.1 The PCB designed for characterizing the SoC prototype described in chapter 3...... 214 A.2 The PCB designed for characterizing the SoC prototype described in chapter 4...... 214 XXVII

List of common acronyms

ADC Analog to Digital Converter BPF band-pass filter CMFB common-mode feedback CMRR common-mode rejection ratio DAC digital-to-analog converter ECG Electrocardiography EEG Electroencephalography EMG Electromyography FDA food and drug administration FPGA field-programmable gate array HDL hardware description language HPF high-pass filter IC integrated circuit LFP local field potentials LPF low-pass filter NEF noise efficiency factor OTA operational transconductance amplifier PSRR power supply rejection ratio RMS root mean square RNS responsive neurostimulator SAR successive approximation register SNR signal-to-noise ratio VNS vagus nerve stimulation UEA Utah electrode array VLSI very-large-scale integration 1

Chapter 1

Introduction

1.1 Objective

This work focuses on the development of a fully-wireless and battery-less implantable micro-system for monitoring and treatment of various neurological disorders. The development was done as a multi-step path where a multi-die and a single-die versions of such system were designed and validated prior to the implementation of the latest generation. All the presented SoCs are inductively powered and integrate multiple recording and stimulation channels, digital signal processing, and multi-band wireless transmitters. The latest-generation SoC features a new ΔΣ-based compact neural front-end that yields signiﬁcant channel- and system-level performance improvements. It also allows for expanding the applications of the SoC to record various physiological signals (e.g. EEG, EMG, ECG, EOG). Additionally, a hybrid stimulator SoC with high voltage compliance is implemented separately, and can be added to any of the recording systems to extend the use of the device to applications such as functional neural stimulation, cochlear and epiretinal implants and seizure induction. A simpliﬁed block diagram of the battery-less and wireless neurostimulator brain CHAPTER 1. INTRODUCTION 2

DIAGNOSTIC DATA EXTERNAL MODULES NEURO-MONITOR AND DATA RECEIVER

CLOSED-LOOP SCALP POWER NEURO-STIMULATOR SoC POWER/COMMAND

ELECTRODES TRANSMITTER ECoG & DEPTH ECoG CONFIGURATION COMMANDS IMPLANTED COIL & ECoG ANTENNA ELECTRODES SKULL BONE SCALP DURA DEPTH ELECTRODES

Figure 1.1: Block diagram of a wireless closed-loop neurostimulator. An envisioned implanting conﬁguration is also depicted. implant is shown in Figure 1.1. Depending on the application, the system interfaces with EEG, ECoG or optical electrodes for physiological signal recording and electrical/optogenetic stimulation. For animal experiments, the system is typically mounted on the head of a freely-moving rodent, and for human trials, it is envisioned to be fully implanted under the skin, in the skull bone. This thesis describes initially the design and validation of a modular multi-die wireless brain implant for intractable epilepsy and Alzheimer’s disease (Chapter 2). Next, a single chip that integrates all the functionalities of the multi-die system is presented (Chapter 3). The third prototype described is the latest generation of this SoC, with circuit and system innovations that enables new applications and a higher level of integration (Chapter 4). The last set of prototypes described in this thesis are two board- level and chip-level modules attachable to the main system, for high-voltage electrical current/voltage and optogenetic stimulation (Chapter 5). CHAPTER 1. INTRODUCTION 3

In this introductory chapter, Section 1.2 introduces implantable brain machine interfaces and reviews main system modules and their system-level design requirements. Section 1.3 reviews state-of-the-art academic and commercial large-form-factor devices designed to perform neurostimulation in animals or humans. Section 1.4 reviews the circuits and systems requirements for an integrated single-die wireless responsive neurostimulator, with a summary of the state-of-the-art SoCs. Section 1.5 discusses the same thing for different types of neurostimulators, with a summary of the state of the art. Lastly the thesis organization is provided in Section 1.6.

1.2 Implantable Brain Machine Interfaces

1.2.1 System Overview

The book “Neurological disorders: Public health challenges” published by WHO (World Health Organization), reports that there are one billion people worldwide affected by neurological disorders [1]. Today 65 million suffer from epilepsy and 27 million from Alzheimer’s and other dementias. There is a significant portion (up to 30%) of these patients who remain refractory to the currently-available pharmacological solutions and brain surgery [1]. Monitoring and treatment of neurological disorders using a microelectronic brain implant has been investigated as a promising alternative for patients who are refractory to current pharmacological solutions [2, 3, 5–9, 56]. Ideally this requires the implanted system to record neural activity at high spatial resolution, process recorded signals, and, in some cases, trigger responsive action to control an undesired neurological event. Recently several implementations have been reported for multi-site brain-activity monitoring [2, 3, 5–14, 56], some with signal processing and closed-loop neurostimulation [2,8,15]. These advances, alongside the growth in our understanding of the human CHAPTER 1. INTRODUCTION 4 brain makes such implants a promising treatment alternative for neurological disorders. A general block diagram of a wireless closed-loop neurostimulator brain implant is shown in Figure 1.1. The figure also shows an envisioned implantation configuration of the SoC (system on a chip) in the proximity of an animal brain where it is connected to an array of ECoG or depth electrodes. The system communicates diagnostic data to an external module (e.g., a computer) through a wireless link and receives power and configuration commands through an inductive link. To monitor high-spatial-resolution brain activity, the SoC must integrate many low-noise neural recording channels to collect data from a large population of neurons. The overall size and power consumption should be minimized to follow the safety guidelines [16, 17]. The vision of a fully-autonomous brain implant requires micro-systems that record neural signals at a high spatial resolution, process them in real-time, and efficiently modulate brain activity to avoid an undesired neurological outcome (e.g., a patholog- ical brain state such as an epileptic seizure). Although several implant designs that target such functionality have been reported both in academia [10,18–24] and commercially [25–33], chronic implantation constraints such as the ease of implantation and use, and long lifetime are often ignored, which prevents such systems from being used in long-term animal (e.g., rodent) studies and in clinics. A microsystem designed for long-term monitoring or treatment, must not only be good in brain neural signal recording, but also have a small form factor, be fully wireless and operate fully-autonomously.

1.2.2 System Design Requirements

Recording at high spatial resolution from a large section of the brain requires a large number of recording channels. Also to record both local field potentials (LFPs) and action potentials (APs), each of these channels must have a low-noise front-end that CHAPTER 1. INTRODUCTION 5 amplifies signals with amplitudes ranging from 10μV to 1mV and the bandwidth from sub-Hz to 10kHz [18]. To detect various neurological events, signal properties of each recording channel such as amplitude, power and phase as well as inter-channel information such as phase synchrony must be extracted. For a timely and effective responsive neuromodulation feedback, both power dissipation and stimulation latency must be minimized, which emphasizes the necessity of an on-chip implementation of such a signal processing unit. An implantable/wearable microsystem such as the one shown in Figure 1.1, must be able to communicate recorded data and signal processing results wirelessly and receive its energy from a battery or through magnetic induction. Using a battery that is suitable for chronic experiments (i.e., which can last more than a few months) increases the system weight and size significantly [10,21]. Also if the system is implanted, a routine follow-up surgery is required once the battery is discharged [45]. On the other hand, inductive powering imposes no limitation on the system lifetime and can either be used to directly provide energy to the system or to recharge a smaller battery. Both of the wireless links for data and power must have a reasonable range (>10 cm) to ensure the ease of use. Also for the inductive link, the specific absorption rate (SAR) must be kept below the safety-permitted limit [16]. To realize a stand-alone fully-implantable system, some additional steps must be taken compared to the case where the SoC is mounted on a large test board. The chip must be directly bonded to a miniaturized PCB that also hosts all the necessary peripheral circuits as well as the digital chip controller implemented on an FPGA or microcontroller. Since everything must fit within a miniaturized implant, antennas must be replaced with planar designs implemented on the board. CHAPTER 1. INTRODUCTION 6

DIAGNOSTIC DATA EXTERNAL MODULES NEURO-MONITOR AND DATA RECEIVER CLOSED-LOOP NEUROSTIMULATOR POWER POWER/COMMAND DEVICE

ELECTRODES TRANSMITTER ECoG & DEPTH ECoG CONFIGURATION COMMANDS RX COIL RECORDING/ STIMULATION SITES

Figure 1.2: Simpliﬁed block diagram of the presented high-voltage miniaturized neurostimulator. An envisioned implanting conﬁguration is also depicted.

1.3 Large Form-Factor Neurostimulators

1.3.1 Academic Designs

Prior to human trials, brain machine interfaces are tested in extensive animal experiments, typically done in rodents or human primates. Due to the smaller skull size in animals, the devices are normally mounted on the animal’s head or back, and only electrodes are implanted. To conduct freely-moving animal experiments, it is desired that the device has wireless data connectivity and is powered by a battery or inductively. As typical mounting configuration of a large form-factor board-level device is shown in Figure 1.2. The figure also depicts the simplified block diagram of a generic closed- loop wireless device. Recently reported wearable/implantable microsystem designs address some of the challenges described in the previous section. In [21] a 32-channel closed-loop system is reported with promising in vivo experimental results. However, the system is CHAPTER 1. INTRODUCTION 7 battery-powered and lacks signal processing and stimulation units required for detection and control of neurological events. In [22] and [10] wearable closed-loop systems have been reported with in-vivo experimental results. The design in [22] has only four recording/stimulation channels and that in [10] has a low-data-rate wireless link, and both systems rely on a battery as the source of energy. More recently inductively-powered implantable systems have been reported [23, 24]. In [23] the authors present an implantable micro-system with a very small form factor and 64 recording channels that enable high-spatial-resolution monitoring. How- ever it does not have a signal processing unit or responsive neurostimulation. In [24], the system is equipped with both a signal processing unit and neurostimulation, but only has 8 recording/stimulation channels. Moreover, inductive links used in [23] and [24] for power delivery have 16mm and 6mm range, respectively, which requires the power transmitter to be located very close to the implant. This makes a freely-moving animal experiment impossible and poses challenges for convenient human use. Table 1.1 compares the most recent wireless brain neural interfaces reported in the literature. This table only includes the implantable microsystems that are reported as a stand-alone device that includes all the peripheral components (e.g. PCBs, FPGAs, antenna, receiver coil, etc.).

1.3.2 Commercially-Available Neurostimulators

In the past few years, commercial neurostimulator devices have become available for monitoring and treatment of neurological disorders such as Epilepsy and Parkinsons disease. These devices can be categorized into three main groups of Recording (monitoring), open loop (periodic stimulation) and closed loop (stimulation upon detection of a neural event) stimulators. For the open-loop systems, the physicians program the device based on the severity of a patients disease, to determine how often and how intense CHAPTER 1. INTRODUCTION 8 A 2.5* μ × 10 Magnitude < 2.5 & [24] TBIOCAS 2015 Chen × Closed-loop Neurostimulation [23] JSSC 2015 Rabaey Nearal Monitoring stim. 1.5 N/R 3 A - 82.5-229 μ & × 2.2 [10] × TBIOCAS 2013 Genov Rat ECoG Recording 5.1 3 × 20m N/R N/R 6 mm 3.8 > × [21] TBIOCAS 2010 Meng Nearal Monitoring 0.6 3.8 × A - 20-250 μ 1.3 × [22] TBIOCAS 2011 Mohseni State-of-the-art stand-alone neural recording and/or stimulation implantable devices Intracortical Microstimulation Table 1.1: ) 3.6 3 cm of Stim. Channels 4 0 64 0 8 Closed-loop DetectionMethod# Current Range YESBattery Lifetime (hr)Receiver Coil TypeCoil Spike-Discriminator SeparationModulationFrequency 125 - -Range 24 - - - FSK 33 - 433MHz - 1m - 3.9GHz FSK 10 NO - - 2.4GHz ZigBee - Phase YES - 300 MHz 1-layer flex OOK 1.6cm 1-layer flex 10 MHz - ASK 6 mm Size ( Specifications Targeted Application Power Diss. (mW)SIGNAL PROCESSINGNEURAL STIMULATION 0.42 YESENERGY SOURCE YES 142WIRELESS COMM. NO Battery NOIN-VIVO RESULTS N/R YES NO Battery YES YES 0.225 Battery YES NO Magnetic Induction NO YES Magnetic Induction YES YES YES YES YES YES YES YES Weight (gr)Number of Rec. Channels 4 1.7 32 N/R 256 12 64 - 8 20 *: Estimated , -: Not Applicable , N/R: Not Reported CHAPTER 1. INTRODUCTION 9 these pulses need to be. On the other hand, the more recent technology which is the responsive or closed loop, only delivers the impulses when it detect abnormal activity in the brain. This technique is more efficient and subjects the patient to less stimulations. Below is a list of some of these products currently available. A division of Harvard Bioscience, Triangle BioSystems, has developed separate devices for neural recording and stimulation shown in Figure 1.3. Their latest wireless recording system (Size: 32 × 25 × 13 mm3, weight: 7.5 gr) features neural recording up to 128 channels from rodents, with a bandwidth of 0.8 to 7000 Hz [25]. The recording systems up to 64 channels can be powered inductively using a wireless powering module (Size: 40.6 × 33.6 × 12.4 mm3, weight: 5.7 gr) that while placed within a resonant magnetic field, keeps the headstage’s internal battery perpetually charged [26]. The recorded data are then transmitted through a wireless link to a USB dongle in a 4 meter range [25]. An open-loop stimulation module (Size: 19.6 × 17.8 × 10.5 mm3, weight: 3.6 gr) is also designed that has two channels, programmed independently, and deliver pulses of up to 1 mA with 100us pulse width. The stimulation can be controlled with a software interface that communicates with the board using a USB transceiver [27]. Medtronic has a series of open loop brain stimulators that target diseases such as essential tremor and Parkinson’s disease. For instance, the Activa RC shown in Figure 1.4 is a 40 gram device (Size: 54 × 54 × 9mm3 ), typically implanted near the clavicle, and connected to leads implanted in the brain. After being programmed, it delivers controlled electrical pulses to precisely targeted areas of the brain [28]. This deep brain stimulation is done both in current and voltage mode, through up to 4 electrodes. The device is battery powered and the battery lasts for approximately 9 years depending on the frequency of the stimulations. St Jude medical has also introduced the Brio, shown in Figure 1.5 (Size: 45 × 53 × 10 mm3, weight: 29 gr ), with an advanced rechargeable technology that functions for at CHAPTER 1. INTRODUCTION 10

RECORDING MODULE (5-128 CHANNELS)

INDUCTIVE POWERING

STIMULATION MODULE (2 CHANNELS) OR

+/- 500μA MAXIMUM OUTPUT CURRENT 50μS MINIMUM PULSE WIDTH

Figure 1.3: Recording, stimulation and inductive powering modules of the Triangle Biosystems implant.

Figure 1.4: Medtronic’s Activa RC open-loop battery-powered neurostimulator. CHAPTER 1. INTRODUCTION 11

Figure 1.5: St Jude brio open-loop battery-powered neurostimulator. least 10 years [29]. The biggest difference between this open loop neurostimulator for Parkinson’s disease and the others is the use of constant current pulse delivery [30]. It supports 2 leads and 16 contacts, and has three options for the current path: Monopolar, Bipolar and Multipolar. It is implanted under the skin of the upper chest and sends the impulses through wire leads that attach it to electrodes in the brain. Cyberonics is another open loop stimulator that uses the Vagus Nerve Stimulation technique instead of Deep Brain Stimulation. It consists of a 14 cm3 generator device that weights 25 grams. This device is implanted in the left chest area and a thin wire, or lead, connects it to the left vagus nerve in the neck. The device delivers mild pulsed signals of bipolar current from 0 to 3.5 mA to the nerve, which then activates various areas of the brain [31]. By programming the device, the physicians can determine how frequently and with what intensity these pulses need to be sent. The Neuropace RNS neurostimulator is a responsive neurostimulator designed for epilepsy treatment and is shown in Figure 1.6. This device is 28 × 60 × 7.7 mm3 and weighs about 17 grams and is powered by a battery with a longevity around 2 to 3.5 years [32]. It is implanted in the brain and delivers stimulation pulses when detecting brain activities that might lead to a seizure [33]. These current regulated biphasic pulses with 40-1000us pulse width are delivered to 8 electrodes [32]. The recorded brain data are transferred wirelessly or through the internet to a remote monitor and a wand, that are used by the patient or physician. The physicians use the programmer to program CHAPTER 1. INTRODUCTION 12

Figure 1.6: Neuropace’s RNS responsive neurostimulator. the stimulator and the wand to monitor patient brain activity. Table 1.2 compares the most recent commercially-available implantable devices for neural monitoring and stimulation.

1.4 Integrated Circuits for Wireless Responsive Neurostim-

ulators

1.4.1 Electrodes Probe Characteristics Three models used for the small signal impedance of the probes are presented in Fig- ure 1.7. For many cases a simple capacitor shown in Figure 1.7(a) is adequate to describe the probe interface. In these cases, there is no need for a resistive element as it contributes less than 10 percent in the total impedance and the system noise. Despite being a simple model, the capacitance varies significantly (from 2:1 to as large as 10:1) due to manufacturing variations, even when the physical dimensions are precisely controlled [34–37]. A more detailed model is presented in Figure 1.7(b). The model is empirical (with a basis in chemistry) and the parameters are found by curve fitting [38–40]. The impedance of the constant phase element (CPE) in Figure 1.7(b) is always in a way CHAPTER 1. INTRODUCTION 13 7.7 × 60 × Responsive Neurostimulator Epilepsy Open-loop Stimulator Parkinson’s Disease and Essential Tremor 10 14000 28 × 53 × Parkinson’s DiseaseEssential and Tremor Open-loop Stimulator 945 × 54 × Disease and Essential Tremor Open-loop Stimulator Table 1.2: Neural EEG Monitoring 25.4* N/R 54 × 33 State-of-the-art commercial neural recording and/or stimulation systems × and Stimulation )40 3 Targeted AplicationSize Rodent (mm Experiment Epilepsy Parkinson’s SpecificationDevice Type TBSI Neural Monitoring Neurovista Medtronics St Jude Cyberonics NeuroPace Weigth (grams)Stimulation SiteNo. of Stim. ChannelsPower SourceBattery Longevity (years)Wireless Data 13.2 2 DBS N/A Inductive Yes N/R VNS N/R N/A Battery 45 DBS Battery up to 4 9 Yes Battery DBS 10 29 Yes 2 Battery VNS 5-10 25 No Battery N/R DBS 2-3.5 16-18 No 8 Yes *: for a wirelessly poweredN/A: 64 Not channel Applicable recording with noN/R: stimulation. Not Reported CHAPTER 1. INTRODUCTION 14

RDC

RLF RCT

CP RHF RHF W CDL

CPE

(a) (b) (c)

Figure 1.7: Models of probe impedance. (a) For many analyses, the impedance of the signal probe can be modeled as a simple capacitor. (b) A more detailed model with components that are found by curve fitting. (c) The most detailed model that is mostly used in controlled electrochemical experiments. that the magnitude of the real and imaginary parts maintain a constant ratio over all the frequencies [41]. The resistor RHF models the high frequency impedance of the entire path from the tissue to the amplifier input, including interconnect resistance, solution resistance and time-dependent tissue resistance. RLF models the low-frequency impedance and is normally ignored in the amplifier design due to its value. Figure 1.7(c) shows the most complex reported model that is most often used in controlled electrochemical experiments rather than uncontrolled in vivo experiments. It consists of charge transfer resistance (RCT), double layer capacitance (CDL), RHF, Warburg element (W), and RDC (DC resistance). In contrast with the components of Figure 1.7(b) model, these resistors and capacitors are well modeled and supported by theory [42]. As mentioned, models of Figure 1.7(b) and (c) are unnecessarily complex for the design of most amplifiers for extracellular EEG recording. Figure 1.8 shows the impedance of three electrodes made with different materials of Pt, Pt black and TiN, as a function of frequency. As shown, for the EEG signals frequency range, the impedance can be modeled by a single capacitive component. As a result, in this work, unless stated otherwise, the simple capacitor model illustrated in Figure 1.7(a) is considered. CHAPTER 1. INTRODUCTION 15

7 6 Bright Pt Pt Black 5 TiN 4 3 2 Log |Z| (Ohms) 1 0 -2 0 2 4 Log(f) (Hz)

Figure 1.8: Electrode impedance as a function of frequency for 1 cm2 Pt, Pt black, and TiN electrode materials [43]

Electrode-Noise/Ampliﬁer-ZIN Trade-Off

An electrode with a typical impedance of 1MΩ at the frequency of interest generates a thermal noise of VRMS = 4kTRΔf, (1.1) where k is the Boltzman constant, T is the body temperature, and Δf is the bandwidth of interest. For the typical EEG frequency bandwidth of 5kHz, this results in 9.3 μVrms. Including the background noise within the extra-cellular region will double this number to around 20 μVrms. The 1MΩ is the real value of the parallel combination of the constant phase element and the polarization resistance defined in the reference [43] of the thesis. The resistive part of this impedance is the main source of electrode noise. An example of typical values of capacitance and resistance for a 1000 μm2 probe are 200 pF and 0.2 MΩ at 1000 Hz and 290 pF and 1.4 MΩ at 100 Hz, respectively. If we decide to limit the noise contribution of the amplifier to 10 percent of this value, and considering the fact that noises from independent sources are added in a root-sum-square manner, this results in a 9.16 μVrms limit for the input referred noise CHAPTER 1. INTRODUCTION 16 of the amplifier. Another design decision in typically made for input impedance of the amplifiers. The lower limit of the amplifier input impedance is typically set to 10 times larger than the electrode impedance to avoid any considerable signal loss [44]. As a result, as the electrode impedance increases, higher input impedance is required for the amplifier, while its noise requirements are more relaxed due to the increase in the noise generated by the electrode itself. Another conclusion to be made is that decreasing the input-referred noise of the neural amplifier less than a certain value will only have a slight effect in the total system noise, while it could result in sacrificing other parameters such as power, area, or input impedance.

1.4.2 Recording Ampliﬁer

Challenges

Design of a compact low-noise and low-power front-end for recording small-amplitude neural signals (10μV-1mV) that have frequency content in sub-Hz to 5kHz [18] band creates various challenges. As mentioned the amplifier input impedance must be an order of magnitude larger than the electrode impedance, and its input referred noise power must be an order of magnitude smaller than the electrode’s contribution. In addition, flicker noise suppression/removal must be taken into consideration, especially when recording low-frequency (<20 Hz) EEG signals. The above specifications must be met while keeping power and area to the minimum and the amplifier’s gain and consequently channel’s effective number of bits to the maximum possible. The former is important when scaling the number of channels to a very high number, and the latter is important to allow for more accurate back-end signal processing. CHAPTER 1. INTRODUCTION 17

Input-Referred Noise

For the reported neural amplifiers in the literature, techniques such as large input device sizing [46], correlated double sampling [47], and chopping [48] are utilized to reduce the input-referred noise. Large input device sizing significantly limits the channel count. Correlated double sampling partially removes the low-frequency content of the signal at the input of the opamp which includes the offset and the flicker noise. On the other hand, chopper stabilization filters the flicker noise after up-modulating it to a higher frequency [14]. Despite being a very effective technique for flicker noise reduction, chopping has limitations in neural amplifiers. It has been shown that when chopping is applied to a conventional neural amplifier with AC-coupled inputs, it results in noise- multiplication and input impedance reduction [48]. This necessitates the use of large input capacitors and the addition of an impedance boosting loop [49]. To avoid this overhead, the chopping technique can alternatively be used either at the folding node of a folded-cascode amplifier [58] which does not remove the flicker noise of the input transistors, or with a DC-coupled amplifier [48].

DC Offset Removal

Removing DC offset at the input of the recording amplifier is another challenge in the design of neural interface front-ends. The offset is generated due to chemical reactions between brain cells and electrodes and can saturate the amplifier. The offset potential occurs between the working and reference electrode and is a function of chemical composition of the electrode-tissue interface. To avoid this issue, all the solutions suggested in the literature can fall within three methods: low DC gain [50–52], stabilization [53–56] and high-pass filtering. The first two methods are not investigated anymore due to their poor performance in offset removal. On the other hand, high pass filtering has been investigated in many forms as described next. CHAPTER 1. INTRODUCTION 18

R Vin -

OTA Vout +

C1 C2 REF + Vin- Vout+ R - OTA OTA - Vout- Vin+ + C1 C2 C (c) R Vin+ + Vin- - OTA Vout + (a) -

Vin + R OTA Vout C - (d)

C R D VIN+ w w OUT OTA LPF ADC (b) VIN- w, w DIGITAL Vin D DAC + OUT LPF D AMP ADC REF Vref

DAC Digital (f) LPF

(e) VREF D =A(V -V )+Q I OUT IN REF DAC OTA LPF ADC

VIN+VOFF

DIGITAL + D I =I I-DAC REF DAC OFF LPF

(g)

Figure 1.9: (a) Conventional ac-coupled, (b-d) analog-assisted DC-coupled, and (e-g) digitally- assisted DC-coupled neural ampliﬁers. CHAPTER 1. INTRODUCTION 19

High-Pass Filtering Conventionally this is done by adding ac-coupling capacitors between the electrode and the amplifier [2, 6–8, 11–13, 57]. A typical closed-loop ac-coupled neural front-end is shown in Figure 1.9(a). Closed-loop gain, and low- frequency high-pass pole of this circuit is set by C1/C2 and 1/(R·C2), respectively [59]. To prevent parasitic capacitances from causing significant mismatch and gain error, C2 is normally kept above a minimum value of around 200fF. As a result, to achieve both a low-frequency (<1 Hz) high-pass pole and a high voltage gain, C1 capacitors have to be larger than 10pF. Such large capacitance increases channel area significantly and is not scalable with CMOS technology. This negatively affects the channel area and consequently the area of such designs, both being critical constraints in multi-channel neuromonitoring applications. Recently, DC-coupled front-end amplifiers with an offset-removal feedback were proposed as a solution to the issues described above. In [60], an analog feedback loop is used to sense and cancel the DC offset, similar to what is shown in Figure 1.9(c). However, the opamp in the feedback increases the power consumption significantly and its open-loop gain variation results in a varying high-pass pole. Differential difference amplifier topology shown in Figure 1.9(d) is also utilized to remove the DC offset [61]. Despite being effective in DC offset removal, it can only be used for systems with a small number of channels as it requires use of large off-chip passive components in each channel to achieve the low-frequency high-pass pole. A fully-digital implementation of the feedback loop for offset cancellation causes very small additional area and power consumption and allows for adjusting the high- pass pole with high accuracy. A digital feedback implementation is reported in [3] that adds/removes parallel transistors to/from the input differential pair for the input DC offset correction (Figure 1.9(f)). Changing the number of parallel input transistors modifies the input device noise and leads to offset-dependent noise performance. Thus, CHAPTER 1. INTRODUCTION 20 the feedback implementation must be modified to achieve offset-independent noise performance. A typical digitally-assisted DC-coupled open-loop front-end is shown in Figure 1.9(e). For this circuit, the offset is compensated for by a digital feedback loop eliminating the bulky input capacitor. However, only DC offset of up to ±50mV is typically removed using examples of this method shown in Figure 1.9(f) [3] and (g) [48], which is only sufficient when the front-end input impedance is significantly smaller than the electrode impedance. Also the open-loop configuration with channel-to-channel gain variations is an important disadvantage of DC-coupled neural amplifiers. The change in the channel gain is normally due to supply voltage and process variations [3,48]. As a result, the signal amplitude and phase information of different channels cannot be directly compared to each other. Consequently, without channel-to-channel gain-mismatch removal, any multivariate signal processing done among different channels will have a significant error. To solve this issue, the gain of all channels must be set to a nominal value using a calibration block implemented with minimum power and silicon overhead. Due to the problems mentioned for ac-coupled (large area) and DC-coupled (gain mismatch and limited offset compensation) front-ends, a new front-end design is yet to be proposed that is able to remove rail-to-rail DC offset between recording electrodes, while minimizing input-referred noise and area, and maximizing gain and input impedance. In [43], it is shown that Open-circuit potentials in the hundreds of mV have been observed for platinum black microelectrodes in solution. Considering a DC impedance of microfabricated ECoG electrodes to be in the range of tens of MΩ to GΩ, and the input impedance of the amplifier being set to 1-10 MΩ, this offset is normally considered diminished at the input of the front-end amplifier. However, depending on the electrode impedance, the front-end could see any offset value from tens to hundreds of mV, which requires an offset removal loop with maximum possible range. CHAPTER 1. INTRODUCTION 21

1.4.3 Digital Backend

Neurological Event Detection

Following ampliﬁcation and digitizing, signal processing must be performed on the recorded signals to detect neurological disorders. The detection for most cases should be done within a few microseconds after an event occurrence, which emphasizes necessity of an on-chip signal processing unit. Several on-chip processors implemented in neural monitoring SoCs have been reported in which spectral information such as magnitude and energy in each band are extracted from recorded signals [62,63]. Depending on the application, various detection algorithms ranging from simple thresholding to advanced machine-learning-based methods [8,64] are applied to the extracted information to detect different neurological events. For an accurate detection, the signal processing unit is required to extract both magnitude and phase information of neural signals for each channel as well as variations of these parameters among different channels. This yields information on neural activity in each region of the brain along with correlated activities among different regions.

Responsive Neurostimulation

Responsive neuro-stimulation is done upon detection of a neurological event to modulate undesired brain activity. For effective neuro-modulation, many-site electrical stimulation triggered by the detection algorithm is required. For these stimulators, pulse amplitude, frequency and duty-cycle should be programmable for each channel independently to allow for versatile neuro-modulation. The neuro-stimulation is performed using various agents including electrical voltage, current and charge, and optogenetic stimulation. Different types of neuro-stimulators and related challenges are discussed CHAPTER 1. INTRODUCTION 22 in more details in Section 1.5.

1.4.4 Wireless Data and Power

A high-data-rate power-efficient wireless data transmitter is required for the SoC to communicate recorded neural information to a computer for display and/or further processing. Depending on the application, the receiver is typically located 1 cm to 10 m from the implant. The choice of a specific application determines what data rate is required for the wireless link. Some narrow-band transmitters are reported to transmit data to as far as a few meters [8, 13, 65]. However, they typically have high power consumption and a limited data-transfer rate of up to 2 Mbps. Recently, short-range (<1m) ultra-wideband (UWB) transmitters have been used, as they exhibit a much higher data rate while consuming less power [2, 66]. For a versatile wireless communication that covers a wide range of data rates and transmission distances for various applications, multiple transmitters with different data modulation schemes, transmission range and frequency of operation must be included in the design of the SoC. For a chronically-implantable system, power and configuration commands should also ideally be provided wirelessly. Conventional chronically-implanted batteries have the disadvantage of making the system heavy and bulky [10, 67]. An inductive powering system enables the use of a smaller rechargeable battery or in some cases removes the requirement for a battery altogether. The inductive link should have a reasonable range (on the order of centimeters) while keeping specific absorption rate (SAR) below the safety-permitted limit [68].

Table 1.3 summarizes state of the art single-die neural monitoring and/or neurostimulation SoCs.

CHAPTER 1. INTRODUCTION 23

Rabaey Recording

ISSCC’14 EEG

[65] Rat

1-layer ﬂex

n Control and

Wu Detection

JSSC’14 Seizure

[8] Epileptic

Wire-wound

Ghovanloo Monitoring

TBCAS’10 EEG

Rodent [5] 12 N/R 1.6

n Control and

Genov Detection

JSSC’13 Seizure

[2] Epileptic

Synchrony /Spectrum

Meng Recording

JSSC’12 EEG

Monkey [157]

Flynn

JSSC’10 Recording

[6] a EEG Rat

State-of-the-art neural recording and/or stimulation SoCs

Yuce

ISSCC’08 Recording

[66] EEG Snail

Table 1.3:

Yoo

JSSC’13 Detection

[9] Blink Eye A) - - 3-135 - 10-1200 - 30 - ) - - - - - 4.5 5.72 0.42 μ H) - - - - - 0.41 N/R N/R 2 μ ) 0.7 0.3 0.1 0.26 0.09 0.1 0.5 0.025 2 Vrms) 0.91 4.9 5.24 14 4.7 9.3 5.23 1.43 μ m) 0.18 0.35 0.35 0.13 0.13 0.5 0.18 0.065 μ of turns - - - - - 2 4 1 of Voltage Levels - - - - - N/R 3 2 of Rec. Channels 8 128 8 96 64 32 8 64 of Stim. Channels 0 0 64 0 64 0 1 0 Inductance ( # Type - - - - - 1-layer Size/Area(cm Coil Separation (cm) - - - - - Power EfﬁciencyFrequency (MHz)# ------N/R 13.56 N/R 13.56 300 N/R Gain (dB)Bandwidth (Hz)Noise ( 0.5-100 50-70 0.1-20k 57-60 16-5.3k 40 1-10k 56 1-5k 54-60 0.1- 8k 0.1-7k 68-78 1-250 59.3 46 Noise BW (Hz)# Chopper Count 0.5-100 8 N/R 0 1-8k 1-100 0 10-5k 0 1-10k 64 0.5-7k 0 1-500 0 0 Area (mm Closed-loopDetectionMethod # Current Range ( Receiver NO Coil SVM NO -Modulation NO*Frequency (Hz) - NO - - - YES 3.1-10.6G UWB Ampl/Phase NO - - - YES - Entropy - NO - 3.1-10.6G UWB 915M FSK 401M OOK 300M OOK Area (mm)Supply (V)Power Diss. (mW) N/R 25 1.8 6 65 3.3 0.09 2.7 1.8 6.5 12 1.2 1.4 12 1.2 7.05 16.4 3 2.8 13.47 1.8 0.225 5.76 0.5 Spec. Targeted Application Tech. ( NEURAL FRONT-END SIGNAL PROCESSING YESNEURAL STIMULATION NOWIRELESS POWER YES NO NO YESWIRELESS NO COMM. YES NOIN-VIVO RESULTS NO NO NO YES YES YES YES NO NO NO NO NO NO YES NO NO YES YES NO NO YES NO YES YES YES YES NO YES YES YES YES -: Not Applicable N/R: Not Reported *: Off-chip CHAPTER 1. INTRODUCTION 24

1.5 Electrical Current/Voltage and Optogenetic Stimu-

lation

1.5.1 Electrical High-Voltage Stimulators

As mentioned, electrical neurostimulation has been proved to be an effective drug alternative for a various range of applications. Today, there are FDA-approved cochlear and retinal neurostimulator implants [69, 70], deep brain stimulators for Parkinson’s disease [71], and Functional Neuromuscular Stimulation (FNS) that has been demonstrated effective for a variety of functions following spinal cord injury. These applications include restoration of hand grasp, standing, walking, hearing, bladder and bowel control and respiratory assistance [8, 72]. Electrical neurostimulation has also become a necessary component of brain-machine interface implants, turning neuro-monitoring devices into closed-loop responsive neurostimulators which are being established as an alternative treatment option for several neurological disorders [2, 73, 74]. Voltage-controlled stimulation (VCS) [178], current-controlled stimulation (CCS) [2, 15, 74] and switched-capacitor charge-base stimulation (SCS) [75] are the three existing methods to provide electrical stimulation to the body. VCS cannot control the amount of the injected charge during stimulation and could cause sub-optimal results and tissue damage. SCS has the disadvantage of limited control over the stimulation pulse shape. Current-based stimulators, on the other hand, have excellent control of charge injected into the tissue and can deliver a precisely-programmed current pulse shape. Despite their advantages, current-controlled stimulators typically suffer from poor power efficiency compared to VCS and SCS. This is mainly due to the supply voltage of these stimulators that is set to accommodate a sufficient headroom voltage for the worst-case scenario, which is stimulating with the highest-amplitude current into the CHAPTER 1. INTRODUCTION 25 largest possible tissue impedance. This power loss could be significant depending on the load impedance and the required stimulation current amplitude. For a rectangular current-mode stimulation pulse with an amplitude of Istim, the minimum required supply voltage is:

IstimTstim VDDmin = Istim · Relec + + Vheadroom, (1.2) Celec

where Relec and Celec are resistive and capacitive components, respectively, and Vheadroom is the minimum required headroom voltage. This equation shows that the required voltage compliance for a neuro-stimulator is set by stimulation current amplitude and the electrode impedance. Also, it shows that unless a stimulation pulse with a signiﬁcantly long width (>100s) is required, the effect of electrode capacitance can be ignored. For deep brain stimulation, where the electrode resistance is up to 1kΩ and the stimulation current is up to 1mA, the stimulator could be implemented in a standard CMOS process with thick oxide devices that can tolerate up to 3.3V [2]. However, for some applications such as muscle stimulation high current amplitudes up to tens of Milli-Amperes are required. Also, in the applications such as epi-retinal implants and trans-cranial stimulators that require small stimulation currents (<100μA), electrode impedance could be as high as 50kΩ. Based on Eq. 1.2, both these cases demand for voltage compliance that is much higher than what is available in a standard CMOS process.

High Voltage Compliance

Reported solutions to address this issue are either using a high-voltage process [75–79], or using standard CMOS process, but with a circuit architecture that does not impose a greater-than-supply voltage between device terminals at any time [80–82]. In [80], the CHAPTER 1. INTRODUCTION 26 authors have reported multiple-supply voltage compliance using 3.3V devices. How- ever, the maximum stimulation current amplitude is very limited in these designs (up to <50μA). Additionally, in case of a charge accumulation on the capacitive part of the electrode, the low-voltage device might see a high voltage across their terminals during negative phase of stimulation which could result in their breakdown. On the other hand, using high voltage devices to achieve high compliance, allows for simple circuit architectures supplied by a 20-50v voltage source, that does not have the risk of a device breakdown. The disadvantage of such high supply voltages is when stimulating with lower-than-maximum current amplitudes or into smaller-than- maximum electrode-tissue impedances, which results in a signiﬁcant portion of the consumed power being wasted. Considering high voltage levels in these systems, the wasted power could be as signiﬁcant as ×10 the delivered power to the tissue.

Adaptive Power Supply

To address the power loss issue, some power adaptive neurostimulators are reported [76, 77, 83, 178]. The common goal of all these designs is to set the supply voltage at the minimum required compliance. This demands for the supply voltage to be adaptive to the stimulation current amplitude, that is set by the user, as well as to the electrode impedance variations. In [83], the authors have reported an energy efﬁcient stimulator with adaptive supply voltage. The stimulator essentially mimics the electrode voltage that is expected for a particular current. The supply voltage variation is done by tapping into different terminals of a secondary power telemetry coil which has the advantage of not needing a DC-DC converter. However, there are only a few possible voltage levels. This means that the stimulation current is not controlled precisely. Also the reported design does CHAPTER 1. INTRODUCTION 27 not take electrode impedance variations into account. In [178], the authors have reported an energy efﬁcient charge-balanced voltage- mode neurostimulator. To guarantee a charge-balanced operation, the stimulation current is sensed and compared with a reference value, and if needed, the electrode voltage is changed to adjust the current to the desired value. Using this method, the electrode voltage is always set at the exact required value that is demanded by the stimulation current and electrode impedance. However, this method require a DC-DC converter with bulky external components in each channel, which prevents it from being scaled to multiple channels. In [77] a fully integrated DC-DC converter is designed to set the supply voltage slightly higher than the minimum required electrode voltage for a particular stimulation current. Despite being fully integrated and scalability, the supply is only adaptive to current variations and does not operate as expected if electrode impedance varies. Also unlike [178], the supply voltage has only 4 different levels (3v, 6v, 9v, 12v) which result in a maximum of 50% power saving. In [76] a scalable current-mode neurostimulation channel is reported. Supply voltage is adjusted based on the output of a feedback circuit that monitors available voltage headroom for the current driver transistors. The stimulator receives power and commands wirelessly but can only provides current amplitudes up to 1mA. Based on the above, there is still a need for a multi-channel neuostimulator that can deliver a charge-balanced electrical pulses (ideally, of arbitrary waveforms) to the brain with a high voltage compliance, while minimizing its power consumption. Such design must have an adaptive control system that adjusts the system’s supply voltage based on (a) the stimulation current amplitude, and (b) instantaneous electrode impedance of each channel. For this system, power and stimulation commands should ideally be provided through a wireless link. CHAPTER 1. INTRODUCTION 28

Chronic Implantation

Chronic implantation constraints such as the ease of implantation and use, and long lifetime must also be considered when designing an implantable device. Ignoring such aspect of the design could prevent such systems from being used in long-term animal (e.g., rodent) studies and in clinics. A multi-channel implantable system designed for long-term neurostimulation, must not only exhibit excellent performance in terms of electrical properties, but also should have a small form factor, be fully wireless and operate fully-autonomously. The SoC silicon die must be directly wire-bonded to a PCB (or bonded using ﬂip chip) , and minimum number of peripherals must be used. The neurostimulator must receive the stimulation pulse-shape parameters (e.g. amplitude, frequency, and duty cycle for a rectangular pulse) wirelessly. Power should also be provided by a battery or inductively. Despite high instantaneous power during stimulation, the average power consumption of a stimulator is very low, considering the number stimulations per day. As a result, using inductive powering with an energy saving component such as a super capacitor, is a viable option, and it eliminates the need for a heavy and bulky battery in the implant.

State-of-the-art High Voltage Compliance Neurostimulators

Table 1.4 summarizes the state of the art neurostimulator SoCs with high voltage compliance and/or adaptive supply control.

1.5.2 Optogenetic Stimulation

As mentioned, neurostimulation can be performed using agents other than electrical voltage or current. The relatively-new optogenetic neurostimulation technique has opened a new avenue for better understanding of mechanisms of neural function. Optogenetic CHAPTER 1. INTRODUCTION 29 5 % × 60 < 1.12 2.4 × % 62 < 0.26 0.52 × *No 0.47 0.31 % × 74 < Table 1.4: 1.2 0.5 State-of-the-art neurostimulator SoCs × [185] [76] [78] [178] [75] Biphasic Exponential ) (3.9) (10) (20) (1) (0.5)) Ω m) 0.7 HV 0.35 HV 0.18 HV 0.35 0.35 ) 1.2 2 μ ) 1.44 0.47 26.52 0.58 12 2 For Nominal Load (k Area (mm Independent 1 2 256 1 1 Waveform Programmable Arbitrary Arbitrary Biphasic Decaying Max Stim. Current(mA)Dynamic Range (mA) 1 1 1 1 0.5 0.003-0.5 0.45 0.45 4 4 of channels 1 8 256 1 4 Stimulus ControlWireless PowerWireless Data Comm. Current No No Voltage No Voltage Yes Current No Yes charge No No Yes Yes Area (mm SpeciﬁcationTechnology ( TBioCAS’07Channel: ISSCC’11 JSSC’10 TBioCAS’12 JSSC’15 Supply# Power Saving 15 No 20 32 3.3 3.3 N/A: Not Applicable N/R: Not Reported * : SIMULATION RESULTS. CHAPTER 1. INTRODUCTION 30 cell-type-speciﬁc modulation of neuronal activity opens up the prospect of initiating or preventing abnormal brain states that result in certain neurological conditions [84]. Unlike electrical stimulation, optogenetic stimulation selectively modulates neuronal activity in a local neural network and this modulation does not generate artifacts in the recording. In this thesis we have investigated use of an implantable wireless device for epilepsy and Alzheimer’s disease.

Optogenetic Stimulation for Seizure Induction

Epilepsy a chronic neurological disorder characterized by recurrent seizures. There is a profound need to better understand epileptogenesis and seizure onset since nearly one- third of all epilepsy patients remain refractory to conventional therapeutic interventions [85]. Electrical neuro-stimulation is an established effective drugs-alternative treatment option for a variety of neurological disorders including epilepsy. High-frequency (130 Hz) and low-frequency (0.5-5 Hz) deep brain stimulation have been shown to be effective in seizure reduction in patients and animal models [86–90]. While both have resulted in suppressing the seizure duration and propagation [86, 89, 90], the low- frequency stimulation is often preferred due to the lower power requirement and subse- quently lower risk of tissue damage. In [89] the authors have shown the effectiveness of the low frequency stimulation in a closed-loop conﬁguration. It is also shown that low-frequency neurostimulation causes a short-term synaptic depression of excitatory neurotransmission [91], and recently we have reported its effect in reduction of overall neural excitation at seizure onset [92]. Our group has also demonstrated that the seizure can be interrupted at an earlier stage before its full progress and propagation contralaterally, both in short-term [15] and long-term [93] animal experiments. Despite all the progress in the recent years, the exact mechanism behind neuromodulation using electrical stimulation in many cases CHAPTER 1. INTRODUCTION 31

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Figure 1.10: Envisioned implantation conﬁguration of the wireless electro-optical neurostimulator and its three main components. Illustration done by M. T. Salam.

remains unknown in part due to the lack of a proper tool enabling cell-type-selective neural excitation or inhibition in addition to simultaneous high-resolution spatiotemporal neural recording. Electrograph seizure onset has been correlated with augmented GABAergic neurotransmission in in vivo [94], in vitro [95–98], and clinical [99, 100] investigations. Convergence from both rodent and human studies indicate GABAergic circuitry is responsible for transition into electrographic seizures with a low voltage, fast activity (LVF) onset pattern [101–104]. It has been shown in both acute and chronic epilepsy models that prior or during an epileptic seizure, GABAergic activity is either pre- served [105] or increased [106–109]. Also in [103,110], the authors have demonstrated that a 300–1000ms optogenetic stimulation in in vitro 4-aminopyrmidine (4-AP) seizure model, which results in sustained activation of GABAergic interneurons can initiate epileptic ictal events. Our group have recently shown in an in vivo 4-AP seizure model that optogenetic activation of GABAergic interneurons in layer 2/3 of the neocortex is sufﬁcient to trigger LVF ictal events [111]. Based on our group success in using optogenetic and electrical stimulation for initiating and aborting epileptic seizures, respectively, it seems that a combination of electrical and optical stimulation on a wireless and battery-less device such as the sys- CHAPTER 1. INTRODUCTION 32 tem presented in Fig.1.10, is a potent novel technique for better understanding of the brain function and dysfunction, and for generating optimal brain modulation for treat- ing neurological disorders.

Optogenetic Stimulation for Alzheimer’s disease

Neurodegenerative diseases affect millions of people worldwide. The most common type is the Alzheimer’s disease (AD), affecting approximately 5.9 million people only in the North America [112]. It is a progressive disorder that slowly erodes memory and thinking skills, and eventually results in inability to carry out simple tasks. Epidemi- ological studies have discovered that excessive REM (rapid eye movement) sleep is a potential risk factor for the AD [113]. As shown in Fig. 1.12, sleep is dominated by cyclic occurrences of SWS (slow- wave sleep) and REM stages. It is commonly accepted that during SWS, also known as non-REM (NREM) sleep, active consolidation of memory takes place by reactivation of the newly encoded memories, which are then integrated into the existing network of associated memories [114]. On the contrary, the conclusion of REM sleep may wake up the subject and these repeating awakenings, can possibly disrupt the memory consolidation process [115]. A recent study demonstrates that antidepressant drugs suppress REM sleep and no impairment of the consolidation of procedural memory [116] takes place. However, many patients have signiﬁcant systemic side-effects and some are drug-resistant. These poor outcomes and adverse effects of the drugs motivate for an alternative treatment to supplement the conventional options for REM sleep suppression. Studies show that during sleep, θ oscillations from the ﬁltered hippocampus EEG are most prevalent during REM sleep and awake stages, and δ oscillations from the CHAPTER 1. INTRODUCTION 33

Figure 1.11: Light-triggered ictal activity in an epileptic VGAT-ChR2 mice [111].

LONGER REM SHORTER NREM AWAKE ~ 90 MINUTES REM

NREM S3

S4 DEEP SLEEP (SWS)

0.0 1.5 3.0 4.5 6.0 7.5 TIME SINCE START OF SLEEP (Hr)

Figure 1.12: Cyclic occurrences of slow wave sleep (SWS) and rapid eye movement (REM) sleep during a typical 9 hour sleep cycle. CHAPTER 1. INTRODUCTION 34

filtered cortex EEG are found during NREM sleep. EMG high frequency oscillations can be used to classify the awake stage. In addition to signal power of θ-oscillation that is used for REM detection, they can also serve another purpose as the key trigger to start the optogenetic stimulations to suppress the REM sleep stage. To properly evaluate the effects of REM sleep suppression experimentally however, all other known controls must be taken into account. Studies have shown that rhythmicity plays an important role in neural activity during mental processing [117]. One study proved the role it plays by blocking hippocampal theta activity while providing electrical stimulation to restore rhythmicity. Even though information was lost because of the block, the frequency of rhythmicity affected neuronal firing during cognitive processing in the hippocampus [118]. These findings show that optogenetic stimulation should be applied in a rhythmic frequency close to theta oscillations. This allows stimulation during the peak amplitude values of the oscillation while avoiding changing the phasic activity of surrounding neurons. To perform such experiment on rodents, an implantable wireless device capable of sleep-stage classification and triggering closed-loop responsive optogenetic stimulation at θ-band peaks and troughs is required.

1.6 Thesis Organization

Figure 1.13 outlines the organization of the thesis. This ﬁgure shows an outline of the implantable SoC that is described in this thesis and highlights the major blocks that each prototype described in different chapters includes. Also a photograph of the prototypes with a brief summary of their performance parameters are presented. The details of each chapter are described below.

• Chapter 2 presents a multi-die wireless device that is designed and implemented CHAPTER 1. INTRODUCTION 35

as the first step toward a fully-integrated brain machine interface SoC. The device takes advantage of previously-reported neurostimulator ICs that were designed and tested in our lab as the core component for neural recording and stimulation. The device is sized at 2 × 2 × 0.7 cm3, weighs 6 grams. It is comprised of two mini-boards and a power receiver coil. The first board hosts a 24-channel neurostimulator SoC developed in a 0.13μm CMOS technology [2] and performs neural recording, electrical stimulation and on-chip digital signal processing. The second board communicates recorded brain signals as well as signal processing results wirelessly, and generates different supply and bias voltages for the neurostimulator SoC and other external components. The multi-layer flexible coil receives inductively-transmitted power and sends it to the second board for power management. The neurostimulator IC used on the first board is designed by a previous PhD student, K. Abdelhalim. Also the wireless communication board and the inductive coil are designed by N. Soltani. Details of the above are not discussed in this thesis as they are not my contributions. FPGA coding for different testing scenarios is done by or with the assistance of A. Chemparathy, P. Li, F. Bekmam- betova, and S. Tonekaboni.

• Chapter 3 presents a 16 mm2 0.13 μm CMOS SoC. The chip essentially integrates all the functionalities of the two PCBs described in chapter 2, on a single chip. Additionally, the ac-coupled front-ends of the previous design were replaced with a compact DC-coupled front-end design. It has 64 neural recording channels, each with a digitally-assisted DC-offset cancellation feedback. Chop- per stabilization is employed in each neural ampliﬁer to suppress its ﬂicker noise. Channel-to-channel gain mismatch is removed by utilizing a multiplying ADC, CHAPTER 1. INTRODUCTION 36

included in each channel, in a digital calibration loop. A multi-core digital processor shared between all the channels, is used to carry out signal feature extraction and epileptic seizure detection. The chip also has 64 programmable bi-phasic current-mode stimulators that are triggered by the on-chip digital processor upon detection of a neurological event, to modulate brain activity. Three wireless transmitters are included in the design that enable communication of diagnostic data to a wide range of distances over three different bands of frequency. The chip is powered wirelessly using a magnetic inductive link, with energy signals that are amplitude shift-keyed to communicate configuration commands to the chip. The chip is validated in-vivo on four freely-moving rats and off-line on three human patients. The first version of the DC-coupled front-end is reported in [48], and the multiplying SAR ADC is first reported in [2].

CHAPTER 1. INTRODUCTION 37

& POWER & COMMANDS COMMANDS DATA DATA tions. /CHANNEL 2 < 1mV NEF=4.4 MULTI-DIE AC-COUPLED 6.3 μW/CHANNEL 0.09 mm

VOLTAGE RECORDING 0.3 mm 0.3 LONG-RANGE SHORT-RANGE POWER RECEIVER COMMAND RECEIVER DATA TRANSMITTER DATA TRANSMITTER WIRELESS COMMUNICATION NEUROSTIMULATOR SYSTEM COMMAND AND POWER RECEIVER 0.3 mm

/CHANNEL L A N G I S

L G A T N I I S G I S D E C O R 2 P

CHAPTER 3

NEF=7 <1mV SYNCHRONY-BASED SINGLE-DIE DC-COUPLED 6.5 μW/CHANNEL 0.09 mm

3.3 mm

4.85 mm 4.85 0.1 mm 0.1 RECORDING VOLTAGE RECORDING 0.13 mm FRONT-END RECORDING STIMULATOR STIMULATOR OPTOGENETIC STIMULATOR CURRENT-MODE MULTI-CHANNEL HIGH-VOLTAGE HV CURRENT-MODE X4 X4 X64 X64 STIMULATOR X16 CURRENT NEF=2.86 SINGLE-DIE RESPONSIVE NEUROSTIMULATOR < 1.2 V SWITCHED-CAP 0.63 μW/CHANNEL 0.013 mm2/CHANNEL CHAPTER 4 CHAPTER 2 2.3 mm

VOLTAGE &

2.6 mm 2.6 I4 I1

V4 V1 V1

I64

O16 V64 20 mm 5 mm 25 mm BUFF Thesis organization outline. All credits for collaborative efforts are given in section 1.6. and throughout this thesis and in all relevant ﬁgure cap

CHAPTER 5.1 CP CHAPTER 5.2

20 mm 20

STIMULATION CHANNELS 30 mm 30 DIGITAL

Figure 1.13: 2 mm 2 CHAPTER 1. INTRODUCTION 38

• Chapter 4 presents the latest generation of 64-channel responsive neurostimulator SoCs. A Δ2Σ-based neural recording front-end is featured in this design that enables recording signals with rail-to-rail input amplitude and rail-to-rail DC offset variations. In addition, the SoC keeps all the system-level features of previous generations including digital signal processing, multi-band wireless transmitters and power and command receiver. The Δ2Σ-based recording channel eliminates the need for bulky DC-removing passive components and yields a compact 0.013 mm2 integration area for amplifier and ADC. Using a current-DAC that is placed in the feedback path of the Δ2Σ ADC, a mixed-mode analog-digital multiplication is performed in each channel. The multiplication is used for compact implementation of band-pass digital filters, as well as voltage gain scaling. The analog multiplication circuit is reused as a current stimulator when the SoC is configured to perform responsive neurostimulation. The chip occupies 6 mm2 and is validated in an in vivo epilepsy monitoring and treatment experiment.

• Chapter 5 presents two neurostimulation systems, one board-level and one chip- level. These systems can work as a stand-alone device and also can be added as an additional module to the closed-loop neurostimulator system presented in chapter 2. Both systems are inductively powered and receive commands wirelessly. They both beneﬁt from different load-aware power-adaptive design techniques to save power consumption. In the ﬁrst section of this chapter, a hybrid current-mode and optogenetic miniature neurostimulating system is presented. The system performs electrical current-mode (0.05mA to 10mA) and optogenetic stimulation with a maximum 24V voltage compliance. The LEDs are assembled within a custom-made 4×4 ECoG grid electrode array, which enables precise optical stimulation of neurons CHAPTER 1. INTRODUCTION 39

with a 300μm spatial resolution and simultaneous monitoring of the neural response by the ECoG electrode, at different distances of the stimulation site. The implantable system is a 3×2.5×1cm3 stack of a receiver coil and two mini- boards, and both its electrical and optogenetic stimulators are validated in vivo. The HV stimulator board and the FPGA programming is done with F. Chen and B.Vatankhah assistance. Also the animal experiments are done with the help of F. Chen, Ch. Lucasius, and M. Chang. In the second section, a wireless high-voltage-compliance implantable 4- channel dual-mode neurostimulator SoC is presented. The SoC is capable of both current- and voltage-mode stimulation with a voltage compliance of up to 20V, and operates in both mono-polar and bi-polar conﬁgurations. Each channel is wirelessly programmable to generate an independent arbitrary waveforms (8-bit resolution). A dual-loop impedance- and current-monitoring digital controller is designed to adjust both the voltage headroom in each channel, and the system voltage supply for all channels. The controller ensures the supply voltage is set to the minimum required value based on the stimulation current amplitude and instantaneous electrode impedance of each channel. Our experimental results shows a 68.5% saving in the power consumption due to the load-aware adaptive supply voltage.The SoC is implemented in a 0.35μm HV-CMOS process, takes 10 mm2. The system is miniaturized and is implemented using a stack of two rigid and one ﬂexible PCBs (printed circuit board), with the size of 2 × 2 × 0.7 cm3, and weight of 6 grams. The chip design is done with the assistance of Y. Hu and Ch. Liu. The board design is done with the asistance of G. Dutta.

• Chapter 6 highlights future work related to the neural interface SoCs described in this thesis. CHAPTER 1. INTRODUCTION 40

Table 1.5: Summary of chapters

Chapter 2 3 4 5.1 5.2 Contribution of My Time 15% 15% 50% 5% 15% My Contribution In The Project* 50% 90% 100% 50% 70%

* : Out of all the students and post-doctoral fellows involved in that project.

For all the systems, the animal experiments are performed with assistance of Dr. M. T. Salam in Toronto Western Hospital or Toronto Hospital for Sick Children. Table 1.5 summarizes the importance of each chapter in my PhD thesis (contribution of my time) as well as my contribution toward each project which are performed as a team. 41

Chapter 2

Implantable Wireless Mini-Board for Monitoring and Treatment of Neurological Disorders

This chapter presents two board-level wireless devices that were designed and implemented as the first step toward a fully-integrated brain machine interface SoC. Both devices take advantage of previously-reported neurostimulator ICs that were designed and tested in our lab as the core component for neural recording and stimulation. In the first section, an inductively-powered implantable microsystem for monitoring and treatment of intractable epilepsy is presented. The miniaturized system is comprised of two mini-boards and a power receiver coil. The first board hosts a 24-channel neurostimulator SoC developed in a 0.13μm CMOS technology [2] and performs neural recording, electrical stimulation and on-chip digital signal processing. The second board communicates recorded brain signals as well as signal processing results wirelessly, and generates different supply and bias voltages for the neurostimulator SoC and other external components. The multi-layer flexible coil receives inductively- CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 42 transmitted power and sends it to the second board for power management. The system is sized at 2 × 2 × 0.7 cm3, weighs 6 grams, and is validated in control of chronic seizures in vivo in freely-moving rats. In the second section of this chapter, first, existing sleep stage classifier sensors and algorithms are reviewed and compared in terms of classification accuracy, level of automation, implementation complexity, invasiveness, and targeted application. Next, the implementation of a miniature microsystem for low-latency automatic sleep stage classification in rodents is presented. The classification algorithm uses one EMG (electromyogram) and two EEG (electroencephalogram) signals as inputs in order to detect REM (rapid eye movement) sleep, and is optimized for low complexity and low power consumption. It is implemented in an on-board digital VLSI (very-large-scale integration) processor to achieve low-latency (order of 1ms or less) classification. Off-line experimental results using pre-recorded signals from nine mice show REM detection sensitivity and specificity of 81.69% and 93.86%, respectively, with the maximum latency of 39μs. The device is designed to be used in a non-disruptive closed-loop REM sleep suppression microsystem, for future studies of the effects of REM sleep depriva- tion on memory consolidation.

2.1 Battery-less Modular Responsive Neurostimulator

for Prediction and Abortion of Epileptic Seizures

2.1.1 Introduction

This section presents a 24-channel inductively-powered implantable microsystem for neural signal monitoring, on-chip signal processing and biphasic current-mode stimula- CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 43

POWER & COMMAND DATA & POWER COMMUNICATION PCB INDUCTIVE POWER WIRELESS POWER & COMMAND TX AND DATA RECEIVER DATA WIRELESS DATA WIRELESS DATA TRANSMITTER RECEIVER

ECoG V1 ELECTRODE MULTI-CHANNEL NEURAL RECORDING RODENT V24 BRAIN I1 MULTI-CHANNEL MULTI-CORE NEURAL STIMULATION PROCESSOR I24 SIGNAL DIGITAL RESPONSIVE NEUROSTIMULATION PCB

Figure 2.1: Block diagram of the wireless closed-loop neurostimulator microsystem implanted on a rat’s brain. tion. A general block diagram of a wireless closed-loop neurostimulator brain implant is shown in Figure 2.1. The figure also shows an envisioned implantation configuration of the SoC (system on a chip) in the proximity of an animal brain where it is connected to an array of ECoG or depth electrodes. A 12 mm2 0.13 μm CMOS SoC performs the core of signal recording, processing and stimulation [2]. The system transmits the diagnostic data to the outside of the body wirelessly and receives its energy directly from an inductive powering link several centimeters away. The system’s efficacy in epileptic seizure detection and abortion is validated in vivo on freely-moving rats with temporal lobe epilepsy.

2.1.2 Methods and Material

Figure 2.2(a) shows a system block diagram of the implantable closed-loop neurostimulator. The system is comprised of the receiver coil, the wireless interface board and the neurostimulator board. The core of the system is the neurostimulator SoC which has 64 neural recording channels that receive and amplify EEG/ECoG signals from a microelectrode array implanted in the rodent brain. The ampliﬁed signals are ﬁltered

CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 44

7 mm 7

COMMAND

20 mm 20 POWER & POWER

FLOOR 45 cm 45 INDUCTIVE POWERING

20 mm

26 cm

20 mm 20 20 mm 20 mm 20 20 mm ) BOARD INDUCTIVE b ( POWER RECEIVER POWER RECORD/STIMULATION COMMUNICATION + SIGNAL PROCESSING

SERIALIZER DATA COIL FPGA CONFIG. DECODER COMMAND GENERATOR LOW-POWER DATA/COMMAND 10

LOW-POWER FPGA LOW-POWER OSCILLATOR DIGITAL PROCESSOR DIGITAL

TX ASK CORDIC-BASED TRI-CORE RECEIVER

CONTROLLER

MUX DE-MUX 8 8 8 LDO ) (FPGA VDD) a ( 8 DAC 8-BIT LDO SAR ADC DC-to-DC CONVERTER (ANALOG VDD) WIRELESS DATA/POWER WIRELESS DATA/POWER COMMUNICATION BOARD COMMUNICATION NEUROSTIMULATOR SoC NEUROSTIMULATOR V/I LDO FILTER BAND-PASS CONVERTER RECORDING STIMULATION (DIGITAL VDD) (DIGITAL RX C RECTIFIER FSK / UWB DRIVER TRANSMITTER CURRENT BOARD AMP. NEURAL (a) Simpliﬁed block diagram of the implantable inductively-powered closed-loop neurostimulator, (b) different components of the NEUROSTIMULATOR NEUROSTIMULATOR POWER & POWER COMMAND

DATA TRANSMITTER I2 I1 V2 V1 V24

I24

VREF INDUCTIVE INDUCTIVE FSK RECEIVER FSK Figure 2.2: multi-PCB microsystem. (Wireless communication boardM. and Aliroteh.) inductive coil were designed by N. Soltani. The inductive floor was designed by CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 45 and digitized in each channel and then fed to an on-chip multi-core digital processor shared among channels, to extract their amplitude and phase information. The digital processor uses this information to detect an upcoming epileptic seizure and activate a subset of 24 current-mode stimulators available on the chip to abort it. The chip is interfaced with an on-board FPGA that serializes the chip output and sends it to the wireless communication board through a vertical connector bus. The FPGA uses the same bus to receive configuration commands from the wireless board. The implantable system is powered wirelessly using an inductive powering system presented in [120]. The inductive powering system is comprised of an inductive power transmission floor that sits under the animal cage, a receiver coil, and power management circuits including rectifiers and regulators. As shown in Figure 2.2(b), the receiver coild is implemented using a flexible polymide substrate, and the power management circuits are placed on a rigid miniPCB, that also houses radio transmitters to transmit recording data to a computer base station. Both the flexible coil and the rigid mini-PCB interface with the neurostimulator miniPCB through vertical connectors. During the animal experiments, the device is either placed on rats head, or inside a backpack for freely moving animals. The inductive powering system is designed to provide sufficient energy to the system for a distance of up to 15cm. However, for special situations where the TX/RX coil separation becomes larger than this value (e.g. when the rodent stands up in the cage, or when the coils are not in the right angle), the power delivery might become limited or interrupted. To ensure continuous operation of the device in such situations, a super capacitor is placed on the wireless data/power miniPCB, that can provide power to the neurostimulator board until the inductive powering link is connected. CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 46

Rodent Headset

Figure 2.2(b) shows the miniaturized headset microsystem that is comprised of the two printed circuit boards (PCBs) and a coil powered by an inductive powering rodent cage floor [120]. As illustrated, the coil (top) is a polyimide-based flexible coil that receives power transmitted by means of near-field magnetic induction. The coil is connected to the first board (middle) that performs power management and supplies energy to different blocks of the system. The second board (bottom) hosts the neurostimulator SoC, directly wirebonded on it and covered by epoxy, that performs multi-channel signal recording and digital signal processing for monitoring and detection of epileptic seizures. The chip also does automatic multi-channel responsive electrical stimulation for seizure abortion. The minimum size is set by how compact the chip, its interfacing FPGA, and other peripheral components can be laid out on a PCB. The size can be reduced to almost the chip size if smaller trace/space features are used for PCB design, which of course results in higher price for fabrication.

Closed-loop Neurostimulator Board

Figure 2.3(a) shows the top view of the neurostimulator board with the silicon SoC, shown in Figure 2.3(d), directly bond-wired to it as depicted in Figure 2.3(c). Fig- ure 2.3(b) shows the bottom view of the neural interface board. As shown, the board hosts the neurostimulator chip as well as a low-power FPGA that serializes and sends recorded neural data to the wireless board and controls the SoC mode of operation using commands received from that board. Prior to the animal experiments, the board is tested in the lab and all the biasing voltages and conﬁguration parameters set by the FPGA were ﬁne-tuned for a safe operation. For a safe power up during the animal experiment, an Actel FPGA with non-volatile memory was used to ensure a stable and CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 47

12 CHANNEL TOP VIEW CONNECTOR BOTTOM VIEW TO ELECTRODES ACTEL IGLOO NEURO FPGA STIMULATOR VOLTAGE CHIP REGULATOR mm VERTICAL VERTICAL

20 CONNECTOR TO CONNECTOR FOR WIRELESS STACKABILITY BOARD CRYSTAL JTAG/ 20 mm OSC 20 mm CONNECTOR (a) (b) 11 mm 3 mm mm mm 4 13

Figure 2.3: Neural recording/stimulation mini-PCB (a) top and (b) bottom view. (c) Top view of the board showing the bond wires that connect the SoC’s pads to the pads on the board. (d) The micrograph of the neurostimulator SoC designed by K. Abdelhalim, ﬁrst reported in [2]. CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 48

55 45 35

GAIN(dB) 25 -1 0 1 2 3 4 5

10 10 10 10 10 10 10 0 FREQUENCY (Hz) 10 /sqrt(Hz) −1

rms 10 NOISE(IRN)

μV INTEGRATED IRN (10Hz - 5kHz): 4.7 μVrms −2 INPUT-REFERRED 10 0 1 2 3 10 10 10 10 FREQUENCY (Hz)

FSK RECEIVED DATA AT 500 kbps RATE 914.6MHz 916.4 MHz -35.9dBm -35.6dBm

2MHz 10dbm

Figure 2.4: Experimentally-measured frequency spectrum of the recording front-end (top), the input-referred noise (middle), and spectrum of the FSK transmitter (bottom). safe mode of operation once the system is powered up after being connected to the animal. Microelectrode or ECoG arrays used for in vivo experiments connect to two 12-channel connectors on this board using ﬂat ﬂexible cables. Vertical Panasonic connectors are used to connect this board to the wireless communication board on one side, and to additional replicas of the neurostimulator board on the other side. Due to the direct wirebonding constraints, only 24 channels of each SoC are used. For more channel count, more copies of the neurostimulator board are stacked vertically, each adding 24 to the total number of channels.

2.1.3 Results

Figure 2.4(top) shows the amplitude response of the front-end ampliﬁer from sub-Hz frequencies up to the MHz range. The ampliﬁer nominally operates between 0.5Hz to CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 49

10kHz, and its mid-band gain is measured to be over 53dB for all of the channels. The experimentally measured CMRR (Common-Mode Rejection Ratio) at 10 Hz and 1 kHz is 75.4 dB and 71.5 dB, respectively. Both the high-pass and low-pass poles are adjustable, with the maximum bandwidth of 0.01Hz to 10kHz. Figure 2.4(middle) shows the integrated input-referred noise, which is measured to be 4.7μVrms when integrated from 10Hz to 5kHz, and 3.7μVrms for 1Hz to 100Hz. The noise efficiency factor is measured to be 4.4 for the 5kHz bandwidth. Figure 2.4(bottom) shows the frequency spectrum of the FSK wireless transmitter on the communication board that operates at 915MHz. The experimental measurements show a maximum of 500 kbps data rate at 10m distance, that constitutes a relatively high-throughput link for mid-range communications to a receiver connected to a computer base-station. For freely moving rodent epilepsy studies, the implantable system is powered inductively. The powering system consists of a two-layer network of 16 planar high-Q (Q=129) inductive transmitter coils placed under a non-conductive rat cage floor, and a small multi-layer flexible receiver coil, both shown in Figure 2.2(b). The voltage received by the receiver coil is rectified and multiple on-board LDOs (Low DropOut regulator) and DACs (Digital to Analog Converter) are utilized to generate different supply and bias voltages required for the SoC and external components on both boards. The receiver coil is a 20mm × 20mm stack of four flexible two-layer PCBs for a total of eight layers. The flexibility allows to tailor-fit the coil to the shape of the implantation site. The inductive powering system achieves an overall wireless power transfer efficiency of over 40%. The system was validated in a 100-hour study of chronic treatment of temporal lobe epilepsy (rat model) with four Wistar rats. The rats were divided into two groups, a non-treatment (i.e., without stimulation) and a treatment group (i.e., with closed-loop CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 50 stimulation). Fig. 2.5(a) shows an example of in vivo on-line real-time early seizure detection in the non-treatment group. In the treatment group the SoC was configured to automatically trigger a closed-loop current-mode stimulation for the purpose of suppressing upcoming seizures. Fig. 2.5(b) illustrates the SoC-triggered stimulation upon a seizure onset detection in the treatment group. Due to the length of the experiments and to avoid interruption in the experiments, the chip was powered using a loose cable that allowed animal to move freely. A comparative analysis is given in Table 2.1 where this work demonstrates advanced functionality among recently published state-of-the-art miniaturized SoC-based neural interfaces.

2.1.4 Safety

One of the important, and yet rarely investigated, aspects of an implantable medical device is its safety for the user. This includes preventing any short-term and long-term physical damage that the device might cause during start-up, normal operation and fail- ure.

Electrical/Magnetic Safety

According to Health Canada regulations, intra-cortical neural stimulators are among surgically invasive devices that are intended to diagnose, monitor, control or defect the central neural system and are classiﬁed as class IV (Class III in FDA). From Chip-level design to packaging the implant, safety regulations will be considered.

For stimulation, the device must not create a DC current in any part of the body, which is more than 25nA. This will ensure that no corrosion or PH imbalance will happen. To meet this requirement balanced biphasic current stimulation is utilized in our design. Careful design of biphasic stimulation, results in no need for huge DC-blocking CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 51 capacitors (∼100nF) to be used and saves area signiﬁcantly. Also pulse duration, frequency and amplitude will be set to meet the requirements stated in [121, 122]. This will ensure charge per phase and charge density are low enough that does not damage the tissue.

In this design, non-volatile FPGA (Actel Igloo) is used, which keeps its program even after the power is turned off. As a result, the device can be pre-programmed, and once it is connected to the animal and powered on, it goes to normal operation mode, without any safety risks due to the start-up period.

For the telemetry, antennas placed near surface should deliver power of less than 9mW to ensure that Speciﬁc Absorption Rate (SAR), a measure of volume heating caused by the EM ﬁeld in the tissue, is below the FDA approved levels (1.6mW/g for head).

Packaging

Prior to implantation of the neural interface system, a mandatory test should be performed to access implant properties. Based on ISO10993, for an implant to be biocompatible, no residues should be left on the device after implantation. Also no agents should elute out of the material, and materials stability for chronic implants should be assured. Furthermore, mechanical biocompatibility including harmless mechanical interaction between devices corners and sharp edges and the target tissue should be ensured. Due to the above reasons, the neural microsystem is needed to be packaged with biocompatible materials and utilizing processes that has been approved by safety standards.

Based on the speciﬁcations of this neural microsystem, and due to the fact that number of channels coming out of the system is going to be less than 100 in this stage, hermetic packaging (all electronic components and systems in a single housing) is de- CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 52 sired. This type of packaging can be done with deposition of various types of materials on silicon, including Silicon and Carbon oxide or nitride as well as polymers such as silicon rubber and parylene C (Poly Para Xylylene).

Several research laboratories and institutes provide biocompatible encapsulation and packaging for electronic implants differing from each other by their encapsulation methods and materials.

For instance EIC laboratories in Norwood, Massachusetts uses Plasma Enhanced Chemical Vapor Deposition (PECVD) to coat planar and non-planar substrates with insulating, dielectric ﬁlms. They are able to deposit any combination of the four di- electrics, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide at tempera- tures from 100◦C to 400◦C. Another example of commercially-available packaging fa- cility is Fraunhofer institute of biomedical engineering. In this institute, Concepts and technologies for the electrical interface are available. The applied micro-assembly and encapsulation techniques ensure a strict separation between ﬂuid channels and sensible electronic structures on biochips and lab-on-a-chip systems.

As an academic example, microsystem lab in University of Utah provides a con- formal and chronically stable dielectric encapsulation that is able to protect the neural interface device from the harsh physiological environment. They have veriﬁed CVD (chemical vapor deposited) Parylene-C ﬁlms as a potential implantable dielectric encapsulation material in an in-vitro experiment. This lab have had the experience of encapsulation for a neural interface system which shows good stability and functionality over a long period of 150 days which makes them an excellent choice for packaging of our system. CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 53

2.1.5 Conclusion

A 24-channel wireless and battery-less implantable micro-system has been presented. The system records neural signals at high spatial resolution, processes them on-chip to predict epileptic seizures and performs multi-channel responsive current-mode electrical stimulation upon a prediction. A wireless transmitter communicates recorded neural activity as well as signal processing results to a remote computer. Energy is provided to the system using magnetic induction. Small form factor, light weight, lack of wires and autonomous operation make the system excellent for chronic implantation. The system was fully characterized electronically and was validated on freely-moving animals with temporal lobe epilepsy. CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 54

1 ICEEG FROM RIGHT HIPPOCAMPUS 0.5 SEIZURE ONSET

(mV) 0 RH V -0.5 NORMAL PREICTAL SEIZURE NORMAL -1 ICEEG FROM LEFT HIPPOCAMPUS 0.5

(mV) 0 LH V -0.5 1 SEIZURE PRECURSOR SEIZURE DETECTION THRESHOLDTHRESHOLD 0.8 DETECTION 0.6 0.4 0.2 0 0 50

PHASEC SYNCHRONY 100 150 200 TIME (sec) (a) 1 ICEEG FROM RIGHT HIPPOCAMPUS ELECTRICAL 0.5 STIMULATION

(mV) 0 RH V -0.5 NORMAL PREICTAL NORMAL -1 ICEEG FROM LEFT HIPPOCAMPUS 0.5

(mV) 0 LH V -0.5 1 SEIZURE DETECTION 0.8 SEIZURE PRECURSOR DETECTION THRESHOLD 0.6 0.4 0.2 0 0 50 100 150 200 PHASEC SYNCHRONY TIME (sec) (b)

Figure 2.5: Experimentally measured results: (a) an example of an early seizure detection in the non-treatment group, and (b) an example of a seizure abortion in the treatment group of rats. (Animal experiments were done with the assistance of M.T. Salam.) CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 55 0.7 × 2 15cm A - 1mA THIS WORK < μ × Epileptic Seizure Detection and Control A10 2.5* 2 μ × 10 5.8 Magnitude Phase Synchrony < 2.5 & [24] TBIOCAS 2015 Chen × Closed-loop Neurostimulation [23] JSSC 2015 Rabaey Nearal Monitoring stim. 1.5 N/R 3 A - 82.5-229 μ & × 2.2 [10] × TBIOCAS 2013 Genov Rat ECoG Recording 5.1 3 × 20m N/R N/R 6 mm 10m 3.8 > × [21] TBIOCAS 2010 Meng Nearal Monitoring 0.6 3.8 × A - 20-250 State-of-the-art miniaturized neural recording and/or stimulation SoC-based systems μ 1.3 × [22] TBIOCAS 2011 Mohseni Intracortical Microstimulation Table 2.1: ) - - - - - 88-96 ) - - - - - 89-97 % % ) 3.6 3 cm of Stim. Channels 4 0 64 0 8 24 Selectivity ( Current Range 125 Closed-loop DetectionMethod# YESBattery Lifetime (hr)Receiver Coil TypeCoil Spike-Discriminator SeparationModulationFrequency - -Range 24 -Sensitivity ( - - FSK 33 - 433MHz - 1m - 3.9GHz FSK 10 NO - - 2.4GHz ZigBee - Phase YES - 300 MHz 1-layer flex OOK 1.6cm 1-layer flex 10 MHz YES - ASK 6 8-layer mm flex 915MHz - FSK Specifications Targeted Application Power Diss. (mW)SIGNAL PROCESSINGNEURAL STIMULATION 0.42 YESENERGY SOURCE YES 142WIRELESS COMM. NO Battery NOIN-VIVO RESULTS N/R YES NO Battery YES YES 0.225 Battery YES NO Magnetic Induction NO YES Magnetic Induction YES Magnetic Induction YES YES YES YES YES YES YES YES YES YES YES Size ( Weight (gr)Number of Rec. Channels 4 1.7 32 N/R 256 12 64 - 8 20 24 6 *: Estimated , -: Not Applicable , N/R: Not Reported CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 56

2.2 Electronic Sleep Stage Classiﬁers: A Survey and

VLSI Design Methodology

2.2.1 Introduction

Electrical brain stimulation has been established as an effective drugs-alternative treatment option for a variety of neurological disorders [10, 15, 123]. For REM sleep, it has been shown that stimulating the lateral hypothalamus immediately after θ-oscillation (4- 8Hz) peaks and troughs, significantly increases the chance of REM suppression [124]. This necessitates the development of a sleep stage classifier that can detect REM stage, not only with a high accuracy, but also within a very short period of time (order of 1ms or less), allowing for a timely stimulus to be delivered. Several mathematical algorithms have been proposed for sleep classification and are tested on off-line data using computer software [125, 126, 128, 129]. Benefiting from high-performance computational schemes, these algorithms often succeed to yield a high detection accuracy and a low false positive rate. However, they require high computational power, typically not available in portable/wearable devices. Also, using a data acquisition module that sends the recorded brain signals to a computer results in delays that are orders of magnitude longer than timing-requirements for a REM-suppressing responsive stimulation. On the other hand, some simpler methods are reported for clinical and commercial sleep classification devices, which use non- physiological sensory signals that are easier to record and analyze, but yield poor classification performance that is only acceptable for wellness applications [134–140]. In this section, first, we review various types of electronic sleep stage classifiers and compare them in terms of classification accuracy, level of automation, implementation complexity, invasiveness, and targeted application. According to the review, multiple types of physiological signals must be used as sensory information to achieve the CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 57 level of accuracy required for REM sleep detection. An EEG/EMG-based classification algorithm is then proposed with a computational complexity level that allows for its implementation on a low-power field-programmable gate array (FPGA), mounted on a miniature device worn by a small rodent. This yields a sub-ms classification latency which is shorter than the permitted 1% of the θ-oscillation period (125-250ms), to carry out effective REM-suppression [124]. The proposed algorithm architecture and performance are compared with two best- performing FPGA-compatible sleep classification algorithms reported in the literature [152, 154], using our intracerebral EEG (icEEG) and EMG recordings from nine mice. Rodents (mice) are chosen as an accurate and low-cost model of human sleep. All the three algorithms are based on extracting frequency components of the recorded EEG and EMG signals, followed by evaluating simple mathematical functions and thresholding. The REM sleep detection accuracy is evaluated, to illustrate the superiority of the proposed algorithm. Next, the proposed algorithm implementation in an FPGA that was assembled together with a multi-channel recording and stimulation ASIC (application- specific integrated circuit) on a small PCB (printed circuit board) is presented. It is optimized to reduce the use of hardware resources and power. The device is validated using off-line icEEG and EMG data, and its detection performance is compared to the state of the art. Correspondingly, the rest of the chapter is organized as follows. Section 2.2.2 reviews and compares existing sensory methods used for sleep stage classification. Sec- tion 2.2.3 reviews various PSG-based sleep stage classification algorithms implemented in software and hardware. Section 2.2.4 describes the proposed algorithm and compares its MATLAB simulation results to the state of the art. Section 2.2.5 describes the electronic implementation of the proposed algorithm on a miniature device. Section 2.2.6 presents the classification results for both software and hardware implementations of CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 58 the algorithm and compares them with the state of the art.

2.2.2 Review of Sleep-Stage Monitoring Sensors

Patient self sleep assessment report is a common method to obtain information in research and clinical studies. Although sleep diaries and questionnaires are one of the easiest and most affordable methods to collect data over a long period of time, the collected data are subjective and may not always be accurate in both healthy and sleep- disordered groups [131–133]. Moreover, such assessments are limited to sleep/awake results, and cannot provide any information on different sleep stages. Using electronic sensors for the sleep stage classification removes subjectiveness of the results, and unlike the self assessment reports, can provide information regarding different sleep stages. Actigraphy (ACT), autonomic nervous system (ANS) activity, and polysomnography (PSG) are the most popular methods used in the development of both commercial and research-based electronic sleep stage classifiers [125,126,128, 129, 134–140, 150–153]. Fig. 2.6 shows the most common physiological and non-physiological sensors used in each method. In addition to the type of sensory signals used, these methods vary in the level of invasiveness, the classification accuracy, the level of automation, and the targeted application. Generally, using fewer and less-invasive sensors has the advantage of simpler and more comfortable data acquisition for the subject, which is of great importance in wellness applications. However, when sleep monitoring is performed for the purpose of detection or treatment of a neurological disorder, simplicity can be traded for higher classification accuracy. Actigraphy is the most common method used in the commercial wellness devices that are typically designed to be used in conjunction with a smart phone [134]. Over several days, the acceleration of the extremities (typically wrist) is recorded using an CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 59

CORTEX & 1 HIPPOCAMPUS EEG 2 EYE MOVEMENT AIR MOVEMENT 3 EMG (MUSCLE TONE) 4

CHEST MOVEMENT 5 DURING BREATHING

ACTANS PSG HEART RATE 6 1 VARIABILITY ELECTRO- 2 7 CARDIOGRAM 3 HAND 8 4 MOVEMENT 5 OXYGEN 6 LEVEL 9 7 IN BLOOD 8 9 10 LEG MOVEMENT 10

ACT : ACTIOGRAPHY ANS: AUTONOMIC NERVOUS SYSTEM VARIATIONS PSG: POLYSOMNOGRAPHY

Figure 2.6: Electronic sensors used for various methods of sleep stage classification. CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 60 accelerometer and is stored in the cell phone memory or a memory module embedded in the device. Later, the recorded data are fed to a computer-based classifier for sleep/wake classification. Most of the algorithms that have been proposed for actigraphy implementation, classify periods of low activity as sleep [135, 136]. As a result, they cannot cope with the problem of misclassifying low activity tasks, such as reading a book, lying on the bed, watching a movie or the case where the sensor band is not worn. This makes the use of actigraphy-based devices limited to simple wellness applications. For example the electronic devices that are introduced in [137, 138], detect the best sleep stage for easy waking-up in a given time window. Additionally, as there is no set standard for the data collection or sleep classification using actigraphy, comparing the performance of different devices is impossible in most cases [139]. Changes in the activity of the autonomic nervous system, reflected in various physiological signals such as heart rate, blood pressure, and skin conductance, are shown to be a good identifier of sleep/awake transitions [141]. In [142–144], heart-rate variability is used to differentiate between sleep and wakefulness. In [145], respiratory signals are added to the heart-rate variability to classify different sleep stages for patients with obstructive sleep apnea. Based on this, a non-invasive wearable sleep/awake detection system is reported in [150]. The system measures sleepiness of the subjects, but cannot classify different sleep stages. Polysomnography (PSG), first described in [151], is known as the gold standard for assessing sleep in humans due to its high accuracy in sleep stage classification [150]. It combines brain EEG signal with other physiological signals such as EMG, electroocu- lography (EOG), respiratory effort, blood oxygen saturation, ECG, and video analysis (Fig. 2.7(a)). However, to perform a complete PSG, controlled hospital environment and medical assistance for sensor setup and monitoring are required. Additionally, acquired data must be analyzed by a trained professional to prepare a sleep assessment CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 61

ELECTROENCEPHALOGRAM (EEG): BRAIN WAVES

ELECTROOCULOGRAM (EOG): EYE MOVEMENT

ELECTROMYOGRAM (EMG): MUSCLE TENSION

(a) δ θ EMG BAND BAND BAND AWAKE

0.5 4 8 ~ ~ 100 200

REM SLEEP

0.5 4 8 ~ ~ 100 200

AVERAGE SIGNAL POWER NREM SLEEP

0.5 4 8 ~ ~ 100 200 INPUT SIGNAL FREQUENCY (HZ) (b)

Figure 2.7: (a) Placement of different head sensors used for polysomnography (PSG). (b) Ap- proximate average signal power in the δ (cortex) and θ (hippocampus) EEG bands, and the EMG band during different sleep stages.

report. Currently-available PSG sensors are rather bulky, power consuming and susceptible to noise and cannot be directly integrated in wearable devices. Table 2.2 summarizes and compares the existing sleep stage monitoring sensory methods introduced in this section. As will be shown in the next sections, the algorithm suitable for implantable and wearable sleep stage classiﬁcation proposed here is derived from the gold standard polysomnography sensory method and achieves a classiﬁcation accuracy of over 93%. CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 62

Table 2.2: Summary of sensory methods for sleep stage monitoring

Actigraphy Autonomic Nervous Polysomnography (ACT) System (ANS) (PSG)

Stages Classiﬁed Awake/Sleep Awake/Sleep REM/NREM All Stages [134–138] [150] [153] Sensory Signal Types Motion & Heart Rate, Blood EEG, EMG & Acceleration Pressure, Skin EOG Conductance, Respiratory Result Interpretation Automatic Automatic Medical Medical Professional Professional Classiﬁcation Accuracy <40% >90% <50% Gold Standard

Invasiveness No No Yes Implementation Wireless Multiple Electronic Multiple Bulky Headset Modules & Wires Sensors & Wires

2.2.3 Review of Sleep Classiﬁcation Algorithms

Due to the high accuracy of PSG-based monitoring, the vast majority of reported sleep stage classification algorithms are based on this sensory method. In this section, first, we review various PSG-based algorithms implemented in software, and then describe hardware implementations of several existing classifiers that employ full or a partial PSG-based sensory system. The section ends with a discussion on challenges in hardware implementation of a PSG-based classification system, and a proposed viable solution.

Software-Implemented Algorithms

Diagnostics of sleep disorders requires extracting information about one or a few specific sleep stages, which might include duration of the stage, and EEG/EMG time- and frequency-domain activity during that stage [125, 127]. As a result, the goal of CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 63 the majority of sleep classification algorithms reported in the literature is to detect all the sleep stages that happen during a full sleep cycle with the highest possible accuracy [125–127,129]. This level of specificity and accuracy requires either an increment in the number of input sensory signals, or a high level of computational complexity of the algorithm used, or both. In [125], a time-frequency image (TFI) of EEG signals are used to perform sleep stage classification. The TFIs are segmented based on the frequency bands in order to extract features that are later used as inputs of a multi-class least squares support vector machine (MC-LS-SVM) with different kernel functions. Different kernels were compared in terms of their accuracy in sleep stage classification. The reported SVM can classify all 5 sleep stages with an overall accuracy of 88.47%. In [126], wavelet packet coefficients and artificial neural networks (ANN) are applied to a pre-recorded EEG dataset to conduct sleeps stage classification. As it is reported in the paper, REM and stage1 of NREM sleep are indistinguishable using EEG signals only. As a result, the method that has been used can only classify awake, stage1 + REM, stage 2 and the slow wave stage, but with a high average accuracy of 93%, thanks to the sophisticated ANN used. In [127], an 18-channel polygraph is used for sleep classification that includes five EEG channels, EOG for REM detection, tonic chin and diaphragmatic EMGs, electrocardiogram (ECG), body movement detection of upper and lower limbs using piezo- electric crystal transducers, abdominal respiratory movements using a mercury strain gauge, and nostrils airflow, by means of a thermistor. A neuro-fuzzy classifier (NFC) of sleep-wake states and stages was trained, validated and tested on an offline dataset of 14 healthy infants of ages 6 months old and onward. After training with 7 datasets and validating with another 2 datasets, the NFC is tested on 5 datasets and can classify all sleep stages with an overall classification accuracy of 84%. CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 64

In [129], an SVM with a Gaussian radial basis kernel is used to classify between NREM and paradoxial sleep. ECoG and EMG signals are recorded from 6 rats and several time- and frequency-domain features are extracted from the recordings. Thanks to the computationally-sophisticated SVM used, an average 96% classification accuracy is achieved. Besides the classification algorithms described above, there is a second group of algorithms mostly aimed at detection of a specific stage and are optimized for both simplicity and performance at the same time. These systems typically rely on simple mathematical functions applied on a feature that is extracted from one or a few physiological recording types to detect the target sleep stage. Two examples of such systems are reported in [152, 154], in which both algorithms are aimed at classification between REM and NREM sleep without any further information on different NREM stages. Both works use simple mathematical computations for detection, and report high detection accuracy of above 88%. The details of each algorithm are described in Section 2.2.4. Since a hardware implementation (for low latency) of a REM sleep detection algorithm is the main goal of our work, simplicity of the algorithm is of an equal importance to its detection accuracy. As a result, the algorithm proposed in this paper falls within the second group described above, which are aimed at performing a high-accuracy classification of a subset of sleep stages using a simple hardware-implementable method.

Hardware-Implemented Algorithms

There are only a small number of hardware implementations of sleep stage classification algorithms reported in the literature. In [146], a PSG-based fuzzy neuro generalized learning vector quantization (FNGLVQ) is used on EEG and ECG signals to perform CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 65 sleep stage classification. The algorithm is implemented on a high-end Xilinx Spartan- 3AN XCS700AN FPGA with an average power consumption of 40mW and yields a 68.8% classification accuracy and a 790ms delay. The delay is mainly due to the fact that the main part of the algorithm is implemented in software (due to limited resources available on the FPGA) and the FPGA is required to send the signals to a computer for classification after performing some basic arithmetic operations. Although four different sleep stages are classified, neither the power consumption nor the delay meet the requirements for a battery-powered implantable or wearable device for sleep classification. To implement a classification algorithm within the power and resource limits of a miniature device, the majority of reported systems only use a subset of PSG sensory signals. However, the system performance in sleep stage classification highly depends on the selected subset of sensory signal types. In [147], a portable sleep stage classifier is reported that works with signals from one lead of ECG (three electrodes) as inputs. The device is capable of differentiating between sleep and awake stage using a random forest algorithm implemented on an ATMEL microcontroller. The reported average classification delay is 20 seconds. Another ECG-based multi-lead wearable system for monitoring patient sleepiness (i.e., asleep versus awake only) is presented in [150]. The system is comprised of three ECG gel electrodes, EMG and EOG electrodes, inductive belt sensor, three electronic modules, and a NiMH battery. It is tested on multiple users and yields a 85.3% classification accuracy. When the goal is to detect more than one non-awake sleep stages, EEG must be included in the selected subset of PSG sensory signals. As shown in Fig. 2.7(b), the θ (4-8 Hz) oscillations from the hippocampus EEG are the most prevalent during the REM sleep and awake stages, and the δ (0.5-4 Hz) oscillations from the cortex EEG are found during NREM sleep. In addition, neck muscle EMG high-frequency oscillations CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 66

WIRELESS RADIO INTERFACE

WEARABLE CLASSIFIER DIGITAL VLSI CLASSIFIER RESPONSIVE NEURAL

STIMULATOR K

LOW-NOISE R

AMPLIFIER O

H W

EEG1 EEG2 T

C O

EMG

NECK

O N MOUSE F BRAIN

Figure 2.8: A simpliﬁed block diagram of the VLSI (very-large-scale integration) sleep stage classiﬁer with an envisioned closed-loop neurostimulator for REM-sleep suppression.

(100-200 Hz) can be used to distinguish between the REM and awake stages. This motivates for an algorithm that classifies sleep stages based on the extracted frequency components of the recorded EEG and EMG signal in three different bands. This algorithm must be compact enough to be implemented on a low-weight and low-power device with a system architecture such as the one depicted in Fig. 2.8. As shown, the device has three low-noise sensory channels for physiological signal recording, and a digital back-end processor for algorithm implementation. To make the device untethered, it is equipped with a wireless module that transmits data for storage or further processing, and receives commands for system reconfiguration. Embedding responsive stimulation capability into such a device enables REM sleep suppression for the purpose of improving the memory consolidation process, and realizes a promising therapeutic option for the treatment of neurological disorders such as Alzheimer’s disease. While the full system is shown in Fig. 2.8, this work focuses on the wearable classifier only. CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 67

2.2.4 Algorithm Comparative Study

A low-complexity algorithm proposed by our collaborators is selected to be used for sleep stage classification. The algorithm works based on the fact that the three filtered physiological signals provide enough information to distinguish between three stages of awake, REM, and non-REM sleep as it was described in the previous section and illustrated in Fig. 2.7(b). It is first implemented in MATLAB together with two best-performing REM-detection algorithms from the literature [152,154]. Their performance is compared using an off-line sleep dataset as the input. The three algorithms selection was based on the following criteria, besides performance: the use of rodent physiological signals as inputs (for fair comparison) and low computational complexity (all perform classification by evaluating simple mathematical functions on extracted signal spectrum information as needed to be implementable on a low-power FPGA).

Three Selected Algorithms

Algorithm A The ﬁrst algorithm, shown in Fig. 2.9, was originally proposed in [152], and uses a locomotion sensor, EEG, and EMG signals. The power spectrum of the EEG signal is analyzed using FFT with a Hanning window to extract amplitude of the delta and theta waves. Similarly the θ-band EEG activity during awake and REM stages makes them indistinguishable using EEG only. As a result, EMG signals are also used, and comparing the magnitude of the delta wave, the ratio of θ/(δ+θ), and the integral of the EMG signal to different threshold values, the system classiﬁes NREM, REM, and awake stages. The locomotor signal is used to distinguish between active and quiet awake stages. CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 68

LOCO- EEG f f EMG MOTOR L H δ 0.5 4 θ 48 f f INTEGRAL L H δ,θ δ

θ > V NO δ > V NO >V NO>V NO th1 th2 δ+θ th3 th4 YES YES YES YES

ACTIVE QUIET NREM REM AWAKE AWAKE

Figure 2.9: Algorithm A: Signal flow chart of the first sleep-stage classification algorithm originally reported in [152].

f f EMG EEG L H δ 0.5 4 θ 48 f f α 815 10 100 L H β 16 31 γ 32 100

NO δ α NO θ2 NO >V >V >V th1 β γ th2 δ α th3 YES YES YES

ACTIVE QUIET NREM REM AWAKE AWAKE

Figure 2.10: Algorithm B: Signal ﬂow chart of the second sleep-stage classiﬁcation algorithm originally reported in [154]. CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 69

HIPPOCA- EMG CORTEX MPUS EEG EEG

θ δ 100 200 4 8 0.5 4

WINDOW WINDOW WINDOW AVERAGING AVERAGING AVERAGING

θ > V NO >V NO th1 δ th2 YES YES

AWAKE REM NREM

Figure 2.11: Algorithm C (proposed): Signal flow chart of the sleep-stage classification algorithm proposed here implemented in MATLAB. (Algorithm implementation and testing was done by A. Chemparathy). Algorithm B This algorithm which was first introduced in [154] is shown in Fig. 2.10. It compares the filtered EMG signal against a threshold value to detect the active wake stage, characterized by high EMG activity. To classify between the remaining stages, it filters the EEG signal to obtain δ, θ, α, β, and γ band components. Two ratios are calculated and compared with their respective thresholds to classify NREM, REM, and quiet wake stages.

Algorithm C (proposed) In the third algorithm, proposed in this work and shown in Fig. 2.11, three signals are acquired: one EEG signal from the hippocampus, one EEG signal from the cortex, and one EMG signal from a neck muscle. The EEGs from the cortex and hippocampus are filtered to obtain the signal components in the δ and θ bands, respectively. The EMG signal is also filtered between 100Hz to 200Hz. All three filters are fourth-order Chebyshev filters with 0.5 dB peak-to-peak passband CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 70 ripple. The filtered signals are passed through a window averaging block to obtain the mean amplitude of each signal to avoid instantaneous misclassifications. A ratio of the two filtered EEG signals (θ/δ) is then taken and compared with a patient-specific threshold value to distinguish between NREM and REM sleep. The EMG signal is also compared against another threshold value for awake stage detection.

Data Collection

To compare the performance of the three algorithms, they were initially implemented and tested in MATLAB using the EEG and EMG signals that were collected from nine mice, and labeled by a trained sleep neuroscientist as described below:

Animals Nine male C57 mice (from Charles River Lab, Quebec, Canada) were used in the experiments. The entire experiment was reviewed and approved by the animal care committee of the Douglas Health Institute (Montreal, Canada) according to the Canadian Guidelines for Animal Care.

Electrodes Tetrode electrodes were composed of 17.5μm diameter platinum-iridium wire (platinum:iridium 90%:10%) with Teﬂon and VG bond coating (California Fine Wire company, Grover Beach, CA, USA), for insulation and heat-induced annealing, respectively. Epoxy served to insulate any exposed wire at the connection point with the electrode interface board. The annealed tip of the tetrode was cut using sharp scissors immediately prior to surgery to give an impedance of 1 MΩ.

Surgery At 18 weeks age, injected mice were anesthetized with isoflurane (5% induction, 0.5-2% maintenance). The skull was completely cleared of all connective tissue and thoroughly dried using alcohol. For hippocampal electrode placement, a hole was drilled through the skull above the dorsal hippocampus (AP, -2.45; ML, +1.8), with the CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 71 end target being the dorsal hippocampal CA1 pyramidal cell layer. An EEG screw was placed in the skull above the hippocampus in the contralateral hemisphere (AP, -2.3; ML, -1.35). An EMG electrode consisting of stranded tungsten wires (A-M Systems, WA, USA) inserted into the neck musculature was used to record postural tone. Screws placed in the bone above the frontal cortex and cerebellum served as ground and reference, respectively. Following surgery, mice were allowed to recover undisturbed for at least 1 week. Once mice had sufficiently recovered from surgery they were briefly anesthetized with isolflurane (5% induction, 2% maintenance) and a custom-built headstage pre-amplifier tether (Neuralynx, Inc., Boseman, MT, USA) was attached to a connector on the top of the implanted electrode interface board and secured with several small drops of epoxy.

Scoring Recordings began only after mice were habituated to being chronically teth- ered. All recorded signals from implanted electrodes were amplified by the headstage pre-amplifier tether before being sampled and digitized at 16000 Hz. For scoring of behavioral state recorded data from hippocampal LFP, EEG and EMG electrodes, each raw data file was first imported into MATLAB (MathWorks, Natick, MA, USA) and downsampled to 1000 Hz. Data was then plotted and the vigilance state was manually scored in 5s epochs. Scoring was based on visual characteristics of the hippocampal LFP, EEG and EMG data as well as fast Fourier transform analysis of each epoch scored. Wakefulness was defined by a de-synchronized low-amplitude EEG and hippocampal LFP and tonic EMG activity with periods of movement-associated bursts of EMG activity. NREM sleep was defined as synchronized, high amplitude, low- frequuency (0.5-4 Hz) EEG and hippocampal LFP activity that was accompanied by reduced EMG activity relative to that observed during wakefulness. REM sleep was defined as having a prominent theta rhythm (4-8 Hz) and an absence of tonic muscle CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 72 activity.

Comparative Study Simulation Results

The outputs of the three algorithms implemented in MATLAB using the data collected as described above are shown in Fig. 2.12. The first and second plots depict the two EEG signals from the hippocampus and the cortex, respectively. The third plot shows the filtered EMG signal from the neck. The fourth plot is the hypnogram, which is the result of manual sleep-stage scoring by a trained sleep neuroscientist as described in section 2.2.4 and is the reference against the output of various algorithms. The remaining six plots show the outputs of the three algorithms, A, B, C, and their corresponding average cumulative error calculated from point-to-point comparison with the hypnogram. The selected algorithms are patient variant and the threshold values must be tuned for a new subject. For every new subject, 10% of the data points are used for training and optimized selection of threshold values for the best performance, while the remaining 90% is used for testing the algorithm. One trained, the algorithms performance was consistent through the whole dataset. The REM detection sensitivity, accuracy, and specificity are defined to evaluate each algorithm’s performance, and compare it to the state of the art as follows: True positives (TP): REM stage is correctly classified as REM. False positives (FP): NREM or awake stages are classified as REM. True negatives (TN): NREM or awake stages are correctly classified as NREM and awake, respectively. False negatives (FN): REM stage is classified as NREM or awake. Sensitivity: the ratio of TP to TP + FN. Specificity: the ratio of TN to TN + FP. Accuracy: the ratio of TP to TP+TN. The third algorithm, algorithm C, was chosen for hardware implementation because of its low complexity and better performance in terms of REM sleep stage detection average error. CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 73

V) 0.1 m 0 HIPPO-

CAMPUS −0.1 EEG (

V) 0.1 m 0

CORTEX −0.1 EEG (

0.04 V) 0.02 m 0

NECK −0.02

EMG ( −0.04 REM

NREM GRAM HYPNO- AWAKE ALGORITHM A REM

A NREM

OUTPUT AWAKE 100

AVERAGE 0 ERROR A (%) ALGORITHM B REM

B NREM

OUTPUT AWAKE 100

AVERAGE 0 ERROR B (%) ALGORITHM C (PROPOSED) REM

C NREM

OUTPUT AWAKE 100

AVERAGE 0

ERROR C (%) 0 100 200 300 400 500 600 700 800 900 1000 TIME (SECONDS)

Figure 2.12: A 15-minute sample simulation results of the three classiﬁcation algorithms implemented in MATLAB, with their corresponding average error compared to the hypnogram. Simulation results were acquired with A. Chemparathy’s assistance. CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 74

The three algorithms have been compared in terms of their REM sleep detection sensitivity, specificity, and accuracy with each other as well as with all the algorithms described in section 2.2.3, with the comparison results summarized in Table 2.3. In addition to the classification results reported in [152, 154], the algorithms from these works, which were described in section 2.2.4, were also simulated in MATLAB with our animal dataset for a more precise comparison. Based on this comparison, the proposed algorithm, Algorithm C, yields superior classification performance compared to the algorithms reported in the literature.

2.2.5 Electronic Implementation of Algorithm C

As mentioned in section 2.2.1, to stimulate efﬁciently for REM sleep suppression, the REM sleep detection latency has to be less than 1% of the θ-oscillation period (125- 250ms). This motivates for an FPGA-based digital implementation to avoid long delays caused by a data acquisition module and a computer that are required for software-based implementations. A rodent-wearable miniaturized device including a multi-channel physiological signal recording front-end and a digital signal processing FPGA back-end that implements algorithm C described in the previous section has been developed and is presented next. The device also has a wireless transceiver to communicate recorded signals and classiﬁcation results to a computer base-station.

Hardware Implementation

The neural interface design is based on an integrated circuit (IC), that was first reported in [2]. It is used in this system and is configured to perform three-channel signal recording. The rest of the channels are shut off in the case of the application discussed in this section to keep the focus (but can be used for simultaneous monitoring of other signals and for neurostimulation). The IC is what was described in the previous section (Fig- CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 75 & FFT NREM W, REM, Multi-band thresholding & FFT NREM W, REM, Multi-band thresholding As simulated in MATLAB & 96.4 84.3 93.9 84.3471.02 82.54 66.75 93.1 82.9 FFT 9 mice 9 mice 9 mice NREM A [152] B [154] C (Proposed) W, REM, EEG, EMG EEG, EMG EEG, EMG thresholding Motion sensor & EEG, EMG 14 rats Filtering thresholding REM, NREM Active/Quiet W, & FFT NREM 10 rats, 23 mice W, REM, locomotion EEG, EMG, thresholding Motion sensor 96 90.0-90.9 87.9 > NREM SVM 6 rats EMG ECoG, W, REM, 1 5 S1, S2 fuzzy Neuro infants system W, REM Comparison with the existing software-based sleep classification methods 7 S1, S2 ANN adults W, REM 8 Table 2.3: N/R 84.2 N/R N/R N/R N/R N/R 94.4 N/R N/R N/R N/R EEG EEG PSG 88.47 93.0 83.9 adults S1, S2 W, REM LS-SVM TFI, MC- Dataset Method Data Source As reported by authors Reference [125] [126] [127] [129] [152] [154] Signals Used Accuracy (%) Sensitivity (%) Specificity (%) Stages Classified Data for training, validation andTR: test Transition-to-REM datasets (14 infants in total) was reported. In this table only test data is shown. N/A: Not applicable N/R: Not reported 1 2 CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 76

8 NEURAL ADC EMG AMPLIFIER

CORTEX FPGA

HIPPOCAMPUS NEURAL 8 DAC

STIMULATOR (SIGNAL PROCESSING) DEMUX MUX

DEPTH ASIC ELECTRODES WIRELESS TRANSCEIVER

Figure 2.13: Simplified hardware implementation of the small-scale VLSI-based sleep-stage classifier. ure 2.3). Fig. 2.13 shows the system-level block diagram of the multi-channel recording module. The system performs monopolar recording and uses Molex connectors to interface with the microelectrodes. As shown, the outputs of the recording channels are digitized (8 bits) and multiplexed and sent to the on-board FPGA for signal processing. The FPGA also controls a DAC (digital-to-analog converter) module that generates multiple bias voltages for the chip and configures stimulation parameters. Additionally a separate FSK transceiver PCB of the same size is stacked with this system to provide a wireless link that communicates the diagnostic data and classification results to a computer. The wireless link can also be utilized to receive commands to configure the system mode of operation. The system also has a current-mode neurostimulator capable of delivering biphasic charge-balanced pulses within the standard safety limit [11].

Algorithm Implementation

Hardware implementation of the algorithm minimizes classification time and makes the system capable of low-latency recording, detection and, if needed, closed-loop stim- CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 77 ulation. For a rodent-wearable device, the trade-off is the limited resources (logic elements) available on a low-power FPGA compared to the computational power of a computer, or even a high-end FPGA typically used in bench-top systems. For filter implementation, FIR topology was chosen over IIR due to the high sensitivity of IIR coefficients which makes the algorithm performance susceptible to noise. 64-tap FIR filters were chosen for FPGA implementation, as MATLAB simulation results showed that this is the minimum number of taps required to achieve the same level of REM detection accuracy as with the ideal filters. Synthesis and fitting analysis showed that among all the blocks, the FIR filter used the largest number of gates. To fit the algorithm in the FPGA, a single filter (with variable coefficients) was time-shared among three input channels. For this reason the clock frequency of the FPGA (40 MHz) was chosen to be much higher than the sampling rate of the input signals. Additionally, to further improve filtering performance, and consequently detection accuracy, every input channel was filtered twice using the same filter. A block diagram of the hardware implementation of algorithm C is shown in Fig. 2.14, depicting how the input channels are sharing and reusing the FIR filter. The first multiplexer is used to time-share the FIR filters among the three channels, and the second one is used to select whether to filter a new signal or re-filter the previous one for better band selectivity. The control block sends appropriate commands to control the logic and timing of each block. Following the band-pass filter, the three channels are averaged over a moving window with an adjustable size. As this requires significantly less resources compared to FIR filtering, a separate window averaging block is implemented for each channel, which results in lower classification latency (due to no time sharing), and also allows for a different window size for each channel. CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 78 REM NREM AWAKE th1 th2 V V θ δ δ θ EMG ∑ -1 Z -1 Z -1 Z WINDOW AVERAGING WINDOW SIZE

-1

Z DEMUX TIMING/LOGIC CONTROL BPF 64-TAP FIR

MUX

MUX FPGA VLSI architecture implementation of the presented sleep-stage classiﬁcation algorithm. FPGA implementation and opti- EEG EEG EMG NECK CORTEX HIPPOCAMPUS mization were done with the assistance of A. Chemparathy and P. Li, respectively. Figure 2.14: CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 79

100 95

90 90 PERCENT 85 OVERALL AVERAGE REM ACCURACY REM SENSITIVITY REM SPECIFICITY OVERALL AVERAGE (%) 80 85 1 2 3 4 5 6 7 8 9 10 WINDOW SIZE (Sec)

Figure 2.15: Effect of the averaging window size on the sensitivity, speciﬁcity and accuracy of the REM sleep detection.

2.2.6 Proposed Algorithm Results

Simulation Results

To further enhance the performance of the proposed algorithm, the window averaging block was optimized for REM sleep detection. The window length used is a trade-off between sensitivity and specificity. A longer window allows for a larger portion of the signal to be analyzed, increasing the specificity of the detection, while a shorter window increases the sensitivity of the detection. In Fig. 2.15, the relationship between window size, accuracy, sensitivity, and specificity is shown. The average value of the three measures was used for overall performance optimization, which resulted in a window size of 8 seconds.

Experimental Results The algorithm was implemented on an Actel IGLOO FPGA and tested with data from 9 different mice. The FPGA has an average total power consumption of 0.346mW, but only has 1500 logic elements for the algorithm implementation. With the algorithm optimizations done for hardware implementation, it uses 1317 logic elements (85.74% CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 80

REM HYPNOGRAM NREM AWAKE

REM MATLAB OUTPUT NREM AWAKE

REM FPGA OUTPUT NREM AWAKE

1 FPGA

ERROR 0 OUTPUT

100 50 AVERAGE

ERROR(%) 0 0 50 100 150 200 250 300 350 400 450 500

TIME (S)

Figure 2.16: Sample simulation results of the presented classification algorithm implemented on an ACTEL FPGA, with the corresponding average error when compared to the hypnogram. Measurement results were acquired with A. Chemparathy’s assistance. CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 81 of total), four on-chip RAMs to store 64 signal samples (one for the FIR filter and three for the averaging filters) and a flashROM to store filtering coefficients. Fig. 2.16 shows a nominal sample output of the FPGA implementation for a 9- minute recording, compared with the reference hypnogram and software implementation results. The first plot is the hypnogram, which was described previously and is the reference against the output of classification algorithm. The second and third plots depict the classification output of the software and hardware implementation of the proposed algorithm, respectively. The fourth and fifth plot show the instantaneous and cumulative average point-to-point errors of the FPGA implementation results compared with the hypnogram, respectively. The system needs 1562 clock cycles for every sample to generate an output which translates into 39μs latency using a 40 MHz FPGA clock. Table 2.4 shows the accuracy, sensitivity and specificity of the presented implementation compared to the other hardware-based implementations described in section 2.2.3. In addition to classification performance, they are also compared in terms of the sensory signals used, the classification method, and their classification latency. The presented system yields the smallest latency, while exhibiting a comparable level of accuracy, sensitivity and specificity. It also has the smallest size as needed for a rodent-wearable device.

2.2.7 Conclusion

A low-latency, small-form-factor microsystem for sleep stage classiﬁcation and REM sleep detection is presented. Three EEG and EMG signals are utilized to classify REM, NREM, and awake stages. The FPGA implementation is optimized to reduce complexity and power consumption while maximizing REM sleep detection performance. Experimental results show a REM detection sensitivity and speciﬁcity of 81.69% and 93.86%, respectively. A low latency of 39 μs has been achieved, which is a critically CHAPTER 2. BOARD-LEVEL IMPLEMENTATION OF IMPLANTABLE WIRELESS MICROSYSTEMS 82

Table 2.4: Comparison with hardware-based sleep classiﬁcation devices

Reference [147] [146] [150] This work W, W, W, S1,S2, W, Stages classiﬁed REM, Non-wake SWS, Sleep NREM REM ECG, EEG, Signal(s) used ECG ECG Resp. EMG

Random FFT, Filtering+ Method FNGLVQ forest ANN thresholding

Accuracy (%) N/R 68.8 77.8-89.0 81.66

Sensitivity (%) 94.2 N/R N/R 81.69

Speciﬁcity (%) N/R N/R 91.9 93.86

Computation time (ms) 20k 790 3.751 0.039

Real-time Yes No N/A Yes

Order of ﬁlter 3 N/A N/A 64

Dataset 10 adults 10 adults 6 adults 9 mice

N/A: Not applicable N/R: Not reported 1 Estimated value. Algorithm is not implemented due to high power consumption. important design requirement for a closed-loop sleep control systems. Such a system can be used for studies aimed at determining the effects of REM sleep suppression on memory consolidation. 83

Chapter 3

Battery-Less Tri-Band-Radio Neuro-Monitor and Responsive Neuro-Stimulator IC for Diagnostics and Treatment of Neurological Disorders

3.1 Introduction

This chapter presents a 16 mm2 0.13 μm CMOS SoC. The chip has 64 DC-coupled neural recording channels, each with a digitally-assisted DC-offset cancellation feedback. Chopper stabilization is employed in each neural amplifier to suppress its flicker noise. Channel-to-channel gain mismatch is removed by utilizing a multiplying ADC, included in each channel, in a digital calibration loop. A multi-core digital processor shared between all the channels, is used to carry out signal feature extraction and CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 84 epileptic seizure detection. The chip also has 64 programmable bi-phasic current-mode stimulators that are triggered by the on-chip digital processor upon detection of a neurological event, to modulate brain activity. Three wireless transmitters are included in the design that enable communication of diagnostic data to a wide range of distances over three different bands of frequency. The chip is powered wirelessly using a magnetic inductive link, with energy signals that are amplitude shift-keyed to communicate configuration commands to the chip. The chip is validated in-vivo on four freely-moving rats and off-line on three human patients. The rest of the chapter is organized as follows. Section 3.2 describes the motivation for the work presented in this chapter and briefly compares it with the previous generation of the closed-loop neurostimulator presented in the previous chapter. Section 3.3 discusses the VLSI architecture of the neurostimulator SoC. Section 3.4 presents the circuit implementation of the key functional blocks in the SoC. Section 3.5 presents electrical experimental results from individual blocks as well as the full system. Sec- tion 3.6 presents in-vivo online animal epilepsy seizure detection and treatment results and offline human epilepsy seizure detection results. Section 3.7 discusses resource utilization and comparison with the state-of-the-art.

3.2 Motivation

The main motivation for the design presented in this chapter is to integrate all the major blocks of the mini-PCB stack, presented in the previous chapter, on a single chip (except for the antennas used for wireless power/data). This makes the system form factor an order of magnitude smaller while keeping all the system level advantages. Also, as it will be described, the ac-coupled front-end architecture of the system described in the Chapter 2 prevents the channel area and input-referred noise to be CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 85

ELECTRODE ARRAYS RESPONSIVE NEUROSTIMULATOR

V1 OFFSET-CANCELLED CHOPPER-STABILIZED NEURAL RECORDING V64 CHANNEL I1 CURRENT-MODE QUAD-CORE

I64 STIMULATOR LOW-POWER DSP TRI-BAND DATA RADIO 10cm DUAL-BAND UWB TRANSMITTER (3.1-10.6 GHz) 1m UWB RECEIVER UWB TRANSMITTER (<1 GHz) FSK 10m RECEIVER FSK TRANSMITTER (916.4 MHz)

POWER AND COMMAND RECEIVER POWER POWER 1.5 MHz POWER RECEIVER TRANSMITTER

ASK COMMAND 1.5 MHz ASK COMMAND RECEIVER TRANSMITTER COMMANDS

Figure 3.1: A simpliﬁed functional diagram of the presented neurostimulator SoC and peripheral blocks. smaller than a certain limit. To solve this issue, the recording channel is replaced with a digitally-assisted DC-coupled front-end design which resulted in smaller area per channel. Each channel is also chopper stabilized, resulting in lower ﬂicker noise. Finally in terms of application-level novelties, the presented system is validated in- vivo in a 500-hour chronic treatment of a rat model of temporal-lobe epilepsy, and the results of this long-term study are analyzed statistically.

3.3 System VLSI Architecture

A simpliﬁed functional diagram of the neurostimulator SoC is shown in Figure 3.1. An array of intracranially-implanted ECoG (electrocorticography) and depth EEG (electroencephalogram) electrodes connects to the 64 channels available on the chip for voltage recording and current stimulation. The recording front-end in each channel is CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 86

DC-coupled to one data electrode and the reference electrode (not shown in Figure 3.1 for simplicity). It utilizes chopper-stabilization for low-frequency noise suppression. The direct-coupled configuration allows for removal of large DC-blocking capacitors that are conventionally used in each channel [2, 5, 6, 10–13]. The amplified EEG signal is digitized using an ADC and is fed to an on-chip multi- core CORDIC-based signal processing unit that is shared among all channels, to cal- culate magnitude, phase and phase derivative of each recorded signal as well as phase synchrony among them. Upon early detection of an upcoming seizure, the on-chip processor triggers a programmable bi-phasic current-mode stimulation pulse-train generated by a subset of 64 stimulators with a spatio-temporal profile specifically chosen for a given subject (a rodent or a human patient). The chip is also equipped with three wireless transmitters with a different bandwidth, data rate and range of transmission to communicate the raw recorded EEG signal or the processor’s output. The 3.1-10.6 GHz UWB short-range transmitter communicates to an on-skin wearable receiver, The under 1 GHz UWB mid-range transmitter communicates to a hand-held receiver, and the 915 MHz FSK long-range transmitter communicates to an indoor stationary receiver. The whole chip is powered wirelessly using a cellular inductive link operating at 1.5 MHz. The same inductive link is utilized for sending configuration commands and clock signals to the chip. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 87

C2 1 f f3dB-OTA C1 R2.C2 − VREF A V +V + V = C1 (V -V ) IN OFF OUT C2 IN REF C1

R2 C2

(a)

V − REF VOUT = A (VIN-VREF) A VIN+VOFF + + GL V f OFF G .f f K LPF + L 1 3dB-OTA VOUT-DC

f1 (b)

Figure 3.2: Two types of input DC offset removal circuits: (a) AC-coupled closed-loop architecture and (b) DC-coupled open-loop architecture. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 88

3.4 VLSI Circuit Implementation

3.4.1 Neural Recording

DC-Coupled Recording Front-End

Figure 3.2(a) shows an ac-coupled closed-loop single-ended neural ampliﬁer. Different variations of such topology have been used in several works such as [12, 13] and [11].

In this topology the voltage gain is set by C1/C2 ratio, where C1 and C2 are the input decoupling and feedback capacitors respectively. Also the lower 3-dB bandwidth of the

1 amplifier is set by C2×R2 , and the decoupling capacitor is placed at the input to block the DC offset voltage. To prevent any significant signal loss in lower frequencies where majority of epilepsy-related brain activities occur (δ(<4 Hz), θ(4-7 Hz), α(8-15 Hz), and β(16-31 Hz) bands), the lower 3-dB bandwidth of the amplifier should be set to a maximum of 1 Hz. To meet this condition while maintaining a reasonably high voltage gain, and also to keep C1 in a reasonable range for on-chip implementation, C2 is typically chosen to be in the order of 100 fF, that forces Rf to have a very large value(>100GΩ).

Even with above considerations C1 is typically >10 pF, making it the most significant silicon area consumer on the chip considering that it is repeated twice in every channel. In addition, on-chip realization of a >100GΩ resistor is another design challenge in the ac-coupled closed-loop topology. Due to area constrains, passive implementation is impossible for such large resistors. Therefore, multiple active pseudo- resistor implementations are proposed in the literature [12, 13, 59] which despite their high-resistance, often suffer from nonlinear performance when a high-swing signal is applied across them (discussed in details in [59]). In addition to area, poor noise performance is another drawback of ac-coupled neural amplifiers. This is because conventional noise reduction methods such as chopper CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 89 stabilization cannot be used in this topology as it introduces new problems with input impedance. Chopping switches can either be inserted in front of the input decoupling capacitors or after them. If placed in front of the capacitors as suggested in [14], they will reduce input impedance of the amplifier and consequently degrade quality of signal recording. If placed after the capacitors ( [5, 6]), they form a switched-capacitor with the input parasitic capacitance of the amplifier. The equivalent resistance of this SC-circuit shapes the OTA thermal noise power with 1/f2 characteristics when referred to the input, and consequently increases flicker noise considerably. Based on the above discussion, removing input decoupling capacitor seems to be solving several problems at once. However the input DC offset that is now directly connected to the amplifier could result in output saturation. A substitute for input capacitors with minimum overhead area and power is required to remove this offset. Several solutions are suggested in the literature such as differential difference amplifiers ( [7, 61]), which are very effective in removing input DC offset but result in excessive area overhead or additional off-chip passive components. A capacitive-T topology is suggested in [156], that slightly reduces the channel area in cost of significant noise performance degradation. In [56] authors suggest using the electrode capacitance together with a huge resistive component to realize a high-pass pole. This technique removes the input decoupling capacitor and results in saving significant silicon area, but fails to control the high-pass pole accurately. Another option is to implement the front-end in a way that is shown in Figure 3.2(b). Here, the idea is to compare the amplifier’s output DC level with a reference value and feed the average of the difference (error) to the input. Such a loop realizes a low-pass transfer characteristics in the feedback path, which translates into a high-pass transfer- function in the feed-forward path. In this method, the neural front-end performance depends on where the feedback is applied and how it is implemented which is discussed CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 90

f f f M=1/γ Q 2 GL.f1 f2 VREF I γ DAC A LPF + V +V D =A(V -V )+Q IN OFF MADC OUT IN REF

DIGITAL + D I =I I-DAC REF DAC OFF LPF

f f1

Figure 3.3: Simpliﬁed block diagram of the presented open-loop DC-coupled front-end with digital feedback and gain calibration. (The ﬁrst version of this front-end is presented in [48]) in the next section.

Digitally-Assisted Feedback

Figure 3.3 shows the simplified block diagram of the proposed DC-coupled neural front- end with a digitally-assisted feedback loop for DC offset cancellation. As shown, output of the amplifier is fed to a multiplying-ADC (MADC). The multiplying capability of the ADC is only used when there is a channel-to-channel gain mismatch (gain mismatch is shown by a coefficient, γ, in Figure 3.3). The digital output of the ADC is then compared with a reference number that represents the mid-range voltage at the ADC input. The difference is integrated using a digital low-pass filter and then sent to a current- steering DAC that adjusts the biasing of the amplifier to cancel the input offset. Since the output of the ADC is used for DC offset cancellation, sharing it among multiple amplifiers [48] would cause an over 100 ms delay in order for the output to stabilize after switching from one channel to another. This delay is mainly due to the fact that the input DC offset varies among different channels, and its compensation is done gradually due to the long time constant of the digital low-pass filter in the feedback path. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 91

Every time the ADC is switched from one channel to another, the loop should operate for some time so that the digital LPF has integrated enough data points to compensate for the offset completely. During this settling time, the recorded brain signals would not be fully meaningful until the offset-cancellation loop is settled. As a result, a dedicated ADC is placed inside each channel to address the issue. The low-pass filter in the feedback is implemented digitally, that results in very small area and power overhead while providing a very well-controlled bandwidth. This is important as the digital LPF cut-off frequency, f1, causes a high-pass pole in the feed-forward path equal to GL×f1, where GL denotes the loop-gain. As a result, by adjusting f1 using filter’s coefficients, an undesired lower frequency range of the input (including DC) is blocked. As mentioned, the output of the integrator is then fed to a 4-bit current-DAC to apply appropriate corrections to the biasing of the input amplifier and consequently cancel the input DC offset. Figure 3.4 shows the circuit schematic of the neural front-end in more details. As shown, the low-noise amplifier uses a differential folded-cascode topology. As the decoupling capacitors are removed, the input DC offset could result in an imbalance in the differential-pair that leads to amplifier output saturation. In [3], authors cancel the imbalance caused by the input DC offset using a digitally-assisted feedback that adds/removes parallel transistors to/from the input differential pair. This method prevents amplifier saturation in cost of tuning input differential pair device size that leads to input-referred-noise variations. In other words, the noise performance becomes offset- dependent, forcing the designer to size the input pair for the worst-case (highest offset) and results in a significant unnecessary over-design for smaller offset values.

We present a feedback loop that applies a DC current to the folding node of the folded-cascode amplifier [48]. As shown in Figure 3.4 the ADC output is compared CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 92 CAL D DIGITAL OUTPUT 2 8 f 1 L.f CAL 8 REF D 8 FUNCTION 8 CALIBRATION 8 8 MADC M ADDED BLOCKS TO THE DESIGN REPORTED IN [47] 1 f LPF 2 f DIGITAL LPF 4 CMFB I-DAC I 2.4xI CASC V CASC_N V 2.8xI 40x4/0.5 + - IN V CASC_N CASC V Simplified circuit diagram of the chopper-stabilized neural recording front-end [48], with digitally-assisted offset cancellation and V 2.4xI I digital gain-mismatch calibration (The first version of this front-end is presented in [48]) Figure 3.4: 4x1/14x1/1 4x1/1 4x1/1 CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 93 with a reference value and the difference is averaged using a digital low-pass filter. The result is the error caused by the input DC offset that should be removed by injecting current to the folding node of the folded-cascode amplifier. The injected feedback current is set by a current-DAC and is adjusted in accordance to the amount of DC offset. Using this method the imbalance is canceled while noise and other performance characteristics of the front-end remain intact (the feedback will still impact the noise, however, as the feedback application point is the folding node of the folded-cascode amplifier, this impact will be insignificant when it is referred to the input).

Chopper Stabilization

As shown in Figure 3.4, chopper stabilization is used at the input to reduce the input- referred noise of the neural front-end. Thanks to the DC-coupled inputs, there is no need for an extra complex auxiliary circuit such as impedance boosting block at the input. A set of chopping switches is the only additional components that should be added in the feedback injection node (folding node of the ampliﬁer). This is because the input DC offset is up-converted after the input chopper and the offset-cancellation feedback should also be up-converted to ensure the two signals are always out-of-phase, or in other words, feedback is always negative.

Gain Calibration

As input decoupling capacitors are removed, open-loop configuration is chosen for the front-end gain-stage implementation. Unlike the closed-loop configuration, open-loop voltage gain is not very well-controlled and changes with process, supply and temperature variations. This results in a considerable channel-to-channel gain mismatch that leads to significant error in signal processing results and consequently less accurate seizure detection. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 94

An MADC in conjunction with a calibration feedback loop is used to set the total gain of the front-end (Amplifier+ADC) to a constant value for all of the channels. Fig- ure 3.4 illustrates how the gain calibration loop and the MADC are connected with the rest of the recording front-end. Since the SoC is designed to be implanted in the patient body, temperature variations are expected to be very small, making the process and supply variations more important factors. The SoC goes to the calibration mode only after long periods of recording (Calibration is started manually in the beginning of every measurement where all the channels are connected to the same input and the calibration unit calculates the proper multiplicand for each channel.) Once in the calibration mode, same input is applied to all of the channels and their digital output is compared to a reference 8-bit number that represents digital translation of the input amplitude multiplied by the desired gain. An off-chip calibration module implemented on FPGA calculates new coefficients for the MADC to make the digital output of all channels equal to the reference. Figure 3.5 shows the simplified block diagram of the multiplying SAR ADC. The multiplication is performed in the sampling phase and requires an overhead of only three logic gates per bit [13]. When multiplying is not required, the MADC operates as a normal SAR ADC. However, when it is in the multiplying mode, the SAR digital controller selects a subset of capacitor bank based on the 8-bit coefficient set by the calibration function. These capacitors will be the only ones connected to the input voltage during the sampling phase and the rest will be connected to the ground. Using this strategy, input voltage is multiplied by a number between zero and one that can be adjusted by 8-bit accuracy. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 95

V CM

S M VIN CC 2C 64C

V S IN V REF LOGIC

7 MULTIPLY M=∑M 2 -i-1 i SSM M1 SM7 i = 0 0 bit0 bit1 b it7 8 M V + Q CLK 8-BIT SAR REGISTER IN

Figure 3.5: Simpliﬁed block diagram of the multiplying ADC originally reported in [2], utilized for gain mismatch calibration (Q is quantization noise).

Closed-loop Neurostimulation

The digital output of the neural recording channels are fed to an on-chip custom-made CORDIC-based digital processor that calculates magnitude, phase and phase-derivative of signals from each channel as well as phase-synchrony between channels. The phase- synchrony is used for early detection of epilepsy seizure onset [160]. To abort a seizure, the digital processor triggers a subset of current-mode neural stimulators upon detection. The current-mode neurostimulator in each channel (originally presented in [2]) is capable of providing bi-phasic current pulses to the brain with programmable amplitude (0.01-1 mA), duty cycle, and frequency. The choice of stimulation parameters and stimulation pattern came from one of our earlier studies on in vitro [86] and in vivo [93] which demonstrated that early stimulation at seizure onset could prevent a seizure. The stimulation current and pulse width were chosen according to CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 96

t0t1t2 t0t1t2 t0t1t2 CTL CTL CTL C ANTENNA CTL CTL CTL CTL CTL CTL C

CTL CTL CTL CTL CTL CTLCTL C

CTL

DATA IN (MANCHESTER ENCODED)

Figure 3.6: Circuit schematic of the UWB transmitters with a tunable bandwidth originally reported in [166]. CTL controls the output pulse bandwidth by controlling the delay of each inverter cell. safety considerations [161] (three times lower than the maximum deliverable charge per phase [10]). The seizure formation was effectively aborted using low-frequency stimulation by means of the neural inhibition mechanism [92], which could be similar to that of anti-epileptic drugs [162].

3.4.2 Wireless Transmitters

Three wireless transmitters are designed and implemented on-chip to cover a wide range of applications. The ﬁrst and second are both ultra-wideband (UWB) transmitters with a difference in their operating frequency, data-rate and range of transmission. The UWB transmitter circuit schematic is shown in Figure 3.6. UWB pulse bandwidth is controlled by tuning the delay of current-starved inverters using a control voltage. The ﬁrst transmitter operates in the 3.1-10.6 GHz range and has the highest data-rate (45 Mb/s) measured at 10 cm which is the smallest range among three. The transmitter communicates to an on-skin receiver located very close to the implant. Due to its high data-rate, it can be turned off for a long period of time, and transmit buffered data using CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 97

DATA ANTENNA (MANCHESTER POWER REF CLK ENCODED) AMPLIFIER CHARGE LOOP PFD PUMP FILTER VCO

DIVIDE BY 64

Figure 3.7: Simpliﬁed block diagram of the FSK transmitter operating at 916.4 MHz, originally reported in [13]. a few bursts. The second transmitter operates in <1 GHz range and has a maximum of 10 Mb/s data-rate measured at 1 m. This transmitter is designed to communicate neural data at a reasonably high data-rate to a hand-held receiver located at a maximum of 1 m distance from the implant. The third transmitter which is shown in Figure 3.7 utilizes a Manchester-encoded FSK modulation scheme with carrier frequency at 916.4 MHz. It beneﬁts from a closed- loop PLL that prevents carrier frequency drift and allows avoiding an off-chip passive component for tuning. The transmitter has a 1.5 Mb/s data-rate (for both data and address bits) measured at maximum of 10 m which results in a 1.5 kS/s data rate for neural data of each channel when all 64 channels are used, and higher data-rate when fewer number of channels are used. The 10 m range of this transmitter connects the SoC to a stationary receiver connected to a computer in the room.

3.4.3 Inductive Power and Command Telemetry

To enable in-vivo experiments with a freely-moving animal, the SoC has to be wire- free. Since batteries increase total weight of the system significantly, an inductive link is designed to provide energy. The link operates at 1.5 MHz and provides up to 30 mW at a 15 cm range [120]. The operating frequency is chosen as it provides much higher CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 98 magnetic field compared to high MHz frequencies (e.g. >100MHz) and also unlike kHz-range, does not require lossy and heavy ferrite cores for the receiver. The same inductive link is used to send commands to the the SoC. These commands include configuration of SoC’s mode of operation, stimulation pulse-train properties (frequency, duty-cycle, and amplitude), and recording bandwidth.

Coil Design

For both transmitting and receiving coils, planar spiral PCBs are used for implementation. The receiver is sized 2 cm×2 cm with 8 layers (104 turns in total) which results in 176 μH. The copper thickness on the PCB is set to yield highest possible quality factor for the coils, thus a higher power transfer efficiency. An inductive surface sits under the non-conductive animal cage for power transmission. Unlike the receiver coil there is no constraint for the transmitting coil size other than being large enough to cover any possible location of the SoC mounted on top of animal’s head. To reduce magnetic field intensity significantly, a multi-coil architecture is chosen over a single coil. This makes the experiment environment safer for both the technician and the animal under test. Our experimental results also show much higher coupling coefficient at closer distances for the multi-coil implementation. The transmit coils are arranged in two 2 x 4 overlapping arrays of PCB coils each sized at 11 cm x 11 cm making the total area of 45 cm x 26 cm for the inductive floor. The arrays of in- ductor coils are offset by 50 % of the coil pitch in both x and y dimensions to eliminate magnetic field dead zones.

On-chip Receiver

The received energy wave is rectiﬁed and regulated on-chip to provide supply voltage for different blocks of the SoC. As shown in Figure 3.8, two supply voltages of 1.2 V CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 99

POWER & POWER AND COMMAND RECEIVER COMMANDS LDO1 2.5V PA ACTIVE RECTIFIER LTX LDO2 1.2V LRX ASK TX CTX VREF DAC8 C 1.5 MHz RX ASK DAC1 RECEIVER VREF1 COMMAND CLOCK

Figure 3.8: Simplified block diagram of the inductive powering system, and the command receiver, first reported in [2]. and 2.5 V are generated for recording and stimulation blocks respectively. In addition, eight 8-bit DACs are implemented on-chip to provide different biasing voltages. An ASK receiver is implemented on-chip to receive the commands that are also sent through the inductive link for chip configuration. These commands shape the recording bandwidth and set the desired gain, stimulation pulse duty-cycle and amplitude, and assign digital inputs to the DACs that are used to generate bias voltages.

3.5 Experimental Results

Figure 3.9 shows the micrograph of the neurostimulator SoC. The chip is designed and fabricated in a 0.13 μm CMOS technology and is 4.8 x 3.3 mm2. It has two power supplies of 1.2V for neural recording and 3.3V (2.5V, when powered wirelessly) for current-mode stimulation. The floor-plan of each channel is shown in Figure 3.10. As illustrated, each channel houses a recording amplifier, a digitally-assisted feedback, a multiplying ADC, a low-pass filter and a current-mode stimulator as well as 22-bit memory that stores multiplication coefficients and stimulation signal properties. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 100

UWB COMMAND RX DEBUGGING TX2 & TEST FSK STRUCTURES TRANSMITTER RX POWER MULTI-CORE PROCESSOR UWB CLK GEN TX1

DIGITAL BACKEND

8 x 8 ARRAY OF CHOPPER-STABILIZED DIGITALLY CALIBRATED DC-COUPLED NEURAL MONITORS AND CURRENT-MODE NEURO-STIMULATORS 32 SC LOW-PASS FILTERS 32 SC LOW-PASS FILTERS

DIGITAL BACKEND

Figure 3.9: Micrograph of the SoC with major blocks labeled.

V-to-I 8-BIT MULTIPLYING CONVERTER ADC WITH GAIN & CURRENT CALIBRATION DRIVER FOR STIMULATOR

AMPLIFIER DIGITAL AND 4-BIT ANALOG LOW-PASS CURRENT LPF FILTER DAC

Figure 3.10: Floor plan of the neural recording/stimulation channel. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 101

3.5.1 Analog Front-end

Figure 3.11(a) shows the amplitude response of the front-end ampliﬁer from sub-Hz frequencies up to MHz range. The 5-bit coefﬁcient of the feedback digital LPF, λ, can adjust the lower 3-dB frequency from 1 Hz to 220 Hz. The mid-band gain is measured to be over 51 dB for all the channels. The experimentally measured CMRR at 30 Hz and 900 Hz is 69.2 dB and 64.1 dB, respectively. The frequency response of multiple channels were measured on-chip and excellent consistency was observed. Figure 3.11(b) shows the experimentally measured FFT of the front-end output with 130 Hz input frequency sampled at 7.2 KS/s. The SFDR and ENOB of the ADC are measured to be 56.5 dB and 6.7 bits respectively. THD was measured to be lower than

-50 dB for input amplitudes up to 1 mVpk−pk which is the nominal higher limit of neural signals. Figure 3.11(c) shows the experimentally measured input-referred noise with and without chopper stabilization. As shown, the integrated input-referred noise is measured to be 7.5 and 4.2 μVrms before and after adding chopping switches, respectively. Regarding the residual flicker noise after chopping, we believe the OTA flicker noise is up-modulated to a higher frequency (2kHz) and the ADC aliasing causes this noise to fold back to frequencies lower than the chopping frequency. Also the OTA offset caused by mismatches in the open-loop OTA configuration is up-modulated and appears at the output. Additionally, the noise current due to the addition of input chopper, which is converted to voltage at the input is effective in this increase. The MOSFET switches used for chopping result in an increase in input noise current mainly due to charge injection and clock feed-through effects. When used with high- impedance bio-potential electrodes, this current noise is converted into voltage, which will then add to the amplifiers total IRN. As shown in [159], this noise has a white power spectral density and is linearly proportional to the chopping frequency. In this design, we sized switches to minimize both charge-injection and CFT, and also chopped CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 102

30 = 220Hz fHPF f = 100Hz 20 HPF GAIN(dB) = 50Hz fHPF f = 20Hz 10 HPF = 8Hz fHPF

0 0 1 2 3 4 5 6 10 10 10 10 10 10 10 FREQUENCY (Hz) (a) 0 −20 −40 −60

MAG (dB) −80 −100 −120 10 100 1000 10000 INPUT FREQUENCY (Hz)

1 (b) 10 WITHOUT CHOPPER WITH CHOPPER 0 10 /sqrt(Hz)

rms −1

μV 10 INTEGRATED IRN (1Hz - 1kHz): WITHOUT CHOPPER : 7.5 μVrms WITH CHOPPER : 4.2 μVrms −2 INPUT-REFERRED NOISE(IRN) 10 0 1 2 3 10 10 10 10 FREQUENCY (Hz) (c)

Figure 3.11: Experimentally measured results for the analog front-end: (a) transfer characteristics spectrum of the recording front-end with digitally-adjustable high-pass pole, (b) power spectral density of the ADC with 130 Hz input at full scale, and (c) input-referred noise with and without chopper-stabilization. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 103

80 CMRR 70 PSRR 60

MAG (dB) 50

40 (a) 4.5 4.4

Vrms) 4.3 μ 4.2 4.1

NOISE( 4

INPUT-REFERRED −50 −40 −30 −20 −10 0 10 20 30 40 50 (b) INPUTOFFSET(mV)

Figure 3.12: Experimentally measured (a) analog front-end CMRR and PSRR vs input DC offset, and (b) input-referred noise (integrated from 1 Hz to 1 kHz) vs input DC offset. the input signal at lowest possible frequency to minimize the mentioned current noise. However, as shown in Figure 3.11(c), the white baseline of IRN is increased after chopping. This has not affected the system performance significantly due to the mentioned precautions that was taken as well as using low-impedance recording electrodes. Figure 3.12(a) shows the experimentally measured CMRR and PSRR of the front- end amplifier for different input DC offset voltages. Both parameters stay higher than 50 dB for the entire range of input offset values. Also they both have their maximum very close to zero DC offset which shows minimized mismatch of differential amplifier. Input referred noise is also measured for different offset values and is shown in

Figure 3.12(b). As illustrated, IRN stays below 4.5 μVrms for the entire range. Figure 3.13(a) shows gain variations for different channels before and after calibration. As illustrated in this ﬁgure, the measured open-loop voltage gain changes from 385 to 508 before calibration and 385 to 389 afterwards. The voltage gain distribution CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 104

500 480 460 440 420 WITHOUT CALIBRATION WITH CALIBRATION 400 FRONT−END GAIN (Amp+ADC) (V/V) 380 0 2 4 6 8 10 12 14 16 18 20 22 CHANNEL NUMBER (a) 12 WITHOUT CALIBRATION: 8 STD_DEV = 37.9 4 0 380 400 420 440 460 480 500 520 12 WITH CALIBRATION: 8 STD_DEV = 1.2

CHANNEL COUNT 4 0 380 400 420 440 460 480 500 520 FRONT−END GAIN (AMP.+ADC) (V/V) (b)

Figure 3.13: Experimentally measured (a) voltage gain values for several channels before and after gain-mismatch calibration, and (b) histogram of gain value distribution before and after calibration. is also demonstrated in Figure 3.13(b) where it has standard deviation of 37.9 and 1.2 before and after calibration respectively, exhibiting an over 30x improvement. The current-mode stimulator is also tested to generate various biphasic pulse shapes with different amplitude, frequency and duty-cycle. For the electrodes that are used for neurostimulation, a typical resistive impedance of 1kOhm is assumed which has allowed us to stimulate up to 2mA peak-to-peak using the 3.3V voltage compliance.

3.5.2 Wireless Transmitters

Three wireless transmitters were tested experimentally with receivers located in different distances from the SoC. For the FSK radio, the receiver was the RFM 868MHz to 960MHz TRC103 transceiver. The transmitter used a quarter-wave 915MHz antenna and the receiver used a half-wave 915MHz antenna, both connected through SMA con- nections. The UWB pulses are measured using custom-built UWB antennas (10 cm and 1m spacing between the transmitter and receiver) and a custom-built receiver board. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 105

Figure 3.14: Experimentally measured (a) output spectrum of the pulse for the ﬁrst UWB transmitter (BAND1: 3.1-10.6 GHz), and (b) an example of a transmitted pulse train. The experimental measurements were performed by N. Soltani.

Figure 3.14(a) shows the frequency spectrum and sample received pulses for the ﬁrst UWB transmitter operating in the 3.1-10.6 GHz band. The experimental measurements show a maximum of data-rate of 45 Mbps at 10 cm, that promises a high- throughput link for short distance communications to a wearable on-skin receiver. Fig- ure 3.15 shows the same result for the second UWB transmitter that operates under 1 GHz range and has a maximum data-rate of 10 Mbps measured at a distance of 1 m. Figure 3.16(a) shows the frequency spectrum of the Manchester-encoded FSK transmitter measured at the receiver with the highest measured data-rate of 1.2 Mbps. Also Figure 3.16(b) shows the pulse-train for a sample sent and received using the Manchester-encoded FSK modulation. To avoid excessive power dissipation that could cause tissue damage, the three radios are not turned on simultaneously. The wireless transmitters are turned on depending on the application and proximity of the receiver (on-skin, hand-held or stationary). In the worst case, when all three transmitters have to CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 106

Figure 3.15: Experimentally measured (a) output spectrum of the pulse for the second UWB transmitter(BAND2: <1 GHz), and (b) an example of a transmitted pulse train. The experimental measurements were performed by N. Soltani.

BAND 3: FSK MANCHESTER ENCODED RECEIVED 915.6MHz DATA AT 1.2 Mbps 917.6 MHz -33.9dBm -33.6dBm

10dbm 1MHz

(a) RECEIVED MANCHESTER FSK DATA 01=0 01=0 01=010=1 10=1 01=0 01=010=1 10=1 10=1 01=0 10=1 1

0.5

0 0 2 4 6 8 10 RAW TRANSMITTED DATA AT 1.2 Mbps

AMPLITUDE(V) 1 0.5 0 0 2 4 6 8 10 TIME(μs) (b)

Figure 3.16: Experimentally measured (a) spectrum of the FSK transmitter, and (b) an example of transmitted and received Manchester-encoded data at 1.2 Mbps using FSK modulation. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 107 be on, the total power consumption will be 6mW, which is still within the power budget allocated to the inductive link. The experimental measurements for Figures 3.14, and 3.15 are performed by Nima Soltani.

3.5.3 Inductive Power and Command Telemetry

Figure 3.17(a) shows experimentally measured power transfer efficiency for various currents consumed by the load. The ideal loading condition is when the system consumes approximately 15 mA, at which point the input impedance of the active rectifier is matched to the output impedance of the receiver coil. Figure 3.17(b) depicts the power received at different intensities of the magnetic field at the receiver. Due to the significantly increased quality factor, the stacked configuration results in more power harvested from the transmitted magnetic field as compared to a conventional single- layer coil, for the same field intensity. Based on the experimental measurements, the variations of the field intensity are 13% from the nominal value of 6 μT. The multi- layer receiver coil is measured to have high quality factor of 24 despite the small size resulting in an overall wireless power transfer efficiency of 40%. The experimental measurements for the inductive powering system which resulted in Figure 3.17 is done by Nima Soltani. The RX coil receives a signal with the amplitude limited to 3V. The rectifier outputs a noisy DC signal at 2.9V with a 70mV ripple, which is fed to two LDOs on the chip. The outputs of LDOs are steady 2.5V and 1.2V DC, both with less than 5mV ripple at all time, which is acceptable considering the PSRR values shown in Figure 4.15(a). These voltages are used as reference inputs to the 8-output 8-bit voltage DAC, to generate biasing voltage on the chip. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 108

POWER SUPPLY 40 CURRENT 0.2A

MATCHED

IMPEDANCE 0.1A 20

EFFICIENCY(%) 0.05A 10 0.02A

0.01A 0 0 10 20 30 40 50 60 70 LOAD CURRENT(mA) (a)

1000

100

OPERATING POINT OUTPUT POWER (mW)

10 1 10 100 MAGNETIC FIELD (μT) (b)

Figure 3.17: Experimentally measured results for inductive link: (a) power transfer efﬁciency, and (b) output power versus magnetic ﬁeld. The experimental measurements were performed by N. Soltani. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 109

3.6 Experimental Validation

An on-chip-calculated phase-synchrony indicator is used for early detection of epilepsy seizures [2]. The phase synchrony is calculated between pairs of channels and seizure is detected using thresholding. Upon detection, a programmable pulse-train is triggered to a subset of current-mode stimulation channels for seizure abortion.

3.6.1 In-vivo Early Seizure Detection and Control

The efficacy of the responsive neurostimulator at aborting ictal events was assessed in a 500-hour chronic treatment of a rodent model of temporal lobe epilepsy. For this purpose, kainic acid was injected intraperitoneally into four Wistar rats to induce the appearance of recurrent spontaneous temporal lobe seizures one to two months after the injection. At this point, rats underwent craniotomy with general anaesthesia and micro-electrodes were implanted into the hippocampus. Following the implantation and recovery period, the rats were connected to the presented system for the spontaneous recurrent electrographic seizures recordings and automatic seizure detection. As well, rats were connected to a commercial recording system and were video-monitored for the clinically associated behaviors during seizure activity (e.g. convulsions). Thus, seizures were classified according to electrographic and behavioral features for 24 hours a day, 7 days a week. For every subject, EEG was collected for one hour and seizures were labeled by a professional epileptologist. The labeled data are used to set the threshold for the specific subject and the chip is programmed with the offline-calculated threshold. This threshold is then used for long-term (>1 month) online seizure detection and abortion. The rats were divided into two groups: (1) non-treatment group and (2) treatment group. In the non-treatment group (two rats), seizures were monitored and labeled CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 110

SEIZURE DETECTION (NO STIMULATION)

1 RIGHT HIPPOCAMPUS EEG (V)

RH 0 V

NORMAL SEIZURE -1 (V) 1 LEFT HIPPOCAMPUS EEG

LH V 0 -1 SEIZURE ONSET DETECTION SEIZURE DETECTION THRESHOLD 0.4 00.8 PHASE SYNCHRONY 0 80 160 TIME (SEC) (a) SEIZURE ABORTION BY STIMULATION

1 SEIZURE ONSET ELECTRICAL STIMULATION (V)

V 0

SEIZURE SUPPRESSION -1 (V) 1

LH V 0 -1 SEIZURE ONSET DETECTION 0.8 0.4 0

PHASE SYNCHRONY 0 80 160 TIME (SEC) (b)

Figure 3.18: Experimentally measured seizure detection and control results: (a) an example of seizure detection for the non-treatment group of rats, and (b) an example of a seizure abortion for the treatment group of rats. (Animal experiments were done with the assistance of M. T. Salam). CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 111

(seizure start and stop time recorded) and the seizure frequency per hour was deter- mined. In the treatment group (two rats), initially seizures were also monitored and labeled; later the stimulators on the SoC were activated to inject automatically-triggered biphasic current pulses to suppress an upcoming seizure. Figure 3.18(a) shows phase synchrony indicator (PLV) value in the non-treatment group during a detected seizure where it is increased rapidly to over 0.6 at the seizure onset. Figure 3.18(b) shows an example of seizure onset detection and subsequent seizure suppression with self-triggered stimulation in treatment group. Figure 3.18(a) shows the sudden appearance of the typical neural discharges following low-voltage fast activity recording at the seizure onset and later an increase in frequency and amplitude of the neural signals during the seizure period. Figure 3.18(b) illustrates an initiation of a 5Hz pulse-train current-mode stimulation upon detection of the discharge and low-voltage fast activity (seizure onset) and disruption of the frequency and amplitude growth. Following the stimulation, neurons generate 5 Hz rhythms similar to the stimulation pattern, which prevents them from initiating epileptic high-frequency seizure activity.

3.6.2 Ofﬂine Early Seizure Detection in Humans

Figure 3.19 shows an example of off-line early seizure detection in human ECoG data from a University of Toronto epileptic patient. Eight hours of ECoG data was collected from three patients including a total of 12 seizures. These were fed to the SoC and its detection performance was evaluated. As shown, the seizure is detected prior to its clinical onset (high amplitude activity in the recording) using the on-chip synchrony- based algorithm. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 112

Figure 3.19: An example of ofﬂine early seizure detection in a human patient. Human data were provided by M. T. Salam.

3.6.3 Statistical Analysis

Figure 3.20(a) demonstrates the SoC’s seizure onset detection performance. As shown, treatment was started once the number of seizures per day were higher than 6. Also this figure shows the seizure onset detection performance that is evaluated online, using intracranial EEG signals recorded by the SoC from four animals, two in the non-treatment group and two in the treatment group. The detection performance was characterized by calculating detection sensitivity, false positive rate, and false negative rates. After PLV calculation, it was observed that normal EEG signals had an average PLV in the range of 0.3 to 0.7. However, the PLV increased rapidly up to 0.8 at seizure onset and gradually decreased to under 0.5 during the seizure. To evaluate overall performance of the SoC in terms of seizure detection and abortion, sensitivity and specificity of detection were defined as: Sensitivity: the ratio of TP to TP + FN. Specificity: the ratio of TN to TN + FP where true positive (TP) is the CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 113

ANIMAL # NORMAL SEIZURE 1 NON-TREATMENT 2 3 TREATMENT 4 NORMAL EEG SEIZURE ONSET 20 SEIZURE DETECTION THRESHOLD 10

TREATMENT

NUMBER OF SEIZURES OF NUMBER STARTS 0 0.2 0.4 0.6 0.8 1 PHASE SYNCHRONY (a) SENSITIVITY SEIZURE REDUCTION SPECIFICITY

NON-TREATMENT GROUP TREATMENT GROUP 0 0 1 50 PERCENTAGE (%) PERCENTAGE

0 1 2 3 4 ANIMAL NUMBER (b)

Figure 3.20: (a) Statistical analysis for the in-vivo experiments. (b) Seizure detection sensitivity, specificity and seizure reduction rate of the epileptic rats in in-vivo experiments. Statistical analysis was done by M. T. Salam. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 114 number of discharge events following the detection of the putative discharge precursor; False positive (FP) is when a discharge event does not follow the detection of the discharge precursor; True negatives (TN) is the absence of discharge activity correctly identified as non-discharge; and false negatives (FN) is the discharges that occurs without detection of the discharge precursor. The average sensitivity and specificity of the detection are 87% and 95%, respectively. The average false positive and false negative frequencies are 0.52 and 0.33 times per hour, respectively. Seizure frequency has been reduced on average by over 78% in the treatment group compared to the non-treatment group, as shown in Figure 3.20(b).

3.7 Discussion

3.7.1 Resource Utilization

A summary of experimental measurement results is shown in Table 4.2. Also Fig- ure 3.21(a) and (b) shows the power breakdown of the chip when operating with UWB and FSK transmitters, respectively. The SoC dissipates 2.17 mW when operating with UWB transmitters and 5.8 mW with the FSK transmitter. Also the feed-forward path of the SoC which includes analog front-end and digital back-end consumes 1.32 mW for 64 channels resulting in 21 μW per channel. When operating in stimulation mode, the SoC dissipates 1.14 mW or 18 μW per channel, from a 2.5 V supply. With cost of 30 % more power consumption, the supply voltage can be increased to 3.3 V for higher stimulation headroom when the SoC is not inductively powered. Since the SoC goes to the stimulation mode for less than 1 % of the experiment time, this increase affects total power consumption insigniﬁcantly. Figure 3.21(c) shows the area breakdown of the chip (excluding routings, IO pads CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 115

Table 3.1: Summary of the experimental results

SYSTEM: Technology IBM 0.13μm Supply Voltage (Rec.) 1.2V Supply Voltage (Stim.) 2.5/3.3V Die Dimensions 4.8mm×3.3mm Area Per Channel 300μm×300μm No. of Recording Channels 64 No. of Stimulation Channels 64 Power Dissipation (Rec.) 2.17(UWB)/5.8(FSK)mW Power Dissipation (Stim.) 1.14mW RECORDING CHANNEL: Gain 51.5-51.8dB Input-Ref. Noise (1Hz-1kHz) Without Chopper 7.5μV With Chopper 4.2μV LNA NEF 6.9 CMRR 65dB THD @ 130 Hz 0.8% ADC SNDR 44.5 ADC SFDR 59.5 ADC ENOB 7.1 bits Power Diss. (LNA+ADC) 9.1μW Number of FIR Filters 64 NEURAL STIMULATION: Type Biphasic current Current Range 10μA-1.0mA DAC Resolution 8 bits Duty Cycle Resolution 4 bits WIRELESS TX: BAND1 BAND2 BAND3 Modulation UWB UWB FSK Freq. Band 3.1-10.6 <1 916.4 GHz GHz MHz Data Rate 45Mbps 10Mbps 1.2Mbps Range 10cm 1m 10m Power Diss. 100μW 100μW 3.7mW WIRELESS POWER: Receiver Coil: Type 8-layer flexible Size 2cm x 2cm No. of turns 104 Inductance 176 μH Coil Separation 15cm Power Transfer Efficiency 40% Frequency 1.5 MHz No. of Voltage Levels 10 CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 116 and decoupling capacitors for supplies). The total area occupied by 64 recording and stimulation channels together with the digital back-end, wireless transmitters and power management circuits is 7.275 mm2. 64 recording front-ends have the biggest quota with 46 % followed by the digital back-end (FIR filters and on-chip processor). The 64 stimulators are added to the chip with very small area overhead of 5 % since they share some blocks such as DAC and 12-bit memory (for duty-cycle control) with the recording circuitry.

3.7.2 Comparison to the State of the Art

A comparison with other neural monitoring and/or neurostimulation SoCs is given in Table 3.2. This work demonstrates the highest degree of integration among recently published state-of-the-art SoCs by combining 64 recording channels with digital offset-cancellation feedback loop and chopper-stabilization, 64 current-mode stimulation channels, 64 multiplying SAR ADCs, a multi-core DSP unit, three wireless transmitters, and wireless power and command receivers. It also has the smallest front-end area and beneﬁts from the most versatile wireless data transmission. The extensive in- vivo validation of the work with statistical data analysis is also unique among published works.

3.7.3 In-vivo Results

We note that in our study we detect an increased value of the synchrony index rather than the typical decreased reported in other studies ( [10, 11, 160]) because the time window used to average the phase differences to compute the synchrony index was longer (4 seconds), which precluded the observation of the sharp decrease previously found in this animal model that requires a <1 second averaging. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 117

POWER BREAKDOWN WITH UWB TX

RECTIFIERS & DIGITAL REGULATORS BACKEND 600 μW 500 μW

LPF & UWB TX BUFFERS 100 μW 160 μW BIASINGS 80 μW

64 RECORDING CHANNELS TOTAL POWER: 2.17mW (a) 735 μW POWER BREAKDOWN WITH FSK TX RECTIFIERS & DIGITAL REGULATORS BACKEND 600 μW 500 μW LPF & BUFFERS 160 μW 64 RECORDING CHANNELS 735 μW BIASINGS FSK Tx 80 μW 3.17 mW

TOTAL POWER: 5.8mW (b)

AREA BREAKDOWN

64 STIMULATORS POWER 5% MANAGEMENT DIGITAL 6% BACKEND 26% LPF & BUFFERS 9%

UWB TX1 & 2 0.4% FSK TX 8% 64 RECORDING CHANNELS 46%

TOTAL AREA: 7.275 mm2 (c)

Figure 3.21: Power breakdown of the integrated circuit operating in two modes: (a) with the UWB transmitters, and (b) with the FSK transmitter. (c) Area breakdown of the IC. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 118

3.8 Conclusion

A CMOS fully-wireless closed-loop neuro-stimulation SoC is presented. The 16 mm2 die integrates 64 differential direct-coupled chopper-stabilized recording amplifiers with in-channel digital offset cancellation feedback, 64 in-channel multiplying ADCs, multi- core digital signal processing unit, triple-band FSK/UWB wireless transmitters, active rectifiers, regulators and DACs for inductive power receiving, ASK demodulator for command receiving, and 64 in-channel synchrony-triggered current-mode stimulators for abortion of undesired neurological events. Gain mismatch is calibrated using the on-chip MADCs and off-chip calibration loop. The SoC is implemented in IBM 0.13 μm technology and dissipates 2.17 and 5.8 mW with UWB and FSK transmitters respectively. It is validated in a chronic in-vivo epilepsy monitoring and treatment for multiple rodents and demonstrates average seizure detection sensitivity and specificity of 87% and 95%, respectively, with 78% seizure frequency reduction. CHAPTER 3. BATTERY-LESS NEURO-MONITOR AND RESPONSIVE NEURO-STIMULATOR IC 119 % 15 THIS WORK Epileptic Seizure Control 0.13 16 1.2/2.5 2.17 0.018 51.5 1-5k 7.5/4.2 1-1k 64 64 YES YES Phase Derivative YES 64 10-1000 YES 8-layer flex 4 104 176 < 40 1.5 10 YES 88-96 89-97 78 25-45 1G 916.4M < Band1UWB Band23.1- Band3 UWB10.6G FSK [65] 1-layer flex ISSCC’14 Rabaey Rat EEG Recording [8] Wire-wound JSSC’14 Wu Epileptic Seizure Control 12 N/R 1.6 [5] < TBCAS’10 Ghovanloo Rodent EEG Monitoring [2] Synchrony /Spectrum JSSC’13 Genov Epileptic Seizure Control [157] JSSC’12 Meng Monkey EEG Recording [6] JSSC’10 Flynn Rat EEG Recording State-of-the-art neural recording and/or stimulation SoCs [66] ISSCC’08 Yuce Snail EEG Recording Table 3.2: [9] JSSC’13 Yoo Eye Blink Detection ) ------% A) - - 3-135 - 10-1200 - 30 - ) - - - - - 4.5 5.72 0.42 μ H) - - - - - 0.41 N/R N/R 2 μ ) N/R ------) 71.4-88 - - - - - 92 % ) 0.7 0.3 0.1 0.26 0.09 0.1 0.5 0.025 % 2 Vrms) 0.91 4.9 5.24 14 4.7 9.3 5.23 1.43 μ m) 0.18 0.35 0.35 0.13 0.13 0.5 0.18 0.065 μ of turns - - - - - 2 4 1 of Rec. Channelsof Stim. Channels 8 128 0 8of Voltage Levels 0 96 64 64 - 32 0 64 8 - 0 64 - 1 - - 0 N/R 3 2 Size/Area(cm # Inductance ( Type - - - - - 1-layer Power Efficiency - - - - - N/R N/R N/R Gain (dB)Bandwidth (Hz)Noise ( Noise BW (Hz)# Chopper CountClosed-loopDetectionMethod 0.5-100# 50-70Current Range ( 0.1-20k 0.5-100Receiver 57-60 Coil 16-5.3k N/R 8 1-10k 40 NO 1-5k 1-8k 0Coil Separation (cm) SVM 56 1-100 NO 0.1- 8k# - 10-5k 54-60 0 0.1-7k NO* 1-10k 68-78 1-250 - 0 NO - 0.5-7kSensitivity( 59.3Specificity( YESSeizure 64 - Reduction( 1-500 Advanced - Detection (s) 46 NO Ampl/Phase 0 - - YES 0 N/R Entropy NO - - - 0 ------Frequency (MHz) - - - - - 13.56 13.56 300 Area (mm ModulationFrequency (Hz) - - 3.1-10.6G UWB - - - - 3.1-10.6G 915M UWB 401M FSK 300M OOK OOK Area (mm)Supply (V)Power Diss. (mW) N/R 25 1.8 6 65 3.3 0.09 2.7 1.8 6.5 12 1.2 1.4 12 1.2 7.05 16.4 3 2.8 13.47 1.8 0.225 5.76 0.5 Spec. Targeted Application Tech. ( NEURAL FRONT-END SIGNAL PROCESSINGNEURAL STIMULATIONWIRELESS POWER YES YES NO YES NO NO NO YES YES NO NOIN-VIVO RESULTS NO YES NO YES NO NO NO NO YES YES YES NO NO YES NO YES NO YES NO YES YES WIRELESS COMM. NO YES NO NO YES YES YES YES -: Not Applicable, N/R: Not Reported, *: Off-chip 120

Chapter 4

64-channel Rail-to-Rail-Input Inductively-Powered Dual-Radio Closed-Loop Neurostimulator

4.1 Introduction

Demonstrated by several researchers around the world including our group [2, 15, 74, 80,164], closed-loop wireless neurostimulators, triggered by an epileptic seizure detection, is effective in intractable epilepsy patients. However, when the detection is made based on interictal epileptiform abnormalities [123,164], only up to 9 percent of patients are rendered seizure-free. Epileptic seizures are generally preceded by sharp variations in the synchrony among intracranial EEG signals in various regions in the brain as shown in Figure 4.1(a). In a 6-month animal study, we have successfully demonstrated that current-mode stimulation upon an accurate time-advanced phase-synchrony-based seizure detection performed on a computer-in-the-loop, renders approximately 83% of subjects seizure-free. [93]. CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 121

POST-ICTAL ICTAL (SEIZURE) PRE-ICTAL

0 0.2 0.4 0.6 0.8 1 PHASE SYNCHRONY INDEX (a) DIAGNOSTIC DATA EXTERNAL MODULES NEURO-MONITOR AND DATA RECEIVER SYNCHRONY-TRIGGERED SCALP POWER CLOSED-LOOP POWER/COMMAND NEUROSTIMULATOR SoC ELECTRODES TRANSMITTER ECoG & DEPTH ECoG CONFIGURATION COMMANDS IMPLANTED COIL & SKULL ANTENNA BONE ECoG DEPTH ELECTRODES ELECTRODES

SCALP (b)

Figure 4.1: (a) Phase synchrony index in different brain regions before, during and after an epileptic seizure [163]. (b) Block diagram of a wireless closed-loop neurostimulator. An envisioned implanting conﬁguration is also depicted. CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 122

This chapter presents a 6 mm2 0.13 μm CMOS 64-channel neurostimulator SoC with an entirely new channel design that realizes a low-power highly-scalable system that leverages our synchrony-based algorithm using a compact mixed-mode implementation. The synchrony-based algorithm for epileptic seizure detection and its hardware implementation for closed-loop responsive neurostimulation is first presented in [158] and [2], respectively. An envisioned implantation configuration of the SoC in the proximity of a human brain is shown in Figure 4.1(b). Similar to previous designs, the SoC is connected to an array of ECoG (Electrocochleogram) or depth electrodes for EEG (Electroencephalogram) signal recording. The diagnostic data and seizure detection results are communicated to an external module using wireless transmitters, and energy and commands are received through magnetic induction. The chip has 64 neural recording channels that are designed based on an area-efficient low-power oversampled Δ2Σ-based method that allows for recording neural activity in the presence of a rail- to-tail varying input DC offset. The method works based on the difference between two consecutive samples of the input signal, and ignores its absolute ac or DC value, resulting in the ability to record a signal with rail to rail input DC offset variation. Correlated double-sampling is employed in each channel to suppress the flicker noise. A mixed-mode analog-digital compact multiplier is implemented in each channel to perform voltage gain scaling as well as FIR (finite impulse response) filtering. A multi-core digital processor shared between all the channels, is used to carry out signal feature extraction and epileptic seizure detection. The chip also has 64 programmable arbitrary-waveform biphasic current-mode stimulators that are triggered by the on-chip digital processor upon detection of a neurological event, to modulate the brain activity. Two UWB (ultra wideband) wireless transmitters are included in the design that enable communication of diagnostic data to a wide range of distances. The chip is powered wirelessly using a magnetic inductive link, with energy signals that are amplitude shift- CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 123 keyed to communicate configuration commands to the chip. The SoC is validated in an in vivo epilepsy monitoring (seizure detection) and treatment (seizure suppression). The rest of the chapter is organized as follows. Section 4.2 describes the motivation for the work presented in this chapter and briefly compares it with the previous generation of the closed-loop neurostimulator presented in the previous chapter. Section 4.3 discusses the challenges in design of a compact low-noise neural recording channel in the presence of large input DC offsets, and describes the selected VLSI architecture of the neurostimulator recording channel and its advantages. Section 4.4 presents the circuit implementation of the key functional blocks in the SoC, and provides theoret- ical noise and speed analysis for the recording front-end. Section 4.5 discusses the VLSI architecture of the neurostimulator SoC. Section 4.6 presents electrical experimental results from individual blocks as well as the full system. Section 4.7 presents in-vivo online animal epilepsy seizure detection and treatment results and offline human epilepsy seizure detection results. Section 4.8 discusses resource utilization, power and area scalability, and comparison with the state-of-the-art.

4.2 Motivation

As mentioned earlier, electrochemical reactions at the electrode-tissue interface result in a significant DC input voltage level offset and DC drift, up to several hundred mil- livolts. To avoid front-end amplifier saturation, this DC offset is either removed using AC coupling [5, 7, 12–14, 22, 148], or, to an extent, compensated for using a digitally- assisted feedback loop [3, 15, 48]. However, as it is described in the previous chapters, the DC removal using these methods is achieved at the cost of either sacrificing noise performance and area per channel (AC-coupled case) or channel-to-channel gain mismatch while only partially compensating for the offset (DC-coupled case). CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 124

The system presented in this chapter features a novel recording front-end architecture that solves the issue with input DC offset without sacrificing other performance parameters. In this design, the flicker noise is almost completely removed using correlated- double sampling, and the thermal noise floor is reduced by increasing oversampling ratio. Additionally, to reduce resource utilization for the digital back-end, an analog multiplier is embedded into the front-end quantizer, which results in more than 30× improvement in power-area product. Moreover, a decimation technique in utilized in the front-end design to generate both in-phase and quadrature outputs with only adding a digital counter. The I/Q signals are later used for phase calculations, and resulted in removing 128×64-tap FIR filters, that was otherwise required. In terms of system-level functionality, the system keeps all the system-level advantages of the previous generations, while it adds arbitrary-waveform stimulation with a resolution of 8 bits, as well as variable front-end gain to cover a larger range of signal amplitudes.

4.3 Rail-to-Rail-Input Signal Aquisition

4.3.1 Architecture Selection

Figure 4.2(a) depicts a conventional ﬁrst-order ΔΣ modulated ADC. It typically does not require any bulky passive component, which results in small and technology-scalable area. The input-referred thermal noise of this circuit is ηkT/(OSR×C) where k is the Boltzman constant, T is temperature, OSR is the oversampling ratio, C is the input sampling capacitance, and η is a factor related to the topology of the ampliﬁer used in the input integrator. With a reasonable value chosen for C and a high OSR (>500), which is CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 125

Q Δ ∑ N UP/DN

V [n] OUT IN COUNTER D (a) RST

∑1 Q N Δ1 Δ2 V [n] UP/DN IN COUNTER OUT RST=0 D Q V [n-1] N (b) IN V [n-1]+ IN OSR ∑2

∑1 Q Δ1 Δ2 N UP/DN V [n] OUT IN COUNTER D (c) RST=0 V [n-1] IN ∑2

∑1 Q Δ1 Δ2 N (I) V [n] UP/DN IN COUNTER OUT D (d) RST=0

UP/DN (Q)

COUNTER OUT V IN[n-1] D Δ ∑2 RST ∑1 Δ1 Δ2 (I) V IN[n] UP/DN

OUT COUNTER

RST=0 M D (e) ∑2 IMDAC UP/DN (Q)

COUNTER OUT

V [n-1] D IN C INT Δ

8 RST 1/M M

Figure 4.2: Incremental evolution of the block diagram of Δ2Σ-based neural recording channel with quadrature outputs and in-channel mixed-mode analog-digital multiplier, implemented using a current-mode multiplying DAC (IMDAC). CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 126 feasible for biomedical signals due to their low frequency bandwidth, this noise can eas- ily be set <10μVrms that is required for a neural front-end with an electrode impedance of 1MΩ. Despite the area and noise beneﬁt, this circuit cannot be utilized as a neural front-end as it saturates for large input DC offsets. In Figure 4.2(b), the integrator (Σ) is split into two integrators (Σ1 and Σ2) that are placed earlier in the signals paths. To avoid saturation, a Δ stage is added in front of the ΔΣ modulator, that subtracts two consecutive samples, VIN[n] and VIN[n- 1]. The quantized difference is later integrated by a non-resettable up/down counter. Figure 4.2(b) also shows that the previous sample plus the ADC quantization noise,

VIN[n-1]+QN /OSR, is reconstructed at the output of the feedback integrator, Σ2, since the input of Σ2 is equivalent to the signal derivative. This signal is connected to the subtracting input of Δ1, to form a Δ2Σ modulator, as shown in Figure 4.2(c).

4.3.2 Quadrature Output

Since the output bit-stream of the Δ2Σ ADC represents the signal derivative, the non- resettable counter (digital integrator) shown in Figure 4.2(c), outputs the digital equivalent of the signal amplitude. Figure 4.2(d) shows that by adding a resettable counter to the Δ2Σ modulator, the signal is only decimated without being integrated, and the output bitstream represents the signal derivative that has a natural 90◦ phase difference with reference to the signal. This results in two quadrature outputs, I and Q, enabling subsequent phase computation on a signal tone. Compared to [2], where I and Q signals are generated by employing two 16-tap allpass and Hilbert FIR ﬁlters, the two counters yield 6.45 times savings in silicon area, while dissipating 110 times less energy, resulting in a signiﬁcant 709 times improvement in power-area product. The tone selection within I and Q is later done by a transposed mixed-signal FIR CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 127

filter which employs in-channel mixed-mode analog-digital multipliers implemented in the Δ2Σ modulator to scale the input signal by various coefficients required for an FIR filter. Figure 4.2(e) depicts how the multiplication by a factor of M is implemented within the modulator, by multiplying the feedback integrator (Σ2) gain by a coefficient 1/M. More details on the multiplier implementation is presented in section 4.4.4.

4.3.3 Input Dynamic Range

This configuration does not impose any amplitude or frequency constraints on the input, as larger signal amplitudes or higher frequencies that have sharper instantaneous slope only require the feedback loop to be faster to compensate for the difference between the two consecutive samples. This can be done either by increasing the clock frequency at the cost of higher dynamic power, or by multiplying the feedback integrator (Σ2) gain by a coefficient greater than one, compounded with the FIR coefficient 1/M.

4.3.4 Differential Recording

Figure 4.3 shows the differential implementation of the 64 differential recording channels. To eliminates the effect of common-mode (CM) noise, the input signal derivative is additionally subtracted by the respective reference signal derivative, calculated by the reference channel, which is the only single-ended-input channel on the chip. An 8-bit current-output multiplying DAC (IMDAC) and an integrating capacitor form the multiplying integrator (Σ2). The presented in-channel neural ADC records intracranial EEG signal with an arbitrary rail-to-rail DC level, different for each of the 64 channels. CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 128

∑1 Δ1 Δ2

V [n] (I) IN UP/DN

OUT Δ1 COUNTER

RST=0 M D V [n] REF ∑2 [n-1]

IN IMDAC

V UP/DN (Q)

C COUNTER OUT INT D 8 RST Δ [n-1] X64 RECORDING CHANNEL 1/M M REF V

X1 REFERENCE CHANNEL

Figure 4.3: 64 differential Δ2Σ-based neural recording channels. 4.4 VLSI Circuit Implementation

4.4.1 Neural Front-End

The recording channel circuit is shown in Figure 4.4. A parasitics-insensitive differential integrator performs both Δ1 and Σ1 in one clock cycle. COFF samples the ampliﬁer input offset and 1/f noise during Φ1, and keeps the common terminal of C1 and C1 at

VCM during Φ2. During Φ1, C1 and C1 are charged to VIN[n]-VCM and VREF [n-1]-

VCM, respectively. During Φ2, one common terminal of C1 and C1 remains at the same voltage (VCM) but the other terminal changes to VIN[n-1] and VREF [n], respectively.

As a result the lower branch pushes a charge equal to C1×(VIN[n]- VIN[n-1]) and

the upper branch pushes a charge equal to C1 ×(VREF [n-1]-VREF [n]). The charges are added and integrated on C2 thus implementing subtraction of the two derivatives and integration Σ1. The two-stage 10T ampliﬁer is duty-cycled 5-50% for 0.5-5kHz bandwidth respectively. One-bit quantization is performed by a low-power 7T dynamic comparator. CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 129 [7:0] (I) M

(Q) IMDAC / O OUT REF I OUT INT D V D C M M Δ EN A C2 [7:0] CM OFF RST M RST=0 V / C REF UP/DN UP/DN I COUNTER COUNTER [n] [n-1] IN REF V V C1 C1’ : 2 O V EN 2 A O C V CM 1 V EN -based neural recording front-end with correlated double-sampling, quadrature output and Σ A 2 2 1 Δ 1/f NOISE REMOVAL C2 OFF CM C V OFF C 1’ 1 C C [n] CM NOISE REMOVAL [n-1] IN 2 V 1 REF V C1’ C1 [n-1] 2 1 IN : V 1 INPUT DC REMOVAL Simpliﬁed circuit diagram of the [n] [n] IN [n-1] REF V V REF in-channel mixed-mode multiplication. V Figure 4.4: CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 130

4.4.2 Noise Analysis

Input-referred noise of the channel is comprised of thermal and ﬂicker noise, which are suppressed by oversampling and correlated double-sampling, respectively.

Thermal Noise

Thermal noise of the circuit in Figure 4.4 is,

fs/(2·OSR) 2 2 Vni1 2 Ni1 = |NTFi1(f)| df (4.1) fs/2 0 2 V 5fs 2fs π = ni1 − sin( ) fs/2 2 · OSR π OSR

2 where Vni1 is the thermal noise power contribution of the input switches and the amplifier in the input integrator (Σ1). Switches are implemented with bigger-than-minimum size to decrease their ON resistance, and consequently, make their noise contribution insignificant compared to the amplifier. This yields the noise power of the input integrator to be,

2 Vni1 4kT · ηf /(3 · C1) (4.2) where ηf is the ampliﬁer topology-dependent noise coefﬁcient. By sizing active load PMOS transistors to have a transconductance considerably smaller than the input NMOS devices, the ηf is minimized.

Noise/Speed Trade-Off

Equations 4.1 and 4.2 suggest that increasing C1 and OSR decreases the noise indefi- nitely. However, since the input impedance of a switched-capacitor is set by 1/f·C, with f being the sampling frequency, larger C1 or OSR results in smaller input impedance for the front-end, which could degrade the input signals received from electrodes. Ad- CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 131 ditionally, the C1 size is set by the area allocated for each channel and should be kept smaller than a certain value. Also, Higher OSR which means higher clock frequency demands the amplifier to settle in a shorter time. To be more specific, if τ is the period of the sampling clock, and N is the target resolution for the neural ADC

−1 2 −(N+1) e fsτ < 2 (4.3)

f3dB π > (N +1)· Ln(2), fs where f3dB is equal to

βgm f3dB = . (4.4) 2πC0

By sizing C1 to be much larger (x10) than both C2 and load capacitance of the ampliﬁer (input capacitance of the comparator), Eq. 4.4 is simpliﬁed to

2fsLn(2)(N +1) gm = . (4.5) C1

Replacing C1 by its equivalent from Eq. 4.1 and 4.2 and with the assumption of a high OSR (>1000) 2fsLn(2)(N +1)· 5kT gm = 2 (4.6) Ni1 · OSR

20(N +1)Ln(2) · kT · fb = , 2 Ni1 where fb is the target frequency bandwidth of the neural signal. Eq. 4.6 shows the

2 trade-off between total integrated noise (Ni1), oversampling ratio (OSR), resolution (N) and power consumption (gm). This equation can be used as a start point for ΔΣ-based neural ADC design for a target noise budget, resolution and power budget for a certain CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 132 input signal frequency bandwidth.

Flicker Noise

The ﬂicker noise is suppressed by correlated double sampling implemented using COFF .

As shown in Figure 4.4, during Φ1,COFF samples the input offset, low-frequency drift and ﬂicker noise at the ampliﬁer input. It holds this voltage during Φ2, which results in

keeping the common-node between C1 and C1 at VCM. To prevent the CDS technique from hampering the noise performance of the front-end, the amplifier input devices are sized to have minimum parasitic capacitance while their transconductance as high as possible. This ensures that a COFF of 1pF is significantly larger that the input parasitic capacitance of the amplifier, which results in effective flicker noise suppression [165].

Noise-Input Impedance Trade-Off

High input impedance is one of the main requirements of a neural front-end. Since the input impedance of the front-end and the electrode impedance form a voltage divider, a commonly-accepted value for the ZIN is ten times larger than the electrode impedance, to avoid any loss of signal. More importantly, the mismatch between the impedance seen by different electrodes could be as large as 100%. This could result in a signiﬁcant common mode noise to appear at the output, even with a ZIN 10 times larger than the electrode impedance. To avoid such problem, ZIN must be large enough to ensure a high (>70 db) CMRR even with a 100% electrode impedance mismatch between different channels. This requires the ZIN to be at least 3 orders of magnitude larger than the impedance seen by the electrodes. For the presented front-end, the input impedance is the equivalent impedance of the switched-capacitor,

1 1 ZIN = = (4.7) fs · C1 2 · OSR · fB · C1 CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 133

where fs is the sampling frequency, fB is the input signal bandwidth, and OSR is the oversampling ratio. Based on this equation, to achieve higher input impedance, OSR must be decreased. However, as was shown in Equation 4.1, decreasing OSR directly increases the front-end input-referred noise. As a result, OSR must be selected in a way that it satisfy both noise and input impedance requirements. Based on the Equation 4.1 and 4.2, input referred noise power of the presented front-end can be written as,

VRMS = 2kT · ηf /(C1 · OSR). (4.8)

This noise is added to the noise generated by the electrode impedance,

VRMS = 4kTRΔf (4.9)

and the background noise within the extra-cellular region (10μVrms) in a root-sum- square manner. To ensure that the front-end circuit adds less than 10% to the total noise at the input, its noise power must be less than 21% of the total noise from electrode and the background noise. Therefore,

2 2kT · ηf 0.21(4kTRelec · Δf + N ) > , (4.10) i−BG C1 · OSR

2 where Ni−BG is the background noise power. Also, to satisfy input impedance requirement, 1 ZIN = > 10Relec. (4.11) 2 · OSR · fB · C1

Using Equations 4.10 and 4.11, a lower and a higher limit for OSR can be set based on the electrode impedance. Figure 4.5(a) shows the oversampling ration versus the electrode impedance for two different input signal bandwidth. The area highlighted by green colour is where both noise and impedance (CMRR) requirements are met. As CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 134 shown, for ECoG signals with the bandwidth of 500Hz, the circuit satisﬁes both noise and impedance requirements up to an electrode impedance of 30 kΩ. This number reduces to 3 kΩ for EEG action potential with the bandwidth of 5 kHz.

Figure 4.6 shows the electrode-tissue interface impedance for recording electrodes made of different materials, all sized at 1 mm2, which is a typical lower limit for ECoG recording electrodes. As shown in this ﬁgure, the impedance remains under 10 kΩ for frequencies below 0.1Hz. Using the impedance-vs-frequency information from [43] and Figure 4.5(a), a range of permitted OSR can be calculated for different input signal frequencies. This is illustrated in Figure 4.5(b), where it shows that for ECoG signals (BW: 500 Hz) and EEG signals (BW: 5000 Hz), brain activity from 0.07 Hz and 0.7 Hz (respectively), can be recorded without sacriﬁcing noise or CMRR, while having up to 100% variations in electrode-tissue interface impedance.

It should be noted that, as clear from Figure 4.5(a) and (b), for smaller electrode sizes (higher electrode-tissue impedance), this circuit might experience degraded CMRR in recording very low frequencies (<1 Hz). If recording such low frequencies is necessary, the problem can be solved by limiting the recording bandwidth on the upper end. Reducing the recording bandwidth allows for achieving the same OSR (consequently, same noise performance) with smaller sampling frequency. A smaller sampling frequency means a higher input impedance, which directly improves CMRR.

CMRR

In addition to high input impedance, neural front-ends must also yield high common- mode rejection ratio. This is to reject the common-mode electrical interference among channels. For this purpose, any mismatch in the signal path of input and reference electrodes must be eliminated. A common problem in most of multi-channel neural recording systems is the shared CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 135

5 10 BANDWIDTH = 500 Hz IMPEDANCE LIMIT 4 10 NOISE LIMIT 3 10 2 10 1 10 0 10 101 102 103 104 105

5 10 BANDWIDTH = 5000 Hz IMPEDANCE LIMIT 4 10 NOISE LIMIT 3 10

OSR2 OSR 10 1 10 0 10 101 102 103 104 105 ELECTRODE IMPEDANCE (:) (a)

6 10 IMPEDANCE LIMIT BANDWIDTH = 500 Hz NOISE LIMIT 104

2 10

0 10 6 10 IMPEDANCE LIMIT BANDWIDTH = 5000 Hz 104 NOISE LIMIT

2 OSR10 OSR

0 10 10-2 10-1 100 101 102 103 FREQUENCY (Hz) (b)

Figure 4.5: Oversampling ratio versus the electrode impedance for (a) ECoG, and (b) EEG bandwidth. The green area shows the OSR and RELEC values that satisfy both noise and input impedance requirements. CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 136

7 6 Bright Pt Pt Black 5 TiN 4 3 2 Log |Z| (Ohms) 1 0 -20 2 4 Log(f) (Hz)

Figure 4.6: Electrode impedance as a function of frequency for 1 mm2 Pt, Pt black, and TiN electrode materials [43] reference electrode among all channels, which results in a signiﬁcantly lower input impedance for the reference electrode compared to the signal electrode in each channel. In other words, even if the ICMRR (Independent CMRR) of each channel is above the commonly-accepted threshold (i.e., 70 dB), the Total CMRR (TCMRR) is degraded signiﬁcantly as the number of recording channels are increased. For the presented front-end, since the reference electrode is connected to all of the channels (VREF input), the input impedance seen from this electrode is

1 ZIN = , (4.12) N · fs · C1 where N is the number of recording channels. Based on this equation, the input impedance mismatch between the signal input and reference input increase linearly with the number of channels. To avoid this issue, the reference electrode must be connected to the recording channels in a time-multiplexed fashion. Figure 4.7 depicts the timing strategy for the signal and reference electrodes connected to all the channels. In this design, each channel uses 1016 different clocks each with a delay relative to CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 137

N,1 N,2 1,1 1,2 2,1 2,2 N-1,1 N-1,2 N,1 N,2 1

TIME

Figure 4.7: Time-multiplexed sampling of signal and reference electrodes for different channels.

others. The clocks are used for sampling, comparator (preset, decision, output settling), ampliﬁer power-gating, charge-pump timing, etc. The total duration of on-time of these clocks should not exceed the period of the sampling frequency. As a result, even in the original design which did not have the time-multiplexing feature for the reference electrode, we had to reduce the sampling clock duty cycle to 1/100 of its period. As a result, adding time-multiplexing up to 100 channels wont affect the settling time requirements of the front-end, and consequently does not result in higher power consumption.

4.4.3 Closed-Loop Neurostimulation

Each channel is equipped with a neural stimulator that generates arbitrary-waveform current-mode pulse-trains. The stimulator circuit, depicted in Figure 4.8 is comprised of two segments of 4-bit binary-weighted programmable push/pull current sources. The segments are biased using two current references different by a factor of 16 for a total of 8 bits of resolution. Thick-oxide transistors are used to be able to increase the stimulator voltage compliance up to 3.3V. Also the minimum current (ILSB) is programmable which allows for changing the minimum/maximum stimulation current for different applications. The biasing circuit of the current DAC is shown in Figure 4.9. CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 138

Vdd Vdd Vdd Vdd

5/0.4ȝm Vbp_H 0.5/0.4ȝm Vbp_L 10/0.4ȝm 1/0.4ȝm

b7 b4 b3 b0 TRIG U/D U/D U/D U/D Electrode b7 b4 b3 b0 U/D U/D U/D U/D I (I )/8 (16I )/8 REF REF 16IREF REF 10/0.4ȝm 5/0.4ȝm 1/0.4ȝm 0.5/0.4ȝm Vbn_H Vbn_L

Figure 4.8: Circuit schematic of 8-bit current-DAC used for current-mode stimulation as well as in-channel multiplication (all the transistors are thick oxide).

0.5/0.4ȝm 2.5/0.4ȝm 6/0.4ȝm 3.5/0.4ȝm 1/0.4ȝm

VPG-LOW VPG-HIGH 1.6k 0.4/1ȝm 1/0.4ȝm

0.5/0.4ȝm 1.5/0.4ȝm 0.4/1ȝm

IBIAS 0.5/0.4ȝm 0.4/1ȝm

1/0.4ȝm 1/0.4ȝm 1/0.4ȝm 1/0.4ȝm VG-LOW VG-HIGH

Figure 4.9: Circuit schematic of the biasing circuit for the 8-bit current DAC (all the transistors are thick oxide). CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 139

Q VCM N 1 V DOUT= CH1 k1 k2 VIN Z-1

k2 Z Z-1 (a)

DIN M63 M62 M1 M0

1 1 1 1 DOUT Z Z Z Z (b)

Figure 4.10: (a) Simpliﬁed z-domain block diagram of the recording front-end with in-channel multiplier. (b) Transposed-form 64 tap FIR ﬁlter implemented using in-channel analog-digital multipliers.

4.4.4 In-Channel Multiplication

As was shown in Figure 4.3, and described earlier, multiplying a number to the gain of the feedback integrator (Σ2) helps the front-end to record signals with large amplitudes (as large as vdd) without increasing the clock frequency that increases the dynamic power consumption. The current-mode DAC described in the previous section can be reused as an analog-digital multiplier. On/off programmability of the current sources by an 8-bit word 1/M, effectively implements compact multiplication. For the block diagram shown in the Figure 4.10(a),

( ) ( − 1) Y z = | k1 z | 2 , (4.13) X(z) (z − 1) + k2(z − 1) + k1 · k2 CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 140 where z is equal to,

⎛ ⎞ ⎛ ⎞ j2π · fs · Ts j2π ⎝ ⎠ ⎝ ⎠ (jωTs) n · OSR n · OSR z = e = e = e (n ≥ 2) (4.14)

As a result, equation 4.13 can be simpliﬁed to,

Y (z) π (4.15) X(z) k2 · OSR which shows that a coefﬁcient in the feedback integrator has an inverse effect on the channel digital output. Equation 4.15 also shows that increasing clock frequency (i.e. OSR) has a similar effect and scales down the digital output, but in cost of higher dynamic power consumption.

4.4.5 Dual-Input-Mode Operation

Figure 4.11 shows how the presented voltage-recording front-end could be configured for current recording. Using four additional switches, shown in Figure 4.11(a), the the DC-removing input voltage integrator is bypassed and the electrode is directly connected to the comparator positive input terminal. In this mode, the negative input of the comparator is connected to a fixed DC voltage ideally close to a value where it is most sensitive at (0.4V). In this configuration, CINT adds and integrates both input current and the output current of the current DAC in the feedback. With a high enough oversampling ratio, the ΔΣ loop ensures that the two input terminals of the comparator remain at the same voltage levels. This eliminates the need for an OpAmp which is required in conventional current recording systems. CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 141

VREF[n]-VREF [n-1] 0.4V ∑1 Δ1 I / V V / I Δ2 (I) ELECTRODE UP/DN OUT I / V COUNTER RST=0 M D

∑2 (Q) UP/DN

V / I COUNTER OUT IDAC D V [n-1] RST Δ IN CINT M

(a)

VREF[n]-VREF [n-1] ∑1 Δ1 Δ2

ELECTRODE (I) UP/DN OUT

COUNTER D RST=0 ∑2

UP/DN (Q) COUNTER OUT

IDAC D

RST Δ

CINT

(b) Δ2 0.4V O (I) UP/DN COUNTER OUT ELECTRODE O D ∑2 RST

IDAC

CINT

(c)

Figure 4.11: (a) Simpliﬁed block diagram of the presented dual-mode voltage-current recording neural ADC. (b) The neural ADC, when operating in voltage-recording mode. (c) The neural ADC, when operating in current-recording mode.

CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 142

FOCUS OF THIS WORK THIS OF FOCUS

Z Z

OUT

1 D 1

M1 M64 DSP

BPF &

IN SEIZURE DSP FOR 64-TAP D

64-to-8 DETECTION

PHASE-BASED FIR FILTER

[1:64] [1:64]

OUT OUT

D M M D M Δ

(3.1-10.6GHz, <10cm) (3.1-10.6GHz,

UWB TX UWB DELAY-BASED RST RST=0

UP/DN UP/DN

(3.1-10.6 GHz, <2m) GHz, (3.1-10.6 REC/STIM COUNTER COUNTER UWB TX UWB

STIM. POLARITY

VCO-BASED

MUX REUSED 1 0 STIM. PARAM. 8 IMDAC MUX

10 MUX 0 1 1/M TIMING CONTROL CONTROL CONTROL N CONTROL WIRELESS TX RECORDING Q STIMULATION INT C REC/STIM 1/f NOISE CMD CLK 3 V 1.2 V FOCUS OF THIS WORK LOW-FREQ CM NOISE CH COMPONENT V ASK A simpliﬁed functional diagram of the presented neurostimulator SoC and peripheral blocks. ACTIVE ACTIVE REC/STIM CHANNEL AND LDOs RECEIVER RECTIFIER RECEIVER REFERENCE CHANNEL X64 1.5 MHz INDUCTIVE 64 CLOSED-LOOP ARBITRARY-WAVEFORM NEUROSTIMULATOR POWER & COMMAND POWER X1

Figure 4.12:

IN REF OUT [1:64] V V [1:64] I CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 143

4.5 System VLSI Architecture

Figure 4.12 depicts the system VLSI architecture of the fabricated responsive neurostimulator SoC. It includes 64 closed-loop neurostimulators, a low-power DSP with a compact mixed-signal FIR ﬁlter, two UWB transmitters, and an inductive command and power receiver.

4.5.1 Tone-Selection Filter

In the seizure detection mode, a high-Q bandpass filter is required. Since the analog EEG signal is digitized by the front-end, a digital filter must be used. An FIR filter is preferred over IIR (infinite impulse response) as it preserves the phase. Based on our MATLAB simulations, for an FIR filter, the minimum number of taps for such quality factor is 64. A conventional implementation of this filter requires 64 8-bit digital multipliers for each recording channel. This number can be reduced by half when there is symmetry in the filter coefficients (|Mi| = | M63–i| for i = 0,1,...,63) so only 32 filter coefficient absolute values are utilized in the multiplication. Conventional implementation of a 64 tap 12-bit FIR filter with symmetric coefficients, requires 32 12-bit digital multipliers per filter, which results in 2048 (32 × 64) 12-bit multipliers for 64 channels. The other option is to share one 12-bit multiplier for all the taps and clock it 64 times faster, which results in a more compact design, but has significantly higher dynamic power consumption, and requires additional memory cells for the filter coefficients. In this design, by taking advantage of in-channel mixed-mode multipliers, a bank of 32 adjacent channels is used to implement this computation in parallel as depicted in Figure 4.12. We have previously shown the idea of compact FIR implementation using CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 144

Table 4.1: Comparison of Different Implementations for 64 64-tap FIR ﬁlters.

Spec. 64x32 Digital Multipliers *64x1 Digital Multipliers This Work

Power Diss. of Mult. 2048×PMult 64×32×PMult 0 Power Diss. of ADC 64×PADC 64×PADC 64×32×PADC Power Diss. of Add./Reg. 64×PAdd,reg 64×PAdd,reg 64×PAdd,reg Area of Mult. 2048×AMult. 64×AMult. 0 Area of Add./Reg. 64×AAdd,reg 64×AAdd,reg 64×AAdd,reg Power Diss. 2048×PMult.+64×PADC 64×32×PMult+64×PADC 64×32×PADC +64×PAdd,reg +64×PAdd,reg +64×PAdd,reg Est. Power Diss. (mW) 2.79 2.79 1.45 Total Area 2048×AMult.+64×AAdd,reg 64×AMult.+64×AAdd,reg 64×AAdd,reg Est. Area (mm2) 78.53 7.1 4.8 Power×Area 219.1 19.8 6.96

2 2 Note: AMult.=0.036mm , AAdd,reg=0.075mm ,32×PADC =4.16μW, Padd,reg=18.5μW, PMult.=0.78μW *Additional area and power dissipation required for memory. in-channel multipliers of SAR ADCs [2]. When operating in the filtering mode, at each sample, all the 32 channels are connected to one of the electrodes using a 32-to-1 multiplexer. To maintain the same output data-rate, channels are clocked 32 times faster. Table 4.1 compares the three mentioned methods in terms of area×power efficiency. As presented, the mixed-mode multiplication results in 31.5 times lower power-area product compared to the filter with 64 multipliers, and 2.84 times compared to the case with one over-clocked multiplier. Since implementing 64 64-tap adders and registers banks required 4.8 mm2, we only implemented 8 FIR filters which are shared by the 64 channels. Even for 8 filters, the power-are product is reduced by x14 and x1.3 compared to the other two implementation options.

4.5.2 Seizure Detection and Closed-Loop Stimulation

The FIR filter selects a targeted tone and its output is fed to an on-chip DSP that calculates the phase synchrony among channels to detect epileptic seizures. Once a detection is made, an arbitrary-waveform current-mode stimulation is applied to a subset of the CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 145 stimulation electrodes with a spatio-temporal profile specifically chosen for a given subject. In each neurostimulator channel the IMDAC utilized in the neural recording Δ2Σ ADC is reused for current-mode stimulation (at a different programmable bias point) in a time-multiplexed fashion. Thus arbitrary-waveform stimulation enabled by analog-digital multiplication is performed at almost no extra area cost. The recorded EEG/ECoG data and status signals are also transmitted out transcutaneously. One low- power delay-based short-range UWB transmitter [166] and one VCO-based long-range UWB transmitter [167] are used to communicate data to on-skin wearable receivers (d<10cm) and indoor stationary receiver (d<2m), respectively. Energy is transmitted by a single coil through a multi-coil cellular inductive link at 1.5MHz frequency. The power receiver outputs 30mW maximum power for the 15cm transmission distance with power efficiency of 40 percent [15]. An ASK-demodulating command receiver reuses the same inductive link to recover transmitted commands and the clock.

4.6 Experimental Results

Figure 4.13(a) shows the micrograph of the neurostimulator SoC. The chip is designed and fabricated in a 0.13 μm CMOS technology and is 2.6 × 2.3 mm2. It has two power supplies of 1.2V for neural recording and 3.3V (2.5V, when powered wirelessly) for current-mode stimulation. The ﬂoor-plan of each channel is shown in Figure 4.13(b). Thanks to removing large input passive components and the compact architecture of Δ2Σ ADC, the channel only occupies 0.013mm2. As illustrated, each channel houses a recording neural multiplying ADC, a current-mode stimulator, two up/down counters for quadrature decimation, and a memory that stores multiplication coefﬁcients and stimulation signal properties. CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 146

2.3 mm

POWER & COMMAND RX UWB TX2 4x 64-TAP FIR FILTERS UWB TX VCO-BASED 8 x 8 ARRAY OF NEUROSTIMULATION

2.6 mm CHANNELS

DIGITAL 4x 64-TAP PROCESSOR FIR FILTERS

(a) 0.13 mm 12-BIT COUNTER LOGIC RATOR INPUT COMPA- INTEG- RATOR CLK DRIVER CONTROL 0.1 mm MULTIPLIER STIMULATOR/ 12-BIT COUNTER OUTPUT MUX/DRIVER MEMORY

0.13 mm (b)

Figure 4.13: (a) Micrograph of the SoC with major blocks labeled. (b) Floor plan of the neural recording/stimulation channel. CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 147

4.6.1 Mixed-Signal Front-End

Figure 4.14 depicts experimentally measured data for the neurostimulation channel. Figure 4.14(a) shows the experimentally measured FFT of the ADC output with 130 Hz input sampled with an OSR of 1000. The channel yields an SNR and ENOB of 82.2dB and 11.7 bits, respectively. Figure 4.14(b) shows the input-referred noise without and with correlated double sampling, measured to be 8.19 and 1.13μVrms, respectively, when integrated over 0.1 to 500Hz ECoG frequency band. this results in a noise efficiency factor of 2.86 for the whole front-end (amplifier + ADC). Figure 4.14(c) shows three examples of waveforms generated by the arbitrary- waveform current-mode stimulator witha1kΩ load. The amplitude is set with 8 bits of resolution and it can be updated every 22 clock cycles. The experimentally measured CMRR at 30 Hz is 89.1 dB. Figure 4.15(a) shows the experimentally measured CMRR (using the setup shown in figure 4.16) and PSRR of the front-end amplifier for a double-supply range of input DC offset voltages. As shown, unlike the digitally assisted DC-coupled front-ends [3, 48, 74], both parameters are independent of offset values as the front-end works based on the difference between two consecutive samples and the absolute value of the DC offset does not change feedback current-DAC output.

4.6.2 Mixed-Signal FIR Filter and Digital Backend

Figure 4.17(a) shows the frequency response of the 64 tap FIR filter when it is programmed to perform bandpass filtering with three different center frequencies. As shown, with a sampling rate of 80 S/sec, the 64 tap filter yields a high selectivity for CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 148

Figure 4.14: Experimentally measured results for the neurostimulator channel: (a) power spectral density of the neural ADC with 130 Hz input at full scale, (b) input-referred noise with and without correlated double sampling. (c) Neural stimulating current into a 1kΩ load for different pulse shapes and duty cycles. 100 95

90 CMRR

MAG (dB) 85 PSRR 80 -1 -0.8 -0.6-0.4 -0.2 0 0.2 0.40.6 0.8 1 INPUTOFFSET(V)

Figure 4.15: Experimentally measured neural front-end CMRR and PSRR vs input DC offset. CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 149

FFT OF THE VDD GND OUTPUT

SIN(ȦW '& VIN ǻ2Ȉ%$6(' SIN(ȦW '& V REF NEURAL ADC

-1v < DC1-DC2 < 1v Faraday Cage

Figure 4.16: Experimental test setup for CMRR measurements.

(a)

0 fs: 80 Hz 64 TAPS −10 −20 MAG (dB) −30 (b) 0 5 10 15 20 25 30 35 40 INPUT FREQUENCY (Hz) 0.01 0 INPUT:8Hz+40Hz

INPUT(V) −0.01 2560 2048 DIGITAL OUTPUT 1536 200 HPF at 20Hz 0

DIGITAL −200 OUTPUT FILTERED 0 50 100 150 200 TIME (ms)

Figure 4.17: (a) Frequency responses of the programmable FIR ﬁlter for different center frequencies, (b) An example of the FIR ﬁlter performance for a two-tone input (8Hz and 40Hz) and the FIR being programmed as a HPF with a pole at 20Hz. CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 150

MULTI-TONE INPUT 1 ) V 0 m (

INPUT -1 (a) QUADRATURE FILTERED OUTPUTS 0.5

V) 0 m ( 0.5 FILTERED (b) OUTPUT PHASE ERROR 1 0

ERROR -1 (DEGREE) (c) ON-CHIP CALCULATED PHASE 400 200

PHASE 0

(DEGREE) 0 5 10 15 20 25 TIME (ms) (d)

Figure 4.18: Experimentally measured (a) input multi-tone sinulsoidal signals (b) reconstructed output of the FIR band-pass filter programmed at 200Hz for both in-phase and quadrature signals, (c) quadrature output phase error with reference to ideal 90 degrees, (d) 8 bit phase output of the on-chip processor. center frequencies of 10, 20 and 30Hz. Figure 4.17(b) shows the front-end output for a two-tone input. As shown, the input is comprised of a 40Hz as signal and an 8Hz as low frequency drift. The digital output shows that the neural ADC captures both the signal and low frequency drift. To remove the low frequency component, the FIR filter is programmed as a high-pass filter with a corner frequency of 20Hz. The digital output after filtering is shown in the bottom of Figure 4.17(b). Figure 4.18(b) shows the quadrature outputs of the channel for a multi-tone input CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 151

Figure 4.19: Experimentally measured output spectrum of the pulse for the (a) delay-based UWB transmitter, and (b) VCO-based UWB transmitters. The experimental measurements were performed by N. Soltani. shown in Figure 4.18(a). The phase error compared to the ideal 90◦ phase difference, and the calculated phase using the on-chip processor are also shown in Figure 4.18(c) and (d), respectively.

4.6.3 Wireless Radio, and Inductive Powering

Two wireless transmitters were tested experimentally with receivers located in different distances from the SoC. For both transmitters, a custom receiver board was used and placed in 10 cm and 2 m distances. Figure 4.19(a) and (b) show the power spectral density of the short- and long-range UWB transmitters, respectively. For the short-range transmitter, the experimental measurements shows a maximum of 10 Mbps data-rate at 10 cm, that promises a high-throughput link for short distance communications to a wearable on-skin receiver. Higher data-rate and longer transmission range are achieved using the VCO-based UWB transmitter, in cost of higher power consumption. The experimental results shows a maximum of 46Mbps measured at a maximum distance of 2m from the SoC. The inductive power/command receiver is designed to work with an inductive pow- CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 152 ering system, previously reported by our group [120]. For the inductive transmitter, the load current is optimized for the highest power transfer efficiency. At this point, the input impedance of the on-chip active rectifier is matched to the output impedance of the receiver coil. Ton increase the quality factor of the receiver coil, a 32-layer stacked flexible PCB coil is used. The experimental results show a quality factor of 24 and a power transfer efficiency of 40 %. The RX coil receives a signal with an amplitude limited to 3V [120], which is converted to a noisy DC signal at 2.9V with 70mV ripple at the output of active on-chip rectifier. The output of rectifier is fed to on-chip LDOs with steady 2.5V and 1.2V DC outputs, both with less than 5mV ripple at all time, which only limits the system from recording signals with lower than 0.1μV amplitude, considering the front-end high PSRR. These voltages are used as reference inputs to the 8-output 8-bit voltage DAC, to generate biasing voltage on the chip.

4.7 In Vivo Experiments

An on-chip-calculated CORDIC-based phase-synchrony indicator is used for early detection of epilepsy seizures [158]. The absolute phase and phase synchrony are calculated between pairs of channels and seizure is detected by applying thresholding on the phase synchrony indicators. Upon detection, a programmable arbitrary-waveform pulse-train is triggered to a subset of 64 current-mode stimulation channels for seizure abortion.

4.7.1 In-vivo Early Seizure Detection and Control

The SoC was validated in vivo for both detection (experiment 1) and control (experiment 2) of temporal lobe epilepsy (rat model). For this purpose, 4AP was injected CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 153

(a) SEIZURE DETECTION (NO STIMULATION) ,&((*)5205,*+7+,332&$0386 6(,=85(216(7 (mV) 01 RH

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TIME (sec) Figure 4.20: Experimentally measured seizure detection and control results: (a) an example of seizure detection for the first experiment (no stimulation), and (b) an example of a seizure abortion for second experiment (detection+SoC-triggered stimulation). Animal experiments are done with the assistance of M. T. Salam CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 154 intraperitoneally into a Wistar rat to induce the appearance of recurrent spontaneous temporal-lobe seizures. At this point, rats underwent craniotomy with general anaesthesia and micro-electrodes were implanted into the hippocampus. Following the implantation and recovery period, the rats were connected to the presented system for the spontaneous recurrent electrographic seizures recordings and automatic seizure detection. As well, rats were connected to a commercial recording system and were video-monitored for the clinically associated behaviors during seizure activity (e.g. convulsions). Thus, seizures were classified according to electrographic and behavioral features. Figure 4.20(a) shows an example of in-vivo online on-chip real-time seizure detection without stimulation. In the second experiment, the SoC was configured to automatically trigger the closed-loop electrical stimulation for the purpose of suppressing upcoming seizures. Figure 4.20(b) illustrates the SoC-triggered stimulation upon a seizure onset detection.

4.7.2 Ofﬂine Early Seizure Detection in Humans

Figure 4.21 shows an example of off-line early seizure detection in human ECoG data from a University of Toronto epileptic patient. Eight hours of ECoG data was collected from three patients with a total of 12 seizures and were fed to the SoC and its detection performance was evaluated. As shown, the seizure is detected prior to its clinical onset using the on-chip synchrony-based algorithm. CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 155

Table 4.2: Summary of the experimental results

SYSTEM: Technology IBM 0.13μm Supply Voltage (Rec.) 1.2V Supply Voltage (Stim.) 2.5/3.3V Die Dimensions 2.6mm×2.3mm Area Per Channel 130μm×100μm No. of Recording Channels 64 No. of Stimulation Channels 64 Power Dissipation (Rec.) 1.43/5.8mW RECORDING CHANNEL: Bandwidth 0.01-500 0.01-5kHz Power/Ch 0.63 6.25μW Noise Bandwidth 0.1-500 0.1-5kHz Input-Ref. Noise 1.13 3.53 NEF 2.86* Area 0.013 CMRR @ 30 Hz 89.1 dB THD @ 130 Hz 0.6% ADC SNDR 82.2 ADC ENOB 11.8 bits STIMULATION CHANNEL: Type Arbitrary current Voltage Compliance 3.1V Current Matching 1 % Current Range 10μA-1.35mA DAC Resolution 8 bits WIRELESS TX: Modulation UWB Freq. Band 3.1-10.6 GHz Architecture Delay-based VCO-based Data Rate 10Mbps 46Mbps Range 10cm 2m Power Diss. 100μW 3.7mW WIRELESS POWER: Receiver Coil: Type 8-layer ﬂexible Size 2cm x 2cm No. of turns 104 Inductance 176 μH Coil Separation 15cm Power Transfer Efﬁciency 40% Frequency 1.5 MHz No. of Voltage Levels 10

*: Ampliﬁer + ADC CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 156

6(,=85('(7(&7,21

5,*+7+,332&$0386((* 9

5+ 9

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9 6(,=85(216(7'(7(&7,21 '(7(&7,217+5(6+2/' 3+$6(6<1&+521< 7,0( 6(& Figure 4.21: An example of ofﬂine early seizure detection in a human patient. Human data were provided by M. T. Salam.

4.8 Discussion

4.8.1 Resource Utilization

A summary of experimental measurement results is shown in Table 4.2. Also Fig- ure 4.22(a) and (b) shows the power breakdown of the chip when operating with the delay-based and VCO-based UWB transmitters, respectively. When operating with 5kHz bandwidth, the SoC dissipates 1.43 mW with the delay-based UWB transmitter and 5.8 mW with the VCO-based transmitter. For the same bandwidth, the 64 neural ADCs consume around 0.4 mW for 64 channels resulting in 6.25 μW per channel. Figure 4.22(c) shows the area breakdown of the chip (excluding routings, IO pads and decoupling capacitors for supplies). The total area occupied by 64 recording and stimulation channels together with the digital back-end, wireless transmitters and power CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 157 management circuits is 3.86 mm2. The 64-tap FIR ﬁlters and the synchrony processor have the biggest quota with 33 % followed by the 64 recording front-ends with 25.5%. The 64 stimulators are added to the chip with less than 0.1% area overhead since they share some blocks such as DAC and the memory (for duty-cycle control) with the recording circuitry.

4.8.2 Area and Power Scalability

Figure 4.23(a) shows how the power consumption of all the blocks scales linearly with the input signal bandwidth. As shown, the channel dissipates a total of 630nW and 6.25μW for ECoG and EEG bands, respectively. This results the advantage of working with significantly lower power, when recording signals with smaller bandwidth required, such as local field potentials. Figure 4.23(b) shows how the active-component-dominated channel area scales with the CMOS technology node compared to a conventional AC-coupled channel [2]. In this figure, the black line shows how the minimum gate width scales with the technology, and the red circuits shows the estimated scaled channel area based on [168]. Since the presented channel area is dominated by active components, its area scales almost linearly with technology, which allows for integration of 1000+ channels for high-definition brain recording when the design is taken to a newer technology.

4.8.3 Comparison to the State of the Art

The SoC is compared with the state of the art in terms of applications, system integration and performance, and neurostimulation channel performance. A comparison with other neural monitoring and/or neurostimulation SoCs is given in Table 4.3. In terms of applications, the functionality of the presented design is validated in vivo for monitoring, detection and abortion of epileptic seizures. However, due to the CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 158

POWER BREAKDOWN* (WITH DELAY-BASEDUWB TX) DIGITAL POWER & BACKEND COMMAND RXX 600 μW 260 μW UWB TX 100 μW CLK. GEN. & BUFFERS BIASINGS 45 μW 20 μW

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64 RECORDING CHANNELS 403 μW VCO-BASED BIASINGS UWB TX 20 μW 3.7 mW

TOTAL POWER: 5.8 mW (b) AREA BREAKDOWN POWER & COMMAND RX 11.4% DIGITAL BACKEND CLK. GEN. & 33.3% BUFFERS 11.5%

64 RECORDING UWB TX1 & 2 CHANNELS 0.7% 25.5% VCO-BASED UWB TX 17.5% TOTAL AREA: 3.86 mm2 (c) * INPUT FREQUENCY BANDWIDTH : 0 - 5kHz

Figure 4.22: Power breakdown of the integrated circuit operating in two modes: (a) with the delay-based UWB transmitter, and (b) with the VCO-based UWB transmitter. (c) Area breakdown of the IC. CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 159

CHANNELPOWER SCALABILITY

TOTAL 10 PREAMPLIFIER SWITCHED-CAPS

W) COMPARATOR

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100 500 1000 5000 RECORDING BANDWIDTH (Hz) (a)

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0.05 IDEAL 0.01 AC-COUPLED [3] 0.02 0.01

AREA (mm THIS WORK

0 ACTUAL 130 9065 32 CMOS TECHNOLOGY (nm) (b)

Figure 4.23: (a) Channel power scalability with the input signal frequency bandwidth, (b) Com- parison between conventional ac-coupled and presented Δ2Σ-based channel area scalability with CMOS technology node. ability to record signals with rail-to-rail ac amplitude and DC offset variations, the chip is capable of recording other physiological signals with amplitudes much larger than the nominal maximum 1 mV for EEG signals. In terms of system integration, this work demonstrates the highest degree of integration among recently published state-of-the-art SoCs by combining 64 rail-to-rail signal recording channels, 64 current-mode arbitrary-waveform stimulation channels, 64 multiplying Δ2Σ ADCs, a multi-core DSP unit, short- and long-range wireless transmitters, and wireless power and command receivers. In terms of the channel design, this work has the smallest channel area while ampli- ﬁer and ADC and part of the BPF is included in the channel. It also features the lowest integrated input-referred noise and power consumption for the ECoG band, which results in the lowest reported NEF for this band. The power consumption is scalable CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 160 with the input signal frequency bandwidth, and the channel area is scalable with CMOS technology node.

4.9 Conclusion

A CMOS fully-wireless closed-loop neuro-stimulation SoC is presented. The 6 mm2 die integrates 64 rail-to-rail differential Δ2Σ neural recording channels with in-channel correlated double-sampling mixed-signal multiplication, multi-core digital signal processing unit, dual-band FSK/UWB wireless transmitters, active rectiﬁers, regulators and DACs for inductive power receiving, ASK demodulator for command receiving, and 64 in-channel synchrony-triggered current-mode arbitrary-waveform stimulators for abortion of undesired neurological events. The SoC is implemented in IBM 0.13 μm technology and dissipates 1.43 and 5.8 mW with the delay-based and VCO-based UWB transmitters, respectively. The power consumption of neurostimulation channels scales with input signal frequency bandwidth. Also, thanks to removing large passive components, the channel exhibits the smallest reported area, which is dominated by active components that are scalable with technology. The SoC is validated in an in-vivo epilepsy monitoring (seizure detection) and treatment (seizure suppression). CHAPTER 4. 64-CHANNEL RAIL-TO-RAIL-INPUT CLOSED-LOOP NEUROSTIMULATOR IC 161 0.01-5k 5kHz THIS WORK 0.13 1.2/3.3 1.43/5.8 64 64 5.98 Yes 15 200 2.86 0.013 Yes 0.01-1.35 0.01- 500 0.630.1-500 0.1- 6.25 1.13 3.53 - - 0.03 Table 4.3: [2] [23] [169] [80] 1.2 Genov Rabaey Xu Wu State-of-the-art neural recording and/or stimulation SoCs Vrms) 4.7 1.23 4.13 5.23 μ ) 0.09 0.025 0.042 - 2 W) 10 2.3 2.8 53.7 μ m) 0.13 0.065 0.065 0.18 μ ) 12 5.76 - 13.47 2 of Recording Channelsof Stimulation Channels 64 64 64 0 16 0 8 1 Power/Channel( Input Referred Noise( Noise Bandwidth(Hz) 10-5k 1-500 1-8.2k 0.5-7k Bandwidth (Hz) 0.1-7k 1-500 1-8.2k 0.1-7k Supply (V)Power (mW)# # Area (mm Closed-Loop Signal ProcessingWireless Power Range (cm)Wireless Data Comm. Range (cm) Yes 1.2/3.3 0.1 1.4 No N/A 0.5 N/R 0.225 1.6 No 0.5 - N/A N/A Yes 1.8 N/R Area/Channel (mm N/R 2.8 Closed-Loop StimulationStimulation Current (mA) Yes 0.01- No No Yes NEF 4.4 4.76 2.93 1.77 Technology ( SpeciﬁcationSYSTEM: JSSC’13 JSSC’15 ISSCC’15JSSC’14 CHANNEL: -: Not Applicable N/R: Not Reported 162

Chapter 5

Power-Adaptive High-Voltage-Compliance Electrical and Optical Neurostimulators

In this chapter a board-level and a chip-level high-voltage neurostimulators are presented. Both systems are implemented on miniaturized platforms and are interfaced with the wireless data/power communication modules introduced in Chapter 2. Both systems offer high voltage compliance which is required for applications such as muscle stimulation and cochlear and epiretinal implants. In the first section of this chapter, Section 5.1, a hybrid current-mode and optogenetic miniature neurostimulating system is presented. The 16-channel electrical stimulator outputs arbitrary-waveform charge-balanced current-mode stimulation pulses with the amplitude ranging from 0.05mA to 10mA. To optimize power consumption, the supply voltage is automatically adjusted through an impedance monitoring feedback loop that gauges the minimum required headroom voltage. The 8-channel optogenetic stimulator reuses the arbitrary-waveform generation functions of the electrical stimula- CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 163 tor. Each pulse-generator drives one LED with a maximum of 25mA. The LEDs are assembled within a custom-made 4×4 ECoG grid electrode array, which enables precise optical stimulation of neurons with a 300μm spatial resolution and simultaneous monitoring of the neural response by the ECoG electrode, at different distances of the stimulation site. The implantable system is a 3×2.5×1cm3 stack of a receiver coil and two mini-boards. The power is received by a 32-layer flexible inductive coil and is regulated by the wireless communication board. The adaptive neurostimulator board boosts the regulated voltage up to the level set by the feedback loop with a maximum of 24V. The system also receives stimulation parameters wirelessly from the amplitude-shift- keyed power carrier. Both electrical and optogenetic stimulation results from chronic and acute in vivo rodent experiments are presented. In the second section, Section 5.2, a wireless high-voltage-compliance implantable 4-channel dual-mode neurostimulator SoC is presented. The SoC is capable of both current- and voltage-mode stimulation with a voltage compliance of up to 20V, and operates in both mono-polar and bi-polar configurations. Each channel is wirelessly programmable to generate independent arbitrary waveforms (8-bit resolution). A dual-loop impedance-monitoring digital controller is designed to adjust both the voltage headroom in each channel, and the system global voltage supply for all channels. The controller ensures the supply voltage is set to the minimum required value demanded by the stimulation current amplitude and instantaneous electrode impedance of each channel. Our experimental results shows a 68.5% saving in the power consumption due to the load-aware adaptive supply voltage. Also, thanks to the supply variations, the stimulator yields 12 bits of dynamic range for the current amplitude, with a minimum of 23μA and maximum of 95mA. To enable biphasic stimulation in mono-polar configuration, a switched-capacitor voltage divider is designed to keep the reference electrode voltage at VCC/2. The system is powered inductively with amplitude shift-keyed power CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 164 signals that also carry configuration commands. The SoC is implemented in a 0.35μm HV-CMOS process, takes 10 mm2, and is mounted on a miniaturized stack of two rigid and one flexible PCBs, with the size of 2 × 2 × 0.7 cm3, and weight of 6 grams.

5.1 Inductively Powered Arbitrary-Waveform Adaptive-

Supply Electro-Optical Neurostimulator Mini-Board

5.1.1 Introduction

In this section we present a combined 16-channel current-mode and an 8-channel optogenetic stimulating system for neural stimulation. Both stimulators can generate arbitrary waveforms (10-bit resolution) for stimulation. A digital controller adjusts the system’s supply voltage to the minimum required value based on the output of a low-power ADC-based impedance monitoring feedback loop with no headroom voltage overhead. Additional circuits are added to the system to ensure safe and charge-balanced stimulation. For freely moving rodent studies, the neurostimulator system is powered by an inductive powering system and receives conﬁguration commands wirelessly using the same inductive link. The presented device could initiate and suppress electrographic seizures in the whole intact brain of optogenetic mice expressing channelrhodopsin-2 (ChR2) in all sub-types of GABAergic inter-neurons. The device exploited the spatial and temporal control of GABAergic interneuronal activation with optogenetics in a focal seizure model to successfully initiate electrographic seizures on-demand with a single photostimulus (473 nm; <1 s). The transition into seizure using the light pulse as the temporal reference point for seizure onset was then recorded. Intriguingly, the electrographic seizures in the in vivo 4-AP model was reminiscent of the commonly observed electrographic seizures CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 165 with LVF (Low Voltage Fast activity) onset patterns from patients with medically refractory temporal lobe epilepsy (TLE) [104]. The device can be simply adapted to employ other optogenetic strains of mice to target different neuronal populations in a variety of other in vivo seizure models. The ability to study clinically-relevant electrographic seizures in the completely intact neuronal network of adult mice allows us to avoid issues related to the young age of animals [170] or slicing procedure [171] associated with brain slice experiments. The rest of this section is organized as follows. Section 5.1.2 discusses the top level system architecture of the wireless dual-mode neurostimulator. Section 5.1.3 presents the design implementation of the key functional blocks in the system. Section 5.1.4 describes the architecture of the digital controller used to control the system mode of operation and to ensure optimal power consumption. Section 5.1.5 presents the design and fabrication details of the electrode used for multi-channel dual-mode stimulation and electrical recording. Section 5.1.6 presents electrical experimental results from individual blocks as well as the full system. Section 5.1.7 presents in-vivo online animal results for both seizure initiation and suppression using optical and electrical stimulation, respectively.

5.1.2 System Architecture

Fig. 5.1 shows a simpliﬁed block diagram and system breakdown of the wireless electro- optical neurostimulator. The system is comprised of two rigid PCBs and an inductive coil stacked on top of each other. Dual-mode neurostimulation is performed by the ﬁrst board, on the bottom, while the second board, in the middle, and the coil are used to provide energy and commands to this board. The system has 16 electrical and 8 optical stimulation channels. All channels generate independently-programmed arbitrary waveforms for neurostimulation. The system

CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 166

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45 cm 45 25 mm 25 & COMMAND TX & COMMAND INDUCTIVE POWER

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COMMUNICATION BOARD COMMUNICATION ASK DIGITAL CONTROLLER DIGITAL FOCUS OF THIS CHAPTER INDUCTIVE POWER AND DATA AND DATA INDUCTIVE POWER DECODER RECEIVER COMMAND ADAPTIVE NEURO-STIMULATOR BOARD NEURO-STIMULATOR ADAPTIVE Figure 5.1: of the chapter iselectrical testing on is the done high-voltage withN. the electro-optical Soltani. assistance neurostimulator The of inductive mini-board. F. floor Chen was and designed The B. by Vatankhah. stimulator M. Wireless Aliroteh. board communication board design, and firmware inductive coil development, were and designed by CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 167 connects with both ECoG electrodes and LED arrays that are implanted over the brain cortex surface. To minimize the power consumption, the impedance variations seen at stimulation electrodes are continuously monitored and fed to a digital controller that adjusts the system supply voltage as well as the DC level of the reference electrode to keep the voltage compliance at the minimum required. The stimulator board design, firmware development, and electrical testing is done with the assistance of F. Chen and B. Vatankhah. Fig. 5.1 also depicts how the stimulator board is connected to the wireless power and command receiver board through a vertical connector. The wireless board rectifies and regulates inductively-transmitted power that is sent by a cellular inductive powering rodent cage floor [120], and received by the receiver coil mounted on an animal. The inductive link provides up to 30mW of power at the maximum distance of 15cm. The system utilizes the same inductive link to receive configuration commands.

5.1.3 Design Implementation

Fig. 5.2 shows a simplified block diagram of the neuro-stimulator board. The figure also shows the top and bottom views of the board with all the main components labeled. The system is entirely built using commercial off-the-shelf components, including a low power FPGA, digitally controlled current drivers, a programmable boost converter, an 8-channel LED driver, a crystal oscillator, and a number of flexible flat cable (FFC) and vertical connectors for connection to the stimulation electrode arrays and wireless power/data communication board, respectively. The digital controller implemented in the low-power FPGA is used to control the system mode of operation, channel selection, stimulation parameters for each channel (e.g. waveform shape, amplitude, frequency, etc.), and optimal supply voltage. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 168 FPGA IMPEDANCE 8-CHANNEL LED DRIVER REGULATOR MONITORING ACTEL IGLOO ACTEL & SUPER CAP CRYSTAL OSC CRYSTAL TO ELECTRODES TO CURRENT DRIVERS BOOST CONVERTER CHANNEL SELECTOR TO WIRELESS TO BORAD CONNECTOR TO TO LEDs CONNECTOR VERTICAL CONNECTOR VERTICAL DIGITALLY-CONTROLLED 16-CHANNEL CONNECTOR 30 mm TOP VIEW TOP

BOTTOM VIEW BOTTOM

25 mm 25 mm 25 MID

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SELECTOR CHANNEL BOARD OPTICAL ELECTRO- STIMULATOR HIGH-VOLTAGE DC VOLTAGE DOWN-CONVERTER b2 b1 V V SINK SOURCE

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TO REFERENCE ELECTRODETO

CONTROLLER STIMULATION CURRENT STIMULATION ADJUSTABLE 8 SUPPLY BOOST CONVERTER IMPEDANCE CONVERTER CALCULATOR CALCULATOR ANALOG-TO-DIGITAL FPGA CENTRAL CLK PROCESSOR LOW-POWER MEMORY

FRONT-END 16-CHANNEL PROCESSOR CONTROLLER

CRYSTAL VOLTAGE STIMULATION OPTICAL

OSCILLATOR

REGULATOR

LED DRIVER LED 8-CHANNEL Simpliﬁed block diagram of the power-adaptive high-voltage electro-optical stimulator board. The stimulator board design, ﬁrmware O1 O2 O3 O8 POWER development, and electrical testing is done with the assistance of F. Chen and B. Vatankhah. Figure 5.2: COMMANDS CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 169

Load-Adaptive Power Supply

As mentioned, although CCS has the advantage of fine control over the charge flow, it could potentially yield a poor power efficiency in case of a supply voltage excess, which becomes a problem especially for the wirelessly-powered systems. To improve the system power efficiency, supply voltage must be adaptive and always set to provide the minimum required voltage compliance, that is set by the product stimulation current amplitude and electrode impedance. Unlike the stimulation current that is known (e.g., set by the clinician), the electrode impedance typically changes during the experiment and must be continuously monitored. In this design, an 8-bit low-power ADC is used to sample the voltage across the electrode, digitize it, and send it to the FPGA. With this information, the controller implemented on the FPGA determines the minimum supply voltage required for the current stimulator. Initially since the impedance of the tissue is unknown, the supply voltage is set at maximum. A normal-operation window is defined with upper and lower thresholds. To avoid unnecessary changes of the supply voltage due to high-frequency noise or interference, the controller only decides to change the supply voltage if the sampled voltage passes either threshold for a certain period of time. Once a decision is made, a new supply value is sent to a low-voltage digital-to- analog converter (DAC) that feeds a boost converter responsible for generating the supply voltage. The adjustable boost converter receives a steady 3.3V from the inductive power receiver board and generates a DC voltage up to 24V depending on the command it receives from the FPGA. Such high supply voltage provides a large voltage headroom for current drivers and consequently enables higher stimulation currents. Considering a 1.5-2V drop on current sources (Isource and Isink), for a typical 1kΩ tissue resistance, the system can provide up to 10mA current. The updated supply voltage will be posi- tioned at 1.5V higher than the sampled voltage in order to accommodate the headroom CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 170 voltage of the current source. If the new voltage is higher than the boost converter can supply, the FPGA sets the supply voltage to 24 and also generates an overflow signal to notify the user. Once the stimulation for the channel is completed, FPGA saves the last voltage level into the channel profile so that the minimum voltage can be provided at the start of next iteration.

Programmable Pulse Shape

The results in [173, 174] show that the pulse shape does affect the stimulation effectiveness in the amount of charges delivered to the tissue per second. With the optimal waveform, the current amplitude needed can be reduced and ultimately this leads to additional power savings. For the current-mode stimulation, common-base BJT current drivers are controlled using digitally-adjustable potentiometers connected in series with the emitter to generate a current from 50μA to 10 mA. The 10-bit potentiometer itself is controlled digitally by the FPGA and has 1024 positions, which allows for a very ﬁne control on the stimulation pulse shape. Also a timer is implemented on the FPGA to keep track of the stimulation duration.

Safety Features

To avoid charge accumulation, the current-mode stimulator is always programmed for equal overall charges ﬂowing in and out of the tissue. However, the mismatch between the anodic and cathodic currents could result in a residual charge that must be removed.

As shown in Fig. 5.2, a discharging path to the reference electrode VMID for the targeted tissue is employed to compensate for the mismatched error. The same switch is used to discharge accumulated charge on the ac-coupling capacitor due to switches CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 171 leakage current. A sudden high current inrushes into the tissue when switching the stimulation path on and off can alter the stimulation effect or damage the tissue. A voltage limiter built using Zener diodes is employed in the system to prevent a high current ﬂowing into the tissue. When high current is ﬂowing into the electrode, it will induce a high voltage. Once the voltage across electrode reaches above 27V, the Zener diode will fall into the breakdown region, diverting the high current into the ground.

Optical Stimulation

For the optical stimulation, an LED light source is driven by a current as governed by its exponential I-V relationship. As a result, higher stimulation currents does not require a significant increase in the voltage across the LED, which makes the 3.3V sufficient for the operation. Therefore, independent electrical and optical stimulation not only enables simultaneous modes of operation, but also saves a significant amount of energy that would be wasted in LEDs otherwise. An 8-channel digitally-controlled LED driver is utilized to provide up to 25mA current to the LED array and is supplied with a fixed 3.3V voltage.

Wireless Powering and Communication

For an implantable/wearable system designed for rodent studies, power and conﬁgura- tion commands should ideally be provided wirelessly to avoid bulky and heavy batteries and wires. The inductive link provides up to 30mW with the maximum distance of 15cm away from the transmitter. The power carrier is amplitude shift-keyed to communicate the conﬁguration commands from a computer to the implantable system using the same CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 172

TIME MEMORY TRACKER

STIM TRIGGER DATA FROM FRONT-END STIM. CENTRAL

WIRELESS RX PROCESSOR DATA PROCESSOR MEMORY VOLTAGE 16 CHANNEL LEVEL I2C, SPI IC CONTROLLER

Figure 5.3: Block-level architecture of the digital system implemented on the FPGA. wireless link. A 470mF super capacitor is utilized that gets charged during the idle phase and provides stable supply voltage during stimulation phase for a maximum of 2 minutes continuous pulse-train with the maximum signal’s amplitude. A comparator is utilized to monitor the power usage of the system. If the voltage of the super capacitor falls below 3.6V, the FPGA will stop the stimulation to avoid abnormal behavior under low power conditions.

5.1.4 Architecture of Digital System

The architecture of the digital system is presented in Fig. 5.3. The front-end processor can decode commands including start, pause, and stop stimulation, configuring the pulse shape, channel selection, and mode of operation. Most of these commands activate the central processor to generate proper signals to different blocks on the board. For the configuration of pulse shape, the front-end processor places all the incoming data into FPGA memory. The data consists of all the pulse shape information for each channel, including channel identifier, stimulation period, number of repetition, start time, width of pulse-train and amplitude. The receiver stops accepting data once the end of command bit is detected. The protocol also contains reserved bits for checking data integrity. The benefit of collecting all the configuration parameter at start is to reduce CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 173 the use of communication system during stimulation. When the stimulation is triggered, the central processor decodes the data in the memory following a custom protocol. The first word informs the central processor the number of pulses used to define the desired pulse shape. It also tells the central processor which stimulation channel to turn on. After acquiring these information, the central processor decodes one pulse command at a time. The current level encoded in the pulse command is then sent to the potentiometer controller. The potentiometer controller converts the data to the specified SPI protocol and sends it to the IC component. The potentiometer IC requires 10μs to receive the data and to stabilized the resistor. The minimum pulse width for each stimulation pulse is therefore 10μs due to the set-up constraint. During stimulation, the time tracker is turned on and continuously compares the internal timer with the specified pulse width. Once the pulse width is reached, another line of the pulse commands will be decoded in the central processor. This process continues until the central processor decodes the same number of pulse commands specified in the first line of pulse shape command set. The last command for the pulse shape command set defines the wait time between two consecutive stimulation waveforms. During this time, the system is set to the idle state to minimize the power consumption. Also in the idle state, the stimulation channel is grounded to reestablish charge balancing. At the end of every channel stimulation, the highest voltage recorded by the ADC is saved in the channel memory so that the information can be utilized at the start of next repetition of stimulation.

5.1.5 Electrode Design

The ECoG electrode was fabricated on a polyimide sheet with a thickness of 100 μm (The electrode is designed by Dr. M. T. Salam, a post doctoral fellow in our group). Polyimide material was chosen for its ﬂexibility, chemical stability, and biocompatibil- CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 174

(a)

(b) (c)

Figure 5.4: ECoG grid: (a) Layers of ECoG (not to scale), (b) fabricated ECoG electrode array, and (c) LEDs assembled within the dual-layer ECoG electrode array (opcog) and blue light passing through the opcog from LED 1. Electrode design and fabrication is done by M. T. Salam and Ch. Lucasius. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 175

CH1

CH2

CH3 2 ms 5V

CH4

Figure 5.5: Four experimentally-measured arbitrary waveforms generated simultaneously by the neurostimulator for an nominal 1kΩ load. ity properties. For the electrode material, gold was chosen for its biocompatibility and compatibility with the microfabrication process. First metallization layer was formed (800 nm) using DC sputtering deposition and was patterned using photolithography and wet etching to create the routing tracks (Fig. 5.4(a)). The ﬁrst metallization layer was used for the electrode connection routing. The second layer of Polyimide was spin coated and another metallization layer was deposited similarly for the electrode con- tact. Light emitting diodes (LED) were soldered with the electrode contacts of a ECoG and sandwiched in between two ECoG electrode using epoxy. The fabricated ECoG electrode and LEDs assembled in the ECoGs are shown in Figs. 5.4(b) and (c).

5.1.6 Electrical Measurement Result

Fig. 5.5 shows an example of four experimentally-measured simultaneously-generated electrical stimulation waveforms for a nominal 1kΩ load. As illustrated, each channel is CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 176

Figure 5.6: Experimentally-measured voltage waveforms of the adaptive supply and reference voltage. The system keeps the supply voltage at the optimum value for a 2mA stimulation current while load impedance varies.

Figure 5.7: Comparing the power consumption of the system with adaptive supply to the case with the ﬁxed supply, for different electrode impedances. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 177

(mA) 4

STIMULATION CURRENT 0 2 3 4 10 10 10 (a) 10

0.1 CURRENT (mA) ANODIC/CATHODIC 0.01 3 4 10 10 POTENTIOMETER RESISTANCE (:) (b)

Figure 5.8: Experimentally-measured (a) stimulation current, and (b) anodic and cathodic current amplitudes, for different values of the digitally-controlled potentiometer. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 178

RIGHT BIPOLAR ECoG GRID HIPPOCAMPUS ELECTRODE WITH LEDs BIPOLAR WITH ELECTRODE CANNULA

LEFT CORTEX CRANIOTOMY

REFERENCE RIGHT ELECTRODE BRAINSTEM STEREOTACTIC FRAME (a)(b)

Figure 5.9: (a) Microelectrode chronic implantation and (2) placement of LEDs assembled within a ﬂexible ECoG electrode array (opcog) through a craniotomy on the cortex (The procedure is done by Dr. M. Tariqus Salam).

independently programmable with a 50μA resolution and the 10mA maximum amplitude. The highest resolution of the pulse width which the system can invoke is 100μs. This limitation is imposed by the data transmission and the programming time of the potentiometers. Fig. 5.6 shows the adaptive power supply value when the load impedance is changed in small steps from 100Ω to 5kΩ and then back to 100Ω. As shown, the supply voltage increases with a maximum delay of 1ms/volts. The mid-range voltage VMID used for the reference electrode also follows the supply voltage variations with a less than 1 ms delay. Figure 5.7 depicts the comparison of system power consumption in two cases of with and without the adaptive supply control, for different electrode impedances. Figure 5.8(a) shows how the stimulation current driver output varies when the digitally- controllable potentiometer in series with a common-base BJT emitter varies from 20kΩ to 60Ω. Fig. 5.8(b) shows the anodic and cathodic current amplitudes generated by the stimulator for different resistor values. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 179

5.1.7 In Vivo Experimental Results

Two in vivo experiments were performed to validate the stimulator. The procedures for both experiments were approved by the ethics committee of the Hospital for Sick Chil- dren and Toronto Western Research Institute, and the experiments were conducted at the Neuroscience and Mental Health Research Institute and Toronto Western Research Institute, respectively.

Electrical Stimulation

The electrical stimulator was validated by stimulating on a Wistar rat (250 gm) hippocampus in an in vivo chronic experiment. For this purpose, four bipolar microelectrodes were implanted into the right hippocampus, left cortex, right brainstem, and the skull as a reference. The hippocampus was stimulated and icEEG from the hippocampus, cortex and brainstem were recorded using a commercial ampliﬁer (Biopac Inc.). In the chronic experiment, the electrical stimulator triggered pulses with 150ms width and 200μA current at 5Hz for 5sec into the hippocampus. The stimulation effect propagated to the brainstem quickly, which partially inhibited cortical activity (shown in Fig. 5.10).

Optical Stimulation and Electrical Recording

In the second experiment, the optical stimulator was tested by shining blue light on the cortex of a transgenic mouse (p50) in an in vivo acute experiment. The mouse was anesthetized using Ketamine (95 mg/kg) and Xylazine (5 mg/kg) and mounted in a stereotactic frame. The scalp was removed and the OpCoG (optical/ECoG electrode) was placed througha4mmdiameter craniotomy on the somatosensory cortex. VGAT-ChR2 mice was obtained from The Jackson Laboratory (JAX; Maine, USA) expressed channel rhodopsin in all GABAergic interneuronal subtypes [175]. Ketamine CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 180

2 RIGHT HIPPOCAMPUS 2 1 1 50 ms

0 (mV) 0 ELECTRICAL STIMULATION LEFT CORTEX 0.5 0 -0.5

RIGHT BRAINSTEM 0.5 ICEEG RECORDING (mV) RECORDING ICEEG 0 -0.5

1 3 57911 TIME (sec)

Figure 5.10: Electrical stimulation of the hippocampus and icEEG recordings in the hippocampus, cortex and brainstem. The animal experiments are done with the assistance of M. T. Salam and F. Chen.

(95mg/kg) and Xylazine (5mg/kg) were used to anesthetize the selected mice (either sex, 35-60 days old). The selected mice were mounted in a stereotactic frame, and after application of anesthesia (Lidocaine), the scalp removal was done to expose the front oparietal cortex. Sice the somatosensory cortex was covered with warmed isotonic saline solution, a 4 mm diameter craniotomy was then performed (at 2.0mm latero- medial and -2.0 mm rostro-caudal) to expose it. To induce recurrent electrographic seizures, 4 Aminopyridine (4-AP) was dissolved in saline (1.5 mM) and topically applied on exposed cortex [111, 176]. Pharmacolog- ical agents were allowed 10–15 minutes to perfuse before any segments of data were analyzed. In the ﬁrst experiment, the stimulator triggered a blue light pulse for 30ms and the icEEG was recorded using ECoG electrode array contacts. In the acute experiment, the blue light triggered spikes around the LED, and these spikes gradually propagated to regions with an approximately 1mm distance. Due to the abnormal light response of CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 181

LED # 1: ON μV 2 s 500 μV 500 200 ms

LED # 2: ICEEG RECORDING OFF

TIME (sec)

Figure 5.11: A brief (30 ms) optical stimulation using LED1 and spatiotemporal propagation of neuronal excitation in a ChR2-expressing mouse. The animal experiments are done with the assistance of M. T. Salam and F. Chen. this experiment, the OpCog array was tested for a light-induced voltage artifact called ”photoelectric effect”, by observing the light response when the electrode is placed in an agarose gel. since the test result was positive, we decided to ignore all the results from this set of experiments, and repeated all the experiments after the electrode array was fixed. an example of light response recorded from 12 channels is shown in Fig- ure 5.11. In the second experiment Photostimulation (470 nm) of various durations (1–20s) was delivered at a fixed interstimulus interval (period) of 300s, a value close to the in- trinsic rate at which electrographic seizures occurred spontaneously. For electrographic seizures, the onset was defined as the LVF onset pattern4 and the offset was defined to be when rhythmic, high-amplitude ictal activity ceased. Figure 5.12 and 5.13 show two examples of 4-channel recordings of brain neural activity before, during and after 5s and 20s optogenetic stimulations, respectively. As shown, immediately after the optogenetic stimulation is finished, the low voltage fast ictal activity is observed. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 182

Figure 5.12: Four channel recordings of brain neural activity before, during and after 5s optogenetic stimulation in an epileptic animal, illustrating post-stimulation LVF ictal brain activity.

Control experiments were repeated with C57BL/6 mice to test for any photoelectric effects or photostimulus-induced phenomenon (unrelated to ChR2 depolarization) in the naive brain tissue. Figure 5.14 shows an example of control experiment results where no ictal activity is observed following the stimulation. Procedures involving animals were performed in accordance with the guidelines of the Canadian Council on Animal Care and approved by the Institutional Animal Care Committee. The animal experiments are done with the assistance of M. Chang, Ch. Lucasius and F. Chen.

5.1.8 Conclusion

A wireless hybrid current-mode and optogenetic miniature neuro-stimulating system is presented. The 16-channel electrical stimulator outputs arbitrary-waveform charge- balanced current-mode stimulation pulses with the amplitude ranging from 50μAto 10mA and voltage compliance up to 24V. To save power, the system continuously monitors the varying electrode impedance and adjusts its supply voltage accordingly. The CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 183

Figure 5.13: Four channel recordings of brain neural activity before, during and after 20s optogenetic stimulation in an epileptic animal, illustrating post-stimulation LVF ictal brain activity.

Figure 5.14: Four channel recordings of brain neural activity before, during and after 20s optogenetic stimulation in a control animal. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 184

8-channel optogenetic stimulator reuses the arbitrary-waveform generation functions of the electrical stimulator, and drives 8 LEDs with a maximum of 25mA. The dual-mode neurostimulator is connected to a wireless power/data communication board and a ﬂex- ible 32-layer coil, to form a 3×2.5×1cm3 wireless implantable device. To perform simultaneous optical stimulation and electrical recording, a custom-made array of 4×4 ECoG electrodes and LEDs is fabricated, which allows for stimulation with a 300μm spatial resolution and simultaneous monitoring of the neural response by the ECoG electrode, at different distances of the stimulation site. Both electrical and optogenetic stimulation results from chronic and acute in vivo rodent experiments are presented.

5.2 A Battery-less Implantable High-Voltage Arbitrary-

Waveform Dual-Mode Neurostimulator IC with Load-

Aware Current-Optimized Power Supply

5.2.1 Introduction

In this section we present a 10 mm2 4-channel dual-mode neurostimulator SoC (system on a chip), implemented in a 0.35μm HV CMOS process and mounted on a miniaturized inductively-powered wireless platform, with the size of 2 × 2 × 0.7 cm3, and weight of 6 grams. A simplified block diagram of this system as well as its envisioned mounting configuration on a rodent head is depicted in Figure 5.15. Each neurostimulation channel can generate independently-programmable arbitrary waveforms with 8 bit resolution. A dual-loop monitoring digital controller adjusts the channel voltage headroom for each channel and system global supply voltage for all the channels to the minimum required value based on the product of stimulation current amplitude and instantaneous electrode impedance of each channel. A switched-capacitor voltage divider, sets the CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 185 voltage at the reference electrode to VDD/2, to enable bi-phasic stimulation when the stimulator is operating in a mono-polar configuration. For freely moving rodent studies, the neurostimulator system is powered by an inductive powering system and receives configuration commands wirelessly using the same inductive link. The inductively- received power signal is rectified and regulated, and is boosted using a charge-pump that is controlled by the on-chip digital controller, to generate optimum supply voltage for the system. The rest of this chapter is organized as follows. Section 5.2.2 describes the motivation for a custom IC implementation of the HV stimulator. Section 5.2.3 discusses the top level system architecture of the wireless neurostimulator. Section 5.2.4 presents the design implementation of the key functional blocks in the system, and describes the architecture of the digital controller used to control the system mode of operation and to ensure optimal power consumption. Section 5.2.5 presents experimentally-measured results from individual blocks as well as the full system.

5.2.2 Motivation

The system presented in the previous section of this chapter provides 16-channel electrical stimulation with high voltage compliance. Despite the advantages of this system, its 16 channels are time-multiplexed, making it incapable of performing simultaneous multi-channel stimulations. Since the design is implemented using discrete components, implementing more than one physical (real) channel will result in signiﬁcant increase in the area, and makes the device size infeasible for implantation. Additionally, integrating channel-speciﬁc load monitoring feedback loop to such a time-multiplexed system, to optimize power supply for each channel independently, could only be done if switching between channels is done slower than a certain rate. This motivates for a system with dedicated stimulation channels for simultaneous CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 186

POWER & SCALP FOCUS OF THIS WORK COMMANDS

4 CHANNEL INDUCTIVE LOAD-AWARE POWER AND POWER-EFFICIENT COMMAND HIGH-VOLTAGE 8 RECEIVER FLOOR

NEURO-STIMULATOR INDUCTIVE STIMULATION ELECTRODES RECORDING & RX TX TRANSMITTER RX COIL

STIMULATIONMULATION SSITEITE

Figure 5.15: Simplified block diagram of the presented high-voltage miniaturized neurostimulator. An envisioned implanting configuration is also depicted. multi-channel stimulation, with in-channel voltage-compliance controller that allows for setting the supply voltage independently for each channel. To be scalable, the design must be implemented as a silicon integrated circuit in a high-voltage process. This also allows for not being constrained by the commercial ICs specifications, and the capability to optimize all the blocks for power consumption.

5.2.3 System VLSI Architecture

Figure 5.16 depicts the system architecture of the presented neurostimulator. The power and stimulation configuration commands are received by the inductive coil. An ASK demodulator receives the configuration commands and pass them to a low-power FPGA on the board to decode and provide proper commands to the SoC at the right time. The power signals are fed to an active rectifier and then to two low-dropout regulators (LDOs) to provide a 3.3V and a 6V supply voltages. The 3.3V is used for all the low- voltage blocks on the chip, and the 6V serves as the input of the on-chip charge pump CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 187

INDUCTIVE POWER & DATA RX DIGITAL CHARGE REFERENCE CONTROLLER PUMP GENERATOR 6v 3.3v CH4 V CH3 REF CH2 CH1 + L2 - VHR

LOW-DROP LOW-DROP I1 REGULATOR REGULATOR + I2 - VHR I3 LIMIT MONITOR L1 I4 HEADROOM ASK

FPGA CONTROLLER

RECEIVER 8 LOW-POWER

ACTIVE RECTIFIER HV NEUROSTIMULATOR IC

RX COIL FOCUS OF THIS WORK

Figure 5.16: Block diagram of the miniaturized neurostimulator SoC. The HV neurostimulator IC is shown on the right and the block diagram of inductive power and data receiver board is shown on the left.

that generates the SoC global supply voltage. To cope with the voltage compliance requirements of the applications mentioned in the introduction, the SoC is designed and implemented in a high-voltage process that allows for voltage levels of up to 20V. Depending on the commands received from the on-chip digital controller, the charge-pump sets the supply voltage at a level between 6 to 20V, with 3 bits of resolution. The VCC generated by the charge pump is sent to a low-ripple SC-based reference generator circuit that sets the voltage at the reference electrode to VCC/2 to ensure bi-phasic stimulation is possible for all the channels. All the channels on the SoC are independently programmable and generate arbitrary waveforms with a resolution of 8 bits. To minimize power consumption, two nested control loops are employed to ensure that the available voltage compliance in each channel is set to the minimum required value. The first loop that is implemented in the CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 188 channel level, monitors both targeted stimulation current and instantaneous electrode- tissue impedance in each channel, and feeds the recordings to an in-channel digital headroom controller that adjusts the voltage at the electrode to the minimum value that can deliver the target stimulation current to that particular electrode impedance. The second control loop that is implemented once for the entire chip is used to adjust the global VCC, and only gets activated if the limit-monitoring blocks implemented in each channel send a flag signal indicating the first loop inability to provide the optimum compliance. If any of the limit monitors detects that the channel cannot provide the required headroom voltage with the current value of the VCC, it triggers the second loop to increase the supply voltage. On the other hand, the loop only reduces the VCC if all the in-channel limit monitors indicate that the required headroom can be provided by a smaller VCC.

5.2.4 VLSI Circuit Implementation

Figure 5.17 depicts the circuit implementation of the load- and current-optimized dual- mode neurostimulation channel with peripheral circuits required for its operation. The channel is equipped with a low-power area-optimized 8-bit current DAC (digital to analog converter) to generate arbitrary stimulation waveforms. At each clock cycle, the current DAC generates the desired stimulation current amplitude, ISTIM, and a control loop (L1) ﬁxes the voltage at the electrode to VCC/2 + ISTIM × RL to ensure constant current stimulation. The stimulation current and the reference current are converted into voltages and fed to a comparator, effectively comparing the current values.

Addaptive Supply Control

In case of a load impedance variation, the stimulation current changes instantaneously, causing a change in comparators negative input terminal. Depending on whether impedance

CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 189

CM V =VCC/2 C

C GENERATOR FPGA LOW-POWER CM CH1 CH2 CH3 CH4 V

I V VCC C C V ADAPTIVE VCC GENERATOR R-to-R − + STIMULATION VOLTAGE/CURRENT CURRENT DAC PUMP CHARGE + + − − 6v 3 CP_CLK R-to-R R-to-R VCC R 20R VCC VCC Q 3-BIT VOLTAGE DAC COUNTER rst C C R-to-R V L2 8 L1 VCC VCC VCC VCC 3.3 3.3 Simpliﬁed circuit schematic of the load- and current-efﬁcient neurostimulator channels with the in-channel and backend digital QADJ UP/DN HEADROOM CONTROLLER 2 4 8 LIMIT B7..B0 B7..B4 CONTROL SUPPLY CONTROLLER SUPPLY Figure 5.17: controller, and switched-capacitor voltage divider. The chip design and layout is done with the assistance of Y. Hu and Ch. Liu, respectively. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 190

200/1.4 200/1.4 VBP 200/1.4

200/1.4 200/1.4 200/1.4 200/1.4 500/2.4 VN VP V1

1pF V2 V2 1pF 100/1 100/1 100/150/1V3 50/1 100/1

100/1 100/1 260/2.4

VBN 100/1 100/1

RAIL-TO-RAIL OUTPUT INPUT STAGE STAGE

Figure 5.18: Simpliﬁed circuit schematic of the rail-to-rail opamp.

is increased or decreased, the comparator output sends an up- or down-counting command to a counter that sets the digital input of an 8-bit voltage DAC used to adjust the voltage at the electrode. A change in the reference current also gets compensated through a similar process done by the internal loop, L1. This dedicated in-channel control loop allows for optimizing the electrode voltage of each channel independently, which results in a signiﬁcant saving in power consumption. An in-channel limit control block constantly monitors the 4 most signiﬁcant bits of the counter, and the result is fed to a chip-level control loop (L2) that increases or decreases the global VCC with a 3 bit resolution. To enable bi-phasic stimulation using a single supply, a switched-capacitor voltage divider always makes sure that the reference electrode voltage, VCM is set to VCC/2. An SPDT (single-pole double-throw) switch at the channel output provides the option of connecting the output to a voltage buffer, which enables power-optimized voltage-mode stimulation. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 191

RAIL-TO-RAIL DYNAMIC PREAMPLIFIER COMPARATOR

10/1.4 10/1.4 40/1.4 40/1.4 40/1.4 40/1.4 20/1.4 20/1.4 clk clk

V +V- IN 80/1 80/1 IN

20/1 20/1 OUT- OUT+ clk 10/1

80/1

80/1 clk 10/1.4

clk 10/1

VIN-V40/1.4 40/1.4 IN+

80/1 80/1

Figure 5.19: Circuit schematic of the rail-to-rail clocked comparator.

VDDLOW VDDMID VDDMID VDDHIGH VDDHIGH

2.8/0.35ȝm 20/0.6ȝm 20/0.6ȝm 20/1.1ȝm 20/1.1ȝm VO1 VOUT VIN 1.4/0.35ȝm 20/0.5ȝm 20/0.5ȝm 60/0.5ȝm 60/0.5ȝm V VIN O1

Figure 5.20: Circuit schematic of tri-stage logice level shifter connecting high voltage blocks to low-voltage digital controller. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 192

Vdd Vdd Vdd Vdd

160/1.4ȝm 20/1.4ȝm 160/1.4ȝm 20/1.4ȝm Vbp_H Vbp_L

b7 b4 b3 b0 TRIG U/D U/D U/D U/D Electrode b7 b4 b3 b0 U/D U/D U/D U/D I (I )/8 (16I )/8 REF REF 16IREF REF 20/1.4ȝm 20/1.4ȝm 160/1.4ȝm 160/1.4ȝm Vbn_H Vbn_L

Figure 5.21: Circuit schematic of 8-bit current-DAC used for reference current generation.

Circuit Implementations

Figure 5.18 shows the simplified circuit schematic of the rail-to-rail opamp used in the design of the stimulation channel. The opamp must be able to operate with an input DC that varies from 6 to 20V, as its inputs are connected to the stimulation electrodes directly. Therefore, a rail-to-rail folded-cascode architecture with both NMOS and PMOS input stage is chosen. Also, to drive large currents, a common-source buffering output stage is added. As the output of the opamps are connected to the comparator, this block is also designed to be able to handle rail-to-rail inputs. Figure 5.19 shows the simplified circuit schematic of the dynamic comparator with a rail-to-rail preamplifier. Figure 5.20 shows the circuit schematic of the level shifter used to shift the logic level of digital signals from 3.3 to 20v and vice versa, with minimum power dissipation. Figure 5.21 shows the circuit implementation of the current-DAC used to generate reference stimulation current. To make a compact design and also avoid ratio mismatch, the circuit is designed with two separate banks of current mirrors that use parallel reference current sources with a ratio of 16 to 1. This effectively yields a resolution of 8 bits for the stimulation current amplitude. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 193

TMH=1

TMH Q [7:4]=1000 DEL=DEL+1 VCC TOO ADJ LIM_MID=0 LIM_MID=1 HIGH

COMP=0 DEL=0 NORMAL Q =Q +1 Q =Q -1 Q =3b’0 OPERATION ADJ ADJ ADJ ADJ RESET=1 VCC COMP=1

COMP=0 COMP=1 Q [7:5]=111 LIM_ANY ADJ Q =Q +1 VCC TOO LIM_EDGE LIM_EDGE VCC VCC LOW =0 =1

Figure 5.22: State diagram of the digital FSM controller used for supply voltage control.

Digital Controller

Figure 5.22 shows the state diagram of the on-chip digital controller. During the normal operation mode, the in-channel comparator output is used to increase/decrease the digital equivalent of the voltage (QADJ ) at the electrode connected to that channel. The

4 and 3 most significant bits of QADJ are constantly monitored to detect the lack or excess of voltage headroom in any of channels, respectively. The QADJ changes according to the stimulation current or load impedance variations. Once the 3 MSBs of the QADJ become all ones (or all zeros for a negative pulse amplitude), it means that the voltage compliance required for stimulation is very close to the maximum that the current VCC can provide. This triggers the LIMEDGE flag which sends a command to the on-chip charge pump to increase the VCC by one step. If the 4 MSBs of QADJ become 4b’1000, and stays at this value for a certain amount of time, it means that the required electrode voltage is close to half of the supply voltage (i.e. far from the lower and upper limit). This triggers the LIMMID flag, and if the flags for all channels are up for a certain period of time, it means that the supply voltage is higher than the minimum required level, and must be decreased. As shown, the LIMMID signals of all channels CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 194 are connected to an AND gate, and once the gate output becomes 1, the controller waits for a certain programmable amount of time and then goes to the start-up mode to recal- culate the minimum required supply voltage.

System Miniaturization

Figure 5.23 shows the miniaturized neurostimulation system with an inductive floor used to transmit energy and configuration commands to the system. The implantable system is comprised of two mini-boards and a 32-layer inductive receiver coil [120], stacked on top of each other. The receiver coil and the wireless board are used to provide power and configuration commands to the first board. The wireless board receives inductively-transmitted waveforms from the receiver coil, rectifies and regulates them, and provides multiple DC voltages for the neurostimulator SoC through a vertical bus connector. The power receiver outputs 30mW maximum power for the 15cm transmission distance with power transfer efficiency of 40 percent. An ASK-demodulating command receiver reuses the same inductive link to recover transmitted commands and the clock. The first board has the neurostimulator IC implemented in a 0.35 mumHV process directly wire-bonded on it. Both of the mini-boards are equipped with a low- power FPGA, one for receiving and decoding stimulation commands, and the other for controlling the SoC mode of operation. Figure 5.24 shows the top and bottom view of the neurostimulator board with the IC being directly wire-bonded on it (under the epoxy glob top). The HV stimulator board design is done with the assistance of G. Dutta.

5.2.5 Experimental Results

Figure 5.25(a) shows the micrograph of the 4-channel neurostimulator SoC. The chip is designed and fabricated in a 0.35 μm CMOS technology and is 5 × 2mm2. It has a CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 195

20 mm

7mm 20 mm

INDUCTIVE 20mm 20mm POWER RECEIVER 20 mm POWER & POWER COMMAND COMMUNICATION THIS BOARD CHAPTER

26 cm 45 cm 20 mm INDUCTIVE POWERING FLOOR HV STIMULATOR BOARD

Figure 5.23: Components of the wireless implantable high-voltage neurostimulator device. The HV stimulator board design is done with the assistance of G. Dutta. Wireless communication board and inductive coil were designed by N. Soltani. The inductive ﬂoor was designed by M. Aliroteh.

ﬁxed power supply of 3.3V for low-voltage blocks and a variable adaptive supply of 6- 20V for high-voltage blocks, both provided inductively. The ﬂoor-plan of each channel is shown in Figure 5.25(b). Each channel includes a current DAC, a voltage DAC, three rail-to-rail opamps, a rail-to-rail comparator, a few voltage level-shifters and a digital controller. Except for the blocks that were directly connected to a high-voltage node, all the blocks are implemented using low-voltage devices to realize a compact design. The chip design and layout is done with the assistance of Y. Hu and Ch. Liu, respectively.

Dynamic Range

Figure 5.26 shows the measured stimulation current amplitude versus load impedance for different VCC values. Each channel can provide currents from 23μA to 95mA as CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 196

TOP BOTTOM EPOXY DIRECT ON PCB GLOB TOP WIREBONDING

Figure 5.24: Top and bottom view of the neurostimulator mini-PCB with the IC being directly wire-bonded on it. The HV stimulator board design is done with the assistance of G. Dutta. The chip design and layout is done with the assistance of Y. Hu and Ch. Liu, respectively. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 197

5 mm

DIGITALCP

STIMULATION CHANNELS 2 mm

BUFF

(a)

OPAMPS +COMPARATOR +BIASINGS HHEADROOM CONT. DAC 1.05 mm

VOLTAGE CURRENT DAC

1.25 mm

(b)

Figure 5.25: (a) The chip micro graph with major blocks labeled. (b) Floor plan of a neurostimulation channel. The chip design and layout is done with the assistance of Y. Hu and Ch. Liu, respectively. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 198

0.1 VCC=6v 0.08 VCC=10v VCC=14v 0.06 VCC=20v

0.04

0.02

STIMULATION CURRENT (A) 0 2 3 4 5 10 10 10 10 LOAD IMPEDANCE (Ohms)

Figure 5.26: Experimentally measured stimulation current amplitude versus load impedance for 4 VCC examples. the load is varied from 100kΩ to 100Ω, which is approximately equivalent to a 12 bit dynamic range. The output stage of the rail-to-rail opamp connected to each channel output is designed to handle a maximum of 100mA, to enable stimulating very high currents to load impedances smaller than 100Ω, which is unique compared to the state of the art.

Current DAC

Figure 5.27(a) and (b) show the experimentally measured differential (DNL) and integral nonlinearity (INL) of the DAC, respectively. Both parameters are below 0.2 LSB. Also the mismatch between anodic and cathodic stimuli measured at the full-scale current of 9.5mA for a 1kΩ load is 2.1%.

Arbitrary Waveform

Figure 5.28 shows four different experimentally-measured stimulation waveforms generated by 4 channels on the stimulator. The ability to generate arbitrary waveforms, en- CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 199

0.2 0.1 0 −0.1 −0.2 0 32 64 96 128 160 192 224 255

0.2 0.1 0

INL (LSB)−0.1 DNL (LSB) −0.2 0 32 64 96 128 160 192 224 255 DAC CODE

Figure 5.27: Experimentally measured differential and integrated nonlinearity of the 8-bit current DAC used for reference stimulation current generation.

MINIMIZED STIMULATION-INDUCED TISSUE DAMAGE MINIMIZED ENERGY REQUIRED FOR STIMULATION

MAXIMIZED CHARGE DELIVERY

5V OVERALLY

2S OPTIMIZED

ALL WAVEFORMS MEASURED FOR 1KΩ LOAD

2.50 V 2.50 V 2.50 V 2.50 V

Figure 5.28: Experimentally measured waveforms generated by the 4 stimulation channels, optimized for a different purpose. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 200

20 15 10 (V)

ELECTRODE 5 CONSTANT STIMULATION CURRENT V 256 HIGH LIMIT

ADJ 128 LOW LIMIT Q 0 20 15 10 VCC (V) 5 0 VCC TOO SMALL 1 LIMIT EDGE 0 0 1 2 3 4 5 6 TIME (s)

Figure 5.29: Electrode voltage, digital controller outputs and supply voltage when load impedance is varied. ables the stimulator to be optimized for different purposes. In this case the stimulation waveforms are optimized for (a) minimized stimulation induced tissue damage [179], (b) minimized energy required for stimulation [180,181], (c) maximized injected charge for a stimulation energy budget [182,183], and (d) optimized over all the mentioned purposes [184].

Adaptive Supply

Figure 5.29 shows the experimentally measured global VCC and electrode voltage of one of the channels as the impedance is increased continuously. As shown, an increment in the load impedance, causes the electrode voltage to increase, and once the QADJ reaches its highest permitted value close to its maximum (high limit), the limit controller signal, edge limit, becomes one, which triggers the charge-pump to increase the VCC. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 201

Also, in case of excess of available headroom, which keeps QADJ close to its mid-range (8b1000xxxx), the other limit controller signal, low limit, becomes one, and if it stays one for a certain amount of time that is set by a digital delay controller, the VCC is recalculated to ensure it has the minimum required value.

5.2.6 Discussion

Energy Saving

Figure 5.30 shows the energy saving efficiency of the stimulator with reference to the case that its VCC is fixed at the highest value (20V). As shown, the efficiency is a function of both load impedance and stimulation current amplitude. For lower impedance×current that requires smaller supply voltages, using an adaptive supply voltage results in saving a significant amount of energy. On the other hand, high impedance×current values require supply voltage close or equal to the maximum which results in small or no saving in the energy consumption. Since the minimum supply voltage is set to 6V, the energy saving efficiency is limited to 70% theoretically. The maximum measured power saving efficiency is 68.5%.

Resource Utilization

Figure 5.31(a) shows the power breakdown of the chip. The static power consumption of the on chip ampliﬁers, comparators, current and voltage DACs, charge pump, and the digital processors adds up to 530μW when there is no stimulation. Figure 5.31(b) shows the area breakdown of the chip (excluding routings, IO pads and decoupling capacitors for supplies). The total area occupied by 4 stimulation channels together with the digital processor, charge pump and power management circuits is 5.3 mm2. The stimulation channels have the biggest quota with 20 % for each channel. The charge pump capacitors are implemented off-chip to achieve low supply ripple. This does not CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 202

100

60 R =1k: 40 L R =2k: 20 L R =5k: L

ENERGY SAVING EFFICIENCY (%) −2 −1 0 1 10 10 10 10

ISTIM(mA)

Figure 5.30: Experimentally measured energy saving for different stimulation current amplitudes and three examples of load impedance. affect scaling of the stimulator to higher number of channels, as the charge pump block is only repeated once for the entire chip.

Comparison With the State of the Art

The SoC is compared with the state of the art in terms of system integration and performance, as well as neurostimulation channel performance. A comparison with other high-voltage or power adaptive neural stimulator SoCs is given in Table 5.1. In terms of applications, the four independently-programmable stimulating channels, each capable of generating an arbitrary waveform, gives the advantage of stimulating different patterns to the brain simultaneously, each optimized for a different purpose. Also, the dual-mode voltage-current stimulation extends the range of applications for this SoC. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 203

POWER BREAKDOWN

IN-CHANNEL LEVEL SHIFTERS PROCESSOR (X4) DIGITAL BACKEND AND BUFFERS

CHARGE PUMP

VOLTAGE DAC (X4)

CURRENT OPAMP DAC (X4) (X4)

COMPARATOR (X4) (a)

AREA BREAKDOWN

HEADROOM DIGITAL CONTROL PROCESSOR CHARGE PUMP VOLTAGE DAC (X4) LEVEL SHIFTERS AND BUFFERS

OPAMPS (X4)

CURRENT DAC (X4) COMPARATORS (b) (X4)

Figure 5.31: Power and area breakdown of the integrated circuit. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 204

In terms of system performance, the dual-loop adaptive power supply allows for adjusting supply voltage and results in saving power consumption up to 68.5%, compared to a ﬁxed supply voltage. Also miniaturizing the system together with the inductive powering and wireless communication of conﬁguration commands makes the SoC fully-implantable. The presented stimulator achieves the highest stimulation current amplitude of 95mA while having a resolution of 23μA, yielding 12 bits of dynamic range.

5.2.7 Conclusion

A fully-wireless miniaturized 4-channel dual-mode neurostimulator SoC (system on a chip) is presented. The SoC provides current- and voltage-mode stimulation with a voltage compliance of up to 20V. Each channel can generate independently-programmable arbitrary waveforms (8-bit resolution) for stimulation. A dual-loop impedance- and current-monitoring digital controller adjusts the channel voltage headroom for each channel and system supply voltage for all channels to the minimum required value based on the stimulation current amplitude and instantaneous electrode impedance of each channel. The adaptive supply control results in up to 68.5% saving in power consumption. A switched-capacitor voltage divider, keeps the voltage at the reference electrode to VDD/2. The neurostimulator system is powered by an inductive powering system and receives configuration commands wirelessly using the same inductive link. The SoC is implemented in a 0.35μm HV-CMOS process, takes 10 mm2. The system is miniaturized and is implemented using a stack of two rigid and one flexible PCBs (printed circuit board), with the size of 2 × 2 × 0.7 cm3, and weight of 6 grams. CHAPTER 5. POWER-ADAPTIVE ELECTRICAL AND OPTICAL NEUROSTIMULATOR 205 % 1.2 68.5 × THIS WORK 0.35 HV 10 20 4 4 < CURRENT/ VOLTAGE YES YES 1 95 0-1 (10) ARBITRARY 5 % × 60 < 1.12 2.4 × % 62 < 0.26 0.52 × *NO 0.47 0.31 % × Table 5.1: 74 < State-of-the-art neurostimulator SoCs 1.2 0.5 × [185] [76] [78] [178] [75] BIPHASIC EXPONENTIAL ) (3.9) (10) (20) (1) (0.5) Ω m) 0.7 HV 0.35 HV 0.18 HV 0.35 0.35 μ ) 1.2 2 ) 1.44 0.47 26.52 0.58 12 2 FOR NOMINAL LOAD (k INDEPENDENT 1DYNAMIC RANGE (mA)WAVEFORM 1 2 256 PROGRAMMABLE ARBITRARY ARBITRARY 1 BIPHASIC DECAYING 1 0.003-0.5 0.45 1 4 MAX STIM. CURRENT(mA) 1 1 0.5 0.45 4 AREA (mm OF CHANNELS 1 8 256 1 4 AREA (mm SUPPLY# POWER SAVINGSTIMULUS CONTROLWIRELESS POWERWIRELESS DATA COMM. CURRENT 15 NO NO NO VOLTAGE VOLTAGE CURRENT 20 CHARGE NO YES 32 NO YES 3.3 NO NO YES 3.3 YES SpecificationTECHNOLOGY ( TBioCAS’07 ISSCC’11CHANNEL: JSSC’10 TBioCAS’12 JSSC’15 N/A: Not Applicable N/R: Not Reported * : SIMULATION RESULTS. 206

Chapter 6

Conclusions and Future Work

6.1 Contributions and Relevant Publications

The details of each Chapter are described below.

• chapter 2 presents two board-level wireless devices that were designed and implemented as the first step toward a fully-integrated brain machine interface SoC. Both devices take advantage of previously-reported neurostimulator ICs that were designed and tested in our lab as the core component for neural recording and stimulation. In the first section, an inductively-powered implantable microsystem for monitoring and treatment of intractable epilepsy is presented. The miniaturized system is comprised of two mini-boards and a power receiver coil. The first board hosts a 24-channel neurostimulator SoC developed in a 0.13μm CMOS technology [2] and performs neural recording, electrical stimulation and on-chip digital signal processing. The second board communicates recorded brain signals as well as signal processing results wirelessly, and generates different supply and bias voltages for the neurostimulator SoC and other external components. The CHAPTER 6. CONCLUSION AND FUTURE WORK 207

multi-layer flexible coil receives inductively-transmitted power and sends it to the second board for power management. The system is sized at 2 × 2 × 0.7 cm3, weighs 6 grams, and is validated in control of chronic seizures in vivo in freely- moving rats. This work has resulted in two papers published in the proceeding of IEEE BioCAS 2013 and ISCAS 2016 [59] and another paper submitted to IEEE TBioCAS 2016. In the second section of this chapter, first, existing sleep stage classifier sensors and algorithms are reviewed and compared in terms of classification accuracy, level of automation, implementation complexity, invasiveness, and targeted application. Next, the implementation of a miniature microsystem for low- latency automatic sleep stage classification in rodents is presented. The classification algorithm is implemented in an on-board digital VLSI (very-large-scale integration) processor to achieve low-latency (order of 1ms or less) classification. This work has resulted in two conference paper that is published in the proceeding of IEEE BioCAS 2014, and IEEE ISCAS 2016 [155]. An extended journal version of this paper is accepted to appear in IEEE TBioCAS 2016.

• Chapter 3 presents a 16 mm2 0.13 μm CMOS SoC. The chip has 64 DC-coupled neural recording channels, each with a digitally-assisted DC-offset cancellation feedback. Chopper stabilization is employed in each neural ampliﬁer to suppress its ﬂicker noise. Channel-to-channel gain mismatch is removed by utilizing a multiplying ADC, included in each channel, in a digital calibration loop. A multi-core digital processor shared between all the channels, is used to carry out signal feature extraction and epileptic seizure detection. The chip also has 64 programmable bi-phasic current-mode stimulators that are triggered by the on- chip digital processor upon detection of a neurological event, to modulate brain CHAPTER 6. CONCLUSION AND FUTURE WORK 208

activity. Three wireless transmitters are included in the design that enable communication of diagnostic data to a wide range of distances over three different bands of frequency. The chip is powered wirelessly using a magnetic inductive link, with energy signals that are amplitude shift-keyed to communicate conﬁgu- ration commands to the chip. The chip is validated in-vivo on four freely-moving rats and off-line on three human patients. This work has resulted in two conference paper that is published in the proceeding of IEEE ESSCIRC 2014, and IEEE ISCAS 2016 [15]. An extended journal version of this paper is accepted for publication in IEEE JSSC 2016 [74].

• Chapter 4 presents a 0.13 μm CMOS SoC for 64-channel neuro-electrical monitoring and responsive neurostimulation. The Δ2Σ-based neural recording front- end records signals with rail-to-rail input amplitude and rail-to-rail DC offset. The Δ2Σ-based recording channel eliminates the need for bulky DC-removing passive components and yields a compact 0.013 mm2 integration area for amplifier and ADC. Using a current-DAC that is placed in the feedback path of the Δ2Σ ADC, a mixed-mode analog-digital multiplication is performed in each channel. The multiplication is used for compact implementation of band-pass digital filters, as well as voltage gain scaling. The same DAC, is reused as a current stimulator when the SoC is configured to perform responsive neurostimulation. A multi-core low-power DSP performs synchrony-based neurological event detection and triggers a subset of 64 programmable arbitrary-waveform current-mode stimulators for subsequent neuro-modulation. A dual-band UWB wireless transmitters communicate to receivers located at 10 cm to 2 m distance from the SoC. An inductive link that operates at 1.5 MHz, provides power and is also used to communicate commands to an on-chip ASK receiver. The chip occupies 6 mm2 CHAPTER 6. CONCLUSION AND FUTURE WORK 209

and is validated in an in vivo epilepsy monitoring and treatment experiment. This work will be submitted to IEEE ISSCC 2017 (an extended version to IEEE JSSC).

• Chapter 5 presents two neurostimulation systems, one board-level and one chip- level. These systems can work as a stand-alone device and also can be added as an additional module to any of the closed-loop neurostimulator systems presented in the previus chapters. In the ﬁrst section of this chapter, a hybrid current-mode and optogenetic miniature neurostimulating system is presented. The 16-channel electrical stimulator outputs arbitrary-waveform charge-balanced current-mode stimulation pulses with the amplitude ranging from 0.05mA to 10mA. To optimize power consumption, the supply voltage is automatically adjusted through an impedance monitoring feedback loop that gauges the minimum required headroom voltage. The 8-channel optogenetic stimulator reuses the arbitrary-waveform generation functions of the electrical stimulator. Each pulse-generator drives one LED with a maximum of 25mA. The LEDs are assembled within a custom-made 4×4 ECoG grid electrode array, which enables precise optical stimulation of neurons with a 300μm spatial resolution and simultaneous monitoring of the neural response by the ECoG electrode, at different distances of the stimulation site. The implantable system is a 3×2.5×1cm3 stack of a receiver coil and two mini-boards. The power is received by a 32-layer ﬂexible inductive coil and is regulated by the wireless communication board. The adaptive neurostimulator board boosts the regulated voltage up to the level set by the feedback loop with a maximum of 24V. The system also receives stimulation parameters wirelessly from the amplitude-shift-keyed power carrier. Both electrical and optogenetic stimulation results from chronic and acute in vivo rodent experiments are pre- CHAPTER 6. CONCLUSION AND FUTURE WORK 210

sented. This work has resulted in a conference paper that is published in the proceeding of IEEE BioCAS 2015 [177]. An extended journal version of this paper is submitted for publication in IEEE TBioCAS 2016. In the second section, a wireless high-voltage-compliance implantable 4- channel dual-mode neurostimulator SoC is presented. The SoC is capable of both current- and voltage-mode stimulation with a voltage compliance of up to 20V, and operates in both mono-polar and bi-polar configurations. Each channel is wirelessly programmable to generate an independent arbitrary waveforms (8-bit resolution). A dual-loop impedance- and current-monitoring digital controller is designed to adjust both the voltage headroom in each channel, and the system voltage supply for all channels. The controller ensures the supply voltage is set to the minimum required value based on the stimulation current amplitude and instantaneous electrode impedance of each channel. Our experimental results shows a 68.5% saving in the power consumption due to the load-aware adaptive supply voltage. Also, thanks to the supply variations, the stimulator yields 12 bits of dynamic range for the current amplitude, with a minimum of 23μA and maximum of 95mA. To enable biphasic stimulation in mono-polar configuration, a switched-capacitor voltage divider, keeps the reference electrode voltage at VCC/2. The system is powered inductively and receives configuration commands using the same inductive link. The SoC is implemented in a 0.35μm HV-CMOS process, takes 10 mm2. The system is miniaturized and is implemented using a stack of two rigid and one flexible PCBs (printed circuit board), with the size of 2 × 2 × 0.7 cm3, and weight of 6 grams. This work will be submitted to IEEE symposium on VLSI circuits 2016 (an extended version to IEEE JSSC).

• Chapter 6 highlights future work related to the neural interface SoCs described in CHAPTER 6. CONCLUSION AND FUTURE WORK 211

this thesis.

6.2 Future Work

6.2.1 Improvements to SoCs

On-chip Power/Command Receiving Coil

The latest generation of the neurostimulator SoC still requires an off-chip inductive receiver coil to receive power and commands. One improvement option for the next generation of such chip is to implement the receiving on the silicon IC together with the rest of electronic circuits. This of course introduces new challenges due to signiﬁcantly lower power budget that an on-chip coil can receive continuously compared to the multi- layer board level coild. However, such implementation will result in a SoC with an order of magnitude smaller form factor that requires no peripheral components for operation.

Integration of the HV module

Combining the closed-loop neurostimulator SoC with the HV stimulation module on a single system is another system-level effort that could be taken as a future step to this work. It results in a complete system that includes all the features that a subset of them are available in the existing described designs. This is a short step from the current state of the work, as the HV chip described in the second section of chapter 5 is already bonded on a mini-PCB system that interfaces with the wireless data/power miniPCB. The only additional step to reach this goal is to replace the silicon chip on the neurostimulation board described in chapter 2 with the IC that were described in chapter 4. This will result in a 4-board stack with:

• HV stimulation miniPCB (already available from Chapter 5.2) CHAPTER 6. CONCLUSION AND FUTURE WORK 212

• Neurostimulator miniPCB with the IC described in Chapter 4.

• Wireless communication miniPCB (already available from Chapter 2)

• Inductive receiver coil (already available from Chapter 2)

Extending the Dynamic Range

As mentioned, the latest generation of neurostimulator SoC records physiological signals with any amplitude from 10μV up to 1.2V. However, this is not the dynamic range of the front-end, and it only works similar to a variable gain ampliﬁer. A natural next step to improve the current front-end is to extend its dynamic range to the entire possible input range. This will enable the SoC to record EEG signals during neurostimulation which opens up the opportunity of studying the effect of different electrical stimulation waveforms on brain activity, and results in development of optimal electrical stimulation schemes.

6.2.2 Future In-Vivo Experiments

Except for the system described in Chapter 2.b and Chapter 5.b, the rest of board- level and chip-level designs are tested in-vivo. An in-vivo validation experiment is a necessary next step for these systems. 213

Appendix A

Supplementary Hardware Documentation

Two 6-layer PCBs were designed and used to test the chips described in Chapter 3 and Chapter 4. They were designed using the Altium Designer 14.3 software. The manu- factured boards with components are shown in Figure A.1 and A.2. The PCBs could be reconﬁgured via FPGA code and jumpers for different SoC’s mode of operation.

A few of the key components on both PCBs are listed below:

• FPGA 544-2417-ND: Altera CYCLONE III FPGA 10K 256-FBGA. (Board 1)

• FPGA 544-2078-ND: Altera CYCLONE III FPGA 24k 324-FBGA. (Board 2)

• Voltage Regulator, 497-8717-1-ND: Regulator for on-chip 1.2V and 3.3V VDD supply.

• Oscillator Crystal, 40MHz, 3.3V XC1437CT-ND: Clock for FPGA.

• crystal, 14.3MHz, 1.8V, 478-4777-1-ND: Clock for the SoC.

• EEPROM 544-1379-5-ND: Required for FPGA programming. CHAPTER A. SUPPLEMENTARY HARDWARE DOCUMENTATION 214

28 cm

INPUT TO 21 of the 64 RECORDING CHANNELS CURRENT BIASING 17 cm

ALTERA FPGA VARIOUS VDDs FOR ANALOG AND DIGITAL RF BLOCKS 14.4 MHz XTAL 40 MHz XTAL NEUROSTIMULATOR SoC EXTERNAL PROM DIGITAL DEBUG PINS 5V POWER SUPPLY 1 FSK AND 2 UWB OUTPUTS ANALOG DEBUG PINS DC BIAS VOLTAGE

Figure A.1: The PCB designed for characterizing the SoC prototype described in chapter 3.

18 cm

40 MHz XTAL DIGITAL DEBUG PINS CURRENT BIASING ALTERA FPGA NEUROSTIMULATOR SoC 3 UWB OUTPUTS 10 cm INPUT TO 21 of the 64 RECORDING CHANNELS

EXTERNAL PROM

DC BIAS VOLTAGE SPECIAL ELECTRODE CONNECTORS 14.4 MHz XTAL VARIOUS VDDs FOR ANALOG AND DIGITAL AND RF BLOCKS 5V POWER SUPPLY

Figure A.2: The PCB designed for characterizing the SoC prototype described in chapter 4. CHAPTER A. SUPPLEMENTARY HARDWARE DOCUMENTATION 215

• Octal DAC AD5328BRUZ-ND: 8 output, 12-bit DAC for on-chip bias voltages.

• OTA1 296-24548-6-ND: Used for on-chip ADC reference.

• OTA2 LMV774MT-N: Used for voltage buffers. 216

Appendix B

Control Signals

Below is the list of signals that are sent and received between FPGA and the closed-loop neurostimulator IC: Control signals sent to the chip from the FPGA:

• Select CORDIC operation (3 bits)

• CORDIC clock

• CORDIC reset

• Off-chip clock for transmitter

• Select FIR or raw recording mode for channels

• Select digital output to be CORDIC output or raw recording output

• Select CORDIC inputs (3 bits)

• Select channel for outputs (6 bits).

• In-channel shift register clock CHAPTER B. CONTROL SIGNALS 217

• Global controller reset

• Off-chip data to wireless transmitters (for test)

• Transmitter to receive off-chip or onchip data

• Select off-chip or onchip clock for channels

• Channel selection for shift register programming (6 bits)

• Reset in-channel shift registers

• Serial data bits for the in-channel shift registers

• Select recording or stimulation mode for channels

• Reset for the in-channel decimating counters (2 bits)

• Reset for the delta-sigma modulator operation (1 bit)

• Off-chip clocks for the delta-sigma channel operation (8 clocks)

• Select for which counter output (In-phase or Quadrature) is sent for FIR ﬁltering

• Reference clock for the on-chip clock generator

• Clock for the ASK receiver

• Test data for the ASK receiver

Control signals received from the chip by the FPGA:

• Chip digital output (ADC output or cordic) (12 bits)

• Serial data that is sent to the transmitter

• Bit-stream output of delta sigma channel before decimation

• In-channel comparator outputs (2 bits) 218

Appendix C

Sample Verilog codes

C.1 Sample code for the HV stimulator IC

‘timescale 1ns / 1ps module main_code( input fpga_sys_clk,output reg s,output reg rn,output reg ana_mux1,output reg ana_mux2, output reg [3:0]fpga_ctrl_elec,output reg clk_dig,output reg swcap_clk,output reg clk, output reg clk_b, output reg [7:0]b0,output reg [7:0]b1,output reg [7:0]p2,output reg [7:0]p3);

// initialization block starts here

// for start and the reset signal always @(*) begin rn =1’b0; // the system is made to reset here, so that all the flip flops have 0. s =1’b1; // s is set to ensure that the start signal operates perfectly. rn =1’b1; // now the flip flops are ready to operate normally. end

parameter clkindex = 0;// set the value for which bit of count is required. reg [7:0]count =8’b00000000;

always @(posedge fpga_sys_clk)begin count = count+1; if((s == 1’b1)&(rn ==1’b1))begin clk_dig <= count[clkindex]; clk_b <= ˜(fpga_sys_clk); clk <= fpga_sys_clk ; swcap_clk <= count [4]; CHAPTER C. SAMPLE VERILOG CODES 219

end end

// selection of channels and analog multiplexers always@(*) begin if((s==1’b1)& (rn==1’b1)) begin ana_mux1 = 1’b1; // this selects the channel vcc from the charge pump(1) or externally(0) ana_mux2 = 1’b1; // this selects the adjustable voltage internally(1) or externally(0). fpga_ctrl_elec = 4’b1111;// this selects the channel that is needs to be operated(1111 selects all and 0000 selects none). end end // initialization block ends here.

endmodule module stimulation_test( input clk,output reg [7:0]b0,output reg [7:0]b1,output reg [7:0]p2,output reg [7:0]p3, output reg [3:0]u_d);

integer index=0; integer loop_var=0; parameter freq_ctrl = 100 ; parameter cnt_dtpnts = 16 ; //reg [0:0]flag= 1’b1; // initialize the look up table reg [7:0]look_up_ch1[0:(cnt_dtpnts-1)]; reg [7:0]look_up_ch2[0:(cnt_dtpnts-1)]; reg [7:0]look_up_ch3[0:(cnt_dtpnts-1)]; reg [7:0]look_up_ch4[0:(cnt_dtpnts-1)]; initial begin $readmemh("stim_data_ch1.txt",look_up_ch1); $readmemh("stim_data_ch2.txt",look_up_ch2); $readmemh("stim_data_ch3.txt",look_up_ch3); $readmemh("stim_data_ch4.txt",look_up_ch4); end

/* The parameter freq_ctrl is designed to make the value of index to be stationary for a certain amount of time. So, the basic idea is to wait at a constant value of index for some timebefore moving on to the next one. More the waiting time, lesser the frequency.

*/ always@(posedge clk)begin b0<=look_up_ch1[index]; b1<=look_up_ch2[index]; p2<=look_up_ch3[index]; CHAPTER C. SAMPLE VERILOG CODES 220

p3<=look_up_ch4[index]; loop_var = loop_var + 1;

if(loop_var > freq_ctrl ) begin loop_var = 0; if(index < (cnt_dtpnts-1))begin index = index+1; end else begin index = 0; u_d[0]= ˜u_d[0]; u_d[1]= ˜u_d[1]; u_d[2]= ˜u_d[2]; u_d[3]= ˜u_d[3]; end

end end endmodule

C.2 Sample code for the closed-loop neurostimulator IC

module control_pins ( clkIn, CLK_SR_PAVCO, CLK_SR_transmitter, cap_res0_ON_filter, res1_filter, res2_filter, res3_filter, column0ctl, column1ctl, CLK_FSM3_se, CLK_FSM4_se, FSM_data_se, enable_analog_MUX_channels, GAIN_boost_SE, data_signFIR_SE, CLK_SR_sign3, CLKscX16, CLK_sc, enable_2nd_stage, offset_on1_off0, RST_ADC_LOGIC, CLK_FSM1_diff, CHAPTER C. SAMPLE VERILOG CODES 221

CLK_FSM2_diff, ADC_CLK_onchip1_offchip0, on_chip_transmitter_data1_offchip0, on_chip1_offchip0, bit7_0_bit6_1_outputreg, forward_reverse_count, FIR0_DIG1, REFCLK1_offchipCLK0, CLK_FIR0_reg_offchip, CLK_FIR0_offchip, offchip_data_to_transmitter, outputreg_adc_offchip, trig_adc_offchip_CLK, off_chip_CLK_to_controller, reset_controller, CLK_SR_sign0, mux_onchip1_offchip0, mux0offchip, mux1offchip, mux2offchip, mux3offchipadd0, mux4offchipadd1, mux5offchipadd2, DATA_IN_SR_TRANS, RST_transmitter_SR, column1_adctest0, RST_cordic_chip2, CLK_cordic_chip2, FSM_ctl0_diff, FSM_ctl1_diff, FSM_ctl2_diff, RST_FSM_SR, FSM_data_in_diff, CLK_FSM3_diff, CLK_FSM4_diff, reset_STIM_SR, DATA_IN_STIM_sign_diff, CLK_SR_sign1, CLK_SR_stim, SC_output_filter_on1_off0, SC_OFF1_ON0, channel1_column0, cordic1_digital_out0, offchip_CLK_to_trans, threshold_SR_CLK_chip2, threshold_SR_rst_chip2, threshold_SR_datain_chip2, enabled_2nd_stage_HP_TC_chip2, CLK_SR_sign2, switch_FE_on1_off0_chip2, select_filter0_chip1_select_cordic_in1_chip2, select_filter1_chip1_select_cordic_in0_chip2, cordic_op2_chip2, neg_flag_cos_chip2, CHAPTER C. SAMPLE VERILOG CODES 222

neg_flag_sin_chip2, FSM_ctl2_se, FSM_ctl1_se, FSM_ctl0_se, CLK_FSM1_se, CLK_FSM2_se_chip12, ASK1_FSM0, serial_out, out9ii_chip1, out7ii_chip1, out6ii_chip1_cordicop1_chip2, out5ii_chip1_cordicop0_chip2, out4ii_chip1_out0_chip2, out3ii_chip1_out1_chip2, out2ii_chip1_out2_chip2, out1ii_chip1_out3_chip2, out0ii_chip1_select_cordic_in2_chip2, out9_chip1, out7_chip1, out6_chip1, out5_chip1, out4_chip1, out3_chip1, out2_chip1, out1_chip1, out0_chip1, out4_chip2, out5_chip2, out6_chip2, out7_chip2, out8_chip2, out9_chip2, mux_counter1, mux_counter0, turnOnStimulation ); input clkIn; output CLK_SR_PAVCO; output CLK_SR_transmitter; output cap_res0_ON_filter; output res1_filter; output res2_filter; output res3_filter; output column0ctl; output column1ctl; output CLK_FSM3_se; output CLK_FSM4_se; output FSM_data_se; output enable_analog_MUX_channels; output GAIN_boost_SE; output data_signFIR_SE; output CLK_SR_sign3; output CLKscX16; CHAPTER C. SAMPLE VERILOG CODES 223

output CLK_sc; output enable_2nd_stage; output offset_on1_off0; output RST_ADC_LOGIC; output CLK_FSM1_diff; output CLK_FSM2_diff; output ADC_CLK_onchip1_offchip0; output on_chip_transmitter_data1_offchip0; output on_chip1_offchip0; output bit7_0_bit6_1_outputreg; output forward_reverse_count; output FIR0_DIG1; output REFCLK1_offchipCLK0; output CLK_FIR0_reg_offchip; output CLK_FIR0_offchip; output offchip_data_to_transmitter; output outputreg_adc_offchip; output trig_adc_offchip_CLK; output off_chip_CLK_to_controller; output reset_controller; output CLK_SR_sign0; output mux_onchip1_offchip0; output mux0offchip; output mux1offchip; output mux2offchip; output mux3offchipadd0; output mux4offchipadd1; output mux5offchipadd2; output DATA_IN_SR_TRANS; output RST_transmitter_SR; output column1_adctest0; output RST_cordic_chip2; output CLK_cordic_chip2; output FSM_ctl0_diff; output FSM_ctl1_diff; output FSM_ctl2_diff; output RST_FSM_SR; output FSM_data_in_diff; output CLK_FSM3_diff; output CLK_FSM4_diff; output reset_STIM_SR; output DATA_IN_STIM_sign_diff; output CLK_SR_sign1; output CLK_SR_stim; output SC_output_filter_on1_off0; output SC_OFF1_ON0; output channel1_column0; output cordic1_digital_out0; output offchip_CLK_to_trans; output threshold_SR_CLK_chip2; output threshold_SR_rst_chip2; output threshold_SR_datain_chip2; output enabled_2nd_stage_HP_TC_chip2; output CLK_SR_sign2; CHAPTER C. SAMPLE VERILOG CODES 224

output switch_FE_on1_off0_chip2; output select_filter0_chip1_select_cordic_in1_chip2; output select_filter1_chip1_select_cordic_in0_chip2; output cordic_op2_chip2; input neg_flag_cos_chip2; input neg_flag_sin_chip2; output FSM_ctl2_se; output FSM_ctl1_se; output FSM_ctl0_se; output CLK_FSM1_se; output CLK_FSM2_se_chip12; output ASK1_FSM0; output out6ii_chip1_cordicop1_chip2; output out5ii_chip1_cordicop0_chip2; output mux_counter1; output mux_counter0; input serial_out; input out9ii_chip1; input out7ii_chip1; // input out6ii_chip1_cordicop1_chip2; // input out5ii_chip1_cordicop0_chip2; input out4ii_chip1_out0_chip2; input out3ii_chip1_out1_chip2; input out2ii_chip1_out2_chip2; input out1ii_chip1_out3_chip2; input out0ii_chip1_select_cordic_in2_chip2; input out9_chip1; input out7_chip1; input out6_chip1; input out5_chip1; input out4_chip1; input out3_chip1; input out2_chip1; input out1_chip1; input out0_chip1; input out4_chip2; input out5_chip2; input out6_chip2; input out7_chip2; input out8_chip2; input out9_chip2; output turnOnStimulation;

// BEGIN TESTING˜

// Registers reg [30:0] timer = 0; reg [30:0] set_timer = 100000000; // Length of stimulation reg turnOnStimulation = 0; reg reset = 1; reg coolDown = 1; wire [9:0] PLV; CHAPTER C. SAMPLE VERILOG CODES 225

wire [9:0] bottomThreshold; assign PLV = {out9_chip2, out8_chip2, out7_chip2, out6_chip2, out5_chip2, out4_chip2, out1ii_chip1_out3_chip2, out2ii_chip1_out2_chip2, out3ii_chip1_out1_chip2, out4ii_chip1_out0_chip2,}; //assign PLV = {out4ii_chip1_out0_chip2, out3ii_chip1_out1_chip2, out2ii_chip1_out2_chip2, out1ii_chip1_out3_chip2, out4_chip2, out5_chip2, out6_chip2, out7_chip2, out8_chip2, out9_chip2}; assign bottomThreshold = 10’b0011001000; reg debugPin; reg [30:0] tester; reg result = 0; reg startUp = 1; always @(posedge clkIn) begin

//debugPin = ((out4ii_chip1_out0_chip2 == 0) && (out3ii_chip1_out1_chip2 == 0) && (out2ii_chip1_out2_chip2 == 0) && (out1ii_chip1_out3_chip2 == 0) && (out4_chip2 == 0) && (out5_chip2 == 0) && (out6_chip2 == 0) && (out7_chip2 == 0) && (out8_chip2 == 0) && (out9_chip2 == 0) && (˜turnOnStimulation));

// if(˜(õut9_chip2 && õut8_chip2 && õut7_chip2 && õut6_chip2 && õut5_chip2 && õut4_chip2 && ˜ out1ii_chip1_out3_chip2 && õut2ii_chip1_out2_chip2 && õut3ii_chip1_out1_chip2 && õut4ii_chip1_out0_chip2) && (PLV < bottomThreshold) || (reset)) begin // if (˜coolDown) begin // Turn on stimulation for given duration // if(˜turnOnStimulation) begin // reset <= 1; // turnOnStimulation<= 1; // end else if(timer >= 100000000) begin // timer <= 0; // coolDown <= 1; // end else begin // timer <= timer + 1; // end // end else if (coolDown) begin // Let PLV settle for given duration // if(turnOnStimulation) begin // turnOnStimulation <= 0; // end else if(timer >= 700000000) begin // timer <= 0; // reset <= 0; // coolDown = 0; // end else begin // timer <= timer + 1; // end // end // end end

// END TESTING˜ CHAPTER C. SAMPLE VERILOG CODES 226

// *** BEGIN SETUP ***

//Transmitter/wireless assign CLK_SR_PAVCO=clkout1; assign CLK_SR_transmitter=clkout2; assign DATA_IN_SR_TRANS=dataout; assign ASK1_FSM0=1’b1; //set FSK to 0, ASK to 1 assign on_chip_transmitter_data1_offchip0=1’b0; //offchip transmitter data //assign offchip_data_to_transmitter=dither; //ASK/OOK assign offchip_data_to_transmitter=1’b1; assign RST_transmitter_SR=1’b0; //set to 0 to allow RF shiftreg assign offchip_CLK_to_trans=1’b0;

//switch capacitor filters assign cap_res0_ON_filter=1’b1; assign res1_filter=1’b1; assign res2_filter=1’b1; assign res3_filter=1’b1; assign SC_output_filter_on1_off0=1’b1; reg SC_OFF1_ON0; reg CLKscX16; reg CLK_sc; always@(turnOnStimulation or count_STIM[12] or count_SC[13-3] or count_SC[13+1]) begin if(˜turnOnStimulation) begin SC_OFF1_ON0<=1’b0; //turn switch cap on CLKscX16<=count_SC[13-3]; //assign CLK_sc=count_SC[13+2]; //count[15] for alpha, count[13] for gamma CLK_sc<=count_SC[13+1]; end else begin SC_OFF1_ON0<=1’b1; //turn switch cap on CLKscX16<=count_STIM[12]; //assign CLK_sc=count_SC[13+2]; //count[15] for alpha, count[13] for gamma CLK_sc<=1’b1; end end

//adjust if we want bivariate or univariate for FIR filters assign column0ctl=1’b1; assign column1ctl=1’b1;

//analog tuning assign enable_analog_MUX_channels=1’b1; assign GAIN_boost_SE=1’b1; assign enable_2nd_stage=1’b1; assign offset_on1_off0=1’b1;

//program all internal shift registers reg CLK_FSM1_diff; reg CLK_FSM2_diff; reg CLK_FSM3_diff; reg CLK_FSM4_diff; reg CLK_FSM1_se; CHAPTER C. SAMPLE VERILOG CODES 227

reg CLK_FSM2_se_chip12; reg CLK_FSM3_se; reg CLK_FSM4_se; always@(turnOnStimulation or clkoutFIR1 or clkoutFIR2) begin if(˜turnOnStimulation) begin CLK_FSM1_diff<=clkoutFIR2; CLK_FSM2_diff<=clkoutFIR1; CLK_FSM3_diff<=clkoutFIR2; CLK_FSM4_diff<=clkoutFIR1; CLK_FSM1_se<=clkoutFIR1; CLK_FSM2_se_chip12<=clkoutFIR2; CLK_FSM3_se<=clkoutFIR1; CLK_FSM4_se<=clkoutFIR2; end else begin CLK_FSM1_diff<=clkoutFIR1; CLK_FSM2_diff<=clkoutFIR1; CLK_FSM3_diff<=clkoutFIR1; CLK_FSM4_diff<=clkoutFIR1; CLK_FSM1_se<=clkoutFIR1; CLK_FSM2_se_chip12<=clkoutFIR1; CLK_FSM3_se<=clkoutFIR1; CLK_FSM4_se<=clkoutFIR1; end end reg CLK_SR_sign3; reg CLK_SR_sign2; reg CLK_SR_sign1; reg CLK_SR_sign0; always@(turnOnStimulation or clkout_sign1 or clkout_sign2)begin if(˜turnOnStimulation) begin CLK_SR_sign3<=clkout_sign1; CLK_SR_sign2<=clkout_sign2; CLK_SR_sign1<=clkout_sign2; CLK_SR_sign0<=clkout_sign1; end else begin CLK_SR_sign3<=clkout_sign1; CLK_SR_sign2<=clkout_sign1; CLK_SR_sign1<=clkout_sign1; CLK_SR_sign0<=clkout_sign1; end end assign FSM_data_in_diff=dataoutFIR; assign FSM_data_se=dataoutFIR; assign DATA_IN_STIM_sign_diff=dataout_sign1; assign data_signFIR_SE=dataout_sign1; reg FSM_ctl2_se; reg FSM_ctl1_se; reg FSM_ctl0_se; reg FSM_ctl0_diff; CHAPTER C. SAMPLE VERILOG CODES 228

reg FSM_ctl1_diff; reg FSM_ctl2_diff; always@(turnOnStimulation or add2 or add1 or add0 or add2_STIM or add1_STIM or add0_STIM)begin if(˜turnOnStimulation) begin FSM_ctl2_se<=add2; FSM_ctl1_se<=add1; FSM_ctl0_se<=add0; FSM_ctl0_diff<=add0; FSM_ctl1_diff<=add1; FSM_ctl2_diff<=add2; end else begin FSM_ctl2_se<=add2_STIM; FSM_ctl1_se<=add1_STIM; FSM_ctl0_se<=add0_STIM; FSM_ctl0_diff<=add0_STIM; FSM_ctl1_diff<=add1_STIM; FSM_ctl2_diff<=add2_STIM; end end assign RST_FSM_SR=1’b0; //turn off all shift registers (set to 1) reg reset_STIM_SR; reg CLK_SR_stim; always@(turnOnStimulation or clkout_stim)begin if(˜turnOnStimulation) begin reset_STIM_SR<=1’b1; CLK_SR_stim<=1’b0; end else begin reset_STIM_SR<=1’b0; CLK_SR_stim<=clkout_stim; end end

//CLKs and controls assign RST_ADC_LOGIC=1’b1; assign ADC_CLK_onchip1_offchip0=1’b1; assign on_chip1_offchip0=1’b0; assign REFCLK1_offchipCLK0=1’b0;

//assign off_chip_CLK_to_controller=count2[6+3]; //sample rate=40MHz/(2ˆ(count2[x+1]*11*8)) //assign off_chip_CLK_to_controller=count_SC[6+3+2]; //count[11] for alpha, count[9] for gamma reg off_chip_CLK_to_controller; always@(turnOnStimulation or count_SC[6+3+1] or count3[18])begin if(˜turnOnStimulation)begin off_chip_CLK_to_controller<=count_SC[6+3+1]; end else begin off_chip_CLK_to_controller<=count3[18]; end end CHAPTER C. SAMPLE VERILOG CODES 229

assign reset_controller=1’b1;

//debug assign bit7_0_bit6_1_outputreg=1’b0; assign forward_reverse_count=1’b0; reg CLK_FIR0_reg_offchip; always@(turnOnStimulation)begin if(˜turnOnStimulation) begin CLK_FIR0_reg_offchip<=1’b0; end else begin CLK_FIR0_reg_offchip<=1’b1; end end assign CLK_FIR0_offchip=1’b0; assign outputreg_adc_offchip=1’b0; assign trig_adc_offchip_CLK=1’b0;

//For ADC testing, channel testing or FIR filtering mode assign column1_adctest0=1’b1; // set to 0 for adctest input. reg channel1_column0; // set to 1 for amplifier-channel input, 0 for FIR/ADC test input always@(turnOnStimulation)begin if(˜turnOnStimulation)begin channel1_column0<=1’b0; // set to 1 for amplifier-channel input, 0 for FIR/ADC test input end else begin channel1_column0<=1’b1; // set to 1 for amplifier-channel input, 0 for FIR/ADC test input end end

//2nd chip extras assign threshold_SR_CLK_chip2=1’b0; assign threshold_SR_rst_chip2=1’b0; assign threshold_SR_datain_chip2=1’b0; assign enabled_2nd_stage_HP_TC_chip2=1’b1; assign switch_FE_on1_off0_chip2=1’b0;

//DSP assign select_filter0_chip1_select_cordic_in1_chip2=1’b0; assign select_filter1_chip1_select_cordic_in0_chip2=1’b0; assign mux_onchip1_offchip0=1’b0; assign FIR0_DIG1=1’b0; reg mux0offchip; reg mux1offchip; reg mux2offchip; reg mux3offchipadd0; reg mux4offchipadd1; //diff=1, SE=0; reg mux5offchipadd2; //hilbert=1, allpass=0 always@(turnOnStimulation or channel_mux[1])begin CHAPTER C. SAMPLE VERILOG CODES 230

if(˜turnOnStimulation) begin mux0offchip<=1’b1; mux1offchip<=1’b1; mux2offchip<=1’b1; mux3offchipadd0<=1’b0; mux4offchipadd1<=1’b0; //diff=1, SE=0; mux5offchipadd2<=1’b0; //hilbert=1, allpass=0 end else begin mux0offchip<=1’b0; mux1offchip<=1’b0; mux2offchip<=1; mux3offchipadd0<=˜channel_mux[1]; //SE_chan8: 010100,DIFF_chan4: 001100 mux4offchipadd1<=channel_mux[1]; //diff=1, SE=0;0; mux5offchipadd2<=1’b0; //hilbert=1, allpass=0 end end

//*********************************** Parameter Declaratoins for states********************************** // sin=0, cos=1, angle1=2, angle2=3, magn1=4, magn2=5, phase_diff=6, synch=7; //names of states for FSM

//***********************************Flip Flop assign RST_cordic_chip2=1’b1; reg cordic1_digital_out0; reg CLK_cordic_chip2; reg cordic_op2_chip2; reg out6ii_chip1_cordicop1_chip2; reg out5ii_chip1_cordicop0_chip2; reg mux_counter1; reg mux_counter0; always@(turnOnStimulation or count_SC[9+2+1] or count_mux[1] or count_mux[0] or channel_mux[1])begin if(˜turnOnStimulation)begin cordic1_digital_out0<=1’b1; CLK_cordic_chip2<=count_SC[9+2+1]; cordic_op2_chip2<=1’b1; out6ii_chip1_cordicop1_chip2<=1’b1; out5ii_chip1_cordicop0_chip2<=1’b1; mux_counter1<=count_mux[1]; mux_counter0<=count_mux[0]; end else begin cordic1_digital_out0<=1’b0; CLK_cordic_chip2<=1’b1; cordic_op2_chip2<=1’b1; out6ii_chip1_cordicop1_chip2<=1’b1; out5ii_chip1_cordicop0_chip2<=1’b1; mux_counter1<=channel_mux[1]; mux_counter0<=channel_mux[1]; end end

// ** END SETUP *** CHAPTER C. SAMPLE VERILOG CODES 231

reg dither; reg [19:0] LFSRout; reg linear_feedback; always@(turnOnStimulation or LFSRout[19] or LFSRout[16]) begin if(turnOnStimulation) begin linear_feedback <= !(LFSRout[19] ˆ LFSRout[16]); // 20 and 17 end end reg [3:0]channel_mux; reg [3:0]new_channel_mux; always @(posedge count_STIM[11]) channel_mux<=new_channel_mux; always @(channel_mux or turnOnStimulation) begin if(turnOnStimulation) begin if(channel_mux==15) new_channel_mux=0; else new_channel_mux=channel_mux+1; end end

always @(posedge count_STIM[4])begin if(turnOnStimulation) begin if (˜rst_reg_STIM) begin dither <= 1’b0 ; LFSRout <= 20’h0_0000; end else begin LFSRout[19:1] <= LFSRout[18:0] ; LFSRout[0] <= linear_feedback; dither <= LFSRout[19]; end end end reg [12:0]count; reg [12:0]new_count; reg [12:0]count_STIM; reg [12:0]new_count_STIM; reg [9:0]count2; reg [9:0]new_count2; reg [18:0]count3; reg [18:0]new_count3; reg [6:0]adc_clk_div; reg [6:0]new_adc_clk_div; reg [6:0]count_shift; CHAPTER C. SAMPLE VERILOG CODES 232

reg [6:0]new_count_shift; reg [17:0]count_SC; reg [17:0]new_count_SC; reg [17:0]count_SC_int; reg [17:0]new_count_SC_int; reg [1:0]count_mux; reg [1:0]new_count_mux; always @(posedge clkIn) count2<=new_count2; always @(posedge clkIn) count<=new_count; always @(posedge clkIn) count_STIM<=new_count_STIM; always @(posedge clkIn) count3<=new_count3; always @(posedge clkIn) adc_clk_div<=new_adc_clk_div; always @(posedge clkIn) count_shift<=new_count_shift; always @(posedge clkIn) count_SC<=new_count_SC; always @(posedge count_SC_int[15+1]) count_mux<=new_count_mux; always @(posedge clkIn) count_SC_int<=new_count_SC_int; always @(count_mux or turnOnStimulation) begin if(˜turnOnStimulation) begin if(count_mux==3) new_count_mux=0; else new_count_mux=count_mux+1; end end always @(count or turnOnStimulation) begin if(˜turnOnStimulation) begin if(count==8191) new_count=0; else new_count=count+1; end end always @(count_STIM or turnOnStimulation) begin CHAPTER C. SAMPLE VERILOG CODES 233

if(turnOnStimulation) begin if(count_STIM==8191) new_count_STIM=0; else new_count_STIM=count_STIM+1; end end always @(count2 or turnOnStimulation) begin if(turnOnStimulation) begin if(count2==1023) new_count2=0; else new_count2=count2+1; end end always @(count3 or turnOnStimulation) begin if(turnOnStimulation) begin if(count3==524287) new_count3=0; else new_count3=count3+1; end end always @(adc_clk_div or turnOnStimulation) begin if(turnOnStimulation) begin if(adc_clk_div==127) new_adc_clk_div=0; else new_adc_clk_div=adc_clk_div+1; end end always @(count_shift or turnOnStimulation) begin if(˜turnOnStimulation) begin if(count_shift==127) new_count_shift=0; else new_count_shift=count_shift+1; end end always @(count_SC or turnOnStimulation) begin if(˜turnOnStimulation) begin if(count_SC==262143) new_count_SC=0; else new_count_SC=count_SC+1; end end always @(count_SC_int or turnOnStimulation) begin if(˜turnOnStimulation) begin if(count_SC_int==262143) new_count_SC_int=0; else new_count_SC_int=count_SC_int+1; end end CHAPTER C. SAMPLE VERILOG CODES 234

// RF ****************************shiftreg******************************************************** reg dataout; reg [39:0]dataoutreg; reg clkout1; reg clkout2; reg [6:0]count_RF_SR; reg [6:0]new_count_RF_SR; reg [6:0]count_RF_SR_STIM; reg [6:0]new_count_RF_SR_STIM; reg [3:0]count2_RF_SR; reg [3:0]new_count2_RF_SR; reg [3:0]count2_RF_SR_STIM; reg [3:0]new_count2_RF_SR_STIM; reg rst_reg; reg new_rst_reg; reg rst_reg_STIM; reg new_rst_reg_STIM; always @(posedge clkIn or negedge rst_reg) begin if (˜rst_reg) count_RF_SR<=0; else count_RF_SR<=new_count_RF_SR; end always @(posedge clkIn or negedge rst_reg_STIM) begin if (˜rst_reg_STIM) begin count_RF_SR_STIM<=0; end else begin count_RF_SR_STIM<=new_count_RF_SR_STIM; end end always @(posedge clkIn) begin count2_RF_SR_STIM<=new_count2_RF_SR_STIM; end always @(count_RF_SR_STIM or turnOnStimulation) begin if(turnOnStimulation) begin if(count_RF_SR_STIM==40) new_count_RF_SR_STIM=40; else new_count_RF_SR_STIM=count_RF_SR_STIM+1; end end always @(count2_RF_SR_STIM or turnOnStimulation) begin CHAPTER C. SAMPLE VERILOG CODES 235

if(turnOnStimulation) begin if(count2_RF_SR_STIM==15) new_count2_RF_SR_STIM=15; else new_count2_RF_SR_STIM=count2_RF_SR_STIM+1; if(count2_RF_SR_STIM==14) rst_reg_STIM=0; else rst_reg_STIM=1; end else rst_reg_STIM = 0; end

always @(posedge count_SC_int[17])begin count2_RF_SR<=new_count2_RF_SR; end

always @(count_RF_SR or turnOnStimulation) begin if(˜turnOnStimulation) begin if(count_RF_SR==40) new_count_RF_SR=40; else new_count_RF_SR=count_RF_SR+1; end end always @(count2_RF_SR or turnOnStimulation) begin if(˜turnOnStimulation) begin if(count2_RF_SR==15) new_count2_RF_SR=15; else new_count2_RF_SR=count2_RF_SR+1; if(count2_RF_SR==0) rst_reg=1; else if (count2_RF_SR==1) rst_reg=1; else if (count2_RF_SR==2) rst_reg=1; else if (count2_RF_SR==3) rst_reg=1; else if (count2_RF_SR==4) rst_reg=1; else if (count2_RF_SR==5) rst_reg=0; else if (count2_RF_SR==6) rst_reg=0; else if (count2_RF_SR==7) rst_reg=0; else if (count2_RF_SR==8) rst_reg=0; else if (count2_RF_SR==9) rst_reg=0; else if (count2_RF_SR==10) rst_reg=0; else if (count2_RF_SR==11) rst_reg=0; CHAPTER C. SAMPLE VERILOG CODES 236

else if (count2_RF_SR==12) rst_reg=0; else if (count2_RF_SR==13) rst_reg=1; else if (count2_RF_SR==14) rst_reg=1; else rst_reg=1; end else rst_reg=0; end always@(turnOnStimulation or count_RF_SR or count_RF_SR_STIM) begin if(˜turnOnStimulation) begin dataout<=dataoutreg[count_RF_SR]; dataoutreg<=40’b11_00_00_11_00_11__11_11_00__11_11_00__11_11_11_11__11_11_11_00_;

// cap0_cap1_cap2_res0_res1_res2__FSK0_FSK1_FSK2__CP_Manchest_OOK__PA0_PA1_PA2_PA3_vcotune3_vcotune2_vcotune1_vcotune0

clkout1=count_RF_SR[0]&(count_RF_SR<16); clkout2=count_RF_SR[0]&(count_RF_SR>15); end else begin dataout<=dataoutreg[count_RF_SR_STIM]; dataoutreg<=40’b11_00_00_11_00_11__11_11_00__11_11_00__11_11_11_11__11_11_11_00_;

// cap0_cap1_cap2_res0_res1_res2__FSK0_FSK1_FSK2__CP_Manchest_OOK__PA0_PA1_PA2_PA3_vcotune3_vcotune2_vcotune1_vcotune0

clkout1<=count_RF_SR_STIM[0]&(count_RF_SR_STIM<16); clkout2<=count_RF_SR_STIM[0]&(count_RF_SR_STIM>15); end end

//**************************** done RF shiftreg********************************************************

//**************************** FIR SHIFT REG******************************************************** reg dataoutFIR; reg [287:0]dataoutregFIR; reg [287:0]dataoutregFIR2; reg clkoutFIR1; reg clkoutFIR2; reg add0; reg add1; reg add2; reg add0_STIM; reg add1_STIM; reg add2_STIM; reg [9:0]count_FIR_SR; reg [9:0]count_FIR_SR2; CHAPTER C. SAMPLE VERILOG CODES 237

reg [9:0]count_FIR_SR3; reg [9:0]count_FIR_SR_STIM; reg [9:0]new_count_FIR_SR; reg [9:0]new_count_FIR_SR2; reg [9:0]new_count_FIR_SR3; reg [9:0]new_count_FIR_SR_STIM; reg shift_reg_flag; reg new_shift_reg_flag;

//*************** START FIR 1 always @(posedge clkIn or negedge rst_reg_STIM) begin if (˜rst_reg_STIM) count_FIR_SR_STIM<=0; else count_FIR_SR_STIM<=new_count_FIR_SR_STIM; end always @(posedge count_shift[6] or negedge rst_reg) begin if (˜rst_reg) begin count_FIR_SR<=0; count_FIR_SR3<=0; shift_reg_flag<=0; end else begin count_FIR_SR<=new_count_FIR_SR; count_FIR_SR3<=new_count_FIR_SR3; shift_reg_flag<=new_shift_reg_flag; end end always @(count_FIR_SR_STIM or turnOnStimulation) begin if(turnOnStimulation) begin if(count_FIR_SR_STIM==287) new_count_FIR_SR_STIM=287; else new_count_FIR_SR_STIM=count_FIR_SR_STIM+1; end end always @(count_FIR_SR or turnOnStimulation) begin if(˜turnOnStimulation) begin if(count_FIR_SR==287) begin new_count_FIR_SR=287; end else begin new_count_FIR_SR=count_FIR_SR+1; end end end always @(count_FIR_SR3 or turnOnStimulation) begin if(˜turnOnStimulation) begin if(count_FIR_SR3==287) CHAPTER C. SAMPLE VERILOG CODES 238

begin new_shift_reg_flag=1; new_count_FIR_SR3=287; end else begin new_count_FIR_SR3=count_FIR_SR3+1; new_shift_reg_flag=0; end end end

//*************** END FIR 1 //*************** START FIR 2 always @(posedge count_shift[6] or negedge rst_reg) begin if (˜rst_reg) count_FIR_SR2<=0; else count_FIR_SR2<=new_count_FIR_SR2; end always @(count_FIR_SR2 or count_FIR_SR or turnOnStimulation) begin if(˜turnOnStimulation) begin if (count_FIR_SR2==287) new_count_FIR_SR2=287; else if(count_FIR_SR==287) new_count_FIR_SR2=count_FIR_SR2+1; else new_count_FIR_SR2=0; end end

//*************** END FIR 2 //*************** START FIR 1 DATA always @(count_FIR_SR or count_FIR_SR2 or shift_reg_flag or turnOnStimulation) begin if(˜turnOnStimulation) begin if (shift_reg_flag==0) begin if ((count_FIR_SR<36)) begin add0<=0; add1<=0; add2<=0; end else if ((count_FIR_SR<72)&(count_FIR_SR>35)) begin add0<=1; add1<=0; add2<=0; end else if ((count_FIR_SR<108)&(count_FIR_SR>71)) begin add0<=0; add1<=1; add2<=0; end else if ((count_FIR_SR<144)&(count_FIR_SR>107)) CHAPTER C. SAMPLE VERILOG CODES 239

begin add0<=1; add1<=1; add2<=0; end else if ((count_FIR_SR<180)&(count_FIR_SR>143)) begin add0<=0; add1<=0; add2<=1; end else if ((count_FIR_SR<216)&(count_FIR_SR>179)) begin add0<=1; add1<=0; add2<=1; end else if ((count_FIR_SR<252)&(count_FIR_SR>215)) begin add0<=0; add1<=1; add2<=1; end else if (count_FIR_SR>250) begin add0<=1; add1<=1; add2<=1; end else begin add0<=0; add1<=0; add2<=0; end end

else if (shift_reg_flag==1) begin if ((count_FIR_SR2<36)|(count_FIR_SR2<36)) begin add0<=0; add1<=0; add2<=0; end else if ((count_FIR_SR2<72)&(count_FIR_SR2>35)) begin add0<=1; add1<=0; add2<=0; end else if ((count_FIR_SR2<108)&(count_FIR_SR2>71)) CHAPTER C. SAMPLE VERILOG CODES 240

begin add0<=0; add1<=1; add2<=0; end else if ((count_FIR_SR2<144)&(count_FIR_SR2>107)) begin add0<=1; add1<=1; add2<=0; end else if ((count_FIR_SR2<180)&(count_FIR_SR2>143)) begin add0<=0; add1<=0; add2<=1; end else if ((count_FIR_SR2<216)&(count_FIR_SR2>179)) begin add0<=1; add1<=0; add2<=1; end else if ((count_FIR_SR2<252)&(count_FIR_SR2>215)) begin add0<=0; add1<=1; add2<=1; end else if (count_FIR_SR2>250) begin add0<=1; add1<=1; add2<=1; end else begin add0<=0; add1<=0; add2<=0; end end end end always @(count_FIR_SR_STIM or turnOnStimulation) begin if(turnOnStimulation) begin if (count_FIR_SR_STIM<36) begin add0_STIM<=0; add1_STIM<=0; add2_STIM<=0; CHAPTER C. SAMPLE VERILOG CODES 241

end else if ((count_FIR_SR_STIM<72)&(count_FIR_SR_STIM>35)) begin add0_STIM<=1; add1_STIM<=0; add2_STIM<=0; end else if ((count_FIR_SR_STIM<108)&(count_FIR_SR_STIM>71)) begin add0_STIM<=0; add1_STIM<=1; add2_STIM<=0; end else if ((count_FIR_SR_STIM<144)&(count_FIR_SR_STIM>107)) begin add0_STIM<=1; add1_STIM<=1; add2_STIM<=0; end else if ((count_FIR_SR_STIM<180)&(count_FIR_SR_STIM>143)) begin add0_STIM<=0; add1_STIM<=0; add2_STIM<=1; end else if ((count_FIR_SR_STIM<216)&(count_FIR_SR_STIM>179)) begin add0_STIM<=1; add1_STIM<=0; add2_STIM<=1; end else if ((count_FIR_SR_STIM<252)&(count_FIR_SR_STIM>215)) begin add0_STIM<=0; add1_STIM<=1; add2_STIM<=1; end else if (count_FIR_SR_STIM>250) begin add0_STIM<=1; add1_STIM<=1; add2_STIM<=1; end else begin add0_STIM<=0; add1_STIM<=0; add2_STIM<=0; end end end always@(turnOnStimulation or count_FIR_SR or shift_reg_flag or count_FIR_SR2 or count_FIR_SR_STIM) begin CHAPTER C. SAMPLE VERILOG CODES 242

if(˜turnOnStimulation) begin clkoutFIR1<=count_FIR_SR[0]; clkoutFIR2<=count_FIR_SR2[0]; dataoutFIR<=(dataoutregFIR[count_FIR_SR]&(˜shift_reg_flag)) | (dataoutregFIR2[count_FIR_SR2]&(shift_reg_flag)); dataoutregFIR<=288’ b00_11_00_00_00_11_11_00__11_00__00_00_00_00_11_11_11_11____11_00_00_00_00_11_00_00__11_00__00_00_00_00_11_11_11_11____00_00_11_00_ ; dataoutregFIR2<=288’ b00_11_00_00_00_11_00_00__00_00__00_00_00_00_11_11_11_11____11_00_11_11_11_00_00_00__00_00__00_00_00_00_11_11_11_11____11_11_00_00_ ; end else begin clkoutFIR1<=count_FIR_SR_STIM[0]; dataoutFIR<=dataoutregFIR[count_FIR_SR_STIM]; //dataoutregFIR=288’ b11_00_00_11_11_11_00_00__00_00__xx_xx_xx_xx_xx_xx_xx_xx____11_11_00_00_00_11_00_00__00_00__xx_xx_xx_xx_xx_xx_xx_xx____00_00_11_00_ ; // assign dataoutregFIR=288’ b11_00_00_11_11_11_00_00__00_00__00_00_11_11_11_11_11_11____11_11_00_00_00_11_00_00__00_00__00_00_00_00_00_11_11_11____00_00_11_00_ ;

//dataoutregFIR<=288’ b11_00_00_11_11_11_00_00__00_00__XX_XX_XX_XX_XX_XX_XX_XX____11_11_00_00_00_11_00_00__00_00__XX_XX_XX_XX_XX_XX_XX_XX____00_00_11_00_ ; dataoutregFIR<=288’ b11_00_00_11_11_11_00_00__00_00__00_00_00_00_00_00_00_11____11_11_00_00_00_11_00_00__00_00__00_00_00_00_00_00_00_11____00_00_11_00_ ;

//dataoutregFIR<=288’ b11_00_00_11_11_11_00_00__00_00__00_00_00_11_11_11_11_11____11_11_00_00_00_11_00_00__00_00__11_00_00_00_00_00_00_11____00_00_11_00_ ; end end

//****************************FIR SIGN SHIFT REG******************************************************** reg dataout_sign1; reg [63:0]dataoutreg_sign; reg [86:0]dataoutreg_sign_STIM; reg clkout_sign1; reg clkout_stim; reg dataout_sign2; reg [63:0]dataoutreg_sign2; reg clkout_sign2; reg [7:0]count_sign_SR; reg [7:0]new_count_sign_SR; reg [7:0]count_sign_SR2; reg [7:0]new_count_sign_SR2; reg [4:0]count_stim_SR_STIM; CHAPTER C. SAMPLE VERILOG CODES 243

reg [4:0]new_count_stim_SR_STIM; reg [7:0]count_sign_SR_STIM; reg [7:0]new_count_sign_SR_STIM; always @(posedge count_shift[6] or negedge rst_reg) begin if (˜rst_reg) count_sign_SR<=0; else count_sign_SR<=new_count_sign_SR; end always @(posedge count_shift[6] or negedge rst_reg) begin if (˜rst_reg) count_sign_SR2<=0; else count_sign_SR2<=new_count_sign_SR2; end always @(posedge clkIn or negedge rst_reg_STIM) begin if (˜rst_reg_STIM) begin count_sign_SR_STIM<=0; count_stim_SR_STIM<=0; end else begin count_sign_SR_STIM<=new_count_sign_SR_STIM; count_stim_SR_STIM<=new_count_stim_SR_STIM; end end always @(count_sign_SR or turnOnStimulation) begin if(˜turnOnStimulation) begin if(count_sign_SR==63) new_count_sign_SR=63; else new_count_sign_SR=count_sign_SR+1; end end always @(count_sign_SR2 or turnOnStimulation) begin if(˜turnOnStimulation) begin if(count_sign_SR2==63) new_count_sign_SR2=63; else new_count_sign_SR2=count_sign_SR2+1; end end always @(count_sign_SR_STIM or count_stim_SR_STIM or turnOnStimulation) begin if(turnOnStimulation) begin if(count_sign_SR_STIM==63) begin new_count_sign_SR_STIM=63; if (count_stim_SR_STIM==22) CHAPTER C. SAMPLE VERILOG CODES 244

new_count_stim_SR_STIM=22; else new_count_stim_SR_STIM=count_stim_SR_STIM+1; end else begin new_count_sign_SR_STIM=count_sign_SR_STIM+1; new_count_stim_SR_STIM=0; end end end always@(turnOnStimulation or count_sign_SR or count_sign_SR2 or count_sign_SR_STIM or count_stim_SR_STIM) begin if(˜turnOnStimulation) begin dataout_sign1<=dataoutreg_sign[count_sign_SR]; dataout_sign2<=dataoutreg_sign2[count_sign_SR2];

//assign dataoutreg_sign=64’ b11_11_11_11_00_00_00_00_00_00_00_00_11_11_11_11___11_11_11_11_11_11_11_11_00_00_00_00_00_00_00_00;

//assign dataoutreg_sign=64’ b11_11_11_11_11_11_11_11_00_00_00_00_00_00_00_00___11_11_11_11_00_00_00_00_00_00_00_00_11_11_11_11; dataoutreg_sign2<=64’ b11_11_11_11_11_11_11_11__00_00_00_00_00_00_00_00___11_11_11_11_00_00_00_00_00_00_00_00_11_11_11_11; dataoutreg_sign<=64’ b11_11_11_11_00_00_00_00_00_00_00_00_11_11_11_11___11_11_11_11_11_11_11_11__00_00_00_00_00_00_00_00;

clkout_sign1<=count_sign_SR[0]; clkout_sign2<=count_sign_SR2[0]; end else begin dataout_sign1<=dataoutreg_sign_STIM[count_sign_SR_STIM+count_stim_SR_STIM]; dataoutreg_sign_STIM=86’ b11_00_00_00_00_00_00_00_00_11_11______11_11_11_11_11_00_00_00_00_00_00_11_11_11_11_11___11_11_11_11_11_00_00_00_00_00_00_11_11_11_ ; clkout_sign1<=count_sign_SR_STIM[0]; clkout_stim<=count_stim_SR_STIM[0]; end end endmodule

C.3 Sample code for programming on-board DAC

module Voltage_DAC ( clkIn, clkDAC, start, Data, din1, ldac1, sync1, CHAPTER C. SAMPLE VERILOG CODES 245

din2, ldac2, sync2 //idle );

// Inputs input clkIn; input start; // Start signal input [17:0] Data; // Incoming data

// Outputs output wire din1; output reg ldac1 =1; output reg sync1 =1; output wire din2; output reg ldac2 =1; output reg sync2 =1; output wire clkDAC;

// Registers reg [4:0] timer = 5’b00000; reg [15:0] Dataout; reg idle; reg ldac = 0; reg sync =1; reg chip0, chip1; always @(posedge clkIn) begin case (timer) 0: begin idle <= 0; sync <= 0; ldac <= 1; end 15: begin sync <= 1; ldac <= 0; end 17: begin ldac <= 1; sync <= 1; end endcase if (timer < 17 & ˜idle) timer <= timer + 1; if (timer < 15 & ˜idle) CHAPTER C. SAMPLE VERILOG CODES 246

Dataout <= { Dataout[14:0] , Dataout[15]};

if (idle && start) //idle begin // Start operation timer <= 0; Dataout <= Data[15:0]; // Load the incoming data

// chip selection // This has to be done here, so as sync and idle are not changed between cycles chip0 <= ˜Data[17] && ˜Data[16]; chip1 <= ˜Data[17] && Data[16]; end if (˜idle && ˜start) begin idle <= 1; // when start goes down, go back to idle ldac <= 1; sync <=1; end end assign din1 = Dataout[15]; assign din2 = Dataout[15]; always @ (sync) begin if (chip0) sync1 <= sync; if (chip1) sync2 <= sync; end always @ (ldac) begin if (chip0) ldac1 <= ldac; if (chip1) ldac2 <= ldac; end assign clkDAC = clkIn &&˜sync; endmodule 247

Appendix D

MATLAB codes

D.1 MATLAB code for playing ofﬂine data

The code below converts a text ﬁle of data into a ﬁle that can be played by the arbitrary waveform generator available in the lab:

function convertToArb(data,samplerate,fName)

%check if data is row vector, if so convert to column if isrow(data) data = data’; end

%data=importdata(filetoread1); numberofpoints = length(data);

%Get max and min values from waveform data data_min=min(data); data_max=max(data);

%range has to be the maximum absolute value between data_min and data_max range=abs(data_max); if(abs(data_min)>abs(data_max)) range=abs(data_min); end

%Data Conversion from V to DAC levels data_conv=round(data*32767/range); fName = [fName ’.arb’]; %add file extension to file name CHAPTER D. MATLAB CODES 248

%File creation and formatting fid = fopen(fName, ’w’); fprintf(fid,’%s\r\n’,’File Format:1.10’); fprintf(fid,’%s\r\n’,’Channel Count:1’); fprintf(fid,’%s\r\n’,’Column Char:TAB’); fprintf(fid,’%s%d\r\n’,’Sample Rate:’,samplerate); fprintf(fid,’%s%6.4f\r\n’,’High Level:’,data_max(1)); fprintf(fid,’%s%6.4f\r\n’,’Low Level:’,data_min(1)); fprintf(fid,’%s\r\n’,’Data Type:"Short"’); fprintf(fid,’%s\r\n’,’Filter:"OFF"’); fprintf(fid,’%s%d\r\n’,’Data Points:’,numberofpoints); fprintf(fid,’%s\r\n’,’Data:’); %Write data to file and close it fprintf(fid,’%d\r\n’,data_conv); fclose(fid);

The input arguments for the convertToArb( ) function are as follows:

• ’data’ is the vector containing the waveform points that you want to convert to a .arb ﬁle

• ’samplerate’ is the sample rate setting for the 33521A or 33522A. The total time of your waveform is equal to: samplerate * number of points in the ﬁle.

• ’fName’ is the name you want to assign to the .arb ﬁle that is created, for instance ”myArb” will create a ”myArb.arb” ﬁle.

This is how to call the function : convertToArb(data,256,’datarb.arb’);

D.2 Reading from USB controller

The following MATLAB code is developed and used for reading continuously from the USB controller (FTDI Inc.) available on some of the boards. clear all; count=0; vec(1:10)=0; while(1) CHAPTER D. MATLAB CODES 249

format long; s1 = serial(’COM8’); s2 = serial(’COM9’); set(s1,’BaudRate’,115200,’DataBits’,8,’Parity’,’none’,’StopBits’,1); set(s2,’BaudRate’,115200,’DataBits’,8,’Parity’,’none’,’StopBits’,1); N=1000; S1BUFF = N; S2BUFF = 2; s1.InputBufferSize = S1BUFF; s1.OutputBufferSize = S1BUFF; s2.InputBufferSize = S2BUFF; s2.OutputBufferSize = S2BUFF; s1.Timeout = 2000; s2.Timeout = 2000; fopen(s1); s1.ByteOrder = ’bigEndian’; x=[4 3]; y=[4 4]; fopen(s2); s2.ByteOrder = ’bigEndian’; fwrite(s2, x , ’int8’); disp(’Writing Data Done’) values(:,1) = fread(s1,N); disp(’Reading Data Done’) x=0; y=0; z=1; fclose(s1) fclose(s2) BB1=1; for i=1:S1BUFF BB = mod(values(i),4); if (BB == 0 & x==0) x=1; y=1; end if(BB == 0) BB1=BB1+1; p1(BB1) = (values(i) - BB)/4; elseif(BB == 1) p2(BB1) = (values(i) - BB)/4; elseif(BB == 2) p3(BB1) = (values(i) - BB)/4; end end for i=1:N/3-20 OUTF1(i) = p1(i);

OUTF2(i) = p2(i)*2ˆ6; OUTF3(i) = p3(i); OUTF(i) = OUTF1(i)+OUTF2(i); OUTflag(i)=OUTF3(i); end H=1; X1=4:1:N/12-21; CHAPTER D. MATLAB CODES 250

y1 = OUTF(4:1:N/12-21); t=size(y1); t=t(:,2); out0=[]; out1=[]; for i=1:N/3-20 if(OUTflag(i)==0) out0 = [out0 OUTF(i)]; elseif(OUTflag(i)==24) out1=[out1 OUTF(i)]; end end hold on subplot(311) plot(out0) drawnow

%axis([count*300 300*(count+1) 0 400]) subplot(312) plot(out1) drawnow

%axis([count*300 300*(count+1) 0 400]) subplot(313) plot(OUTflag) drawnow

%axis([count*300 300*(count+1) 0 30]) hold on count=count+1; if (count==10) break; end

% % % end 251

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