A LOW-POWER RECEIVER FOR SIMULTANEOUS ELECTROCARDIOGRAM AND RESPIRATORY RATE DETECTION by JIFU LIANG Submitted in partial fulfillment of the requirements For the degree of Master of Science Department of Electrical Engineering and Computer Science CASE WESTERN RESERVE UNIVERSITY August, 2016 A Low-Power Receiver for Simultaneous Electrocardiogram and Respiratory Rate Detection Case Western Reserve University Case School of Graduate Studies We hereby approve the thesis1 of JIFU LIANG for the degree of Master of Science Dr. Soumyajit Mandal Committee Chair, Adviser July 1st, 2016 Department of Electrical Engineering and Computer Science Dr. Pedram Mohseni Committee Member July 1st, 2016 Department of Electrical Engineering and Computer Science Dr. Dominique Durand Committee Member July 1st, 2016 Department of Biomedical Engineering 1We certify that written approval has been obtained for any proprietary material contained therein. I would like to dedicate this thesis to my advisor, Dr. Soumyajit Mandal, for his endless guidance of my research. I would also dedicate this thesis to my parents, Yanjun Liang and Jinju Lu, for their support of my study in America. I would also dedicate this thesis to my girlfriend, Shuyue Li, for her encouragement of my study at CWRU. Table of Contents List of Tables vi List of Figures vii Acknowledgements xiii Acknowledgements xiii Abstract xiv Abstract xiv Chapter 1. Introduction1 Motivation1 Research Goals2 Literature Review3 Structure of the Thesis 13 Chapter 2. First Chip Design 14 Impedance Pneumography 14 Block Diagram 16 Clock Generator Block 18 Controlled Injected Current Block and Mixer 20 Preamplifier Block 21 Wide-linear Range OTA and Filters 24 Second Gain Stage for Amplifying RR signal 29 Chapter 3. Measurement Result of First Chip 32 Programmable Injected Current Block and Mixer 34 iv ECG Amplifier 35 RR Measurement 40 Chapter 4. Second Chip Design 43 Fully Differential Wide-linear-range OTA 43 Fully Differential Filters 45 Fully Differential Preamplifier Block 47 Digital Block 52 Second Gain Stage for Amplifying RR signal 57 Layout 60 Chapter 5. Conclusions 63 Appendix A. PCB for testing the AFE 66 Appendix. Complete References 68 v List of Tables 3.1 Comparison table with the state of the art 34 vi List of Figures 1.1 Conceptual view of a wireless biopotential measurement system integrated into a chest band. The three patch electrodes are denoted RA, LA, and REF,respectively.3 1.2 One of the most frequently used topology of bioelectric amplifier1.6 1.3 (a) Typology of MOS pseudo resistor. (b) Basic structure of switched capacitor.7 1.4 Schematic of ECG amplifier in reference2.8 1.5 Schematic of ECG amplifier presented by Wen et al.3. 10 1.6 Schematic of ECG amplifier presented by Burke and Gleeson4. 11 2.1 Simplified structure of the respiration circuit when RA and LA electrodes are used. 15 2.2 Detected respiratory rate signal after filtering with a fourth-order LPF with cutoff frequency of 2 Hz. A commercial AFE (ADS1298R) designed by Texas Instruments is used here to measure RR signal when the volunteer took deep breath. 16 2.3 Simplified block diagram of the integrated front-end receiver. 17 2.4 Typical spectra of the ECG, modulated RR, and baseband RR signals before the HPF, before the quadrature modulator, and after the modulator. 19 2.5 Clock generator circuit used to generate 0±, 90±, 180±, and 270± clocks. 19 vii 2.6 Simulation result of the clock generator block. clk1 and clk2 have 90± phase shift. 20 2.7 Programmable current mirrors and double balanced mixer used for generating I AC . The amplitude of I AC can be programmed over a 1:16 range (4 bits) by the switches Á1-Á4. 21 2.8 Schematic of the low-noise ECG amplifier. 22 2.9 Schematic of the OTA used four times in the preamplifier. 23 2.10 Simulation results of (a) the AC response of the preamplifier. (b) the output of the preamplifier when an input of 2 mV 100 Hz sinusoid wave is used. (c) the output of the ECG path when an input of 2 mV 100 Hz sinusoid wave is used. 25 2.11 (a) First-order G C LPF topology. (b) First-order G C HPF m ¡ m ¡ topology. 25 2.12 Basic single-stage five transistor OTA with NMOS input transistors. 26 2.13 The wide-linear-range OTA used several times in the AFE. 27 2.14 Schematic of the BPF and second gain stage used to process each demodulated RR signal component. The capacitors C1 and C2 are 400 pF off-chip capacitors, while C3 and C4 are 2 pF on-chip capacitors. 29 2.15 Simulation results of (a) the AC response of the BPF after demodulator. (b) the I component of RR at the output of mixer if a 1 ¹V RR signal is applied at the input of the preamplifier. (c) the final output of RR path if a 1 ¹V RR signal is applied at the input of the preamplifier. 31 viii 3.1 Die photograph of the fabricated AFE, which has an active area of 1050 ¹m 600 ¹m. Major blocks are labeled. 32 £ 3.2 The PCB used to test the first chip. 33 3.3 The measured transistor I-V curve used to set the 200 nA off-chip bias current. This curve was measured by using a Keithley source meter. 34 3.4 Circuit used to test the programmable injected current block and the mixer. A fixed resistor (100 k­) was placed between LA and RA. 35 3.5 (a) Square voltage waveforms across the RA and LA with different injected currents when a 100 k­ resistor was used between RA and LA. (b) Measured positive and negative currents as a function of the digital code. 36 3.6 (a) Differential frequency response of both the ECG amplifier and the following LPF. (b) Common-mode frequency response of both the ECG amplifier and the following LPF without utilizing driven-ground circuit. 36 3.7 (a) Output noise of the both the ECG amplifier and the following LPF. (b) Input noise of the both the ECG amplifier and the following LPF. 37 3.8 (a) Output of the ECG path when high-frequency clock is disabled. The input signal is a 2 mV, 10 Hz sinusoid wave. (b) Output of the ECG path to the sum of a 1.5 mV, 10 Hz sinusoid (simulating ECG) and a 1.4 mV, 100 Hz square wave (simulating RR carrier). 38 3.9 Detected ECG signal after baseline removal and filtering with a fourth-order LPF (f 50 Hz). 39 c Æ ix 3.10 The DC voltage at the output of the ECG path shifted from 0.3 V to 2.4 V in around 900 seconds. 40 3.11 (a) Body model used to generate ECG-like and RR-like signals. (b) Simulation result of the modulated RR-like signal when 100 nA 1 kHz AC currents are fed to LA and RA. (c) The FFT result of the transient signal generated by the body model. 41 3.12 Input triangle wave used to modulate the impedance between RA and LA at 0.5 Hz, and measured I and Q RR outputs after filtering with a fourth-order Butterworth LPf with cutoff frequency of 5 Hz. 42 4.1 (a) Fully differential version of wide-linear-range OTA. (b) Differential- difference OTA used in CMFB. (c) Fully differential OTA stage. 45 4.2 (a) A single stage of fully differential OTA in the preamplifier. (b) Bode plot of the fully differential OTA stage. 46 4.3 (a) Fully differential LPF.(b) Fully differential HPF. 47 4.4 The AC simulation results of (a) HPF with cutoff frequency of 1 kHz to remove ECG signal in RR path. (b) LPF with cutoff frequency of 5 Hz to remove high-frequency RR carrier signal in RR path. 3 nF off-chip capacitor is used. 47 4.5 Circuit of fully differential preamplifier. 49 4.6 Modified switched capacitor topology. 51 4.7 Equivalent circuits of the modified switched capacitor topology in two phases. (a) Equivalent circuit when clk1 is on and clk2 is off. (b) Equivalent circuit when clk1 is off and clk2 is on. 51 x 4.8 Transient simulation result at the output of the preamplifier when a 2 mV 100 Hz sinusoid wave simulating ECG signal and a 10 kHz square wave simulating RR carrier signal are used at the input of the circuit. 52 4.9 Digital blocks in the AFE. 53 4.10 Frequency response of the first-order LPF by using switched capacitor. 54 4.11 Programmable counter. 55 4.12 Two-phase non-overlapping clocks generator block. 55 4.13 (a) Programmable bus used to set digital inputs. (b) Timing diagram of SPI. 56 4.14 Simulation results of the circuits generating clocks used in the mixer for modulation and demodulation. (a) The 38 kHz input square wave simulating the off-chip clock. (b) The first output clock with one fourth of the frequency of the input wave. (c) The second output clock with one fourth of the frequency of the input wave and 90 ± phase shift. 57 4.15 Simulation results of the circuits generating clocks used in the switched capacitor. (a) The first output clock. (b) The second output clock. (c) 2 ns delay between the two non-overlapping output clocks. 58 4.16 Second gain stage for amplifying RR signal. 58 4.17 Open-loop Bode plot of the op-amp stage. 59 4.18 Closed-loop Bode plot of the op-amp stage.