Reference Manual

PowerPC™ e500 Core Family Reference Manual Supports e500v1 e500v2 E500CORERM Rev. 1, 4/2005 How to Reach Us: Home Page: www.freescale.com email: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) Information in this document is provided solely to enable system and software +49 89 92103 559 (German) implementers to use Freescale Semiconductor products. There are no express or +33 1 69 35 48 48 (French) implied copyright licenses granted hereunder to design or fabricate any integrated [email protected] circuits or integrated circuits based on the information in this document. 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Document Number: E500CORERM Rev. 1, 4/2005 Part I—e500 Core I Core Complex Overview 1 Register Model 2 Instruction Model 3 Execution Timing 4 Interrupts and Exceptions 5 Power Management 6 Performance Monitor 7 Debug Support 8 Part II—e500 Core Complex II Timer Facilities 9 Auxiliary Processing Units (APUs) 10 L1 Caches 11 Memory Management Units 12 Core Complex Bus (CCB) 13 Appendix A—Programming Examples A Appendix B—Guidelines for 32-Bit Book E B Appendix C—Simplified Mnemonics for PowerPC Instructions C Appendix D—Opcode Listings D Appendix E—Revision History E Index IND I Part I—e500 Core 1 Core Complex Overview 2 Register Model 3 Instruction Model 41Execution Timing 5 Interrupts and Exceptions 6 Power Management 7 Performance Monitor 8 Debug Support II Part II—e500 Core Complex 9 Timer Facilities 10 Auxiliary Processing Units (APUs) 11 L1 Caches 12 Memory Management Units 13 Core Complex Bus (CCB) A Appendix A—Programming Examples B Appendix B—Guidelines for 32-Bit Book E C Appendix C—Simplified Mnemonics for PowerPC Instructions D Appendix D—Opcode Listings E Appendix E—Revision History IND Index Contents Paragraph Page Number Title Number About ThisCont ents Book Audience ....................................................................................................................... xxxii Organization.................................................................................................................. xxxii Suggested Reading....................................................................................................... xxxiii General Information............................................................................................. xxxiii Related Documentation ....................................................................................... xxxiv Conventions ................................................................................................................. xxxiv Terminology Conventions..............................................................................................xxxv Part I e500 Core Chapter 1 Core Complex Overview 1.1 Overview.......................................................................................................................... 1-1 1.1.1 Upward Compatibility ................................................................................................. 1-3 1.1.2 Core Complex Summary ............................................................................................. 1-3 1.2 e500 Processor and System Version Numbers................................................................. 1-5 1.3 Features............................................................................................................................ 1-5 1.3.1 e500v2 Differences .................................................................................................... 1-11 1.4 Instruction Set ................................................................................................................ 1-12 1.5 Instruction Flow.............................................................................................................1-14 1.5.1 Initial Instruction Fetch.............................................................................................. 1-14 1.5.2 Branch Detection and Prediction ............................................................................... 1-14 1.5.3 e500 Execution Pipeline ............................................................................................ 1-16 1.6 Programming Model ...................................................................................................... 1-18 1.7 On-Chip Cache Implementation .................................................................................... 1-20 1.8 Interrupts and Exception Handling ................................................................................ 1-20 1.8.1 Exception Handling ................................................................................................... 1-20 1.8.2 Interrupt Classes ........................................................................................................ 1-21 1.8.3 Interrupt Types........................................................................................................... 1-21 1.8.4 Upper Bound on Interrupt Latencies ......................................................................... 1-22 1.8.5 Interrupt Registers...................................................................................................... 1-22 1.9 Memory Management.................................................................................................... 1-24 1.9.1 Address Translation ................................................................................................... 1-26 1.9.2 MMU Assist Registers (MAS0–MAS4 and MAS6–MAS7)..................................... 1-27 PowerPC e500 Core Family Reference Manual, Rev. 1 Freescale Semiconductor v Contents Paragraph Page Number Title Number 1.9.3 Process ID Registers (PID0–PID2)............................................................................ 1-28 1.9.4 TLB Coherency.......................................................................................................... 1-28 1.10 Memory Coherency ....................................................................................................... 1-29 1.10.1 Atomic Update Memory References ......................................................................... 1-29 1.10.2 Memory Access Ordering.......................................................................................... 1-29 1.10.3 Cache Control Instructions ........................................................................................ 1-29 1.10.4 Programmable Page Characteristics .........................................................................

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