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Embedded Multicore: an Introduction Embedded Multicore: An Introduction EMBMCRM Rev. 0 07/2009 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support Information in this document is provided solely to enable system and software USA/Europe or Locations Not Listed: implementers to use Freescale Semiconductor products. There are no express or Freescale Semiconductor, Inc. implied copyright licenses granted hereunder to design or fabricate any integrated Technical Information Center, EL516 circuits or integrated circuits based on the information in this document. 2100 East Elliot Road Tempe, Arizona 85284 Freescale Semiconductor reserves the right to make changes without further notice to +1-800-521-6274 or any products herein. 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Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: EMBMCRM Rev. 0, 07/2009 Contents Paragraph Page Number Title Number Cont ents Chapter 1 Embedded Multicore, an Overview 1.1 Why Multicore? ...............................................................................................................1-2 1.2 Different Types of Multicore ........................................................................................... 1-3 1.3 Parallelism ....................................................................................................................... 1-5 1.3.1 Bit-Level Parallelism ................................................................................................... 1-6 1.3.2 Instruction-Level Parallelism....................................................................................... 1-6 1.3.3 Data Parallelism...........................................................................................................1-6 1.3.4 Task Parallelism...........................................................................................................1-6 1.4 System and Software Design ........................................................................................... 1-7 1.5 Conclusion ....................................................................................................................... 1-9 Chapter 2 Embedded Multicore from a Hardware Perspective 2.1 Multicore Devices............................................................................................................2-2 2.1.1 Power Savings..............................................................................................................2-5 2.1.2 System-Level Stability and Security............................................................................ 2-5 2.2 From Coprocessors to Multiple Cores ............................................................................. 2-6 2.2.1 Internal Access............................................................................................................. 2-6 2.2.2 Memory Hierarchy....................................................................................................... 2-8 2.2.3 Interfaces...................................................................................................................... 2-9 2.2.4 Debugging and Profiling.............................................................................................. 2-9 2.3 Conclusion ..................................................................................................................... 2-10 Chapter 3 Embedded Multicore: Software Design 3.1 Amdahl’s Law.................................................................................................................. 3-2 3.2 Gustafson’s Law ..............................................................................................................3-3 3.3 Parallelism ....................................................................................................................... 3-4 3.4 Symmetric and Asymmetric Multiprocessing ................................................................. 3-4 3.5 Processes and Threads ..................................................................................................... 3-5 3.5.1 Task and Process Mapping .......................................................................................... 3-6 3.5.2 Run to Completion....................................................................................................... 3-7 3.5.3 Interprocess Communication and Synchronization ..................................................... 3-8 3.5.4 Semaphores and Locks ................................................................................................ 3-8 Embedded Multicore: An Introduction, Rev. 0 Freescale Semiconductor iii Contents Paragraph Page Number Title Number Chapter 4 Embedded Multicore: SMP and Multithreading 4.1 Introduction to Symmetric Multiprocessing .................................................................... 4-2 4.2 Parallelized Application Designs..................................................................................... 4-3 4.3 Macro- and Microparallelization ..................................................................................... 4-3 4.3.1 POSIX Threads ........................................................................................................... 4-4 4.3.2 OpenMP ...................................................................................................................... 4-6 4.4 Performance Constraints and Common Pitfalls............................................................... 4-8 4.5 Summary........................................................................................................................ 4-10 Chapter 5 Embedded Multicore: SMP Operating Systems 5.1 SMP Linux....................................................................................................................... 5-2 5.1.1 Task Schedulers and Load Balancing .......................................................................... 5-2 5.1.2 Core Affinity................................................................................................................ 5-4 5.2 Enea’s OSE for Multicore................................................................................................ 5-6 5.2.1 Architecture Overview................................................................................................. 5-7 5.2.2 Various Multicore Models ........................................................................................... 5-8 5.2.3 Enea OSE Advantages................................................................................................
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