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Measuring Soft Error Sensitivity of FPGA Soft Processor Designs Using Fault Injection

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Measuring Soft Error Sensitivity of FPGA Soft Processor Designs Using Fault Injection Brigham Young University BYU ScholarsArchive Theses and Dissertations 2016-03-01 Measuring Soft Error Sensitivity of FPGA Soft Processor Designs Using Fault Injection Nathan Arthur Harward Brigham Young University - Provo Follow this and additional works at: https://scholarsarchive.byu.edu/etd Part of the Electrical and Computer Engineering Commons BYU ScholarsArchive Citation Harward, Nathan Arthur, "Measuring Soft Error Sensitivity of FPGA Soft Processor Designs Using Fault Injection" (2016). Theses and Dissertations. 5699. https://scholarsarchive.byu.edu/etd/5699 This Thesis is brought to you for free and open access by BYU ScholarsArchive. It has been accepted for inclusion in Theses and Dissertations by an authorized administrator of BYU ScholarsArchive. For more information, please contact [email protected], [email protected]. Measuring Soft Error Sensitivity of FPGA Soft Processor Designs Using Fault Injection Nathan Arthur Harward A thesis submitted to the faculty of Brigham Young University in partial fulfillment of the requirements for the degree of Master of Science Michael J. Wirthlin, Chair Doran K. Wilde James K. Archibald Department of Electrical and Computer Engineering Brigham Young University March 2016 Copyright © 2016 Nathan Arthur Harward All Rights Reserved ABSTRACT Measuring Soft Error Sensitivity of FPGA Soft Processor Designs Using Fault Injection Nathan Arthur Harward Department of Electrical and Computer Engineering, BYU Master of Science Increasingly, soft processors are being considered for use within FPGA-based reliable com- puting systems. In an environment in which radiation is a concern, such as space, the logic and routing (configuration memory) of soft processors are sensitive to radiation effects, including sin- gle event upsets (SEUs). Thus, effective tools are needed to evaluate and estimate how sensitive the configuration memories of soft processors are in high-radiation environments. A high-speed FPGA fault injection system and methodology were created using the Xil- inx Radiation Test Consortium’s (XRTC’s) Virtex-5 radiation test hardware to conduct exhaustive tests of the SEU sensitivity of a design within an FPGA’s configuration memory. This tool was used to show that the sensitivity of the configuration memory of a soft processor depends on sev- eral variables, including its microarchitecture, its customizations and features, and the software instructions that are executed. The fault injection experiments described in this thesis were performed on five different soft processors, i.e., MicroBlaze, LEON3, Arm Cortex-M0 DesignStart, OpenRISC 1200, and PicoBlaze. Emphasis was placed on characterizing the sensitivity of the MicroBlaze soft processor and the dependence of the sensitivity on various modifications. Seven benchmarks were executed through the various experiments and used to determine the SEU sensitivity of the soft processor’s configuration memory to the instructions that were executed. In this thesis, a wide variety of soft processor fault injection results are presented to show the differences in sensitivity between multiple soft processors and the software they run. Keywords: FPGA, reliability, fault injection, soft processor, softcore processor, MicroBlaze, LEON3, Cortex-M0, OpenRISC, PicoBlaze, Xilinx, Virtex-5, XRTC, XRTC-V5FI ACKNOWLEDGMENTS I would like to share my appreciation for my research advisor, Dr. Michael Wirthlin, for giving me an excellent research opportunity and guiding me through the exploration and writing of this thesis work and multiple papers. He has been very patient and encouraging. I also wish to thank Drs. Doran Wilde and James Archibald for being continually supportive and for their service on my thesis committee. I wish to recognize research assistants who have participated in building the fault injector used for this research: Luke Hsiao, Shaelyn Meyer, and Jeremy Butler. I also would like to thank Jon-Paul Anderson for his helpful feedback and advice for this research and Aaron Stoddard for suggestions for improving my thesis draft. I thank and recognize a fellow researcher, collaborator, and friend, Michael Gardiner, for providing several soft processor designs and benchmarks that were used for various experiments in this research. I am very grateful for the love and patience of my wife Caitlin, and my two daughters Jeri, and Isla, who allowed me to pursue my educational goals. I also thank my parents who fueled my fascination with electronics and discovery. I also acknowledge the Xilinx Radiation Test Consortium (XRTC), Gary Swift, and other consortium members for insight and for providing our lab with the use of XRTC hardware. This work was funded by members of the NSF Center for High-Performance Reconfigurable Computing (CHREC), an I/UCRC Program of the National Science Foundation under Grant No. 1265957. TABLE OF CONTENTS LIST OF TABLES ....................................... vi LIST OF FIGURES ...................................... vii Chapter 1 Introduction ................................... 1 Chapter 2 FPGA Radiation Testing and Infrastructure ................. 4 2.1 Radiation Sensitivity of Digital Circuits and FPGAs . .4 2.2 XRTC Test Infrastructure . .7 2.2.1 Xilinx Radiation Test Consortium . .8 2.2.2 XRTC Hardware System . .8 2.2.3 External Connections . 10 2.3 Previous Experiments Performed with XRTC Hardware . 11 Chapter 3 Fault Injection System Based on XRTC Radiation Test Hardware ..... 12 3.1 Background on Fault Injection Systems . 12 3.1.1 Background on Emulation-Based FPGA Fault Injection . 14 3.1.2 Previous FPGA Fault Injection Systems . 16 3.2 Fault Injection on the XRTC Platform . 18 3.2.1 Benefits of Using XRTC Hardware for Fault Injection . 18 3.2.2 Supporting Fault Injection on XRTC Hardware . 19 3.3 Fault Injection Methodology . 20 3.3.1 Sequence for an Individual Injection of a Bit Fault . 21 3.3.2 Running a Fault Injection Campaign . 23 3.3.3 Variations in Methodology . 24 3.4 Comparison with Previous Works on Fault Injection . 25 Chapter 4 MicroBlaze Soft Error Sensitivity Experiments ............... 27 4.1 Soft Processor Background . 27 4.2 Background on the MicroBlaze Soft Processor . 29 4.3 MicroBlaze Design Sensitivity . 29 4.3.1 MicroBlaze Raw Sensitivity Results . 30 4.3.2 Placement Dependencies . 32 4.3.3 Experiments with Additional MicroBlaze Variations . 33 4.4 MicroBlaze Software Sensitivity . 38 4.4.1 Overview of Benchmarks Used . 39 4.4.2 Results of Benchmark Experiments . 39 4.4.3 Sensitivity Cost of an Unutilized FPU . 40 Chapter 5 Fault Injection Experiments on Multiple Soft Processors ................................. 43 5.1 Processor Examples . 43 iv 5.2 Fault Injection of Minimalistic Processors . 44 5.2.1 Overview of Experiment . 45 5.2.2 Raw Sensitivity Results . 47 5.2.3 Reset Recovery Experiment . 48 5.3 Experiments Using Performance Level Processors on Multiple Benchmarks . 49 5.3.1 Overview of Experiment . 49 5.3.2 Results and Analysis . 50 Chapter 6 Conclusion and Future Work ......................... 55 REFERENCES ......................................... 57 v LIST OF TABLES 4.1 Sensitive Bits Measured over Multiple Runs of a Single MicroBlaze Design . 31 4.2 Configuration Bits Common to Multiple Runs . 31 4.3 Variation in Placement and Routing . 33 4.4 Sensitivity Results and Utilization for MicroBlaze with and without LUTRAM Primitives . 34 4.5 Sensitivity Results and Utilization for MicroBlaze with Different Memory Sizes . 35 4.6 Execution Time Dependence on MicroBlaze and Towers of Hanoi Results . 37 4.7 All Benchmark Software Programs . 40 4.8 MicroBlaze FPU Comparison for Integer Benchmarks . 42 5.1 Utilization for Minimalistic Soft Processor Design Implementations . 45 5.2 The Sensitivity Results for Minimalist Soft Processor Design Implementations . 47 5.3 Reset Recovery Results for Various Minimalistic Soft Processors . 49 5.4 Resource Utilization for Performance Processor Design Implementations . 50 5.5 Sensitivity Results for Performance Processor Designs Implementations Running on Multiple Benchmarks . 51 5.6 Normalized Sensitivity Results for Performance Processor Designs Implementa- tions Running on Multiple Benchmarks . 53 vi LIST OF FIGURES 2.1 Configuration Memory . .5 2.2 Resulting Circuit . .5 2.3 Example of an SEU Effect on Routing . .6 2.4 Example of an SEU Effect on Logic . .7 2.5 Picture of (a) XRTC motherboard, (b) V5QV daughtercard, and (c) PROM mem- ory card . .9 2.6 Picture of XRTC BrainBox . 10 3.1 High Level View of Fault Injector Components without the BrainBox . 19 3.2 Both processors are placed on the DUT FPGA. Their outputs are compared with each other on the FuncMon service FPGA. 21 3.3 Diagram Showing the Fault Injection Procedure . 23 4.1 The placement and route layout images of each MicroBlaze where placement was generated from random seeds (a) 22, (b) 49, and (c) 75, and (d) using an area constraint. 32 4.2 Sensitive bits and size in slices for different MicroBlaze placements . 34 4.3 Placement Screenshot for MicroBlaze with (a) and without (b) LUTRAM Primitives 35 4.4 Placement Screenshot for MicroBlaze (a) with and (b) without Added Memory . 36 4.5 Execution Time Dependence on MicroBlaze and Towers of Hanoi Results . 38 4.6 MicroBlaze FPU Comparison for Integer Benchmarks . 41 4.7 Placement Screenshot for MicroBlaze (a) with and (b) without FPU . 42 5.1 Placement Screenshots for Minimalistic Soft Process in Top Left to Bottom Right Order: MicroBlaze, LEON 3, ARM Cortex-M0, OpenRISC, and PicoBlaze . 46 5.2 Minimalistic Soft Processor Sensitive
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