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Intel® Embedded Processor for 2008 (Tolapai) Soc Architecture Overview Intel® Embedded Processor for 2008 (Tolapai) SoC Architecture Overview Pranav Mehta Sr. Principal Engineer & CTO Embedded & Comms Processor Div Session ID: QATS001 Risk Factors This presentation contains forward-looking statements. All statements made that are not historical facts are subject to a number of risks and uncertainties, and actual results may differ materially. Please refer to our most recent Earnings Release and our most recent Form 10-Q or 10-K filing available on our website for more information on the risk factors that could cause actual results to differ. Rev. 4/17/07 2 Legal Disclaimer y INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL® PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. y Intel may make changes to specifications and product descriptions at any time, without notice. y All products, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice. y Intel, processors, chipsets, and desktop boards may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. y Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or configuration may affect actual performance. y Intel, Intel Inside, and the Intel logo are trademarks of Intel Corporation in the United States and other countries. y *Other names and brands may be claimed as the property of others. y Copyright © 2007 Intel Corporation. 3 Agenda y Usage Needs of Small/Medium Enterprise y Tolapai Architecture Overview y Tolapai Silicon Architecture y Tolapai Software Architecture y Solving SME Usage Needs Tolapai = Intel® embedded processor for 2008. 4 Usage Needs of SME Data Flow within an SME 5 6 7 8 9 10 11 Usage Needs of SME Converged Appliance: Requirements Power Delivery & Thermal Constraints Form Factor Throughput AND Compute Constraints Performance Converged Security Appliance Evolving IP Based Traffic Standards & Services 12 Usage Needs of SME Desired Product Architecture Low Power & Perf/Watt/in3 Higher Balanced I/O Integration & & CPU Lower Cost Subsystems Converged Security Appliance Open & Multi-threading Scalable Architecture Desired SME Solution: Affordable Features Today Æ Scalable for Future 13 Tolapai Architecture Overview Intel® QuickAssist Technology Introduction Encompasses Industry Hardware Solutions Future Intel Processor Integration of Accelerators Software Architecture, Libraries, Industry APIs & Tools For Acceleration Comprehensive Approach To Acceleration Copyright © 2007 Intel 14 Tolapai Architecture Overview Introducing…Tolapai Intel® Architecture Attributes • General purpose Scalability • Economies of Scale • Software Infrastructure Intel® QuickAssist Integrated Accelerator •Packet Processing •Security Processing Tolapai: 9TTM 9Power Efficient Performance 9BOM cost Tolapai = Intel® embedded processor for 2008. 15 Tolapai Architecture Overview: Hardware Tolapai: Integration Highlights 37.5 mm IA CPU @ 600, 1066 and 148 M x37.5 mm 1200MHz Transistors DDR2 memory controller (MCH) PCI Express* Standard IA PC peripherals (ICH) 3x Gigabit Ethernet MACs 3x TDM high-speed serial interfaces for 12 T1/E1 or Slic/Codec connections Intel® QuickAssist Integrated Accelerator 1,088-ball - For security and IP FCBGA telephony applications Intel's first integrated IA CPU, chipset and memory controller since 1994's 80386EX. Tolapai = Intel® embedded processor for 2008. 16 Tolapai Architecture OverviewOverview: Hardware Acceleration Details ‡ Services Unit Local MDIO (x1) Expansion TDM GigE GigE GigE CAN (x2) ‡ Security Interface MAC MAC MAC ‡ Bus SSP (x1) Services Unit (16b @ (12 E1/T1) #2 #1 #0 (3DES, AES, (A)RC4, 80 MHz) IEEE-1588 yIA CPU Core w/ 256KB MD5, SHA-x, PKE, L2 cache TRNG) 256 KB - Intel® Pentium® M ASU SRAM processor derivative Acceleration and I/O Complex ‡ Enabling software required. Power efficient - IA Complex IMCH Transparent PCI-to-PCI Bridge EDMA 2 FSB Cache Core IA3 Memory Controller Hub 256K L2 IICH APIC, DMA, Timers, Watch Dog Timer, RTC, HPET( x3) PCI Express Interface Memory Controller (x1) (Gen1, DDR2 1x8, 2x4 or (400/533/667/800, UART (x2) 2x1 root 64b with ECC) SATA2 .0 USB2 .0 GPIO (x37) complex) (x2) (x2) SMBus(x2) LPC1.1 Tolapai = Intel® embedded processor for 2008. 17 Tolapai Architecture OverviewOverview: Hardware Acceleration Details ‡ Services Unit Local MDIO (x1) Expansion TDM GigE GigE GigE CAN (x2) ‡ Security Bus Interface MAC MAC MAC IA CPU Core w/ 256KB ‡ SSP (x1) y Services Unit (16b @ (12 E1/T1) #2 #1 #0 (3DES, AES, (A)RC4, 80 MHz) IEEE-1588 L2 cache MD5, SHA-x, PKE, TRNG) - Intel® Pentium® M 256 KB processor derivative ASU SRAM yIntegrated Memory Acceleration and I/O Complex ‡ Enabling software required. IA Complex IMCH Controller Transparent PCI-to-PCI Bridge EDMA - 1 channel 64-bit DDR2 - 4 channel DMA engine 2 FSB Cache Core IA3 Memory Controller Hub - PCI Express* (1x8, 2x4, or 256K L2 2x1) IICH APIC, DMA, Timers, Watch Dog Timer, RTC, HPET( x3) PCI Express Interface Memory Controller (x1) (Gen1, DDR2 1x8, 2x4 or (400/533/667/800, UART (x2) 2x1 root 64b with ECC) SATA2 .0 USB2 .0 GPIO (x37) complex) (x2) (x2) SMBus(x2) LPC1.1 Tolapai = Intel® embedded processor for 2008. 18 Tolapai Architecture OverviewOverview: Hardware Acceleration Details ‡ Local MDIO (x1) Services Unit Expansion TDM GigE GigE GigE CAN (x2) ‡ yIA CPU Core w/ 256KB L2 Security Interface MAC MAC MAC ‡ Bus SSP (x1) 16b @ (12 E1/T1) #2 #1 #0 Services Unit ( IEEE-1588 cache (3DES, AES, (A)RC4, 80 MHz) MD5, SHA-x, PKE, - Intel® Pentium® M processor TRNG) derivative 256 KB yIntegrated Memory Controller ASU SRAM - 1 channel 64-bit DDR2 Acceleration and I/O Complex ‡ Enabling software required. - 4 channel DMA engine IA Complex IMCH Transparent - PCI Express* (1x8, 2x4, or PCI-to-PCI Bridge EDMA 2x1) yIntel® QuickAssist 2 Acceleration FSB Cache Core IA3 Memory Controller Hub - Multi-core, Multi-threaded 256K L2 Engines - 256KB Internal SRAM IICH - Security Hardware Acceleration APIC, DMA, Timers, Watch Dog Timer, RTC, HPET( x3) for PCI Express Bulk: AES, 3DES, (A)RC4 Interface Memory Controller Hash: MD5, SHA-x (x1) (Gen1, DDR2 Public Key – RSA, DSA, DH 1x8, 2x4 or (400/533/667/800, UART (x2) 2x1 root 64b with ECC) Internal True Random Number complex) SATA2 .0 USB2 .0 GPIO (x37) Generator (TRNG) (x2) (x2) SMBus(x2) LPC1.1 Tolapai = Intel® embedded processor for 2008. 19 Tolapai Architecture OverviewOverview: Hardware Acceleration Details ‡ Services Unit Local MDIO (x1) Expansion TDM GigE GigE GigE CAN (x2) ‡ yIA CPU Core w/ 256KB L2 cache Security Interface MAC MAC MAC ‡ Bus SSP (x1) Services Unit (16b @ (12 E1/T1) #2 #1 #0 - Intel® Pentium® M processor derivative (3DES, AES, (A)RC4, 80 MHz) IEEE-1588 MD5, SHA-x, PKE, yIntegrated Memory Controller TRNG) 1 channel 64-bit DDR2 - 256 KB - 4 channel DMA engine ASU SRAM - PCI Express* (1x8, 2x4, or 2x1) Acceleration and I/O Complex ‡ Enabling software required. yIntel® QuickAssist Acceleration IA Complex - Multi-core, Multi-threaded Engines IMCH Transparent EDMA - 256KB Internal SRAM PCI-to-PCI Bridge - Security Hardware Acceleration for Bulk: AES, 3DES, (A)RC4 Hash: MD5, SHA-x che Public Key – RSA, DSA, DH Ca FSB Memory Controller Hub 256K L2 Internal True Random Number Generator IA32 Core (TRNG) yIntegrated I/O Interfaces IICH - 3x TDM (12 T1/E1) APIC, DMA, Timers, Watch Dog - 3x GbE MAC (RGMII or RMII) Timer, RTC, HPET( x3) - 1x Local Expansion Bus (16b) PCI Express Memory Controller - 2x Controller Area Network (CAN) Interface (x1) - 1x Sync Serial Port (SSP) (Gen1, DDR2 - 2x UART, 37x GPIO, 1x8, 2x4 or (400/533/667/800, UART (x2) 2x1 root 64b with ECC) - 2x SMBus/I2C, LPC SATA2 .0 USB2 .0 GPIO (x37) complex) - 2x USB, 2x SATA (x2) (x2) SMBus(x2) LPC1.1 - WDT, RTC Tolapai = Intel® embedded processor for 2008. 20 Tolapai Architecture Overviewerview: Hardware Acceleration Packet Processing ‡ Services Unit Local MDIO (x1) Expansion TDM GigE GigE GigE CAN (x2) ‡ Security Interface MAC MAC MAC ‡ Bus SSP (x1) Flows Services Unit (16b @ (12 E1/T1) #2 #1 #0 (3DES, AES, (A)RC4, 80 MHz) IEEE-1588 Classic IA (blue) MD5, SHA-x, PKE, y TRNG) - GigE Rx DMA packets to DRAM (includes IA snoop) 256 KB - IA interrupt ASU SRAM - IA CPU runs protocol Acceleration and I/O Complex ‡ Enabling software required. - IA CPU controls GigE TX IA Complex IMCH Transparent y Fastpath (red) PCI-to-PCI Bridge EDMA - GigE Rx DMA packets to DRAM - Interrupt routed to che accelerator Ca FSB Memory Controller Hub 256K L2 - Accelerator operates on IA32 Core packet - Forwarding/filtering and security functions can be IICH handled w/o IA CPU APIC, DMA, Timers, Watch Dog intervention Timer, RTC, HPET( x3) PCI - Accelerator controls GigE Tx Express Interface Memory Controller y Exception Packets (x1) (Gen1, DDR2 (green) 1x8, 2x4 or (400/533/667/800, UART (x2) 2x1 root 64b with ECC) - Move packet to coherent complex) SATA2 .0 USB2 .0 GPIO (x37) DRAM (includes IA snoop) (x2) (x2) SMBus(x2) - Accelerator signals IA CPU LPC1.1 Tolapai = Intel® embedded processor for 2008. 21 Tolapai Architecture OverviewOverview: Hardware How IA and Accelerators share Memory Accelerators run in physical address space Non- − Appear as a PCI device Tolapai- Coherent − Run concurrently, async.
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