DOCSLIB.ORG

Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 2 Parallelismparallelism Isis Here…Here… and and Growing!Growing!

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 2 Parallelismparallelism Isis Here…Here… and and Growing!Growing! ParallelismParallelism forfor thethe Masses:Masses: OpportunitiesOpportunities andand ChallengesChallenges Andrew A. Chien Vice President of Research Intel Corporation Carnegie Mellon University Parallel Thinking Seminar OctobeOctoberr 2299, 2008 OutlineOutline • Is Parallelism a crisis? • Opportunities in Parallelism • Expectations and Challenges • Moving Parallel Programming Forward • What’s Going on at Intel • Questions Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 2 ParallelismParallelism isis here…here… And And Growing!Growing! Future: 100+ Larrabee: 12-32 Nehalem: 8+ Dunnington (6) Core2 Quad (4) Number of Cores Core 2 Duo (2) 2006 20072008 2009 2010 … 2015 Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 3 Q.Q. IsIs parallelismparallelism aa crisis?crisis? A.A. Parallelism Parallelism isis anan opportunity.opportunity. Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 4 Parallelism is a key driver for Energy and Performance Dual-Core 1.73x Performance 1.73x Power 1.13x 1.00x 1.02x 0.87x 0.51x Over-clocked Design Dual-core (+20%) Frequency Underclocked (-20%) Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 5 Unified IA and Parallelism Vision – a Foundation Across Platforms PERFORMANCE Integration Options Example: Graphics Notebook, Desktop and Server Canmore, Tolapai, Atom Intel® Core™ 2, i7 Parallelism for the Masses “Opportunities and Challenges” POWER Visual Computing, Gaming ©Intel Corporation 6 Opportunity in Low-power Computing 10x Lower Power Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 7 Opportunity in Highly Parallel Computing 10x Higher Performance VECTOR VECTOR … VECTOR VECTOR IA CORE IA CORE IA CORE IA CORE INTERPROCESSOR NETWORK … COHERENT COHERENT COHERENT COHERENT CACHE CACHE CACHE CACHE COHERENT COHERENT … COHERENT COHERENT FIXED FUNCTION LOGIC FUNCTION FIXED CACHE CACHE CACHE CACHE INTERPROCESSOR NETWORK and I/O INTERFACES MEMORY VECTOR VECTOR … VECTOR VECTOR Visual Computing IA CORE IA CORE IA CORE IA CORE Financial Modeling Gaming, Entertainment Biological Modeling Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 8 OpportunityOpportunity #1:#1: HighlyHighly Portable,Portable, ParallelParallel SoftwareSoftware • All computing systems (servers, desktops, laptops, MIDs, smart phones, embedded…) converging to… – A single framework with parallelism and a selection of CPU’s and specialized elements – Energy efficiency and Performance are core drivers – Must become “forward scalable” Parallelism becomes widespread – all software is parallel Create standard models of parallelism in architecture, expression, and implementation. Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 9 “Forward Scalable” Software # Cores Academic Research 2N N 512 256 256 128 Today 32 16 16 8 Time Software with forward scalability can be moved unchanged from N -> 2N -> 4N cores with continued performance increases. Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 10 OpportunityOpportunity #2:#2: MajorMajor ArchitecturalArchitectural SupportSupport forfor ProgrammabilityProgrammability • Single core growth and aggressive frequency scaling are weakening competitors to other types of architecture innovation Architecture innovations for functionality – programmability, observability, GC, … are now possible Don’t ask for small incremental changes, be bold and ask for LARGE changes… that make a LARGE difference Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 11 NewNew GoldenGolden AgeAge ofof ArchitecturalArchitectural SupportSupport forfor Programming?Programming? Programming Support Parallelism System Integration Ghz Scaling Issue Scaling Language Support Integration Mid 60’s Mid 80’s Terascale To Mid 80’s To Mid 200x Era Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 12 OpportunityOpportunity #3:#3: HighHigh Performance,Performance, HighHigh LevelLevel ProgrammingProgramming ApproachesApproaches • Single chip integration enables closer coupling (cores, caches) and innovation in intercore coordination – Eases performance concerns – Supports irregular, unstructured parallelism Forward scalable performance with good efficiency may be possible without detailed control. Functional, declarative, transactional, object-oriented, dynamic, scripting, and many other high level models will thrive. Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 13 ManycoreManycore != != SMPSMP onon DieDie Parameter SMP Tera-scale Improvement On-die 12 GB/s ~1.2 TB/s ~100X Bandwidth On-die 400 cycles 20 cycles ~20X Latency • Less locality sensitive; Efficient sharing • Runtime techniques more effective for dynamic, irregular data and programs • Can we do less tuning? And program at a higher level? Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 14 OpportunityOpportunity #4:#4: ParallelismParallelism cancan AddAdd NewNew KindsKinds ofof CapabilityCapability andand ValueValue • Additional core and computational capability can be available on-chip – Single-chip design enables enhancement at low cost – Integration enables close coupling – Security: taintcheck, invariant monitoring, etc. – Robustness: race detection, invariant checking, etc. – Interface: sensor data processing, self-tuning, activity inference Deploy Parallelism to enable new applications, software quality, and enhance user experience Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 15 ExpectationsExpectations andand ChallengesChallenges Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 16 Two Students in 2015 Mine’s an Intel 1,000 How many cores core with 64 Out- does your of-Order cores! computer have? End Users don’t care about core counts; they care about capability Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 17 Chip Real Estate and Performance/Value • Tukwila – next generation Intel Itanium processor – 4 cores, 2B transistors, 30MB cache – 50% cache, 50% logic – 1% of chip area = 30M transistors = 1/3MB – 0.1% of chip area = 3M transistors = 1/30MB • How much performance benefit? • What incremental performance benefit should you expect for the last core in a 100-core? 1000-core? Incremental performance benefit or “forward scalability”, not efficiency should be the goal. Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 18 KeyKey SoftwareSoftware DevelopmentDevelopment ChallengesChallenges • New functionality • Productivity • Portability • Performance, Performance Robustness • Debugging/Test • Security • Time to market ⇒ Software Development is Hard! ⇒ Parallelism is critical for performance, but must be achieved in conjunction with all of these requirements… Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 19 HPC: What we have learned about Parallelism • Large-scale parallelism is possible, and typically comes with scaling of problems and data • Portable expression of parallelism matters • High level program analysis is a critical technology • Working with domain experts is a good idea • Multi-version programming (algorithms and implementations) is a good idea. Autotuning is a good idea • Locality is hard, modularity is hard, data structures are hard, efficiency is hard… • Of course, this list is not exhaustive…. Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 20 HPC… lessons not to learn … • Programmer effort doesn’t matter • Hardware efficiency matters • Low-level programming tools are acceptable • Low-level control is an acceptable path to performance • Horizontal locality / explicit control of communication is critical Move beyond conventional wisdom “parallelism is hard”, based on these lessons. Parallelism can be easy. Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 21 MovingMoving ParallelParallel ProgrammingProgramming ForwardForward Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 22 Spending Moore’s Dividend (Larus) • 30 year retrospective, analyzing Microsoft’s experience •Spent on -- – New Application Features – Higher level programming > Structured programming > Object-oriented > Managed runtimes – Programmer productivity (decreased focus) Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 23 Today, most programmers do not focus on performance Programmer • Productivity: “Quick functionality, adequate Productivity performance” – Matlab, Mathematica, R, SAS, etc. – VisualBasic, PERL, Javascript, Python, Ruby|Rails • Mixed: “Productivity and performance” – Java, C# (Managed languages + rich libraries) • Performance: “Efficiency is critical” (HPC focus) –C++ and STL –C and Fortran Execution Efficiency • How can we enable productivity programmers write 100-fold parallel programs? Parallelism must be accessible to productivity programmers. Parallelism for the Masses “Opportunities and Challenges” ©Intel Corporation 24 Challenge #1: Can we introduce parallelism in the Productivity Layer? • Enable productivity programmers to create large- scale parallelism with modest effort • A simple models of parallelism mated to productivity languages – Data and collection parallelism, determinism, functional/declarative – Parallel Libraries • Generate scalable parallelism for many applications • Exploit with
Load more

Recommended publications
  • QATS001 Agenda
    Overview of Intel® QuickAssist Technology Dr. Nash Palaniswamy Intel Corporation and Guest Speaker Richard Kaufmann HP QATS001 Agenda • Intel® QuickAssist Technology Strategy • Overview of Solutions – Intel® Embedded Processor for 2008 (Tolapai), FSB-FPGA, AAL, etc. • A viewpoint from HP* on Accelerators • Summary 2 Intel® QuickAssist Technology – Comprehensive Approach to Acceleration • Multiple accelerator and attach options with software and ecosystem support • Performance and scalability based on customer needs and priorities Comprehensive Initiative to optimize the use and deployment of accelerators on Intel® architecture platforms. 3 Design Alternatives as Diverse as Application Requirements Accelerator Accelerator Software Design Attach Models Customized Solutions Power Software Maximum Efficiency Scalability Performance 4 Intel® Embedded Processor for 2008 (Tolapai) Single Die integrates - IA 32 based Core @ 600, 1066 and 1200MHz - DDR2 memory controller (MCH) - PCI Express* Technology - Standard IA PC peripherals (ICH) - 3x Gigabit Ethernet MACs - 3x TDM high-speed serial interfaces for 12 T1/E1 or SLIC/CODEC connections - Intel® QuickAssist Integrated Accelerator Vital Statistics - 148 million transistors - 1,088-ball FCBGA w/1.092 mm pitch - 37.5 mm x 37.5 mm package Intel's first integrated x86 processor, chipset and memory controller since 1994's 80386EX 5 Intel® QuickAssist® FPGA Acceleration Platform Source : Pat Gelsinger Keynote Fall IDF 2006 1. Open Ubiquitous Standards Based Approach PCI Express* Gen1, PCI Express* Gen2, Gen 3 in the future 2. Enable third party FSB-FPGA Modules – targeted for Financial Services Industry, Oil and Gas, Life Sciences, Digital Health, etc. FSB-FPGA Modules Targeted 1H08 3. Intel® QuickAssist Technology Accelerator Geneseo – PCI Express* Abstraction Layer (AAL) that seamlessly allows Source : Intel Internal the SW to access acceleration across various technologies.
    [Show full text]
  • System Design for Telecommunication Gateways
    P1: OTE/OTE/SPH P2: OTE FM BLBK307-Bachmutsky August 30, 2010 15:13 Printer Name: Yet to Come SYSTEM DESIGN FOR TELECOMMUNICATION GATEWAYS Alexander Bachmutsky Nokia Siemens Networks, USA A John Wiley and Sons, Ltd., Publication P1: OTE/OTE/SPH P2: OTE FM BLBK307-Bachmutsky August 30, 2010 15:13 Printer Name: Yet to Come P1: OTE/OTE/SPH P2: OTE FM BLBK307-Bachmutsky August 30, 2010 15:13 Printer Name: Yet to Come SYSTEM DESIGN FOR TELECOMMUNICATION GATEWAYS P1: OTE/OTE/SPH P2: OTE FM BLBK307-Bachmutsky August 30, 2010 15:13 Printer Name: Yet to Come P1: OTE/OTE/SPH P2: OTE FM BLBK307-Bachmutsky August 30, 2010 15:13 Printer Name: Yet to Come SYSTEM DESIGN FOR TELECOMMUNICATION GATEWAYS Alexander Bachmutsky Nokia Siemens Networks, USA A John Wiley and Sons, Ltd., Publication P1: OTE/OTE/SPH P2: OTE FM BLBK307-Bachmutsky August 30, 2010 15:13 Printer Name: Yet to Come This edition first published 2011 C 2011 John Wiley & Sons, Ltd Registered office John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, United Kingdom For details of our global editorial offices, for customer services and for information about how to apply for permission to reuse the copyright material in this book please see our website at www.wiley.com. The right of the author to be identified as the author of this work has been asserted in accordance with the Copyright, Designs and Patents Act 1988. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, except as permitted by the UK Copyright, Designs and Patents Act 1988, without the prior permission of the publisher.
    [Show full text]
  • Intel's Core 2 Family
    Intel’s Core 2 family - TOCK lines References Dezső Sima Vers. 1.0 Januar 2019 Contents (1) • 1. Introduction • 2. The Core 2 line • 3. The Nehalem line • 4. The Sandy Bridge line • 5. The Haswell line • 6. The Skylake line • 7. The Kaby Lake line • 8. The Kaby Lake Refresh line • 9. The Coffee Lake line • 10. The Coffee Lake line Refresh Contents (2) • 11. The Cannon Lake line (outlook) • 12. Sunny Cove • 13. References 13. References 12. References (1) [1]: Singhal R., “Next Generation Intel Microarchitecture (Nehalem) Family: Architecture Insight and Power Management, IDF Taipeh, Oct. 2008, http://intel.wingateweb.com/taiwan08/ published/sessions/TPTS001/FA08%20IDFTaipei_TPTS001_100.pdf [2]: Bryant D., “Intel Hitting on All Cylinders,” UBS Conf., Nov. 2007, http://files.shareholder.com/downloads/INTC/0x0x191011/e2b3bcc5-0a37-4d06- aa5a-0c46e8a1a76d/UBSConfNov2007Bryant.pdf [3]: Fisher S., “Technical Overview of the 45 nm Next Generation Intel Core Microarchitecture (Penryn),” IDF 2007, ITPS001, http://isdlibrary.intel-dispatch.com/isd/89/45nm.pdf [4]:Pabst T., The New Athlon Processor: AMD Is Finally Overtaking Intel, Tom's Hardware, August 9, 1999, http://www.tomshardware.com/reviews/athlon-processor,121-2.html [5]: Carmean D., “Inside the Pentium 4 Processor Micro-architecture,” Aug. 2000, http://people.virginia.edu/~zl4j/CS854/pda_s01_cd.pdf [6]: Shimpi A. L. & Clark J., “AMD Opteron 248 vs. Intel Xeon 2.8: 2-way Web Servers go Head to Head,” AnandTech, Dec. 17 2003, http://www.anandtech.com/showdoc.aspx?i=1935&p=1 [7]: Völkel F., “Duel of the Titans: Opteron vs. Xeon : Hammer Time: AMD On The Attack,” Tom’s Hardware, Apr.
    [Show full text]
  • Michael Eisenstadt David Pollock How the United States Benefits from Its
    A WASHINGTON INSTITUTE STRATEGIC REPORT How the United States Benefits from Its Alliance with Israel Michael Eisenstadt David Pollock STRATEGIC REPORT 7 Michael Eisenstadt David Pollock ASSET TEST How the United States Benefits from Its Alliance with Israel STRATEGIC REPORT 7 SEPTEMBER 2012 All rights reserved. Printed in the United States of America. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. © 2012 by The Washington Institute for Near East Policy The Washington Institute for Near East Policy, 1828 L Street NW, Suite 1050, Washington, DC 20036. COVER: Detail from die photo of Intel ‘s Tolapai System on Chip (SoC ). Computer processors developed by Intel’s Israel R&D center account for 40 percent of the company’s revenues worldwide. Contents About the Authors v Acknowledgments vii Executive Summary ix 1 | Introduction 1 2 | The Enduring Strategic Logic 3 3 | Cooperation on Hard Security Issues 10 4 | Cooperation on Soft Security Challenges 30 5 | Future Challenges 51 6 | Conclusion 57 ILLUSTRATIONS Fig. 1a | Arab-U.S. Ties Trend 5 Fig. 1b | Israel-U.S. Ties Trend 5 Fig. 2a | U.S. Exports to Israel (2011) 31 Fig. 2b | U.S. Imports from Israel (2011) 31 Fig. 2c | U.S. Exports to Saudi Arabia (2011) 31 Fig. 2d | U.S. Imports from Saudi Arabia (2011) 31 TABLES Table 1 | Select Israel-Origin Systems in Recent Use by the U.S. Military 18 Table 2 | Select U.S.
    [Show full text]
  • Intel in 1968, Became President and CEO in 1975, Chairman in 1979, Chairman Emeritus in 1997
    [Beginning of recorded material] [Music] [Video] Pat Gelsinger: There is no person on the planet that I would be more pleased to introduce than our next speaker. And as you come to IDF, technology, technologists, great innovation, profound insights, and who better to speak on such topics than Gordon Moore? Gordon co-founded Intel in 1968, became president and CEO in 1975, chairman in 1979, chairman emeritus in 1997. You know, he was the guy who sort of codified what we today call Moore's Law, , this insight that's become not just an insight, but the very nature of our industry's heartbeat and direction. I remember some of my personal interactions with Gordon very early on. And one time we were struggling on the 46th compaction, so this is back when, , we were struggling to make a 1.2 million transistor chip. Myself was leading the design team for that. [Youssef A. El-Mansy] was leading the process technology for it. And we were struggling with this low-yield problem. And were running all sorts of experiments and struggling with trying to figure this out. And Gordon summons me to his office along with Youssef, , on this problem. I felt like I was going and seeing God, right, you know, walk in, the Gordon Moore, right? And Gordon started shelling us with questions. Have you run this experiment? Have you tried that? And so on. And by this point Gordon was not a practicing technologist for quite a number of years, so we felt like we were sort of pacifying the old man, Intel Developers' Forum, 8.18.07, Afternoon Session Page 2 , by answering his questions.
    [Show full text]
  • SMI GPU Roadmap Update
    SMI GPU Roadmap Update October, 2009 Agenda . Company Overview . GPU Roadmap . GPU Technology and Success Story . GPU Selection Guide . GPU Software Driver and Design Tool . Why Choose SMI? About Silicon Motion . Founded in Nov. 1995 . Market Position: A global leader in microcontrollers for NAND flash storage and low-power multimedia devices . Mission: Silicon Motion is a leading fabless semiconductor company that provides universally compatible, high- performance, low-power semiconductor solutions for the multimedia electronics markets. 3 Pacific Rim Operations Support Global Focus Beijing, China Seoul, Korea Yokohama, Japan Shanghai, China Milpitas, CA Jhubei, Taiwan Shenzhen, China Headquarters: Jhubei, Taiwan Other Operations: Seoul (KOR), Milpitas (US), Shenzhen, Shanghai, Beijing (CN), Shin Yokohama (JP), and Taipei (TW) Employees: 600+ (400+ Engineers) Distributors: N. America, Europe, China, Singapore, Taiwan, Korea, Singapore Our Products >>Mobile Storage >>Multimedia SoC >>Mobile Communications • Flash Card Controllers • Portable Multimedia SoC • Mobile TV Tuner IC • Mobile TV SoC • Solid State Drive Controllers • PC Camera Controllers (tuner + demodulator) • USB Flash Drive Controllers • Embedded Graphics • CDMA RF ICs • Embedded Flash Controllers • Electronic Toll Collection System RF ICs • Card Reader Controllers Embedded GPU Roadmap SM107 SM502 SM502 4 MB 8 MB 0 MB •2D Engine •2D Engine Main RISC •Host/PCI interface •Host/PCI interface •4MB Int. SDRAM •8MB Int. SDRAM Interface •1280x1024 •1280x1024 •CRT& DVO •CRT& DVO •I/O Peripherals (limited) •I/O Peripherals •15x15mm BGA •19x19mm BGA •MP •MP SM718 SM718 16 MB 0 MB SM712 SM722 SM750 SM750 •PCI & 16/32b Host I/F 4 MB 8 MB 16 MB 0 MB •2D Engine •16MB Int. DDR •1920x1440 •2D Engine •2D/3D Engine •2D Engine •CRT& Dual-D •PCI interface •PCI/AGP interface •1 lane PCI-E Main X86 •17x17mm BGA •4MB Int.
    [Show full text]
  • Intel® Quickassist Technology Components
    Intel® QuickAssist Technology Components Neal Oliver, PhD Principal Engineer Intel Corporation QATS002 Agenda • Intel® QuickAssist Architecture Overview • Selected Intel® QuickAssist Architecture Components • Intel® Embedded Processor for 2008 (Tolapai) • Hardware Architecture • Software Architecture • Use Cases • Intel® QuickAssist FSB-FPGA Accelerator Platform (FAP) • System Architecture • Accelerator Hardware Module (AHM) • Design Flow • Intel® QuickAssist Technology Accelerator Abstraction Layer (AAL) • AAL services and features • Software Architecture Intel’sSingle responseChip Solutions to customer - VPN/Firewall need for acceleration on2 Intel platforms Intel® QuickAssist Technology – Comprehensive Approach to Acceleration • Multiple accelerator and attach options with software and ecosystem support • Performance and scalability based on customer needs and priorities Intel’s response to customer need to deploy accelerators on Intel® architecture platforms. 3 Intel® Embedded Processor for 2008 (Tolapai) Single Die integrates - IA 32 based Core @ 600, 1066 and 1200MHz - DDR2 memory controller (MCH) - PCI Express* Technology - Standard IA PC peripherals (ICH) - 3x Gigabit Ethernet MACs - 3x TDM high-speed serial interfaces for 12 T1/E1 or SLIC/CODEC connections - Intel® QuickAssist Integrated Accelerator Vital Statistics - 148 Million transistors - 1,088-ball FCBGA w/1.092 mm pitch - 37.5 mm x 37.5 mm package SingleSystem-on-Chip Chip Solutions (SoC) - VPN/Firewall enabling performant, effective4 system solutions Intel® Embedded Processor
    [Show full text]
  • Valpont.Com, a Technology Content Platform Valpont.Com, a Technology Content Platform
    Valpont.com, a Technology Content Platform Valpont.com, a Technology Content Platform Software Development for Embedded Multi-core Systems Valpont.com, a Technology Content Platform This page intentionally left blank Valpont.com, a Technology Content Platform Software Development for Embedded Multi-core Systems A Practical Guide Using Embedded Intel ® Architecture Max Domeika AMSTERDAM • BOSTON • HEIDELBERG • LONDON NEW YORK • OXFORD • PARIS • SAN DIEGO SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO Newnes is an imprint of Elsevier Valpont.com, a Technology Content Platform Cover image by iStockphoto Newnes is an imprint of Elsevier 30 Corporate Drive, Suite 400, Burlington, MA 01803, USA Linacre House, Jordan Hill, Oxford OX2 8DP, UK Copyright © 2008, Elsevier Inc. All rights reserved. Intel® and Pentium® are registered trademarks of Intel Corporation. *Other names and brands may be the property of others. The author is not speaking for Intel Corporation. This book represents the opinions of author. Performance tests and ratings are measured using specifi c computer systems and/or components and refl ect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or software design or confi guration may affect actual performance. Buyers should consult other sources of information to evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products, visit Intel Performance Benchmark Limitations. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of the publisher.
    [Show full text]
  • The Intel X86 Microarchitectures Map Version 3.2
    The Intel x86 Microarchitectures Map Version 3.2 8086 (1978, 3 µm) 80386 (1985, 1.5 to 1 µm) P6 (1995, 0.50 to 0.35 μm) Skylake (2015, 14 nm) NetBurst (2000 , 180 to 130 nm) Series: Alternative Names: iAPX 386, 386, i386 Alternative Names: i686 Alternative Names: SKL (Desktop and Mobile), SKX (Server) (Note : all U and Y processors are MCPs) P5 (1993, 0.80 to 0.35 μm) Alternative Names: Pentium 4, Pentium IV, P4 • 16-bit data bus: Series: Series: Pentium Pro (used in desktops and servers) Series: Alternative Names: Pentium, Series: 8086 (iAPX 86) • Desktop/Server: i386DX Variant: Klamath (1997, 0.35 μm) • Desktop: Desktop 6th Generation Core i5 (i5-6xxx, S-H) 80586, 586, i586 • Desktop: Pentium 4 1.x (except those with a suffix, Willamette, 180 nm), Pentium 4 2.0 (Willamette, 180 • 8-bit data bus: • Desktop lower-performance: i386SX Alternative Names: Pentium II, PII • Desktop higher-performance: Desktop 6th Generation Core i7 (i7-6xxx, S-H), Desktop 7th Generation Core i7 X (i7-7xxxX, X), Desktop 7th Series: nm) 8088 (iAPX 88) • Mobile: i386SL, 80376, i386EX, Series: Pentium II 233/266/300 steppings C0 and C1 (Klamath, used in desktops) Generation Core i9 X (i7-7xxxXE, i7-7xxxX, X), Desktop 9th Generation Core i7 X (i7-9xxxX, X, 14 nm++?), Desktop 9th Generation Core i9 X • Desktop/Server: P5, P54C • Desktop higher-performance: Pentium 4 1.xA (Northwood, 130 nm), Pentium 4 2.x (except 2.0, 2.40A, i386CXSA, i386SXSA, i386CXSB New instructions: Deschutes (1998, 0.25 to 0.18 μm) (i7-9xxxXE, i7-9xxxX, X, 14 nm++?), Xeon W-3175X (W, 14 nm++?)
    [Show full text]
  • Power TECH FOCUS O
    www.elettronica-plus.it COVER STORY Conrad punta sul servizio e potenzia la spedizione in 24 ore Power TECH FOCUS O E Il risveglio delle reti neurali VERTICAL MAGAZINE VERTICAL GIUGNO/LUGLIO 2016 - N° 455 - e 4,50 Mensile di elettronica professionale, componenti, strumentazione e tecnologie Velocità x Spedizione 24h Tekkie = Elettronica In caso di mancato recapito inviare al CMP/CPO di Roserio-Milano per la restituzione al mittente previo pagaamento resi al CMP/CPO di Roserio-Milano per la restituzione al mittente previo In caso di mancato recapito inviare SUM Copertina di MA Conrad Business Supplies N° 455 realizzata GIUGNO/LUGLIO 2016 RY da Franco Tedeschi Accanto ai big, vi sono varie mettente ambito dell’intel- piccole società che operano ligenza artificiale che trova nel settore delle reti neurali potenziali e innumerevoli e di ciò che viene definito applicazioni in un ampio “machine learning”, un pro- TECH-FOCUS spettro di realtà odierne 8 ADVERTISERS 10 WE SPEAK ABOUT 15 EDITORIAL 18 Conrad punta sul servizio e potenzia COVER STORY la spedizione in 24 ore - Massimo Valtorta 22 Memorie prossime venture - Peter Lieberwirth TECH INSIGHT 24 L’evoluzione dei System-on-a-Chip - Andrea Cattania 26 Un tool di progettazione veramente completo - Alessandro Nobile ANALOG/MIXED SIGNAL 28 Come realizzare un amplificatore audio in classe D - Steve Bowling TECH-FOCUS 32 Il risveglio delle reti neurali - Paolo De Vittor 38 La sicurezza delle reti si trasferisce dal dominio software a quello hardware - Ryan Kenny DIGITAL 42 Utilizzo di Sram veloci
    [Show full text]
  • The Intel X86 Microarchitectures Map Version 4.1
    The Intel x86 Microarchitectures Map Version 4.1 8086 (1978, 3 µm) P5 (1993, 0.80 to 0.35 μm) Willamette (2000, 180 nm) Skylake (2015, 14 nm to 14 nm++) 80386 (1985, 1.5 to 1 µm) P6 (1995, 0.50 to 0.35 μm) Alternative Names: Alternative Names: Pentium, Alternative Names: NetBurst, Pentium 4, Pentium IV, P4, , Pentium 4 180 nm Alternative Names: SKL (Desktop and Mobile), SKX (Server) (The Desktop 9th Generation Core processors have the same security fixes as CSL)(All Alternative Names: iAPX 386, 386, i386 Alternative Names: i686 MCS-86 80586, 586, i586 Series: U and Y processors have on-package PCH) Series: Series: Pentium Pro (used in desktops and servers) Series: Series: • Desktop: Pentium 4 1.x (except those with a suffix), Pentium 4 2.0 Series: • Desktop/Server: i386DX Variant: Klamath (1997, 0.35 μm) • 16-bit data bus: • Desktop/Server: P5, P54C • Desktop lower-performance: Celeron 1.x (where x is a single digit between 5-9, except Celeron 1.6 SL7EZ, • Desktop: Desktop 6th Generation Core i5 (i5-6xxx, S-H, 14 nm) • Desktop lower-performance: i386SX Alternative Names: Pentium II, PII 8086 (iAPX 86) • Desktop/Server higher- Willamette-128), Celeron 2.0 SL68F • Desktop higher-performance: Desktop 6th Generation Core i7 (i7-6xxx, S-H , 14 nm), Desktop 7th Generation Core i7 X (i7-7xxxX, X, 14 nm+), • Mobile: i386SL, 80376, i386EX, Series: Pentium II 233/266/300 steppings C0 and C1 (Klamath, used in desktops) • 8-bit data bus: performance: P54CQS, P54CS • Server: Foster (Xeon), Foster-MP (Xeon) Desktop 7th Generation Core i9 X (i9-7xxxXE,
    [Show full text]
  • Pegasus: Coordinated Scheduling for Virtualized Accelerator-Based Systems
    Pegasus: Coordinated Scheduling for Virtualized Accelerator-based Systems Vishakha Gupta Karsten Schwan Niraj Tolia Georgia Institute of Technology Georgia Institute of Technology Maginatics Vanish Talwar Parthasarathy Ranganathan HP Labs HP Labs Abstract higher level programming APIs [19, 28]. Unfortunately, Heterogeneous multi-cores—platforms comprised of technically, this implies that drivers rather than operating both general purpose and accelerator cores—are becom- systems or hypervisors determine how accelerators are ing increasingly common. While applications wish to shared, which restricts scheduling policies and thus, the freely utilize all cores present on such platforms, operat- optimization criteria applied when using such heteroge- ing systems continue to view accelerators as specialized neous systems. devices. The Pegasus system described in this paper uses A driver-based execution model can not only poten- an alternative approach that offers a uniform resource tially hurt utilization, but also make it difficult for appli- usage model for all cores on heterogeneous chip mul- cations and systems to obtain desired benefits from the tiprocessors. Operating at the hypervisor level, its novel combined use of heterogeneous processing units. Con- scheduling methods fairly and efficiently share acceler- sider, for instance, an advanced image processing ser- ators across multiple virtual machines, thereby making vice akin to HP’s Snapfish [32] or Microsoft’s Photo- accelerators into first class schedulable entities of choice Synth [25] applications, but offering additional compu- for many-core applications. Using NVIDIA GPGPUs tational services like complex image enhancement and coupled with x86-based general purpose host cores, a watermarking, hosted in a data center. For such appli- Xen-based implementation of Pegasus demonstrates im- cations, the low latency responses desired by end users proved performance for applications by better managing require the combined processing power of both general combined platform resources.
    [Show full text]