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In‑circuit characterisation of device's impedance for signal integrity analysis
Chang, Richard Weng Yew
2011
Chang, R. W. Y. (2011). In‑circuit characterisation of device's impedance for signal integrity analysis. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/46537 https://doi.org/10.32657/10356/46537
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IN-CIRCUIT CHARACTERISATION OF DEVICE S IMPEDANCE FOR SIGNAL INTEGRITY ANALYSIS
CHANG WENG YEW, RICHARD SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING 2011
IN-CIRCUIT CHARACTERISATION OF DEVICE S IMPEDANCE FOR SIGNAL INTEGRITY ANALYSIS
Chang Weng Yew, Richard
School of Electrical and Electronic Engineering
A thesis submitted to the Nanyang Technological University in fulfillment of the requirement for the degree of Doctor of Philosophy
2011
Statement of Originality
I hereby certify that the content of this thesis is the result of work done by me and has not been submitted for a higher degree to any other University or Institution.
11th November 2011 ______
Date Chang Weng Yew, Richard
Acknowledgments
cknowledgements
The work presented in this thesis has been carried out under the supervision of Dr. See Kye Yak, Associate Professor, School of Electrical and Electronic Engineering, Nanyang Technological University (NTU). I would like to express my most sincere gratitude to him for his invaluable guidance, supervision and technical support throughout this research work. His constant encouragement and patience motivate and inspire me to persevere through the course of my PhD study.
I was fortunate to have the friendly and excellent company of fellow working research colleagues including Mr. Manish Oswal, Ms Soh Wei-Shan, Dr. Chua Eng Kee and Mr. Wang Lin Biao. They are instrumental in helping me in my return to research work in NTU, thanking them for their kind assistance and advice given during the period of my PhD study. I would also like to thank Mr. Tan Hoon Kang, Mr. Wee Seng Khoon and Mdm Chua-Koh Guek Hwa, the technical staff of Electronics Lab II for the laboratory support throughout my research work. I would also like to thank Mr. Kang Meng Fai and Mr. David Robert Neubronner, the technical staff of Integrated System Research Lab for the IT help and office administrative assistance.
I would like to thank DSO National Laboratories for the financial support to pursue my full- time PhD study in NTU to fulfill my dream. Special thanks to Mr. Tan Eng Hwa, former Lab Manager and Dr. Tan Kok Tin, Guided System Division Director, for supporting my scholarship application.
Last but not least, to my family, I like to express my deepest and sincere appreciation to my dear wife, Lay Ling and my three lovely daughters, Alicia, Eleena and Samantha for their kind understanding, tolerance, patient and support through the course of my busy and hectic research work in NTU.
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Summary
ummary
Rapid advances in integrated circuits (ICs) and process technology coupled with surge in consumers expectation for powerful processing capabilities and features dramatically change the way for digital circuit designs. With increasing clock speed and shorter rise time, impedance control for interconnects on the printed circuit board (PCB) to ensure good signal integrity (SI) performance has become a critical factor in high-speed digital design. Besides impedance control of interconnects on PCB, it is also equally important to be equipped with the knowledge of input and output impedances of the devices that will be connected to these interconnects. Any slight impedance mismatch will have an impact on the SI performance of the high-speed digital circuit.
To achieve optimal impedance matching at the digital interfaces, one could only rely closely on the recommended equivalent circuit model of the interface from the manufacturer s datasheet. However, the datasheet is usually suitable for specific application, layout and operating condition. Alternatively, one could utilise circuit simulation together with Input and Output Information Specifications (IBIS) model for input/output (I/O) interface impedance matching, which is straightforward but it provides only an approximate model. For more accurate equivalent interface model, three-dimensional (3D) full-wave modelling tool can be employed but it requires knowledge on the device s internal details, which is often guarded by proprietary issues.
Based on a two-probe inductive coupling approach, the thesis presents a novel in-circuit measurement method to characterise the impedance of any device (either passive or active) under its actual operating condition. With this in-circuit measurement setup, the impedance of a device can be characterised under intended operating conditions with specifics biasing current, voltage and operating frequency. The accurate and complete electrical characteristic extracted enables proper choice of termination component to achieve optimal SI performance in high-speed digital design with confidence.
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List of Tables
Table of Content:
Acknowledgments ...... i Summary ...... ii List of Figures .. v List of Tables ...... vi List of Abbreviation and Acronym ...... vii List of Symbols and Useful constants and Measurement Units ...... vii
1.0 INTRODUCTION 1 1.1 Importance of Signal Integrity in High Speed Digital Design ...... 1 1.1.1 What is Signal Integrity? ...... 1 1.1.2 Industrial Technologies Trend ...... 2 1.1.3 Trend in Signal Integrity ...... 4 1.1.4 Why Consider Signal Integrity? ...... 5 1.1.5 Signal Integrity Challenges ...... 6 1.2 Motivation ...... 8 1.3 Objective and Contributions ...... 10 1.4 Thesis Organization ...... 10
2.0 LITERATURE REVIEW 12 2.1 High-Speed Digital Design Analysis ...... 12 2.1.1 PCB Inter-Layer Vias Design ...... 13 2.1.2 High-speed PCB Interconnects Layout Design ...... 18 2.1.3 Crosstalk of PCB Interconnects ...... 28 2.2 Device Characterization and Modelling ...... 31 2.2.1 Semiconductor Design Model Libraries ...... 31 2.2.2 I/O Buffer Information Specification (IBIS) Model ...... 33 2.2.3 Device Characterization through Measurement ...... 36
3.0 REVIEW OF IMPEDANCE MEASUREMENT 44 3.1 High Frequency Behaviors of Passive Components ...... 44 3.1.1 High Frequency Effects on Resistor Characteristic ...... 45 3.1.2 High Frequency Effects on Inductor Characteristic ...... 46 3.1.3 High Frequency Effects on Capacitor Characteristic ...... 47 3.2 Current Measurement ...... 48 3.2.1 Advantages of Using Current Probe...... 48 3.2.2 Measuring Current Signals ...... 48 3.2.3 Single Probe Measurement Limitation ...... 49 3.3 In-Circuit Measurement using Two Current Probes ...... 50
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List of Tables
3.3.1 High Frequency Current Probe ...... 51 3.3.2 Injecting Current Signals ...... 51 3.3.3 Measurement Setup for Optimum High Frequency Performance ...... 52 3.3.4 Theoretical Background of Two-Probe Measurement ...... 54
4.0 VALIDATION OF TWO-PROBE MEASUREMENT METHOD 61 4.1 In-Circuit Characterization of Passive Components ...... 62 4.2 Measurement Setup for Validation ...... 63 4.3 Equivalent Circuit of the Test Setup ...... 65 4.4 Resistor Measurement Results ...... 70 4.4.1 Nominal Impedance Measurement...... 70 4.4.2 Full Frequency Range Impedance Response ...... 71 4.4.3 Impact of DC Biasing on the Impedance Response ...... 73 4.5 Inductor Measurement Results ...... 74 4.5.1 Nominal Inductance Measurement ...... 74 4.5.2 Full Frequency Range Impedance Response ...... 75 4.5.3 Impact of DC Biasing on the Impedance Response of the Inductor ... 76
5.0 MEASUREMENT OF ACTIVE DEVICE IMPEDANCE FOR SI ANALYSIS 78 5.1 Transmission Line, Reflections and Impedance Matching ...... 78 5.1.1 Transmission line ...... 78 5.1.2 Transient Reflections...... 79 5.1.3 Lattice Bounce Diagram ...... 82 5.1.4 Impedance Matching Technique ...... 84 5.1.5 Challenges in Source Matching...... 89 5.2 Measurement of Output Impedance of Clock Driver ...... 90 5.3 Case Study on Series Termination Selection ...... 92 5.4 Clock Driver Circuit for Case Study ...... 93 5.5 Extraction of Clock Driver Output Impedance ...... 96 5.6 Clock Driver Output Impedance Measurement Results ...... 99 5.7 Validation with Simulation Results ...... 106 5.8 Experimental Validation with Measurement Results ...... 108 5.9 Impact of Series Termination on Rise-time and Emission ...... 110
6.0 CONCLUSION 112 6.1 Major Contribution of the Thesis ...... 112 6.2 Limitations and Recommended Future Research Work ...... 114
Author s Publications ...... 116 Bibliography ...... 118 Author s Biography ...... 128 Appendix A: List of EDA Vendors and Tools ...... 129
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List of Tables
List of Figures:
Figure 1 : Trend in process technology ...... 2 Figure 2 : Trend in cycle time reduction: processor/speed/gate density trend ...... 3 Figure 3 : Design cost structure relationship ...... 5 Figure 4 : High speed digital signal integrity challenges ...... 7 Figure 5 : (a) Typical through hole via structure and (b) common types of vias ...... 13 Figure 6 : Via diameter analysis (a) via structure and parameter setup, (b) TDR response, (c) S21 insertion loss response and (d) S11 reflection loss response [21] ...... 14 Figure 7 : Via height analysis (a) via structure and parameter setup, (b) TDR response, (c) S21 insertion loss response and (d) S11 reflection loss response [21] ...... 15
Figure 8 : S21 improvement for via with and without stub [21] ...... 16
Figure 9 : Improved S21 performance by back drilling (from Sanmina-Sci) [111] ...... 16 Figure 10 : Case study on via effect on SI (a) test structure, (b) TDR response, (c) S11 reflection loss and (d) S21 insertion loss response. [21] ...... 17 Figure 11 : Example of industry impedance solver and layout stackup ...... 18 Figure 12 : TDR impedance measurement of a PCB trace using Agilent TDR system .... 19 Figure 13 : AC resistive losses in the cross sectional view of the conductor wire [39] .... 20 Figure 14 : Cross sectional illustration of a typical PCB surface roughness [39] ...... 21 Figure 15 : Loss tangent of some common substrate material [41) ...... 22 Figure 16 : Typical trace bend structures configurations ...... 23 Figure 17 : Effects of TDR response of various bend structures ...... 24 Figure 18 : Surface current simulation plot (a) right angle (b) round bend ...... 24 Figure 19 : Near-Field emission plot (a) right angle bend (b) round bend ...... 24 Figure 20 : Two conductors microstrip interconnects over common return plane ...... 25 Figure 21 : Interconnects transverse over different return planes ...... 26 Figure 22 : Surface current plot for (a) without and (b) with one ground return via design ...... 26 Figure 23 : Ground return via design (a) 4 ground vias and (b) single ground via ...... 27 Figure 24 : TDR response of one ground return via design configuration ...... 27
Figure 25 : S21 response of one ground return via design configuration ...... 27 Figure 26 : Microstrip FR-4 test structure for crosstalk simulation and measurement (a) electric and magnetic fields and (b) equivalent circuits of two parallel lines . 28 Figure 27 : Microstrip FR-4 test structure for crosstalk simulation and measurement ..... 29 Figure 28 : Crosstalk validation (a) simulation results and (b) measurements ...... 29 Figure 29 : Overall effects of trace separation for microstrip (a) NEXT and (b) FEXT ... 30 Figure 30 : Overall effects of trace separation for microstrip (a) NEXT and (b) FEXT ... 30 Figure 31 : Typical IBIS model, input and output structure ...... 34 Figure 32 : Measurement techniques and frequency range[76] ...... 36
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List of Tables
Figure 33 : Bridge measurement method ...... 37 Figure 34 : I-V measurement method ...... 38 Figure 35 : Resonant or roll-off measurement method ...... 39 Figure 36 : Auto balancing bridge measurement method ...... 40 Figure 37 : Network analysis measurement method and sensitivity comparison [76] ...... 41 Figure 38 : RF I-V measurement method [76] ...... 42 Figure 39 : Equivalent circuit of a non ideal resistor [80] ...... 45 Figure 40 : Characteristic response (a) a 500 thin-film resistor and (b) metal-film with difference values [81] ...... 45 Figure 41 : Equivalent circuit of a non ideal inductor [80,81] ...... 46 Figure 42 : Characteristic response of an inductor [81]...... 46 Figure 43 : Equivalent circuit of a non ideal capacitor [80] ...... 47 Figure 44 : Characteristic response of a capacitor [81] ...... 47 Figure 45 : CT6 probe frequency response [78] ...... 52 Figure 46 : CT6 positioning for HF application [79]...... 53 Figure 47 : (a) Basic test setup; (b) equivalent circuit of two probes measurement ...... 54 Figure 48 : Equivalent circuit of the injection probe ...... 55 Figure 49 : Reflected equivalent circuit of injection probe in CUT loop ...... 56 Figure 50 : Final reflected equivalent circuit of the two probes measurement setup ...... 57 Figure 51 : Measurement setup using the two inductive coupling probes: (a) schematic circuit (b) fabricated test jig ...... 64 Figure 52 : Equivalent circuit for the in-circuit measurement setup ...... 65 Figure 53 : Simplified equivalent circuit for the measurement setup ...... 67
Figure 54 : Magnitude of Zsetup versus frequency ...... 68 Figure 55 : Magnitude of k versus frequency ...... 69 Figure 56 : Impedance profile characterisation validation (a) propose two probe test setup and (b) instrumentation setup using Impedance analyzer ...... 71 Figure 57 : Comparison of impedance versus frequency (a) 30 and (b) 220 resistor 72 Figure 58 : Impedance versus frequency of a 220 resistor under various biasing conditions (0 mA, 5 mA and 15 mA) ...... 73 Figure 59 : Comparison of impedance versus frequency of a 2.2 H inductor ...... 75 Figure 60 : Impedance versus frequency of an inductor under various biasing conditions (0 mA, 5 mA and 15 mA): (a) 250 H (b) 47 H ...... 77 Figure 61 : A 10MHz clock signal measured at a mismatch transmission trace...... 79 Figure 62 : Typical signal source, driving a receiver through a transmission line ...... 80 Figure 63 : Lattice diagram illustrating the effects of signal multiple reflections ...... 82 Figure 64 : Simulated signal at the receiver at the far end of the transmission load side using 2ns rise-time without termination ...... 83 Figure 65 : Simulated signal at the receiver at the far end of the transmission load side using 0.1ns rise-time without termination...... 83
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List of Tables
Figure 66 : Simulated signal at the receiver at the far end of the transmission load side using 0.1ns rise-time with source matched termination...... 84 Figure 67 : Example of an end termination circuit ...... 85 Figure 68 : Example of a source termination circuit ...... 87 Figure 69 : TDR impedance measurement using Tektronix DSA8200 with P8018 TDR probe ...... 91 Figure 70 : (a) Schematic of the application clock driver circuit (b) PCB layout ...... 93 Figure 71 : Waveform at the receiver end of the transmission line with CDCV304PW ... 94 Figure 72 : Waveform at the receiver end of the transmission line with CDCVF2505PW95 Figure 73 : Measurement setup to extract the output impedance of the clock driver ...... 96 Figure 74 : Simplified equivalent circuit of the two probe measurement setup ...... 97 Figure 75 : Schematic of the clock circuit test prototype ...... 99 Figure 76 : PCB layout of circuit under test for CDCV304PW ...... 100 Figure 77 : Actual two probe measurement test setup with device 1: CDCV304PW. .... 100 Figure 78 : Pre-calibration setup to characterise the clock driver device 1: CDCV304PW...... 101
Figure 79 : Magnitude of Zsetup versus frequency ...... 102 Figure 80 : Magnitude of k versus frequency ...... 102 Figure 81 : Measured clock driver output impedance for CDCV304PW (a) Static high, Static low and 1MHz and (b) Dynamic, 10MHz ...... 104 Figure 82 : Measured clock driver output impedance (device 2: CDCVF2505) ...... 105 Figure 83 : CDCVF2505 clock driver output structure and impedance [116] ...... 105 Figure 84 : CST-DS IBIS transient simulation setup ...... 106
Figure 85 : Parametric sweep on Rs simulation (a) CDCV304 and (b) CDCVF2505 ..... 107 Figure 86 : Measured clock waveform at far-end of microstrip line with CDCV304PW108 Figure 87 : Measured clock waveform at far-end of microstrip line with CDCVF2505 . 109 Figure 88 : CST-DS IBIS circuit simulation setup with CDCV304PV clock driver ...... 110
Figure 89 : Simulation result (a) Rs=15 (b) Rs=24 (c) Rs=50 (d) receive signal . 111
List of Tables:
Table 1 : Comparison of measured impedance of resistors at 1 MHz ...... 70 Table 2 : Comparison of measured impedance of inductors at 2MHz* ...... 74
Page vii
List of Abbreviations and Acronyms
List of Abbreviations:
BW Bandwidth BGA Ball Grid Array BER Bit Error Rate CAE Computer Aided Engineering CE Compromising emanations CISPR International Special Committee on Radio Interference CM Common Mode COTs Commercial Off-the-Shelf CST Computer Simulation Technologies CUT Circuit Under Test DUT Device Under Test DM Differential Mode EDA Electronic Design Automation EM Electromagnetic EMI Electromagnetic Interference EMC Electromagnetic Compatibility ESR Equivalent Series Resistance ESL Equivalent Series Inductance FCC Federal Communications Commissions, USA FDTD Finite Difference Time Domain FEM Finite Element Method FEXT Far End Crosstalk FFT Fast Fourier Transform IO Input/Output IC Integrated Circuit IBIS Input/Output Buffer Information Specification NEXT Near End Crosstalk OATS Open Area Test Site PCB Printed Circuit Board PUL Per Unit Length RF Radio Frequency RE Radiated Emission 2D Two-Dimensional 3D Three-Dimensional SPICE Simulation Program with Integrated Circuit Emphasis VNA Vector Network Analyzer SA Spectrum Analyzer SMT Surface Mount Technology SMD Surface Mount Device SI Signal Integrity TBD To Be Defined/Determined TDR Time Domain Reflectormeter
Page viii
List of Symbols and Useful Constants
List of Symbols
Angular frequency Resistance ohms Q Quality factor or Q-factor fres Resonant frequency
Rs Series Resistance
Zx Impedance of x
Zo Characteristic Impedance
ZDUT Impedance of Device Under Test Mx Mutual inductances of circuit x
XL Inductive Reactance
Xc Capacitive Reactance r Relative Permittivity of material = 4 (for typical FR-4 unless otherwise specified) -12 o Permittivity of free space = 8.854 x 10 F/m -7 o Permeability of free space = 4 x 10 H/m c Speed of electromagnetic waves in free space 3 x 108 m/s
List of Measurement units mA Current milli Ampere mV Voltage milli Volt H Inductance micro Henry nH Inductance nano Henry F Capacitance micro Farad pF Capacitance pico Farad k Resistance kilo ohms mm Length milli meter m Length micro meter or micron ns Time nano second ps Time pico second GHz Frequency Giga-Hertz MHz Frequency Mega-Hertz kHz Frequency kilo-Hertz
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CHAPTER 1: INTRODUCTION
hapter 1
1.0 INTRODUCTION
1.1 Importance of Signal Integrity in High Speed Digital Design
1.1.1 What is Signal Integrity?
Signal Integrity [1, 2] is a high-speed design practice that ensures the transmitted signals are received correctly at the receiver. In physical design, it is about meeting voltage and timing specifications to prevent circuit failure and intermittent errors.
Signal Integrity is a field of study involving not only high-speed digital design but also analogue design with operating frequency overlapping into the radio frequency (RF) design arena. It is about signal waveform quality, signal coupling, power distribution network and electromagnetic interference (EMI) compliance to ensure proper functioning of the high-speed design.
Quote from Dr. Howard Johnson, a leading expert on signal integrity:
"Signal Integrity is not just a "nice to know" subject, it is a deterministic, predictable field of study, a "hard science" so as to maximize the performance and minimize the cost of interconnection technology used in high-speed digital designs. It s all about how to build really fast digital hardware that really works.
.
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CHAPTER 1: INTRODUCTION
1.1.2 Industrial Technologies Trend Just in the last decade, the data rates and device s speed have already pushed the digital design to a new era into the RF arena. On-chip speed is now commonly over 500 MHz and board buses speed including the onboard interface signals are well above 500 MHz into the GHz range. These changes can be seen in the trend presented in Fig. 1.
W65C02 1MHz (>4um*) Updated on FY2008 Z8 MCU 1MHz (>4um*) Trend in Process Technology 5.0 6809,1MHz (>4um) Intel QX9775,3.2Ghz (45nm) 40,000 transistors Intel E8500, 3.16GHz, (45nm) IBM Power6 4.7GHz, (65nm) 4.5 STI Cell 4.0Ghz (65nm) 8088 5MHz (>4um) IBM/MS Xenon, 3.5GHz (65nm) 29,000 transistors *Freescale G5 e700 87xx, 3.0Ghz (45nm) 4.0 AMD Opteron64 5200 2.7GHz (65nm)
Intel P4,3.4Ghz (65nm) 68000 10MHz (3.5um) IBM Power5 2.0GHz, (90nm) 3.5 70,000 transistors AMD Opteron64 852 2.6Ghz (90nm) Freescale G5 e600 7448, 1.7Ghz (90nm) 80286 8MHz (3um)
) AD BF533 750MHz (90nm) 134,000 transistors n TI C6455 1.0GHz (90nm)
o 3.0 r Intel P4,1.6Ghz (0.13u) c i 80386, 10MHz (2.5um) AMD Sempron 1.6Ghz (0.13u)
m 275,000 transistor
( 68020 12MHz (2.5um) Freescale MPC7455 1.0GHz (0.13u) 2.5 Marvel/Intel XScale ARMv5 PXA210 (0.18u) s Z8S180, 10MHz (2.5um)
s TI:C6455 750Mhz (0.13u) e R2000 8MHz (2.0um) AD BF533 600MHz (0.13u) c 110,000 transistors o Mips R14000 600MHz (0.13u)
r 2.0
P ARM2 12MHz (2.0um) 80486,20MHz Intel P3-700Mhz (0.13u) 30,000 transistors (1.5um) TI:C67x (0.18u) 1.5 AD:TS201 (0.18u) R3000 20MHz(1.2um) W65C02 12MHz Freescale 7410 (0.18u) (1.2um) MC68040,25MHz (0.8um) TI:C62x (0.25u) 1.0 AD:21160 (0.25u) R4000,100MHz (0.8um) R12000 (0.25u) R4600,133MHz (0.64u) 32nm ?? 0.5 MC68060 50Mhz (0.6u) AD21060 40MHz(0.5u) DEC StrongARM SA-110 200MHz(0.5u) AD21065 (0.35u)
1980 85 1990 95 2000 05 2010
Figure 1 : Trend in process technology
Figure information are compiled based on data from literature survey, various suppliers and manufacturers websites and data sheets.
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CHAPTER 1: INTRODUCTION
Fig. 2 further illustrates the progress of some of the commonly used products in the market. It shows the continuing trends in the following three areas that affect high- speed circuit design:
Reduction in cycle time; Increase in processor operating speed; and Increase in gate density.
Updated on FY2008 Processors/Speed/Gate Density Trend
80386 -16Mhz 275K Transistors Intel-QX9775, Quadcore, 3.2GHz, 2B transistors, 1600MHz FSB, (45nm) Intel E8500, dualcore, 3.16GHz, 1333MHz FSB, (45nm) 60 IBM Power6, multicore 4.7GHz, 800M transistor, (65nm) Sony/IBM/Toshiba STI Multicore Cell, 4GHz, 230M transistor, (90nm) IBM/MS xenon/XCPU 3 PPC core, 165M transistor, 3.5GHz, 65nm AMD Opteron64:8350, Quadcore, 2Ghz, 1600MHz bus. 65nm AMD Athlon64:5200, Dualcore, 2.7GHz, 2000MHz bus, 65nm PowerPC dual e600core, MPC8641D, 1.5GHz, 1023 FC-PBGA, 90nm PowerPC G4 e700 MPC87xx, 3GHz, 45nm**
Pentium4-6xx/6x1,3.4Ghz, 775FC-LGA (90/65nm) AMD Opteron64:852, 2.6Ghz (90nm) IBM Power5, dualcore 2GHz, 183M transistor, 575CBGA (90nm) PowerPC G5 e600, MPC7448, 1.7Ghz, 360LGA (90nm) PowerPC dual e500core, MPC8572E, 1.5GHz, 1023 FC-PBGA (90nm) Analog Blackfin BF533KBC750, 750MHz, 160CSPBGA (90nm) Analog SHarc ADSP21367KBPZ, 400MHz, 256 PBGA (90nm) TI:TMS320C6455 1GHz, 697FCGBA (90nm)
40 Pentium4,1.6Ghz, FC-478PGA,130nm IBM Power4 970FX, 1.5GHz 58M transistor, 90nm )
s AMD Sempron 1.6Ghz,130nm
n 486 -33Mhz PowerPC G4 e600, MPC7455 1G,130nm ( 1200K Transistors Analog Blackfin BF533, 600Mhz, 130nm e R3000 - 40MHz
m 110K transistor (1.2um)
i Pentium3 -700/850Mhz, 130nm
T 30 Dec-Alpha - 750Mhz Ti:TMS320C6415LZ7, 720Mhz, 532BGA, 130nm e l Analog TS201- 500Mhz, 576PBGA,180nm c Freescale MPC7410 - 500Mhz,180nm y MIPS R16000, 700MHz, 110nm C
Pentium1 -166Mhz Analog 21160 - 80Mhz, 10M Transistors (0.25um) 20 MIPS R12000 270MHz, 6.9M Transistors (0.25um)
Pentium-66/90Mhz 3000K Transistors R4600 133MHz 3700K Transitors (0.64um) 10
5 2.5
86 90 94 98 00 02 05 07
Figure 2 : Trend in cycle time reduction: processor/speed/gate density trend
Figure information are compiled based on data from literature survey, various suppliers and manufacturers websites and data sheets.
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CHAPTER 1: INTRODUCTION
1.1.3 Trend in Signal Integrity Signal Integrity (SI) was almost none existence even during the late 80 s as device operating speeds were in the order of 10-20MHz. Entering the late 90 s, device operating speeds were increasing faster than the designer expected and problems of SI began to surface, resulting in signal degradation and even malfunctioning of the circuits. These design challenges and problems related to SI will be discussed in greater details in section 1.1.5. The topic of SI [8, 9] that was once considered good to have, now has been brought back to the front stage and more recently has become one of the most important design issues in the high-speed digital design. A major consideration for all product designers for high-speed digital devices which were once available to the high-end users but now abundantly found in most consumer electronics. The historical development of the device technology and SI design methodologies are briefly summarised as follows:
70 s: Introduction of 7400 class of TTL devices, Bipolar and CMOS and ECL combinational and asynchronous design, operating in several MHz with 5 ns edge rate. Practically, there was no SI issue.
80 s: Introduction of high-speed CMOS and open drain buses, operating speeds at 10 MHz with 2-3 ns edge rate. SI began to surface for long printed circuit interconnects.
90 s: SSTL, AGTL, open collector bus, low voltage devices with edge rate <1 ns were introduced. High-speed differential signalling and synchronous design emerged. Advanced PC s (486 66MHz, 200 MHz and 350 MHz) with affordable prices were available. IBIS was introduced and well accepted. Extensive circuit timing simulation was necessary.
00 s: GHz clock operation with edge rate <500 ps. High-speed serial interface has taken over parallel bus. USB2.0, SATA, PCI express, Gbps Ethernet and SRIO emerge. SI has become a necessity in digital design with extensive simulation using 2.5D/3D field solvers together with comprehensive TDR and VNA measurements for SI analysis, impedance control and extensive termination techniques to minimise reflection and EMI.
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CHAPTER 1: INTRODUCTION
1.1.4 Why Consider Signal Integrity? Fig. 3 gives a clear illustration of the relationship between various design phases and availability of solution techniques, investment cost and cost of rectification due to failure. It clearly shows that as design requirement, complexity and speed increases, and to minimise the cost of product, the optimum choice has shifted down to the design phase over the years. Fixing problems in the production phase is no longer acceptable as it is extremely costly to rectify, less effective and very often no solution exists except to re-design, which causes delay in product launch and significant increase in product development cost. Hence, addressing SI too late at the design phase will incur significant product development cost.
Relative Relative Multiple Multiple Times Times
100 100 d e n n u
a o ti d t e a n l c t s fi s o b i
t i o o
a c C t c l e e i a r
t R
a 10 10 c u i n l v f i i e a t a c m F s t e e s o R u t e f q v i o n n
I 5 5 t h Tec s c hniq ues o e Inv and est C T 2 men 2 t Cost 1 1
Prototype Pre Design Testing Production Phase Phase Phase
Figure 3 : Design cost structure relationship
Was derived with Information taken from (1)Edward K.Chan, Mauro Lai, Myoung Hoon Choi, Woong Hwan Ryu, Intel Corps Concurrent Analysis of Signal-Power Integrity and EMC for high Speed Signaling systems , EMC 2007, (2) Intel Higher Education, class1 by Richard Mellitz Signal Integrity Introduction as well as (3) from author s company past data
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CHAPTER 1: INTRODUCTION
1.1.5 Signal Integrity Challenges The continuous rapid advancement in technologies coupled with an increasing demands in high-tech consumer products that are powerful, compact and cost effective for the consumers; has a direct impact on the design that challenges the ability to deliver products faster, better and reliable. This translates to a very challenging board design requirement, which includes:
Compact and complex board layout requirement; Accurate modelling and simulation to ensure one time success cycle; Advance SI design platform for overall performance analysis; and Accurate high-speed measurement and design validation.
SI issues occur whenever the signal becomes distorted or the signal to noise ratio starts to degrade. As the operating frequency increases, non-ideal effects of PCB traces cannot be ignored. Some of the challenges faces by designers include:
Rise time degradation, inter-symbol interference and collapse of eye pattern. Electromagnetic coupling, crosstalk and EMI radiation effects. Degradation of signal performance due to impedance discontinuities from via, connectors and even signal traces and terminations.
With ever-increasing device speeds, we have reached a point where we must change the way digital products is designed. High-speed design considerations such as issues mentioned above have become highly challenging tasks. Advance SI analysis techniques and tools coupled with in-depth design modelling and simulation to analyse the effects accurately has become a necessity to ensure good design success rate within the tight design schedule. Problems in high-speed digital design are very complex, as shown in Fig. 4.
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CHAPTER 1: INTRODUCTION
Ground Return Effect Analysis Via Design and Analysis B C
Trace Bend Effect Analysis P Bend 1 Bend 3 Device Receiver PCB Routing Effects Signal Analysis: VNA, TDR, Eye Pattern and Jitter Analyses (Skew) on SI Device Driver High Speed Digital I nterface PCB Modeling and Analysis
IC Packaging Crosstalk and SI Analyses
PCB I nterconnect Structure Extractor
Figure 4 : High speed digital signal integrity challenges
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CHAPTER 1: INTRODUCTION
1.2 Motivation
Most high-speed design engineers rely heavily on design guidelines given in the so called well-established standards that were passed down from experienced engineers. These guidelines are usually based upon sound engineering judgments, past experiences and general rules of thumb with little rigorous analyses supporting them. These techniques worked in the past as clock speeds were relatively low and timing margins were large but no longer sufficient and suitable in today s high-speed design.
With the trends of increasing operating frequency, edge rate and PCB packing density, much research work [1-5] has been carried out in the area of SI. Extensive work has been reported in literature on the interconnect-related aspects, such as mismatches due to discontinuities in inter-layer transitions, interconnects modelling and non-ideal ground effect. Due to the demands in SI analyses, advanced EDA and EM solvers have also been developed in the industries for examples; Cadence, Ansoft, Agilent EEsof, CST, just to name a few. A comprehensive list can be found in Appendix A. Besides interconnects, the information on device s input and output impedance are also crucial for SI design. Some work has been reported on the device s input and output interface impedances [82-89] which will be discussed in the literature review in section 3.3. In order to accurately and confidently design high- speed circuit to meet stringent SI requirement for optimised performance. The following key parameters are to be considered in SI design and analysis:
Access to accurate information of IC s output Impedance; Selection of appropriate termination for impedance matching; Accurate design of PCB interconnects for impedance control; and Overall design evaluation platform for performance analysis.
A lot of research work has been carried out in interconnect designs and very little has been reported on the IC s output impedance extraction. Hence, the focus of this thesis will be on the technique to extract the output impedance information of a device for SI design purposes. Off-circuit measurement is commonly adopted by manufacturers
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CHAPTER 1: INTRODUCTION
to characterize the impedance behaviour of a passive component for a specific frequency range. The measured impedance serves well for most design purposes. However, it is not suitable for passive components that exhibit non-linear behaviours (e.g. inductors with ferrite cores) and active components where their impedance behaviours vary due to factors such as biasing condition and load current.
With the constraints of off-circuit measurement, the motivation of this thesis is to develop and validate an in-circuit measurement technique that allows the extraction of a device s output impedance characteristic over a wide frequency range under its intended operating conditions. The extracted impedance information allows the designer to optimise SI performance through proper selection of termination components for impedance matching purposes, which is crucial in high-speed digital design. In-circuit measurement emulates the actual operating condition of the active device and allows the output impedance of the device be extracted with confidence. The proposed two-probe in-circuit measurement approach with careful calibration process to eliminate measurement setup error has demonstrated its accuracy to extract in-circuit impedance up to the GHz frequency range.
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1.3 Objective and Contributions
The main objective of this thesis is to explore an in-circuit measurement method to extract a device s impedance with reasonable accuracy for SI design purposes. A two current probes measurement technique is proposed so that it allows in-circuit measurement of a device s impedance over a wide frequency range up to 1 GHz. The proposed measurement approach has been first validated in the characterization of passive components up to 1 GHz under in-circuit operation. Then the technique is extended to the characterisation of output impedance of an active high-speed clock driver. The results of the output impedance information extracted have been shown to be accurate up to 1 GHz. Finally, these results obtained have been found to be useful with a practical high-speed clock circuit design example.
1.4 Thesis Organization
This chapter gives an overview of SI and the relevant background. The motivation, focus and objective of the thesis are also described. The remaining chapters of the thesis are organised as follows:
Chapter 2 provides a comprehensive literature review of SI related topics such as high-speed digital design analysis, EM field solver and EDA tools, methodology in SI solution as well as the importance of impedance control and interconnects design. It also covers a review of existing device characterisation, modelling tools and measurement instrumentation for SI performance analysis.
Chapter 3 reviews the fundamentals of impedance measurement and describes the theoretical background of single current probe measurement technique. The two current probes in-circuit measurement technique is proposed and the pre-measurement procedure to eliminate possible error due to the measurement setup is described.
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CHAPTER 1: INTRODUCTION
Chapter 4 validates the proposed two current probes measurement approach described in Chapter 3. Using passive components such as resistors and inductors under specific biasing conditions as test cases, the measured results using the proposed approach are compared with those obtained from impedance analyser. The ability of the proposed approached to detect the effects of biasing current on the impedance characteristic of the inductors are also demonstrated.
Chapter 5 extends the proposed two current probes approach to measure the output impedance of active devices. The high-speed clock drivers are used as test cases to demonstrate how their output impedances under actual operating conditions are extracted. The extracted impedance is then used for the validation and analysis on proper selection of series termination resistor to achieve optimised SI, rise-time and EMI emission performances.
Chapter 6 concludes the contributions of the thesis and addresses the limitation of the proposed measurement technique. Finally, some possible future work that is worth exploring is recommended.
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CHAPTER 2: LITERATURE REVIEW
hapter 2
2.0 LITERATURE REVIEW
As operating speed increases, the electronic system s electrical performance is no longer determined only by the ICs but also influenced significantly by metal interconnects on the PCB where these ICs are mounted. As timing budget reduces because of higher operating speed, it increases the timing uncertainty of the digital signal as it arrives at the receiving end of the interconnecting trace. Hence, transmission line effects and signal quality due to IC-interconnect interface that could be neglected in the past can no longer be ignored and must be accounted for in high- speed digital design. In order to predict high frequency effects with good accuracy, fine details of interconnects layouts have to be properly modelled so that the impedance of interconnects, IC s output impedance and the terminations can be well characterised for impedance matching to ensure optimised SI performance.
2.1 High-Speed Digital Design Analysis
In today s high-speed digital design, designers are resorting to using sophisticated modelling tools, such as 3D full-wave EM field solvers to accurately model, simulate and analyze the electrical performance of the signal propagating on interconnect structures. In the last decade, there has been extensive research work in high-speed digital designs, such as via design and modelling, PCB trace layout design and consideration, ground return vias and crosstalk analysis, etc. An overview of the interconnect-related research will be summarised in this section.
3D refers to a 3 dimensional geometry based classification of Electromagnetic field solvers which are specialized software that solve (a subset of) Maxwell s equations directly.
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2.1.1 PCB Inter-Layer Vias Design In high-speed digital design, every slightest discontinuity on the board has to be considered carefully, especially the vias, which are abundantly used in digital design. With signal rise time reduces, impedance discontinuity due to via results in signal reflections and hence, deterioration of SI and system performance. Therefore, the effect of via in high-speed PCB design poises tremendous challenges to the designer and can no longer be ignored. The usual design practices using rules of thumb or past parameters setting are no longer sufficient. Instead a clear understanding of the impact of the mechanical design of a via on the SI performance is important.
A typical via structure is shown in Fig. 5(a) and the various common types of via used in PCB design are shown in Fig. 5(b).
Through Hole Via Blind Via Top Micro-Via
Buried Via Blind Via Bottom (a) (b)
Figure 5 : (a) Typical through hole via structure and (b) common types of vias
There has been extensive research in the electrical model extractions of via structures [10-13], effects of via transition performance analysis and characterisation [14-18], advanced via structure for high-speed applications [19] and even impedance controlled via design [20]. Through hole vias are by far is still and will continue to be the most commonly used in the industry simply because of its ease of manufacturing and low-cost. Looking at the via structure, clearly the via diameter, via height and via stub in a through hole via are crucial parameters of via design [21].
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a) Effects of Via Diameter Variation PCB designers choose via diameter based on suppliers/manufacturers preferred recommendation, which is determined by their confidence and process capability and often with high reliability and high yield. This can range conservatively from 0.1 - 0.9 mm as indicated in Fig. 6(a). It is found that for practical high-speed design, impedance variation should be kept within 10% tolerance. For 50 characteristic impedance, the tolerance will be 5 . Fig. 6(b) shows that via
diameter should not be larger than 0.3 mm so as to yield an insertion loss (S21) of
less than 0.5 dB and a reflection loss (S11) of at least 10 dB, as shown in Fig. 6(c) and Fig. 6(d), respectively.
(a) (b)
(c) (d)
Figure 6 : Via diameter analysis (a) via structure and parameter setup, (b) TDR response, (c) S21 insertion loss response and (d) S11 reflection loss response [21]
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b) Effects of Via Height Variation Height is another primary factor that influences the inductance of a via. Depending on the design complexity, the number of layers of the PCB varies, and hence the overall PCB thickness. The height of the through hole via is determined by the overall thickness of the PCB. Typical high-speed PCB thickness ranges from 1.0 mm to 1.8 mm. For more complex designs and military applications, the PCB thickness can go above 3 mm.
(a) (b)
(c) (d)
Figure 7 : Via height analysis (a) via structure and parameter setup, (b) TDR response, (c) S21 insertion loss response and (d) S11 reflection loss response [21]
From the simulation results shown in Fig. 7, the thicker the board (the longer the via height), the higher the impedance variation during signal transition and leading to higher insertion loss and lower reflection loss. For optimal performance, via height should be kept within 1.5 mm in order to keep impedance variation within
10% tolerance. This would yield an insertion loss (S21) of less than 0.5 dB and
reflection loss (S11) greater than 10 dB.
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c) Effects of Excess Via Stub In high-speed board design utilizing through hole vias, when a signal moves from a top layer to an internal strip line structure, a dangling or excess via stub is created as shown in Fig. 8. Depending of the signal speed and stub length, the signal performance may be compromised. The designers have to decide tradeoffs between cost (using blind via) and performance.
Figure 8 : S21 improvement for via with and without stub [21]
Fig. 8 shows the insertion loss (S21) of the via with stub length varying from 0.5 to 3 mm. The capacitance resulted from the excess via stub causes a resonance with the via inductance. The longer the excess stub results in larger capacitance and hence, leads to a lower resonant frequency. Such resonance is undesirable as it increases the insertion loss significantly near the resonant frequency. Typical PCB
thickness or via height less than 2 mm will allows an operation bandwidth (S21 < 3 dB) in excess of 10 GHz. Fig. 9 shows an illustration of using buried via by back
drilling and the improvement in S21.
Figure 9 : Improved S21 performance by back drilling (from Sanmina-Sci) [111]
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d) Effects of Vias Design on SI Performance To demonstrate the effects of well-designed vias against a typical via design, a 60
mm trace transits between a 4 layer FR-4 PCB ( r = 4, Trace width = 6mil, 50 ) using two different sets of vias design parameters was studied. Set A has a via height of 1.3 mm and a via diameter of 0.2 mm while Set B has a via height of 2.8 mm and a via diameter of 0.5 mm.
(a) (b)
(c) (d)
Figure 10 : Case study on via effect on SI (a) test structure, (b) TDR response, (c) S11 reflection loss and (d) S21 insertion loss response. [21]
The 60 mm stripline structure in Fig. 10(a) shows two vias transitions. Set A has a much better TDR impedance response with less impedance fluctuation hence leading to wider operating bandwidth and lower insertion loss as observed in Fig. 10(b-d). This case study clearly shows the importance of via design on high-speed PCB layout. The seemingly small changes in the via design can affect the impedance mismatch significantly and degrades the signal propagation performance.
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2.1.2 High-speed PCB Interconnects Layout Design For high-speed applications where signal rise time is in the range of sub nano-second region, it translates into a signal bandwidth of more than 1 GHz, overlapping into the RF or microwave region. At these frequencies, the PCB metal interconnects whose physical length becomes comparable to the signal wavelength begins to exhibit transmission line effects [22, 23]. Also, a poorly designed trace without ground return via will cause significant impedance discontinuity, leading to degradation of SI performance. Much work has been reported in the areas of high-speed interconnects modelling and analysis [24-38] for high-speed interconnects designs. The reported work will be briefly summarised in this section.
a) Importance of Trace Stackup and Trace Impedance In today s high-speed layout design, impedance control becomes a primary issue and its effect has to be considered seriously. The design of interconnect trace impedance on the PCB is dependent on the trace dimension, layer stackup and material used. Many industry design tools based on the mathematical formulation are available to assist designer today in the PCB design such as Polar Si8000 Quick Solver and Speedstack . Fig. 11 shows how these tools allow designer to optimise the PCB stack up design for desire trace s characteristic impedance.
Figure 11 : Example of industry impedance solver and layout stackup
Polar Instruments Ltd, Polar Si8000 Quick Solver website: http://www.polarinstruments.com and http://www.polarinstruments.com/pdf/brochures/CITS800s_print.pdf
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However, even with the presence of state of art simulation tool in the stackup design, due to fabrication deviations, the actual trace impedance is often deviated from the desired value. With existing accuracy in the PCB fabrication process, 20% is an industrial acceptable norm while 10% is considered a stringent specification.
Hence, actual trace impedance has to be well characterised in order to ensure impedance matching on actual PCB termination design to ensure optimise SI, which is crucial in high-speed digital design. One such tool that is extremely critical and essential is the time domain reflectormeter (TDR) that is very useful for fast, accurate and reliable PCB impedance characterization as shown in Fig. 12. Its key role is to validate the actual PCB structure characteristic, to create an equivalent model for SI analysis and simulation.
Figure 12 : TDR impedance measurement of a PCB trace using Agilent TDR system
Agilent application note, SI Analysis series, part1: single Port TDR, TDR/TDT and 2-Port TDR , 5989-5763ED Feb. 2007
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b) Non Ideal Interconnect Losses With lower operating speeds, PCB traces can be approximated as perfect conductors (usually defined as Perfect Electrical Conductor-PEC in EM simulation) with their losses ignored. As more designs are operating in very high- speed application not only the transmission lines characteristics are critical but also other non-ideal effects [39, 40]. These effects become significant in high- speed design as they affect the signal propagation behaviour on the interconnects. There are many conventional formulas that are available to determine the characteristic impedance and propagation delay for lossless transmission line model. However, as frequency increases into the GHz range, the following losses of the interconnects can no longer be ignored:
(i) AC Resistive Losses At low frequency, current density within the conductor is uniform across the cross sectional area of the conductor. The resistance is given by:
(2.1) where is resistivity of the conductor, L is the length of the conductor and A is the cross-sectional area. For a PCB trace, w is the trace width and t is the trace thickness. As frequency increases, the current tends to migrate towards the outer surface as shown in Fig. 13, commonly known as the skin effect . It causes the current to flow in a smaller area than the case of lower frequency. Hence, the effective resistance increases with frequency.
Coaxial Cable Cross Section at High Frequency Outer (Ground) conductor
Inner (signal) conductor
Areas of high current density
Figure 13 : AC resistive losses in the cross sectional view of the conductor wire [39]
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(ii) Surface Roughness In the standard transmission line model evaluation, it usually assumes a perfectly smooth surface, which again in reality is never true. All metal interconnect surface are rough under microscopic view as shown in Fig. 14. They are controlled in order to have good adhesion to the laminate in the PCB formation.
Trace Tooth structure
Skin-Depth (4-7 microns)
Plane
Figure 14 : Cross sectional illustration of a typical PCB surface roughness [39]
As frequency increases high enough (~200 MHz), current tend to travel on the outer skin surface due to skin effect and with skin depth approaches the tooth size of copper. (Typical FR-4 boards has a average tooth size of 4-7 m) Hence, the tooth like surface roughness has to be taken into consideration, which increases the effective path length and decreases the area. The roughness can increase the AC resistance by 10-50% and is also frequency dependent. However, as the geometric tooth structure is random in nature, the loss associated with surface roughness can be difficult to predict.
(iii) Dielectric Losses In most cases, dielectric losses can be ignored because the conductor losses are more dominant. However, as frequency increases, this is no longer true. When a time varying electric field is impressed on a material, any molecules in the material that are polar in nature will tend to align in the direction opposite that of the applied field. Permittivity is the measure of how the electric field is affected by the dielectric medium. This relates to the material ability to transmit an electric field.
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Permittivity of a dielectric medium is given by:
' j '' (2.2)
The real part of the permittivity is given by:
' 0 r (2.3)
where o and r are the permittivity of free space and relative permittivity of the dielectric material, respectively. The imaginary part represents the loss which is proportional to frequency. The real and imaginary parts are related by the loss tangent or tan defined as follows: '' tan (2.4) '
The loss tangents of some typical substrate materials are given in Fig. 15.
Figure 15 : Loss tangent of some common substrate material [41)
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c) Effects of Trace Bends on Signal Performance In almost all PCB designs, signal trace routing involves some form of bends to allow the trace to avoid obstacles, such as vias and components. Much research has been done on modelling and analyzing trace bends [42-45]. When a signal on an interconnect encounters a bend, impedance discontinuity occurs and causes reflection of the signal. For thin traces at low speed, this poise negligible effects and if needed, simple lumped capacitance model [40] is usually adequate to model the effect of the bend. However, in high-speed design with space constraints, multiple bends are commonly needed and their effects simply cannot be ignored. Some design issues dealing with trace bend are the effects on SI and the operating bandwidth.
Fig. 16 shows some possible bend structures in high-speed layout design,
w
45 degree
Figure 16 : Typical trace bend structures configurations
The effect of a bend can be clearly seen in the TDR response as shown in Fig. 17 and the surface current using the CST-MWS simulation as shown in Fig. 18 [46]. Fig. 18 clearly shows that there is a current density build-up at the inner corner for the sharp 90° bend. Such an effect is negligible for the case of rounded bend. Similarly, the measured near-field emission pattern using the Langer IC Scanner (FLS-103) has also demonstrated the similar behaviour as shown in Fig. 19.
Langer IC-Scanner Measurement of radiated fields over the PCB: http://www.langer- emv.de/en/products/ic-measurement/field-measuring-on-ic/langer-ic-scanner/
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Figure 17 : Effects of TDR response of various bend structures
`` (a) (b)
Figure 18 : Surface current simulation plot (a) right angle (b) round bend
(a) (b)
Figure 19 : Near-Field emission plot (a) right angle bend (b) round bend
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d) Effects of Ground Return Via Optimization When a signal propagates through the interconnect from the source and a reference, it has to return back to the source through the same reference. While emphasis in the past has been placed significantly on the forward trace routing, the return path through the plane is often neglected. Many designers have overlooked the return ground vias in their PCB designs. However, for high-speed digital design, this aspect cannot be ignored and a return path has to be designed into the layout with as much attention as the signal path.
As it has been shown that at high frequencies, the return current follows closely to the signal path with the least loop inductance. Hence, for PCB interconnects, the path of least inductance is in fact directly next to the signal path. For transmission lines such as microstrip and strip lines where signal is driven with a common reference between them, the return path is easy to determine, as shown in Fig. 20.
Sou rce V L oad
Source V Gnd Plane Load
Figure 20 : Two conductors microstrip interconnects over common return plane
If the signal transits through a multi-layer PCB over different ground planes, the reference plane is no longer common. This gives rise to serious discontinuities problem in the return path and would lead to degradation of signal performance. The return path will go through the nearest surrounding ground via to move from ground plane 2 to ground plane 1, as shown in Fig. 21.
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Source V Gnd P lane 1
Gnd P lane 2 Load
Figure 21 : Interconnects transverse over different return planes
In this configuration, the effects of the presence of even one single ground return via can significantly affect the behaviour of the return current flow, as shown in Fig. 22.
(a) (b)
Figure 22 : Surface current plot for (a) without and (b) with one ground return via design
It has been discussed in section 2.1.1 that with a four ground vias structure to accompany the signal transition as shown in Fig. 23(a), one can control the
capacitance and provide optimum impedance control with excellent S11 and S21 performances. However, typical multilayer PCBs have easily over a thousand signal vias. The four ground via design approach will increase the number of vias significantly and causes tremendous routing constraints and often not practical. Hence, a more practical technique of using single ground via return shown in Fig.
23(b) is explored. This is a typical adopted technique. Its TDR and S21 performances are shown in Fig. 24 and Fig. 25 respectively.
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(a) (b)
Figure 23 : Ground return via design (a) 4 ground vias and (b) single ground via
The study of the single via configuration [46] has shown that the optimum distance of the ground via to the signal via is around 0.35 mm to avoid signal aberration due to the impedance discontinuity when the signal transits between ground layers in the multi-layer PCB. The TDR response shown in Fig. 24 can be
optimised to maintain around 55 avoiding sudden impedance changes. The S21 response in Fig. 25 shows an operating bandwidth of up to 16 GHz is achievable.
Figure 24 : TDR response of one ground return via design configuration
Figure 25 : S21 response of one ground return via design configuration
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2.1.3 Crosstalk of PCB Interconnects Inter-trace electromagnetic coupling or crosstalk [47-49] is another major key issue in high-speed digital PCB design. As frequency of operation increases, PCB traces behave like transmission lines. When a signal propagates along the line, both the electric and magnetic fields shown in Fig. 26(a) are present in the transmission line.
Electric Field Lines
Magnetic Field Lines
Signal trace
Ground
(a) (b)
Figure 26 : Microstrip FR-4 test structure for crosstalk simulation and measurement (a) electric and magnetic fields and (b) equivalent circuits of two parallel lines
For a pair of parallel transmission lines, their equivalent circuits are shown in Fig. 26(b). Neglecting the effects of resistance and conductance, each sub-section of transmission line of length z, can be described by a self-capacitance of C z, a self-
inductance L z. The mutual coupling is described by a mutual capacitance Cm z and
mutual inductance Lm z, where C, L, Cm and Lm are the per unit length self- capacitance, self-inductance, mutual capacitance and mutual inductance, respectively. Crosstalk refers to the coupling of the EM field between traces on the PCB, which are caused by fast changing currents and voltages during the transitions of logic states.
Crosstalk becomes significant as modern high-speed designs are densely populated due to miniaturisation in size and ever-increasing signal speeds. The unwanted couplings on adjacent traces from a signal trace are crucial in high-speed digital interface. Much work has also been carried out in the area of modelling, characterisation and analysis of crosstalk [51-55] and the techniques to minimise the effects associated with crosstalk [56-59].
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To demonstrated the effect of trace to trace separation on near-end crosstalk (NEXT) and far-end crosstalk (FEXT), a full wave simulation using CST Microwave Studio on a microstrip FR-4 PCB test structure shown in Fig. 27 has been carried out. The simulated results are validated with actual time-domain measurement using the
Agilent HP81134A pulse generator (Vp = 1V, tr = 0.1 ns) and Tektronix DSO81204 high-speed real-time oscilloscope with a 12 GHz bandwidth, as shown in Fig. 28.
Figure 27 : Microstrip FR-4 test structure for crosstalk simulation and measurement
(a) (b)
Figure 28 : Crosstalk validation (a) simulation results and (b) measurements
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For a parallel pair of 5 microstrip structure, with a source voltage of Vp of 1V and tr of 0.1 ns, the time-domain simulation of varying separation distance on the NEXT and FEXT are shown in Fig. 29(a) and Fig. 29(b), respectively. The results show that the most significant reduction in coupling occurs when the trace to trace separation is around 2W apart, where w is the trace width.
(a) (b)
Figure 29 : Overall effects of trace separation for microstrip (a) NEXT and (b) FEXT
The time-domain NEXT voltage waveform is a trapezoidal pulse, where its pulse width increases with the line length. However, the FEXT pulse amplitude is not affected by the line length. On the other hand, the pulse amplitude of FEXT varies directly with the line length. In terms of pulse amplitude, FEXT is more significant than NEXT. A summary of the impacts of trace separation for both NEXT and FEXT are plotted in Fig. 30(a) and Fig. 30(b), respectively.
NEXT for coupled microstrip lines FEXT for coupled microstrip lines
0.07 0.35 2" 5" 7" 2" 5" 7" 0.3 e0.06 e g g a a lt lt o o0.25 V0.05 V d d le le p p u u 0.2 o0.04 o C C d d e e0.15 s s li li a0.03 a rm rm0.1 o o N N 0.02 0.05
0.01 0 1 1.5 2 2.5 3 1 1.5 2 2.5 3 Normalized separation (W) Normalized separation (W) (a) (b)
Figure 30 : Overall effects of trace separation for microstrip (a) NEXT and (b) FEXT
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2.2 Device Characterization and Modelling
In the earlier section, the interconnects and their impacts on SI have been reviewed and summarised. Another important factor that affects SI performance is the device I/O impedance. While one can control the termination value at the output of the clock driver IC for impedance matching, it is still important to determine the true device output impedance under its actual operating condition in order to terminate the interconnects properly. The characteristics of the IC s input and output impedances can be obtained from one of the following ways:
a. The model library of the design tools; b. The vendor s IBIS model; or c. Through measurement.
2.2.1 Semiconductor Design Model Libraries In semiconductor design environment, designers utilise layout tools such as Cadence Virtuoso. The design process flow allows the IC designer to choose the specific cell, pad and I/O options from the libraries that it has licensed with. This can vary with specific technologies (for examples, 0.35 m, 0.25 m, 0.13 m, etc.) which also vary across the semiconductor device manufacturers, design houses and foundries.
The model from the design tool s library (standard cell) [60-63] concerns more on the functional aspects of the gate such as the driving capability, speed and power consumption within the device with loading typically at 2-5 pF capacitance ignoring the effects of resistance, wire bonding and package lead frame. Also, external factors due to layout such as trace impedance, device loading and frequency, which affect the SI analysis, are not taken into consideration.
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Most often, the main problem with these tools is that the cell libraries are only available to the IC designers within the IC design environment. These licenses are governed by strict usage control and cannot be shared outside the design environment without written license agreement and vendor approval. Hence, they are not easily available in public domain. Furthermore, the cost of the cell libraries varies from several hundred thousands dollars per library in 0.25 m to several millions of dollars for the latest 90/65 nm technologies. To the designer, typically it may need 3-5 libraries for a specific technology, while to the foundry, it may require more and it also varies for different vendors. Hence, accessibility of the information can be extremely costly.
These models are usually not readily available to the PCB circuit, layout and SI designers. Sometimes, some device manufacturers do not clearly define its technology used in the datasheets. Even if it specifies its technology, it does not reveal its library and foundry vendor information. Worst of all, the I/O pad and cell information are not available. Hence, information pertaining to the device is only as accurate as the datasheet released by the IC manufacturer, which can be overly simplified and mainly for timing specific design purposes. Nothing or little information on SI, which is now becoming one of the key bottlenecks in high-speed product design, is available. The electrical information in typical device datasheet includes:
Functional truth-table, device schematic, package and pin out; Absolute maximum and recommended operating conditions;
Input and output estimated capacitance (Cin, Cout);
DC electrical characteristics (Vcc, Vih, Vil, Voh, Vol, Ioh, lol etc);
AC switching characteristics (Fmax, Tplh, Tphl, Tr, Tf etc); and Typical test circuit and the timing waveform.
Texas CDC337, IDT 49FCT805, National CGS2535
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2.2.2 I/O Buffer Information Specification (IBIS) Model IBIS (Input/Output Buffer Information Specification) is a method of providing the Input/Output device characteristics of an IC to the outside world without disclosing any proprietary circuit/process information. It can be thought of as a behavioral modelling specification suitable for digital circuit simulation that is currently used by many EDA companies. The advantages of IBIS include:
Protection of proprietary information (process parameters, circuit design etc); Facilitate SI analysis before design is fabricated; Plenty of models available from EDA and semiconductor vendors; Faster simulation time compared to structural and SPICE models; and Common standard compatible within all industry simulation platforms.
Since its introduction by Intel in 1993 aiming at CMOS and TTL IO buffers, it has gained acceptance [67-69] with major EDA companies and several semiconductor manufacturers. An IBIS open forum has also been created to promote the application of IBIS as the simulation format and standard, which was finally adopted in December 1995 as ANSI/EIA-656 standard [65]. Some of the key information in a typical IBIS model and a typical behavioral diagram of IBIS are given below:
Component IBIS version, manufacturer information, package information (R_pkg, L_pkg, C_pkg); Component pin information (Pin no, name, model, R_pin, L_pin, C_pin); Model type: open sink/source, I/O drain/sink/source, I/O ECL, inverting/non-
inverting, active-low/high, terminator, Cref, Rref, Vref, Vmeas, C_comp; and Model temperature, voltage range, pullup/pulldown IV, power/ground clamp
IV, Rise/Fall waveform, Vinl/Vinh.
See appendix on IBIS model sample
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A typical IBIS model of a device is shown in Fig. 31.
P o w e r C l a m p
I n p u t P a c k a g e P u l l u p P u ll u p P o w e r R a m p V / I C l a m p G N D C l a m p T h r e s h o l d O u t p u t & P a c k a g e E n a b le P o w e r L o g i c C l a m p P u l l d o w n P u l l d o w n G N D R a m p V / I C l a m p E n a b l e P a c k a g e
G N D C l a m p
IBIS Output Structure Model Vcc Vcc
Vcc
IBIS Input structure R_pkg model C_pkg Power_Clamp L_pkg R_pkg L_pkg C_comp
C_comp GND GND C_pkg GND_Clamp Pullup Power_Clamp Pulldown GND GND_Clamp GND Ramp
Figure 31 : Typical IBIS model, input and output structure
IBIS version 4.2 [66], which is the latest ratified by the IBIS open forum has become very comprehensive. This has led to further developments, such as ICM IBIS interconnects modelling specifications for passive interconnects IMIC IO interface model for IC by Japan JEITA and ICEM Integrated Circuit Electrical Model by IEC draft 62014-3 for EMI behavioral simulation.
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Self generated IBIS: One can create the IBIS from measurement, data books or datasheets based on the I/V data, if available. However, in most cases, this information is too generic and may not show the actual variation that exists in the device. This may be suitable for very general circuit simulations. However, such models are not suitable for modelling in high-speed application where accuracy is critical. Generating IBIS library in-house will be extremely costly and manpower intensive. [75]
Free IBIS model: Many design houses and CAE vendors provide a wide range of IBIS models free of charge but users have to do their own translation or verification before using them as no one would guarantee its accuracy and validation. At many instances, even errors occur in the model syntax. For companies that have developed their own libraries, they are only available within the companies.
There are also translators and utilities (s2ibis, winibis, s2iplt, ibis_chk) available but usually not user-friendly especially for the newer version. They may still contain fixes as IBIS standard continues to evolve and all these software come from different developers or groups that may not continue to upgrade according to the latest standard.
Problems with IBIS model: The IBIS model has been used widely by many EDA tools at board-level circuit simulation. Unfortunately, details of the IBIS model from the semiconductor vendors are not well shared among the EDA tool developers to protect vendor proprietary design information. Although there are signs that more customers have expressed strong interests in the IBIS models, in which the semiconductor vendors have to supply these models for the devices they produced; IBIS models of many devices are still not readily available, which have been the key problems with the users [70-72].
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Also, the device information given is typical value and is not guaranteed. The SPICE model may be a general one and may not reveal the details of the buffers or latest information. Hence, they are not necessary best representatives of the device. As long as information does not flow freely between the semiconductor manufacturers, designers and the EDA industries, which will expect to continue due to proprietary issues, the IBIS models will remain to be used for functional verification and lack of accuracy for SI simulation. [73-74].
2.2.3 Device Characterization through Measurement Another possible way to extract device impedance information is through measurement. Various instruments and techniques are available in the market for impedance measurement with different degree of accuracy and frequency range. Conventionally, the measurement techniques fall under two general categories, LCR or impedance measurements.
A comparison of the different measurement techniques [76-77] is shown in Fig. 32. Their operating capabilities are briefly summarised in this section.
Figure 32 : Measurement techniques and frequency range[76]
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a) Bridge Technique The Wheatstone bridge shown in Fig. 33 is by far the most common technique ever developed and most impedance bridges are derivative of it. It can be highly accurate (0.2 % is achievable) with a wide frequency ranges from DC to 300 MHz. The key advantage is its low cost with reasonable accuracy. However, it is only suitable for research usage and not common in industry application as it needs to be manually balanced and can be rather tedious when the measurement covers over a wide frequency range. Upon balanced condition, no current flows
through the null detector (G), the unknown impedance Z4 can be computed as follows:
Z4 = (Z1/Z2) Z3 (2-5)
Some of the typical bridges include Wien bridge for capacitance measurement, Maxwell bridge for low-Q inductance measurement and Hay bridge for high-Q inductance measurement
B
Z 1 1 Z 2 2
A G C
Z 3 3 Z 4 4 D
Figure 33 : Bridge measurement method
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b) I-V Technique For this method, a sinusoidal voltage signal from a function generator is utilised to cause a current flowing through an unknown impedance with a known resistor R, which is typically low resistance value to prevent the effect of circuit loading, as shown in Fig. 34. Since both voltage and current are needed to determine the unknown impedance, it is commonly known as I-V method. Typical I-V techniques cover from 40 to 110 MHz with a small dynamic impedance range. This technique allows in-circuit testing and hence is quite popular in device
manufacturer for component characterization. The unknown impedance Zx can be determined as follow:
V2 I R (2.6)
V1 V1.R Z X (2.7) I V2
Figure 34 : I-V measurement method
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c) Resonant or Roll-off Technique
In this technique, the unknown inductor Lx is placed in a circuit which is adjusted to resonate with a tuning capacitor C, as shown in Fig. 35. The resonant frequency can be obtained from the oscillator setting. The quality factor Q can be directly
measured using a voltmeter placed across the tuning capacitor. The unknown Lx can be obtained from the resonant test frequency and known C value.
1 At resonance: X = X L Lx c osc x oscC 1 Lx 2 (2.8) osc C
The unknown loss resistance Rx can be found by:
X L At resonance: Q L osc x Rx Rx L R osc x (2.9) x Q
Figure 35 : Resonant or roll-off measurement method
This key advantage of this method is good Q accuracy and therefore very suitable for high Q device measurement. However, it requires manual tuning and can be tedious in measurement process. Typical measurement frequency ranges from 10 kHz to 70 MHz.
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d) Auto-Balance Bridge Technique This technique offers the widest impedance measurement range with typical measurement frequency from 20 to 110 MHz. The current, flowing through the
unknown impedance Zx, also flows through the resistor R as shown in Fig. 36. The potential at point L is maintained at zero volts. The current through R
balances with the current through Zx by operation of the I-V converter amplifier.
The unknown impedance Zx is calculated using voltage measurement (V1) at point
H and that across R (V2).
V V V I 2 L 2 (2.10) R R
V1 V1R Z x (2.11) I V2
Figure 36 : Auto balancing bridge measurement method
This technique is best suited as a general purpose LCR meter for measurement below 100 kHz, which uses a simple operational amplifier for its I-V converter. At higher frequency, it requires to employ I-V converters consisting of sophisticated null detector, phase detector, integrator and vector modulator to ensure good accuracy.
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e) Network Analysis Technique Fig. 37 shows a network analysis technique offers the highest frequency coverage, but only works best when the measurement impedance range is close to 50 . The reflection coefficient is obtained by measuring the ratio of an incident signal to the reflected signal. A directional coupler or a bridge is used to detect the reflected signal and a network analyzer is used to supply the incident signal and measure the reflected signal. This method is most widely used for RF and microwave component and circuit analysis with operating frequency from 300 kHz to several tens of GHz.
Figure 37 : Network analysis measurement method and sensitivity comparison [76]
Reflection coefficient and the unknown impedance are determined by:
VReflected Z x Zo (2.12) VIncident Z x Zo
1 Z x 50 (2.13) 1
Based on equation (2.12), reflection coefficient varies from -1 to 1. Depending on
the impedance Zx, the measurement is accurate when Zx approaches Zo. The
change in gradient of the reflection coefficient when Zx is small and very large, is non linear causing deterioration in measurement accuracy.
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f) RF I-V Technique RF I-V is an enhancement of the I-V technique, offering some of the high frequency benefits of the network analysis beyond the frequency coverage of the auto-balancing bridge method while retaining some of the impedance measurement range of the I-V technique. Since RF I-V method is based on the linear relationship of voltage-current ratio to impedance given by Ohm s law, its sensitivity is more consistent. It also offers high accuracy (~ 1%), wide impedance range (100 m - 10 k ) and wide frequency dynamic range (100 kHz- 3 GHz). It is configured slightly different by using an impedance matched (50 ) measurement circuit and a precision coaxial test port for operation at higher frequencies. Layout is slightly different for low and high impedance measurements as shown in Fig. 38.
Figure 38 : RF I-V measurement method [76]
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In summary, the various measurement techniques mentioned can be summarised as follows: LCR meters: Mainly utilise balancing bridge techniques and most of these are highly accurate for device characterization but have limited measurement frequency range up to 110 MHz. These meters are mostly used in specific spot frequency measurement and hence suitable for general purpose impedance measurement.
Impedance Analyzers: Mostly utilise I-V and RF I-V techniques. They provide accurate measurement over a wide impedance range. However, they are designed mainly for LCR passive components, material and semiconductor devices measurements. They have limited measurement frequency of up to 110 MHz for I- V technique or up to 3GHz for RF I-V technique.
Network Analyzers: Based on transmission/reflection techniques and offer the broadest frequency range up to 100 GHz. However, this technique only delivers
exceptional accuracy when unknown impedance is near Zo (50 or 75 ) and the
accuracy deteriorates for impedance either much higher or much lower than Zo.
All the above mentioned commercial off the shelves (COTs) instruments for impedance measurement are available in the market, for examples, Agilent and Keithley have very comprehensive instruments for various frequency range and impedance range. Some of these are dedicated and can be rather expensive. However, most of them are not designed for in-circuit characterization other than those used in component characterization by manufacturing companies.
As most of these instruments are designed specifically for component characterization, the measurement accuracy requires critical calibration and compensation procedures [76] together with customised and often expensive test jig to ensure high accuracy. None of these instruments are intended for the actual in-circuit measurement with a device in its actual operating conditions.
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hapter 3
3.0 REVIEW OF IMPEDANCE MEASUREMENT
Passive components such as resistors and capacitors are abundantly found in most digital circuit design. Resistors, being the most common components in digital circuits, are used for terminations, impedance matching and current flow regulation. Capacitors are also used extensively in applications such as bypassing, inter-stage coupling, filter and matching network. All integrated devices input and output are terminated by components with their impedances varied with biasing and operating frequency. In-order to match the devices to the PCB interconnects, appropriate understanding of the component impedance characteristic [90] is important to achieve the desired SI performance in high-speed digital design. This chapter reviews the high frequency behavior of the off-chip passive devices. The impedance measurement technique for components in its intended in-circuit operating condition will also be described.
3.1 High Frequency Behaviors of Passive Components
In reality, passive components are never ideal [80-81]. As components such as IC, PCB interconnects and termination resistors are used in ever-increasing operating frequency environment, their parasitic natures begin to surface. These parasitic affect the high frequency behavior of the components. Hence, it is important to take these non-ideal effects into consideration in high-speed circuit design so that proper part for impedance matching purposes can be selected.
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3.1.1 High Frequency Effects on Resistor Characteristic A resistor R is never ideal and in high frequency operation, the hidden schematic of non-ideal parasitic capacitance and inductances begin to surface, as shown in Fig. 39.
Figure 39 : Equivalent circuit of a non ideal resistor [80]
The useful operating range of a resistor is defined as the highest frequency in which the impedance differs by more than that of the specified tolerance typically near its corner frequency. The characteristic of a resistor can varies significantly over the frequency range as shown in Fig. 40(a). Resistors of different values can behave differently as shown in Fig. 40(b), where the highest operating frequency of low-value resistor is limited by the lead inductance while high-value resistor is limited by the parasitic capacitance.
(a) (b)
Figure 40 : Characteristic response (a) a 500 thin-film resistor and (b) metal-film with difference values [81]
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3.1.2 High Frequency Effects on Inductor Characteristic An inductor is basically a coil formed by winding a wire on a cylindrical former to increase its magnetic flux linkage between turns of the coil. The increase in flux linkage increases the self inductances of the wires and creates an inductor. However, as frequency increases, besides the frequency dependent wire resistance, the effect of parasitic capacitance between adjacent turns begin to surface. The equivalent circuit of an inductor is shown in Fig. 41.
Figure 41 : Equivalent circuit of a non ideal inductor [80,81]
The impedance of an inductor increases with frequency, as shown in Fig. 42. Beyond the resonant frequency, the influence of the parasitic capacitance becomes dominant and the impedance of the inductor decreases instead.
Figure 42 : Characteristic response of an inductor [81]
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3.1.3 High Frequency Effects on Capacitor Characteristic Capacitors are used extensively in application such as bypassing, inter-stage coupling, filters and matching network in digital design. At high frequency, a non-ideal capacitor is in fact, a complex impedance whose equivalent circuit consists of series and parallel elements as shown in Fig. 43. Besides the frequency dependent wire resistance, dielectric loss due to dielectric absorption and molecular polarisation become significant at high frequencies.
Figure 43 : Equivalent circuit of a non ideal capacitor [80]
The impedance of a capacitor decreases with frequency. Beyond the resonant frequency, the influence of the parasitic inductance becomes dominant and the impedance increases instead, as shown in Fig. 44.
Figure 44 : Characteristic response of a capacitor [81]
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3.2 Current Measurement
In general, there are three methods for current measurement. The first method inserts a current meter to the circuit under test (CUT) to obtain the current reading. This method requires one to physically break the circuit at some point, which can be cumbersome and at times impractical. The second method connects a voltage probe from an oscilloscope to a known resistor in the CUT. With the measured voltage and the know resistor value, one could calculate the current flows in the CUT. However, it requires an insertion of a known resistance in the CUT if none exist in the measurement setup, which can be inconvenient and the inserted resistor will have an impact on the CUT s operation. The last method uses an inductive coupled clamp-on current probe so that the current of the circuit can be measured without breaking the circuit and introduced negligible loading effects to the CUT.
3.2.1 Advantages of Using Current Probe Usage of current probes has been gaining significant attention in non-intrusive measurement. The advantages of using current probes are as follows: Ease of permanent or temporary installation in CUT; No direct electrical connection and therefore minimises loading effect to the CUT; Clamping type probes offer ease in test setup to measure current of the CUT under its actual operating condition; and Preserve fidelity of the signal without the effects caused by the conventional passive probes as the current probe couples signal magnetically rather than direct electrical connection to the measuring instrument.
3.2.2 Measuring Current Signals A current probe is equivalent to a transformer with a small number of turns on the primary side of the conductor under test and a larger number of turns on the secondary winding that connects to the measuring instrument, usually matched at 50 . When the measured current flows through the conductor in the CUT, by Faraday law, an induced current will be picked up by the instrument at the secondary coil. This is then converted into a measurable voltage. Depending on the probe sensitivity and operating bandwidth, an accurate current reading with good dynamic range and wide bandwidth can be obtained.
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3.2.3 Single Probe Measurement Limitation To obtain impedance information, one needs to know the voltage across a device as well as the current passing through it. An injecting signal from an injecting voltage probe is needed and a current probe will be used to measure the current passing through the device. Unfortunately, most single-ended voltage probes do not cover a wide frequency range due to inherent parasitic capacitances of the probes. Therefore, accurate magnitude as well as phase information at high frequency is limited by the voltage probe s bandwidth. Although there are differential voltage probes that cover wider frequency bandwidth but the measurement setup becomes more complex and the calibration process to eliminate setup error can be tedious.
The proposed two current probes approach, though less straight forward to obtain the impedance information, has simpler test setup. Also, the convenient of the two-port measurement using the VNA, it allows the magnitude and phase information of the impedance to be extracted with relative ease. The thesis has demonstrated that through careful calibration process, the error due to the setup can be eliminated to ensure good measurement accuracy up to 1 GHz. The advantages of the use of two current probes approach for active device impedance measurement were mentioned by Roger as follows:
The inductive coupling of the two probes introduce negligible impedance to the device under test in its operating circuit; and The device under test is not interrupted during the measurement.
At frequencies below 200 MHz, where the phase variation is insignificant, scalar measurement instruments are sufficient to extract reasonably accurate impedance information, which has been reported in earlier works [82-86]. However, as frequency increases beyond 500 MHz, the phase variation due to parasitic effects of the component under test become significant and two-port S-parameters measurement using the VNA is necessary. With the two wide-band two current probes and a careful calibration process, accurate impedance extraction with both magnitude and phase information up to 1 GHz becomes possible, as demonstrated in this thesis.
Roger A. Southwick and Walter C. Dolle, Line Impedance measuring instrumentation utilizing current probe coupling , IEEE Trans. on EMC, Vol. 13, no. 4, Nov 71.
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3.3 In-Circuit Measurement using Two Current Probes
The method of using two current probes in impedance measurement has long been utilised since the mid 60s and much work and research has been done by various researchers and industrial engineers since. Some of the earlier works include that by Brooks [82] in 1965 for the measurement of power-line impedances in frequencies ranging from 20 kHz to 30MHz. This was later improved with calibration techniques for current probe losses by Southwick [83] in 1971 and RF impedance of power lines and LISN in conducted interference work by Nicholson and Malack [84] in 1973. Much research was done in the application of current probe measurement for power device in frequency less than 100MHz. [85-86]. Later improved techniques for power line impedance up to 500 MHz was reported [87-89]. However the results from the reference paper [88] extracted here clearly shows its accuracy deteriorates when the frequency goes beyond 500MHz significantly.
Extracted relative errors in the measurements of (a) 100ohm and (b) 500ohm resistor [88]
There is an increasing need for extending the frequency range up to 1GHz or beyond for high frequency in-circuit characterisation due to rapid increase in operating frequency of high-speed circuits. In this thesis, by introducing a careful and dedicated calibration process, the error due to measurement setup above 500 MHz can be eliminated. It is demonstrated that the two current probes method can be extended up to 1 GHz to characterise both the non-linear passive component as well as the active device output impedance with very good accuracy.
This was the earliest known literature by the author. There may be other research works or published literatures in this area that the author is unaware.
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3.3.1 High Frequency Current Probe The CT6 current probe [78, 79] from Tektronix is a current probe designed and optimised for very high frequency operation. It was chosen for our research work as it has wide bandwidth, low inductance and very small form factor. The key specifications of the CT6 current probe are:
Wide bandwidth up to 1.5 GHz; Low leakage inductance of 1.5 nH; High sensitivity of 5 mV/mA; Ability to detect short rise time of 200 ps; Accuracy of +/- 3%; Maximum peak pulse current of 6A and maximum continuous current (rms) of 120mA without saturation; Low insertion impedance (1.1 @10 MHz, 1.3 @100 MHz & 12 @1 GHz); and Accept un-insulated wire size up to 20 gauge
3.3.2 Injecting Current Signals In the two current probes technique proposed, a second current probe will be configured for signal injection. When used for injecting AC current into a conductor in the circuit under test (CUT), the current probe acts as the primary winding connecting to the signal injection source. The conductor in the CUT acts as the secondary winding of the transformer. The current probe converts the voltage signal on the primary side to a current signal in the current carrying conductor in the CUT.
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3.3.3 Measurement Setup for Optimum High Frequency Performance Several important issues have to be taken into consideration when using the current probe to ensure measurement accuracy. These issues are briefly summarised here:
Current probe transfer impedance Every current probe is characterised individually with a transfer impedance. The frequency response of the transfer impedance has to be observed carefully in order to utilise the probe within its suitable bandwidth of operation for best accuracy. As for CT6, though its specification covers a typical bandwidth of 250 kHz to 2 GHz as shown from the transfer impedance plot in Fig. 45, it is clear that at both the lower and upper end of the frequency, the response deteriorates. Hence, to achieve best accuracy, the desired frequency range of operation should be limited from 2 MHz to 1 GHz.
Figure 45 : CT6 probe frequency response [78]
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Wire size and length The wire gauge and length of the wire used to route the test current through the probe have a direct effect on the amount of stray capacitance and inductance it introduce. The longer the wire, the higher the stray inductance and it adds to the circuit impedance at high frequency. It is recommended that a length not longer than 1 cm be used. The larger the gauge size of the wire, the more stray capacitance exists between the wire and the current probe. The probe, though designed to measure magnetic field, is also sensitive to stray electric field pick up by the stray capacitance. This affects the CUT at high frequency and adds aberrations to high frequency signals. It is best to use a wire with the smallest possible diameter and the recommended wire size should be larger than 27 gauge.
Positioning of probe Each probe also has stray capacitance associated with the case that surrounds the head of the current probe when there is a wire with a relatively large diameter in the probe (approximately 20 to 25 gauges). When measuring high-frequency signals with a wire of larger diameter, it is generally best to position the probe head perpendicular to the circuit board under test as shown in Fig. 46.
Figure 46 : CT6 positioning for HF application [79]
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3.3.4 Theoretical Background of Two-Probe Measurement Unlike the impedance measurement using the conventional voltage probe, with current probe, the measurement using two current probes requires several steps. The
concept of measuring unknown impedance Zx seen at x-x using the two-probe approach can be illustrated by the test setup shown in Fig. 47(a) [85-86]. It consists of an injecting current probe, a receiving current probe and a vector network analyzer (VNA). The two probes are inductively coupled to the circuit without direct
connection to Zx, hence minimizing loading to CUT.
(a)
(b)
Figure 47 : (a) Basic test setup; (b) equivalent circuit of two probes measurement
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The equivalent circuit of the two probes setup is shown in Fig. 48(b). V1 is the output signal source voltage of port 1 of the network analyzer connected to the injecting
probe, and V2 is the resultant signal voltage measured at port 2 of the network analyzer with the receiving probe. Impedances of the VNA ports are usually 50
while Z1 and Z2 are the matching impedances to the injection and receiving probes
seen by ports 1 and 2, respectively. L1 and L2 are the primary self-inductances of the injecting and receiving probes respectively, and L is the loop inductance of the circuit
under test. M1 is the mutual inductance of the injecting probe and the CUT loop, and
M2 is the mutual inductance between the receiving probe and the CUT loop. The
induced voltage at the unknown impedance Zx is V and the induced current through
Zx is I.
(i) Equivalent Circuit of Injection Probe:
Without the receiving current probe, the injecting probe induces a signal current Ii in
the CUT and causes a signal voltage Vi across Zx as shown in Fig. 48.
Figure 48 : Equivalent circuit of the injection probe
At the primary side of the injecting probe:
V1 50 Z1 j L1 I1 j M1Ii (3.1)
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At the secondary side of the injection probe:
Ii ( j L r Zx ) j M1I1 0 (3.2)
From (3.1):
V1 j M1Ii I1 (3.3) 50 Z1 j L1
Sub (3.3) into (3.2) and eliminating I1,
V1 j M1Ii Ii ( j L r Zx ) j M1 0 50 Z1 j L1 2 j M1V1 M1 Ii Ii ( j L r Zx ) 0 50 Z1 j L1 50 Z1 j L1
Ii ( j L r Zx ) VM1 Ii ZM1 0
VM1 Ii ( j L r ZM1 Zx ) (3.4) where
2 M1 ZM1 (3.5) 50 Z1 j L1
j M1V1 VM1 (3.6) 50 Z1 j L1
From (3.4), the injection probe in Fig. 48 is reflected in the CUT loop and represented by Fig. 49.
Figure 49 : Reflected equivalent circuit of injection probe in CUT loop
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(ii) Full Equivalent Circuit in the Coupled Circuit Loop: With the addition of the receiving current probe, it introduces another impedance reflected in the CUT. The final equivalent circuit of Fig. 47(b) is given in Fig. 50,
where ZM2 is the reflected impedance in the CUT due to the receiving probe.
Figure 50 : Final reflected equivalent circuit of the two probes measurement setup
From Fig. 50, the resultant induced current in the CUT loop due to the injecting signal is given by: V I M1 (3.7) ZM 1 ZM 2 j L r Z X
ZM1 and ZM2 are the impedances due to the two probes, while r and j L are the
resistance and inductive reactance of the connecting conductors to Zx. By defining
Zsetup as the impedance due to the measurement setup,
Then Zsetup ZM 1 ZM 2 j L r and equation (3.7) can be rewritten as:
VM1 I (3.8) Z setup Z X
From (3.8), the unknown Zx can be obtained by: V Z M 1 Z (3.9) X I setup
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The induced current measured by the receiving probe can be determined by:
V2 I (3.10) ZT 2
where ZT2 is the calibrated transfer impedance of the receiving current probe, which is defined as the ratio of the voltage measured by the probe and the current flowing
through the probe. The calibrated ZT2 versus frequency can be found in the current probe data sheet [78]. Substituting (3.6) and (3.10) into (3.9);
j M1V1 ZT 2 Zx Zsetup (3.11) 50 Z1 j L1 V2
j M Z Let k 1 T 2 , then (3.11) becomes: 50 Z1 j L1
kV1 Z x Z setup (3.12) V2
(iii) Determination of the coefficient k and Zsetup:
From (3.12), Zx can be determined if k, V1/V2 and Zsetup are known. V1 and V2 relates to the signal voltages of the injecting and receiving probes and can be obtained by the
VNA, V1 and V2 are related by:
V S 2 21 (3.13) V1 1 S11
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where S11 and S21 are the reflection and insertion losses respectively, obtained from the VNA. The magnitude and phase for (3.13) can be obtained as follows [112]:
V S S Magnitude: 2 21 21 (3.14) 2 2 V1 1 S11 1 S11 cos S11 S11 sin S11
V2 S21 1 S11 sin S11 Phase: S21 tan (3.15) V1 1 S11 1 S11 cos S11
From the expression of k, we know that it depends on the characteristic of the probes and the coupling between probes and the CUT. Hence, we can perform a pre-
measurement calibration process to determine k and Zsetup under two known
conditions. Firstly by replacing Zx in (3.12) with a short circuit (Zx = 0 ):
V1 0 k ZSetup V2 Z X 0
V1 ZSetup k V2 Z X 0
V2 k ZSetup (3.16) V1 Z X 0
Next by replacing Zx in (3.12) with a known precision standard resistor Rstd , we have:
V1 Rstd k ZSetup (3.17) V2 Z X Rstd
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Substituting (3.16) in (3.17) and eliminating k, Zsetup can be determined by:
V2 V1 Rstd ZSetup ZSetup V1 V2 Z X 0 Z X Rstd
V2 V1 Rstd ZSetup 1 V1 V2 Z X 0 Z X Rstd
Rstd ZSetup (3.18) V V 2 1 1 V1 V2 Z X 0 Z X Rstd
Substituting (3.18) into (3.16), k can be obtained as follows:
V2 Rstd V1 Z X 0 k (3.19) V V 2 1 1 V1 V2 Z X 0 Z X Rstd
V1 V1 Hence, by measuring and , Zsetup and k can be determined from V2 V2 Z X 0 Z X Rstd
(3.18) and (3.19), respectively. Once Zsetup and k are found, the two-probe setup is
ready to measure any unknown impedance Zx through (3.12). This calibration process allows the impedance due to the test setup to be eliminated or minimised for good measurement accuracy. However, it is important to note that the choice of known
precision standard resistor Rstd has to be carefully chosen such that its impedance remains constant and frequency independent up to the maximum frequency of interest so as to ensure a proper calibration process. The chosen standard resistor has to be measured with an impedance analyser to ensure that its impedance remains flat over the frequency range of 30MHz to 1GHz.
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hapter 4
4.0 VALIDATION OF TWO-PROBE MEASUREMENT METHOD
In order to validate the proposed measurement method using the two current probes approach, the impedance of a few passive components under direct current (DC) biasing condition will be used as test cases for in-circuit measurement. It will be shown later that with a pre-measurement calibration process described in Chapter 3, the proposed method has the ability to eliminate the error due to the measurement setup so as to achieve good measurement accuracy.
Using several resistors and inductors as devices under test, impedance characterization of each passive component up to 1 GHz with good accuracy has been demonstrated [117]. The two-probe measurement approach also provides insight to the impedance behavior of a critical circuit component under its intended in-circuit condition so that proper choice of component can be made for a specific biasing condition to achieve optimal circuit performance. It also allows a designer to perform component sensitivity analysis due to part changes from existing design and to investigate the impact of impedance deviation from the original design to avoid unwanted variation or drift in circuit behavior that causes failure in the functional specifications of the circuit.
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4.1 In-Circuit Characterization of Passive Components
With the trend of increasing operating frequency of the electronic circuit, the impedance characteristic of a critical component up to GHz range becomes important for the circuit designers [90-92]. For example, if the applied biasing current is too high, the ferrite-core of the inductor may become saturated and its impedance can be very different from that when measured off-circuit without applied biasing. The core saturation causes a reduction in inductance of the inductor, which in term, leads to lower inductive reactance1,2. The proposed two current probes method has the ability to detect such behaviour of a ferrite core inductor under in-circuit operating condition and the details are discussed in Section 4.5. Hence, impedance characterization of a critical circuit component with possible non-linear behaviour over a wide frequency range under its intended DC biasing condition serves as a useful assessment of the component for optimal circuit performance.
Conventional impedance measurement of a passive component requires direct electrical contact to the component, such as impedance analyzer, LCR meter and vector network analyzer (VNA) [76-77, 89]. However, such instruments are usually designed for off-circuit impedance measurement. Currently, most component characterization techniques still require direct electrical contact [93-95]. To minimise the measurement error contributed by the electrical contact to the component under test, dedicated and advanced micro probing is necessary and therefore is very costly [96-97].
The purpose of this section is to validate the proposed non-contact two-probe inductive coupling measurement technique to characterise a passive component under specific DC biasing in-circuit condition. The proposed method requires no direct electrical contact to the CUT and therefore its influence to the circuit operation is negligible. Most importantly, with a proper pre-measurement calibration of the test jig, the error contributed by the measurement setup can be eliminated to ensure good impedance measurement accuracy.
1 Chikazumi, S shin (1997). Physics of Ferromagnetism. Clarendon Press. ISBN 0-19-851776-9 2 Choudhury, D. Roy (2005). Modern Control Engineering. Prentice-Hall of India. ISBN 81-203-2196-0
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4.2 Measurement Setup for Validation
The measurement setup consist of an in-house designed test jig that is capable of measuring passive components over a wide range of impedance values accurately from 1 MHz to 1GHz, using the proposed two current probes technique under in- circuit operating condition.
The schematic of the measurement setup for a device-under-test (DUT) is shown in Fig. 51(a). A DC power supply and a load resistor R provide the necessary DC
biasing current for the DUT. C1 and C2 (both 0.22 F SMD tantalum) serve as low- impedance bypass capacitors for the injected AC signal. To facilitate the measurement without direct electrical contact, two identical inductive coupling probes (Model: Tektronix CT-6, bandwidth 250 kHz to 2 GHz), one as injecting probe and another as receiving probe, are coupled to the circuit without direct electrical contact. Port 1 of a VNA (Model: R&S ZVB8, bandwidth 150 kHz to 8.5 GHz) injects an AC signal into the circuit loop through the injecting probe and port 2 of the VNA measures the resulting coupled signal in the circuit loop through the receiving probe.
A test jig using a FR-4 printed circuit board (PCB) is fabricated, as shown in Fig. 51(b). The lower side of the PCB is a complete metal layer serving as a low- impedance signal return path. The DC power supply (Model: Caltron PR 3504D) is connected to a SMA connector and provides the DC biasing current to the DUT through a microstrip trace of length 2 cm, which is much shorter than the wavelength of the highest frequency of measurement (1 GHz). Two pairs of very short jumpers (less than 5 mm) are designed to fix the positions of the two probes to ensure measurement repeatability.
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Vector Network Analyzer Signal (VNA) Spectrum Generator(R&S ZVB8)Analyser (HP PortE44331 B) (HPPort 85912 A)
DUT Injecting Receiver Probe Probe Power Supply C1 C2 R
(a)
Injection Probe Receiving Probe to VNA Port1 to VNA Port2
DUT
35 mm
DC input Decoupling Caps
68 mm
(b)
Figure 51 : Measurement setup using the two inductive coupling probes: (a) schematic circuit (b) fabricated test jig
The purpose of the coupling capacitors (C1 and C2) is to provide the low- impedance path for the injected AC signal without affecting the DC biasing current. The value of the capacitor is chosen at 0.22 F such that its impedance is sufficiently low to the lowest injected signal frequency.
The purpose of the load resistor is to provide a path for the DC biasing current for the DUT. Its value should be sufficiently large enough compared to the capacitive
reactance of the capacitor as it is placed in parallel to C2. It is to ensure the resistor
R is AC shorted by C2. The value is chosen to be 100 . The DC biasing current can be adjusted through varying the DC output voltage of the power supply.
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4.3 Equivalent Circuit of the Test Setup
The equivalent circuit of the test setup shown in Fig. 51(a) can be illustrated in Fig.
52. ZDUT is the impedance of the DUT, ZPS//ZC1 is the parallel impedance of the
power supply and bypass capacitor C1, and ZR//ZC2 is the parallel impedance of the
resistor R and bypass capacitor C2. V1 is the output signal source voltage of port 1 of
VNA, which is connected to the injecting probe; and V2 is the resultant signal voltage
measured at port 2 of VNA through the receiving probe. Z1 and Z2 are the matching impedances to the injecting and receiving probes seen by ports 1 and 2 respectively.
L1 and L2 are the self-inductances of the injecting and receiving probes respectively. L and r are the self-inductance and resistance of the connecting copper traces that form
the coupled circuit loop respectively. M1 is the mutual inductance between the
injecting probe and the coupled circuit loop and M2 is the mutual inductance between the receiving probe and the coupled circuit loop.
Figure 52 : Equivalent circuit for the in-circuit measurement setup
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Applying KVL for the circuit of port 1 of VNA and the injecting probe,
V1 50 Z1 j L1 I1 j M1I x (4.1)
Applying KVL for the circuit of port 2 of VNA and the receiving probe,
50 Z2 j L2 I2 j M 2I x 0 (4.2)
Finally, applying KVL for the coupled circuit loop,
Ix r j L ZR // ZC2 ZPS // ZC1 ZDUT j M1I1 j M 2I2 0 (4.3)
Substituting (4.1) and (4.2) into (4.3) and eliminating I1 and I2 leading to:
I x r j L Z R // ZC 2 ZPS // ZC1 Z DUT VM 1 I x ZM 1 ZM 2 0 (4.4)
where
M 2 2 j M1V1 1 M 2 VM1 , ZM1 and ZM 2 50 Z1 j L1 50 Z1 j L1 50 Z2 j L2
VM1 is the induced signal source into the circuit loop from the injecting probe, and
ZM1 and ZM2 are the reflected impedances from the injecting and receiving probes into the circuit loop respectively. With these reflected signal source and impedances into the circuit loop, the equivalent circuit in Fig. 52 can be reduced to that in Fig. 53, and the resultant induced current into the circuit loop is given by:
VM 1 I x (4.5) ZM 1 ZM 2 r j L Z R // ZC 2 ZPS // ZC1 Z DUT
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L ZR//ZC2 Ix r
ZM2
ZDUT ZM1
+ VM1 _ ZPS//ZC1
ZSetup
Figure 53 : Simplified equivalent circuit for the measurement setup
Similar to the derivation from Chapter 3, the unknown impedance ZDUT can be obtained with equation (4.6):
kV1 ZDUT Zsetup (4.6) V2 where
Zsetup ZM1 ZM 2 r j L ZR // ZC2 ZPS // ZC1
The ratio of V2 and V1 can be easily measured with the VNA. To obtain the two
unknown k and Zsetup, we have to perform a pre-measurement calibration process
before the actual measurement of ZDUT. By replacing ZDUT with a short circuit (ZDUT
= 0 ) and a known precision standard resistor Rstd ( ZDUT = Rstd ), k and Zsetup can be obtained using the procedure describe in Chapter 3. A precision standard 51
SMT resistor is chosen as Rstd.
Once k and Zsetup are found, the measurement setup is ready to measure ZDUT using
(4.6). The magnitudes of Zsetup and k of the test jig versus frequency up to 1 GHz are determined and plotted in Fig. 54 and Fig. 55 respectively.
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Fig. 54 shows that Zsetup is very low and resistive in nature until about 100 MHz,
where the inductive effect (equivalent series inductances of C1 and C2 and the inductance of the coupled circuit loop) of the measurement setup begins to kick in. Based on the impedance magnitude versus frequency above 100 MHz, it is found that the total equivalent inductance due to the setup is about 5 nH. With this
known Zsetup, the effect due to the measurement setup can be eliminated later
while determining ZOUT.
100 p u t e s Z ) f o m 10 h e d O ( u t i n g a M
1 1 10 100 1000 Frequency (MHz)
Figure 54 : Magnitude of Zsetup versus frequency
Fig. 55 shows that k remains nearly constant at 1 up to 200 MHz and increases with
frequency above 200 MHz. From Chapter 3, it is known that k = j M1ZT2/(50 + Z1 +
j L1), i.e. k is the ratio of j M1ZT2 and the impedance of the primary circuit of the
injecting probe. The transfer impedance of the receiving probe, ZT2 = 5 and stays constant from 500 kHz to 1 GHz, as given in the CT6 probe datasheet. Hence,
j M1ZT2 is directly proportional to . The injecting current probe is basically a transformer with multi-turn primary and single turn secondary. The relatively high inductance of the primary coil of the probe causes the impedance in the primary
circuit to be dominated by j L1. As both the terms j M1ZT2 and j L1 are proportional
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to , k becomes a frequency-independent constant. However as frequency increases above 200Mhz, the effect of the parasitic capacitance of the primary coil of the injecting probe begins to show its effect and its impedance in the primary circuit will
be dominated by the 50 . Hence k will be the ratio of j M1ZT2 and 50 , which becomes frequency dependent and increases with frequency.
10 ) m h O ( K f
o 1 e d u t i n g a M
0 1 10 100 1000 Frequency (MHz)
Figure 55 : Magnitude of k versus frequency
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4.4 Resistor Measurement Results
For validation purposes, several selected known precision resistors are treated as unknown DUT and measured using the proposed measurement method. The following three sets of measurements are conducted for validation purposes. These include:
Nominal impedance measurement at 1MHz; Full frequency range impedance response; and Impedance response with varying DC biasing.
4.4.1 Nominal Impedance Measurement The impedance of each of these resistors is measured at 1 MHz using the proposed method without applied DC biasing. The same resistors are also measured directly with a HP 4192A LF Impedance Analyzer (100 kHz to 13 MHz), which is capable of measuring a wide range of resistance between 1 and 1 M with a resolution of 0.01% of the full-scale of the selected range [98]. The comparison of measured impedance using both methods is given in Table 1. The deviation is found to be less than 3.5 % for a wide range of resistors from 30 to 2 k .
Table 1 : Comparison of measured impedance of resistors at 1 MHz
Stated Value of Measured with Measured with Deviation Resistor ( ) HP4192A ( ) Proposed Method ( ) 30 1% 30.35 30.31 -0.1% 51 1% 50.89 50.24 -0.7% 100 1% 100.5 96.85 -3.4% 220 1% 222.0 227.15 +2.3% 510 1% 512.0 504.24 -1.5% 1K 1% 1002.0 1030.3 +2.8% 2K 1% 2007.0 1954.8 -2.5%
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4.4.2 Full Frequency Range Impedance Response For the complete impedance characterization up to 1 GHz, the impedance versus frequency using the proposed method for two precision resistors (30 and 220 ) without DC biasing is measured. Measurement setup is shown in Fig. 56(a). For comparison purposes, the two resistors are measured again using a HP4396B impedance analyzer (bandwidth 1.8 GHz) together with a HP 43961A RF Impedance Test Kit and the HP16194A Component Test Fixture. The integrated instrumentation setup is shown in Fig. 56(b).
(a) (b)
Figure 56 : Impedance profile characterisation validation (a) propose two probe test setup and (b) instrumentation setup using Impedance analyzer
Fig. 57(a) and Fig. 57(b) show the comparison of the two methods which clearly correlates well to the high frequency behaviour of a typical non-ideal resistor. Good agreement is observed between the two methods. The inductive behaviour of the 30 resistor is expected, which is inherent for low-resistance resistor. For larger resistor, the parasitic capacitance will cause the dip in the impedance at higher frequency, which is more significant in larger value resistance.
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30 Resistor (No DC Biasing) 80 300
270 70 e 240 d u
t 60 i 210 ) n e e g
180 r
) 50 a g M m 150 e h d e
40 ( c O
( 120 e n s a 30 90 a d h e P p 20 60 m I 30 10 0
0 -30 1 0 0 0 1 0 0 1 0 1 Frequency (MHz) Tw o-probe Technique (Phase) Tw o-probe Technique (Magnitude) HP4396B Impedance A nalyzer
(a)
220 Resistor (No DC Biasing) 350 360
300
e 270 d u )
t 250 i e n e r g 180 g ) a 200 e M m D h ( e c O e
( 150 n 90 s a a d h e
100 P p
m 0 I 50
0 -90 1 0 0 0 1 0 0 1 0 1 Frequency (MHz) Tw o-probe Technique (Phase) Tw o-probe Technique (Magnitude) HP4396B Impedance A nalyzer
(b)
Figure 57 : Comparison of impedance versus frequency (a) 30 and (b) 220 resistor
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4.4.3 Impact of DC Biasing on the Impedance Response To demonstrate the useful feature of the proposed two-probe approach, the resistor is placed under a specific DC biasing condition and measurement taken to study the effects of the DC biasing on the impedance frequency response. For subsequent analyses, only the magnitudes of the impedance of the resistors will be shown, as the phases remain relatively unchanged. The 220 resistor is chosen as the component for demonstration purposes. Its impedance under no biasing, 5 mA and 15 mA biasing are measured up to 1 GHz and shown in Fig. 58. As expected, the DC biasing current has practically no impact on the impedance response of the resistor.
Figure 58 : Impedance versus frequency of a 220 resistor under various biasing conditions (0 mA, 5 mA and 15 mA)
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4.5 Inductor Measurement Results
For further validation, a set of inductors was measured using the same two probes approach. Using the same in-house developed test jig, three sets of measurements are conducted on each passive inductor as follows:
Nominal inductance measurement; Full frequency range impedance response; and Impedance response with varying DC biasing.
4.5.1 Nominal Inductance Measurement A set of axial inductors (ASJ 1315 series, moulded, wire wound, ferrite core) were measured using the two probes approach. The inductance can be obtained from the measured impedance well below the self-resonant frequency. Hence, for comparison purposes, the inductance of each inductor is calculated based on the measured impedance at 2 MHz. The calculated inductance will be compared to that obtained using the HP 4192A LF Impedance Analyzer (100 kHz to 13 MHz). Table 2 shows the comparison and the deviation is within 10%. The current probe (CT6) has lower roll-off frequency response around 2 MHz (see Fig. 45). For larger value inductors, the self-resonant frequency is lower and closer to the 2 MHz measurement limits of the CT6 probe, hence higher deviation is expected. However for smaller inductance (< 47 uH) with higher self-resonant frequency which is further away from 2 MHz,, the measured inductance is more stable and the deviation is around 5%.
Table 2 : Comparison of measured impedance of inductors at 2MHz*
s/n Ref Measured L Using Measured L using Accuracy HP 4192A ( H) two probes setup ( H) 1 L250u 275.3 303.4 10.21%
2 L150u 155.5 149.6 3.79%
3 L100u 97.1 104.7 7.80%
4 L47u 48.0 50.7 5.62%
5 L22u 23.8 22.6 5.04%
6 L2.2u 2.46 2.32 5.60%
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4.5.2 Full Frequency Range Impedance Response For validation purposes, the proposed method is used to measure a 2.2 H inductor (ASJ 4425-10K, moulded, wire wound, ferrite core, and 10% tolerance) without DC biasing. This inductor is chosen as it has a higher self-resonant frequency so that its impedance behaviour across a wide frequency range can be observed. The inductor is measured with the HP4396B impedance analyzer (bandwidth 1.8 GHz) together with a HP 43961A RF Impedance Test Kit and the HP 16194A Component Test Fixture. The comparison using both methods is shown in Fig. 59, with close agreement between the two methods. Both measurement methods show clearly, a self resonant frequency of around 200 MHz.
2.2uH Inductor 100000 540
450 10000 360 ) ) e m e h
270 r 1000 O g ( e e d
180 ( d u e t i 100 s
n 90 a g h a P
M 0 10 -90
1 -180 1 10 100 1000
Tw o-probe Technique (Phase) Frequency (MHz) Tw o-probe Technique H(MPa4g3n9i6tuBd Iem)pedance Analyzer
Figure 59 : Comparison of impedance versus frequency of a 2.2 H inductor
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4.5.3 Impact of DC Biasing on the Impedance Response of the Inductor In general, ferrite core inductor s impedance characteristic can be affected by the DC biasing when the biasing current becomes too high. The proposed method is employed to study the impedance behaviour of an inductor with varying DC biasing. Two inductors, 250 H and 47 H (ASJ 1315 series, moulded, wire wound, ferrite core and 5%) are selected for validation purposes. For subsequent comparisons, only the impedance magnitude will be shown. The measured impedance for 250 H and 47 H inductors under three different biasing conditions (0 mA, 5 mA and 15 mA) are presented in Fig. 60(a) and Fig. 60(b), respectively. The measured results show clearly that the impedance behaviour does not change much for no biasing and 5 mA biasing. However, when the DC biasing current increases to 15 mA, both inductors suffered significant drop in impedance, which is a clear indication of core saturation of the inductors. Hence, the ability to detect changes in the impedance characteristic of a component under varied biasing condition using the two-probe method has been demonstrated.
250uH Inductor 30000
) 25000 m h O ( 20000 e d u t i 15000 n g a
M 10000 e c n
a 5000 d e p 0 m I
-5000 0 1 0 0 1 0 0 1 0 1 Frequency (MHz) No Biasing 5mA Biasing 15mA Biasing
(a)
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47uH Inductor
3 000 0 )
m 2 500 0 h O (
e 2 000 0 d u t i 1 500 0 n g a
M 1 000 0 e c
n 500 0 a d e
p 0 m I -500 0 1 0 0 0 1 0 0 1 0 1 Frequency (MHz) No Biasing 5mA Biasing 15mA Biasing
(b)
Figure 60 : Impedance versus frequency of an inductor under various biasing conditions (0 mA, 5 mA and 15 mA): (a) 250 H (b) 47 H
In conclusion, the proposed in-circuit measurement method has demonstrated its ability to measure the impedance of any passive component under it in-circuit operating condition with different biasing conditions over a wide frequency range. As expected, the biasing current has little influence in the impedance behaviour of a resistor, which is basically a linear device. However, for a passive component that exhibit non-linear behaviour, for example, a ferrite-core inductor, the impedance can vary under different biasing conditions. The measured impedance results in Section 4.5.3 has demonstrated that the impedance of the ferrite-core inductor changes significantly with differential biasing currents. This allows a designer to perform component sensitivity analysis due to a new part changes for an existing design. Any significant impedance deviation from the original component part enables the designer to ensure the correct selection of component in the circuit, so as to avoid unwanted deviation or drift in functional specifications. For example, the impact of the change of an inductor part on a filter s response under a specific DC biasing condition.
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hapter 5
5.0 MEASUREMENT OF ACTIVE DEVICE IMPEDANCE FOR SI ANALYSIS
The concept of transmission line, reflection and techniques for impedance matching are discussed. With the help of lattice diagram, we explain why signal distortion in a form of ringing is observed and why do we need to perform termination for impedance matching. The two-probe approach is extended to the characterisation of the output impedance of active clock drivers to understand its impact on the selection of the output series terminations for optimal SI performance. The two-probe approach will be employed to characterise the output impedance of a clock driver so that appropriate series termination can be selected systematically [118].
5.1 Transmission Line, Reflections and Impedance Matching
As mentioned in Chapter 1, the importance of interconnects termination designs in high-speed digital design is crucial for SI performance. With integrated circuits (ICs) operating at much faster edge rates (<1ns), PCB trace behave likes transmission lines and proper terminations to ensure good impedance matching become indispensable for functional reliability in high-speed digital systems. Excessive and prolong overshoot can damage devices, and together with undershoot, they cause eye closure in the eye diagram, which can lead to intermittent data error or false triggering.
5.1.1 Transmission line In transmission line behavior, reflections at impedance discontinuity give rise to signal degradation often looks like ringing. In today tight noise margin, if the ringing is severe enough, when the undershoot at high level goes below the threshold or when the overshoot at low level bounce above the threshold, this will cause intermittent and false triggering which is highly undesirable.
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Figure 61 : A 10MHz clock signal measured at a mismatch transmission trace.
Hence to prevent reflections and signal distortion due to impedance mismatch or discontinuity, its important to control the PCB board trace impedance often know as impedance control board which is fast becoming a requirement instead of a mere good to have, due to the its growing important in high speed design. Termination is also becoming an important to maintain the constant impedance seen by the signal as it travels down the transmission line and to prevent undesirable reflections.
5.1.2 Transient Reflections In transmission line theory, two important concepts when a signal travels down a transmission line, part of the signal is transmitted and when impedance mismatch occurs, part of the signal is reflected. This transmission and reflection is function of load and source impedance. Referring to Fig. 62, the source impedance of a signal
source is Rs, the load impedance of a receiver is RL and the transmission line of
characteristic impedance of Zo connects the source and the receiver.
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Signal Source Receiver Characterisatic Impedance Zo RS Transmission line
RL
Figure 62 : Typical signal source, driving a receiver through a transmission line
Let the magnitude of the transmission line propagation function to be Hx. When a step
voltage of magnitude Vo is applied, the initial value of the signal at the input of the transmission line, using voltage divider rule is:
Z0 VINITIAL V0 (5.1) RS Z0
As the signal propagates down the transmission lines, it is attenuated and distorted
(phase shift) by the line propagation function, Hx which is defined as
X R J L G j C 1 / 2 H X e (5.2)
Voltage reflection coefficient at load side describes the fraction of the voltage signal that is reflected back to the source and is defined as:
RL Z o L (5.3) RL Z o
Voltage transmission coefficient describes the fraction of the incident signal voltage that is transmitted through the interface into the load and is defined as:
2RL L 1 L (5.4) RL Zo
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The reflected signal is again attenuated by Hx as it travels back to the source and the source end reflection coefficient describes fraction of the voltage signal reflected back to the load end again as follows:
RS Zo S (5.5) RS Zo
The strength of the first signal emerging from the load side is obtained as follows:
VTx0 Vinitial H X (1 L ) (5.6)
The second signal reflected off the source to emerge back at the load is given by:
2 VTx1 Vinitial H X [H X L S ](1 L ) (5.7)
Subsequently, the emerging signals are characterize by:
2 N VTxN Vinitial H X [H X L S ] (1 L ) (5.8)
The equation at the load after N reflections is obtained by summation of all the emerging signals and the closed form equivalent for this infinite geometric series is:
Vinitial H X (1 L ) V 2 (5.9) 1 H X L S
Howard W. Johnson, High Speed Digital Design A handbook of Black Magic ; Chapter 4, page 160-164.
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5.1.3 Lattice Bounce Diagram To illustrate that without proper terminations, the effects of transient reflections as a result of mismatch will cause signal distortion in the form or ringing as describe in 5.1.2 will occurs, the transmission line lattice bounce diagram is use here. In a typical real world example, a source impedance of 10 and high impedance at the load side as most typical input of CMOS circuit are high in impedance. Together we design the PCB stack-up and trace width such that we have a characteristic impedance of 50 .
RL Zo 50 L 1 (5.10) RL Zo 50
RS Zo 10 50 S 0.667 (5.11) RS Zo 10 50
Z0 50 VINITIAL V0 (1V ) 0.833V (5.12) RS Z0 10 50
s= -0.667 L= 1
Signal Source Receiver
TD = 1ns, Zo= 50 RS Transmission line 10 RL
1V 0.833V
V=0.833+0.833=1.667V
0.833V
-0.558V
V=1.667-0.558-0.558=0.551V
-0.558V
0.3707V
V=0.551+0.3707+0.3707=1.2924V
0.3707V
Figure 63 : Lattice diagram illustrating the effects of signal multiple reflections
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Using a 2ns rise time as in typical older slow speed digital design, 1V input step source at 10 MHz, over a 50 transmission line with 0.5ns delay. Simulated results in Fig. 64 illustrates the ringing (< 10%) is not a concern even if mismatch occurs. No termination is required.
Figure 64 : Simulated signal at the receiver at the far end of the transmission load side using 2ns rise-time without termination
However, in today s high speed operations, the rise time in order of pico-second. When using a 0.1ns rise-time, the ringing effects as describe in 5.1.3 earlier becomes obvious and severe (>60%), which is unavoidable if no terminations are used.
Figure 65 : Simulated signal at the receiver at the far end of the transmission load side using 0.1ns rise-time without termination.
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With the same 0.1ns rise-time, 0.5ns delay, 50ohm characteristic impedance and source impedance of 10ohms, when the appropriate source series termination (40 elected in this simulation) is used, the simulation in Fig. 66 shows that the ringing effects can be control and reduce significantly thus improve the signal integrity. Hence showing the importance of termination in high speed design to avoid signal distortion.
Figure 66 : Simulated signal at the receiver at the far end of the transmission load side using 0.1ns rise-time with source matched termination.
5.1.4 Impedance Matching Technique To control the reflections, termination can be performed either at the load side known as end termination or at the source side known as source termination.
a) Matching at the Receiver If the impedance of the receiver is match to the transmission line characteristic impedance, then the reflection coefficient at the load is zero. Effectively, this eliminates the first reflection the moment the signal travels down the transmission line and hit the load termination and this requires the following condition.
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Rreceiver Zo => L 0 (5.13)
The above is true when the load is match to the transmission line. Matching at the
receiver can be easily done. For example, simply by putting a shunt resistor (RShuntR)
with value equal to the characteristic impedance (Zo) as shown below.
Signal Source Receiver Zo=50 ohms RS
RShuntR, RL
ZRCV
Figure 67 : Example of an end termination circuit
Since the typical input impedance of most CMOS IC input are high impedance, much higher than the matching shunt resistance, the combine parallel impedance at the load will be equal to the shunt resistor which is equal to the characteristic impedance.
RShuntR RL RL >> RShuntR ; Z RCV RShuntR Zo (5.14) RShuntR RL
Hence the effective load reflection coefficient becomes:
ZRCV Zo Z0 Zo L 0 (5.15) ZRCV Zo Z0 Zo
To estimate the signal rise time for a typical capacitive load, assuming no reflections occurs due to load termination, the signal response due to the transmitted signal from Eqn. 5.4 is
2Z L ( ) V ( ) 1 L ( ) Z L ( ) Zo ( ) 2 (5.16) Z ( ) 1 o Z L ( )
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Since receiver load impedance ZL is composed of the parallel impedance of the
terminator resistor RShuntR and the input capacitance of the receiver with a value of C,
1 1 Z L ( ) Zo // X C j C (5.17) ZL Zo
Substituting equation 5.17 into equation 5.16 2 V ( ) 1 1 Zo j C Zo 1 (5.18) Z 1 j o C 2
Hence, for a capacitive loaded end termination, the above shows that of a simple RC
filter response with a time constant of (Zo/2)C.
Problems with load terminations: For end terminations, the driving signal propagates at full intensity directly all the way down the transmission line and all reflections are damped by the terminating resistor. Most TTL and CMOS logic gates may not have sufficient current to drive these end terminators.
At steady state, the impedance seen by the source reduces from RL to RShuntR=Zo 2 (since RL>RShuntR). This increases loading resulting in greater current and I R losses leading to higher power consumption for such termination scheme which is critical consideration in today low power and battery operated environment. Assuming the
transmission line is not so long that it disperses the signal, so we can let Hx to be unity. Hence, at steady state receiver voltage magnitude also reduces as follows:
Vinitial H X (1 L ) Z0 VRCV 2 Vinitial H X V0 (5.19) 1 H X L S RS Z0
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b) Matching at the Source If the impedance of the source is match to the transmission line characteristic impedance, then the reflection coefficient at the source is zero. Hence this effectively eliminates the reflected signal back towards the source which is damped at the source termination. This requires the following condition;
ZSource Z o ; S 0 (5.20)
One of the most common methods of source matching is to insert a series matching
resistor RSeries at the output of the driver as follows:
Signal Source Receiver Zo=50 ohms RS RSeries
RL
ZSource
Figure 68 : Example of a source termination circuit
The series matching terminator RSeries is set such that the combine impedance looking into the source, the series terminator (Rseries) together with the source internal series
resistance (Rs), to be equal to the transmission line characteristic impedance Zo.
ZSource RSeries RS Zo (5.21)
Hence, the effective source reflection coefficient ( s) will becomes zero as follows:
ZSource Zo Zo Zo S 0 (5.22) ZSource Zo Zo Zo
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When driving a receiver which is typically a high impedance and capacitive in nature
with a value of C. Looking back to the source, we see a drive impedance equal to Zo. We would get a response the looks like a simple RC low pass filter with a RC time constant
RC Time constant = ZoC; For a 10-90%, the rise time of the RC filter
T10-90 = 2.2 Req Ceq
T10-90 = 2.2 Zo C (5.23)
Hence, when capacitively loaded in most digital circuit receiver, the rise time is twice
as long as the end terminated circuit whose Req is = Zo//RShuntR = Zo/2. With slower rise time, usually smaller residual reflections that the end termination.
The driving waveform is cut half by the series termination before propagating into the
transmission line at half intensity. At the receiver far end, a typical CMOS circuit (RL is large or behave like a open circuit), the signal load reflection coefficient would be ~ +1. Hence the incoming half voltage together with the half voltage reflected at the receiver will bring the instantaneous voltage to a full level.
At steady state, the impedance seen by the source is ZL which is typically high impedance for most CMOS circuit. The current requires is therefore much lower and hence lower power dissipation. The steady state voltage across the receiver would be almost equal to the full input driving signal without any reductions.
VRCV Vo (5.24)
Reason for Series Terminations Selection Source terminator as shown have a slower rise time, smaller residual reflections, lower power consumption and full receiver voltage compared to the end terminator, hence the reason for its popular applications.
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It is often easier to eliminate reflections at the source which is typically resistive (with a little inductance), while mismatch cause by capacitive load when attempting end termination are often worse and complex. Typically source termination, if terminated correctly, will yield near zero reflection coefficient as compared to the end terminator, leading to flatter overall frequency response .
5.1.5 Challenges in Source Matching
Source impedance matching requires the driver internal resistance Rs together with the series terminator must match the transmission line characteristic impedance.
RSource RS Z o (5.25)
The question is how can we determine the device internal resistance (Rs) accurately?
Typical driver are has low output impedance but exact is unknown. Even TTL and CMOS circuit output impedance have slight different values in their High and Low states. Hence is always never easy to determine the correct source series terminator.
If we have a good model for the driver either SPICE, a good estimate of the output impedance can be extracted using simulations. However many times, the SPICE model is almost not available as critical design proprietary details of the buffers and latest information can be obtained. Instead a general SPICE model is often given instead which may not necessary be the best representation of the device.
As for IBIS, as describe in section 2.2.2, these are typical models suitable for general simulation and not suitable for high speed application. Often designer has to validate and modify the model for in-house usage but this is often costly and manpower intensive [75]. Still IBIS models for many devices are not readily available [70-72] and lack of accuracy for SI simulation [73-74] which has been the key problems with users.
Howard W.Johnson, High Speed Digital Design A handbook of Black Magic ; Chapter 6, page 233. Eric Bogatin; Signal Integrity Simplified , Prentice Hall, chp8, page 286-287.
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5.2 Measurement of Output Impedance of Clock Driver
As mentioned in Chapter 1, the importance of interconnects termination designs in high-speed digital design is crucial for SI performance. With integrated circuits (ICs) operating at much faster edge rates, proper terminations to ensure good impedance matching become indispensable for functional reliability in high-speed digital systems. Excessive and prolong overshoot can damage devices, and together with undershoot, they cause eye closure in the eye diagram, which can lead to intermittent false triggering. Much work in the area of interconnect terminations has been well reported in the 90s [99-102]. There were earlier works on mathematical models on transmission lines with resistive termination as early as the 60s [103,104].
When circuit designers deal with impedance matching, the main issue is that the IC electrical characteristic not only varies with manufacturing process but also changes significantly with operating conditions, such as supply voltage, operating frequency and temperature, leading to variation in the IC s output impedance [105]. Such variation poses challenges to the circuit designer to determine the appropriate value
of the termination impedance. Although on-chip termination [106-109] has been used to minimise the reflections, the implementation can be very complex requiring impedance control circuitries, optimised driver output design against process, voltage and temperature variation and not forgetting the difficulty in overcoming the effects of on-die resistor non-linearity. In most cases, typical circuit/board designers do not have the luxury of requesting such special features in the ICs that they used.
Due to its simplicity and ease of implementation, source series termination, where the IO driver output is matched to the PCB trace characteristic impedance to achieve optimised SI, is the most commonly adopted technique for impedance matching. It also has the advantage of no component between DC bus and ground. It is also less sensitive to physical series resistor placement as compared to parallel terminated circuits [110]. In source series termination design, the knowledge of the device output
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impedance is crucial in determining the precise value of a series resistor for impedance matching. It is very much dependent on the driver output impedance and the PCB trace s characteristic impedance. The trace impedance is a result of the PCB stackup design and is well controlled during fabrication and its value can be measured easily by means of a time domain reflectormeter (TDR) as shown in Fig. 69.
Figure 69 : TDR impedance measurement using Tektronix DSA8200 with P8018 TDR probe
However, the selection of the series terminator often requires trial and error process during the prototyping phase. As for the clock driver s output impedance, only the nominal or typical value is usually given and its accuracy is not guaranteed. Also the output impedance can vary with different operating conditions. Although IBIS models are available, they are not fully validated and users have to ensure their correctness before using them.
The in-circuit two-probe method provides a relatively simple, reliable and accurate means to determine the output impedance of an active device under its intended operating conditions. Accurate extraction of the device s output impedance at the actual operating condition allows precise selection of series resistor to match the device s output to the characteristic impedance of the connecting trace on the PCB.
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In this section, a practical case study of an actual clock driver and its output series termination selection will be used for demonstration purposes. The procedure to extract the output impedance of the clock driver will be described. The device output measurement results obtained using the two-probe approach will be used for the selection of correct source series termination. Finally, validation with the simulation results for optimised SI performance will be demonstrated.
5.3 Case Study on Series Termination Selection
In most high-speed clock circuit designs, impedance matching is crucial to ensure good SI performance. The choice of proper trace termination can be tedious and often requires several iterations to finalise the correct value to be used. In this case study, the selection of series termination for a high-speed clock driver circuit and its effect on the far-end receiver output waveform will be shown. Two clock drivers from the same manufacturer, one for the actual circuit and the other an alternative part replacement are chosen for the study. The two clock drivers chosen for the design are:
Texas Instrument 200 MHz clock buffer (CDCV304PW); and Texas Instrument 200 MHz PLL clock driver (CDCVF2505).
These two clock drivers are specifically chosen for two reasons. In terms of physical sizing, both parts have the same package type (8 pins TSSOP) with the same PCB footprint so that each can be a direct drop-in replacement for the other. In terms of electrical specification, both are capable of clocking up to 200 MHz. The output series termination is chosen such that the fastest rise and fall times are achievable without compromising on the overshoot or undershoot, which is set to be less than 20% (0.66V) of output steady state voltage of 3.3V.
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5.4 Clock Driver Circuit for Case Study Single ended clock distribution tree is commonly used in systems running on clock speed of less than 100 MHz. The clock circuit used in this case study is shown in Fig. 70(a), which is a typical point-to-point direct interface with series termination for impedance matching. It is part of a high-speed clock prototype developed to study the various high-speed design rules and techniques, such as stub effects, serpentine delay and termination. The fabricated FR-4 PCB for the clock circuit is shown in Fig. 70(b).
(a) Clock driver Series Resistor
(b)
Figure 70 : (a) Schematic of the application clock driver circuit (b) PCB layout
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With the clock driver CDCV304 in the circuit, a few values of series terminations are tested on the board. The measured receiver waveforms for three different values of
series terminations are shown in Fig. 71. The best value of Rs is selected based on the optimal signal integrity response that gives the fastest rise-time while keeping the overshoot within +/- 20% (0.66V). Based on the measured waveforms, though the 18 termination has the fastest achieve rise time, but the overshoot exceeds the 0.66V criteria. Instead, the 27 is found to be the best choice for series termination as the receiver waveform exhibits the optimal SI performance. Its rise time is as fast as that of the 18 termination while the overshoot is kept within specifications at 0.42V
CLK304: Comparison of Waveform at RCV
(Vin: 3V, fclock = 10 MHz)
4.5
3.5 )
V 2.5 ( e g a t l 1.5 Rs Risetime (ns) Overshoot (V) o V 18ohm 1.81 1.05
0.5 27ohm 1.92 0.42 36ohm 2.43 0.40
-0.5 -10 -5 0 5 10
Time Scale (ns) 18 ohms 27ohms 36 ohms
Figure 71 : Waveform at the receiver end of the transmission line with CDCV304PW
However, when the clock driver is replaced with the alternative replacement part (CDCVF2505), it is found that termination between 22 30 are no longer providing similar SI performance as the rise time are degraded. Instead, the 10 series termination provides the most optimal SI performance as shown in Fig. 72 with the fastest achieved rise-time and yet the overshoot stays within the limits.
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CLK2505: Comparison of Waveform at RCV
(Vin: 3.3V, fclock = 10 MHz)
4.5
3.5
2.5 e g a t l
o Rs Risetime (ns) Overshoot (V)
V 1.5 10ohm 1.81 0.52
0.5 22ohm 1.93 0.39 30ohm 2.43 0.24
-0.5 -10 -5 0 5 10
Time Scale (ns) 10 ohms 22 ohms 30 ohms
Figure 72 : Waveform at the receiver end of the transmission line with CDCVF2505PW
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5.5 Extraction of Clock Driver Output Impedance
To investigate the difference in the series termination values for the two seemingly similar clock drivers, the two-probe method will be used to extract the output impedance of the clock driver under its in-circuit operating conditions. As the current probes do not require direct electrical contact to the clock driver, the proposed method minimises the loading effect and disturbances to the clock driver circuit. Also, with a pre-measurement characterization process, the method has the ability to eliminate measurement error contributed by the measurement setup as mentioned in Chapter 3.For the measurement result, only the impedance magnitude will be shown. The measurement setup to extract the output impedance of the clock driver is shown in Fig. 73.
Vcc Arbitrary Function Generator (AFG) (AFG3000)
Vector Network Analyzer (VNA) (R&S ZVB8)
Vcc VDD-6 OE-2
SMA-P1 ZOUT CKIN-1 1Y1-5
W2 ~ GND-4 R
Port1
Port2 .
Figure 73 : Measurement setup to extract the output impedance of the clock driver
The setup consists of two identical current probes (Model: Tektronix CT-6, bandwidth 500 kHz to 1.5 GHz) coupled to the output of the clock driver circuit inductively without direct connection. Both probes are connected to a Vector Network Analyzer (Rohde & Schwarz ZVB8 bandwidth 150 kHz-8.5 GHz). Port 1 of a VNA injects an AC signal into the clock driver output circuit through the injecting probe and port 2 of the VNA measures the resulting coupled signal in the same output circuit through the receiving probe. By reflecting the impedances of the current probes to the output circuit loop, the equivalent circuit of the output circuit loop is given in Fig. 74.
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Figure 74 : Simplified equivalent circuit of the two probe measurement setup
ZOUT is the output impedance of the clock driver to be determined, ZM1 and ZM2 are the reflected impedances of the injecting and receiving probes into the clock driver
output circuit loop respectively. VM1 is the induced signal voltage in the loop from the output signal source of port 1 of the VNA. R is a resistor (47 ) to emulate the output circuit termination to the device and is chosen according to the actual circuit operating condition. L and r are the effective clock driver loop inductance and resistance at the clock driver output circuit respectively.
Based on the same techniques described in Chapter 3, the resultant current flowing in the coupling loop due to the injecting signal is given by:
VM 1 I (4.7) R ZM1 ZM 2 r j L ZOUT
Since only the impedance of the clock driver (ZOUT) is of interest, the other impedances in the circuit loop due to the measurement setup are grouped together as
Zsetup = R + ZM1 + ZM2 + r + j L. Then, equation (4.7) can be simplified as follows:
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VM 1 I (4.8) Zsetup ZOUT
The unknown output impedance of the driver ZOUT under in-circuit condition can be determined using the following equation.
kV1 ZOUT Zsetup (4.9) V2
By replacing ZOUT with a known precision standard resistor Rstd (ZOUT = 50 ) and
then with a short (ZOUT = 0 ) during the pre-measurement calibration process, the
impedance introduced by the measurement setup can be eliminated. Once Zsetup and k are found using (3.18) and (3.19), respectively; the measurement setup is ready to
measure the unknown output impedance of the clock driver, ZOUT.
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5.6 Clock Driver Output Impedance Measurement Results For the extraction and validation of the clock driver output impedance, a test circuit is developed and fabricated as shown in Fig. 75. With the test circuit, the output impedances of the CDCV304 and CDCVF2505 clock drivers will be extracted.
Since the two clock drivers have the same PCB footprint, only a PCB test jig is needed. It will be shown later that both devices though look similar, have very different output impedance. Hence, the designer has to be prudent to select the proper output series termination value for matching purposes. The in-circuit measurement setup for the clock driver under test is shown in Fig. 75.
Vcc U1:CDCV304
Vcc 6 VCC To Oscilloscope Clock Input 2 Tline: 6", Zo=50ohms SMA-P2 SMA-P1 OE-2 5 R1 R5 1 1Y1 CKIN 4 W2 GND R2
W3 W4 For CT6 Probes
Figure 75 : Schematic of the clock circuit test prototype
Fig. 76 shows the fabricated FR-4 printed circuit board (PCB) to be mounted with the clock driver to emulate the actual in-circuit operating condition. A jumper (W2) at the input of the clock driver allows it to activate static logic High or Low logic level. The SMA connector to the input (SMA-P1) allows an external clock signal for continuous logic changes. The clock output pin connects to a resistor pad (R1) for series source termination prior to the 6 inch, 50 microstrip. Provision for a direct load (R2) whose value is very closed to the actual driver output loading is chosen. In our case, a 47 is selected. Two jumper pads (W3 & W4) are catered for insertion of the CT6 probes to measure the clock driver s output impedance. The zoom in view of the measurement setup with the current probes is shown in Fig. 77.
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Clock driver pin out
Clock Output Series termination Bypass Load r esistor for o/p characterization
Tek CT6 p robe for Output characterization
Figure 76 : PCB layout of circuit under test for CDCV304PW
Receiving CT6 Probe P2
Injecting CT6 Probe P1 External Clock Input
TI CDCV304 Clock Buffer
Figure 77 : Actual two probe measurement test setup with device 1: CDCV304PW.
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In general, the procedure mentioned in Chapter 3 is adopted with some slight variation. In order to extract the impedance of the clock driver output before the series
termination R1 prior to its connection to the transmission line, the test circuit
incorporated an additional connected load resistor R2. The value of R2 is chosen such that it emulates the actual circuit load termination, which in this case is the 50
oscilloscope at the far end of the transmission line. The load resistor R2 must be
placed very close to the series termination R1 so as to characterise the driver as close as possible to the point of interface, as shown in Fig. 78.
Vcc U1:CDCV304 Vcc 6 VCC Clock Input 2 SMA-P1 OE-2 5 R1 R5 1 1Y1 CKIN 4 W2 GND R2
W3 W4 For CT6 Probes
Figure 78 : Pre-calibration setup to characterise the clock driver device 1: CDCV304PW.
For the the pre-measurement calibration process, R1 is removed and only the clock
driver output and R2 is connected. By the same calibration procedure using 0 (direct short) and 50 standard resistor in place of the clock driver output, the two
unknown, k and Zsetup can be found in this calibration process.
The magnitudes of Zsetup and k versus frequency up to 1 GHz are given in Fig. 79 and
Fig. 80, respectively. Fig. 79 shows Zsetup is nearly constant at 47 (dominated by
R2) but at about 600 MHz, the loop inductance of the output loop of the clock driver begins to kicks in. Based on the Zsetup measurement, the inductance is found to be around 20 nH. From Fig. 76, the circuit loop inductance consists of 18 mm of the PCB trace length, two 5 mm conductors for the placements of current probes and the
equivalent series inductance of R2. The PCB trace is designed to have a characteristic impedance of 50 with a trace width of 2 mm, trace thickness of 0.0356 mm and trace height of 1 mm. The 18 mm trace length works out to be 5.36 nH. The inductance of each 5 mm conductor is found to be 2.5 nH and the equivalent
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series inductance of the resistor (from the manufacturer data sheet) is 9.12 nH. The total resultant inductance is 19.48 nH, which agrees rather well with the earlier estimated value of 20 nH from the measured Zsetup.
1000
~ 47 p
u 100 t e s Z ) f o m h e d O ( u t i
n 10 g a M
1 1 10 100 1000 Frequency (MHz)
Figure 79 : Magnitude of Zsetup versus frequency
Similar to the explanation in section 4.3 for Fig. 55, Fig. 80 here shows that k remains constant at 1 and becomes frequency dependent above 800 MHz due to the effect of parasitic capacitance of the primary coil of the probe.
100 ) m
h 10 O ( K f o e d u t i n
g 1 a M
0 1 10 100 1000 Frequency (MHz)
Figure 80 : Magnitude of k versus frequency
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With the values of k and Zsetup determined, the setup is ready to measure the output impedance of the clock driver. The circuit is first characterised under static condition with input kept at 3.3V logic High and then at OV logic Low. The input is driven by a 1 MHz clock. The results are shown in Fig. 81(a). Next the circuit operating in a dynamic mode with input now excited by a 10 MHz clock signal, the measured output impedance of the clock driver for CDCV304PW is found to be around 23 , as shown in Fig. 81(b).
This is in line with the value of the typical impedance of the CDCV304 LVCMOS output [114] of around 20 . Above 700 MHz, the clock driver output impedance exhibits inductive behaviour. Based on the measured impedance of 50 at 1 GHz as shown in Fig. 81, the estimated inductance is about 4.3 nH, which is the typical lead frame and wire bonding inductance to be expected. Hence, to match with the 50 microstrip line, the output series termination resistor of around 30 is recommended. In our case, since the measured output impedance was found to be 23 , the series termination of 27 will provide best impedance matching to the microstrip line for optimal SI performance.
Clock Driver Output Impedance Response (CDCV303PW) Static High, 1MHz and Static Low 1000 ) s 100 ~ 28 ~ 23 m h o ( e d u t i n g
a 10 M ~ 19
1 1 10 100 1000 Static High '3V' Frequency (MHz) 1 MHz Static Low '0V'
(a)
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Clock Driver Output Impedance Response CDCV304PW 1000 ) s
m 100
h ~ 23 o ( e d u t i n
g 10 a M
1 1 10 100 1000 Frequency (MHz)
(b)
Figure 81 : Measured clock driver output impedance for CDCV304PW (a) Static high, Static low and 1 MHz and (b) Dynamic, 10 MHz
However, the measured output impedance for CDCVF2505 is found to be 45 , as shown in Fig. 82, which is nearly two times larger that that of CDCV304PW. This is due to the additional internal 25 output resistance of the clock driver. Based on the measured impedance of 196 at 1GHz, the estimated inductance is 24 nH which is
much higher than the CDCV304PW. This is the additional inductance to be expected due to the added equivalent series inductance of the embedded series resistor. The output impedance stays constant at 45 and increases with frequency above 300 MHz due to the inductive effect of the internal output resistance, which is rather common for small-value resistor.
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Clock Driver Output Impedance Response CDCVF2505 1000 )
s ~ 45
m 100 h o ( e d u t i
n 10 g a M
1 10 100 1000
Frequency (MHz)
Figure 82 : Measured clock driver output impedance (device 2: CDCVF2505)
The datasheet of CDCVF2505 clock driver shows an additional embedded output series resistor of 25 [115]. Further search on the manufacturer website [116] shows a more detailed output characteristic of the CDCVF2505 clock driver as shown in Fig. 83. The estimated total output impedance is approximately between 37 and 40 . Based on the actual measured clock driver output impedance of 45 , a series termination of around 5-10 would provide the best matched condition to the microstrip line.
Figure 83 : CDCVF2505 clock driver output structure and impedance [116]
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5.7 Validation with Simulation Results
The clock driver circuit will be simulated using Computer Simulation Technology Microwave Studio (CST-MWS) and Design Studio (CST-DS). The IBIS models of both clock drivers are obtained from manufacturer website while the layout of FR-4 printed circuit boards (PCB) will be imported into CST simulation environment in Gerbel format. The simulated circuit shown in Fig. 84 consists of the clock driver, the source output series terminator (R1) and a 6 50 transmission line. The far-end load termination of the transmission line consists of a 3 pF capacitor in parallel with a 40 k resistor emulating the Tektronix TAP3500 probe loading.
Clock Driver output Emulating the Tektronix series terminator R1 TAP3500 probe
6 Microstrip
Figure 84 : CST-DS IBIS transient simulation setup
With the IBIS model and Gerbel imported to the CST time-domain simulator, a parameterised sweeps on the output series terminator RS across a range of values from 10 to 30 for CDCV304 and 0 to 20 for CDCVF2505 are performed. The output overshoot behaviour at the receiver end is simulated and shown in Fig. 85.
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(a) (b)
Figure 85 : Parametric sweep on Rs simulation (a) CDCV304 and (b) CDCVF2505
The simulated results are consistent with the measured results shown previously. Both simulated and measured results indicate clearly that although the clock drivers look similar, but their output impedances can be significantly different. Therefore, when the same series termination resistor is used, the SI performance can be drastically different. For CDCV304, the output resistance is around 25-30 and hence an output source series termination resistor of value 30 is a good choice. However, it is not suitable for CDCF2505, which contains an integrated output series resistor of 25 making the total output impedance to be around 40 [116]. Hence, the source series termination resistor should be changed to 10 instead for optimal SI performance.
The practical case study in this section has demonstrated the ability to extract the output impedance characteristic of the clock driver under its intended operating condition, which is very useful on proper series termination design to achieve optimised SI performance.
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5.8 Experimental Validation with Measurement Results
The clock driver circuit is designed and fabricated for this experimental measurement validation purpose. With the extracted clock driver output impedance, it allows accurate selection of the series terminating resistor at the output of the clock driver for matching to the transmission line to achieve optimal SI performance. The actual circuit shown in Fig. 75 consists of the clock driver, the source output series
terminator (R1) and a 6 50 transmission line. The board is powered up by a 5V source through a 3.3V regulator. A repetitive square pulse of 25 MHz, 3V amplitude with 50 % duty cycle is connected to the input of the clock driver from Tektronix arbitrary function generator (AFG 3101). The signal waveform at the far end of the microstrip line is measured with a Tektronix digital phosphor oscilloscope (DPO 7354 3.5 GHz).
For the first clock driver, CDCV304PW, its extracted output impedance is 23 and therefore a series resistor of 27 is chosen for optimal SI performance. Fig. 86 shows the signal waveform measured at the far end of the microstrip line with a 27 series resistor. To illustrate the effect of unmatched condition, the measured waveform with a 5 series resistor is included in Fig. 86. As expected, the measured waveforms for both cases show clearly that with the 27 series resistor, the waveform exhibit minimum signal reflections when compared to that with the 5 series resistor.
Clock Signal at Far-End of Microstrip Line CDCV304PW
5.0
4.0 V /
e 3.0 d u t i l
p 2.0 m A 1.0
0.0 0 5 10 15 20 25 30 Time / ns
5 ohm 27 ohm
Figure 86 : Measured clock waveform at far-end of microstrip line with CDCV304PW
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For the second clock driver CDCVF2505 with extracted output impedance of 45 , a series resistor of 5 will provide the optimal SI performance. Fig. 87 shows the measured waveforms at the other end of the microstrip line for both 5 series resistor and 27 series resistor. The measured waveforms indicate that the 5 series resistor has minimal signal slew as compared that with the 27 resistor. This shows that the 27 series resistor is too large a value to match this CDCVF2505 clock driver to the microstrip line causing the signal waveform to degrade.
Clock Signal at Far-End of Microstrip Line CDCVF2505
4.0
3.0 V / e d u
t 2.0 i l p m A 1.0
0.0 0 5 10 15 20 25 30 Time / ns
5 ohm 27 ohm
Figure 87 : Measured clock waveform at far-end of microstrip line with CDCVF2505
The measured results demonstrate that the ability to extract the output impedance of the active clock driver under its actual operating condition allow precise selection of the series resistor value for good SI performance and eliminate the usual trial-and- error design process.
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5.9 Impact of Series Termination on Rise-time and Emission
To ensure optimised SI, one also has to take note of the EMI emission control in the circuit design, especially when series termination selection is concerned. Too large a series terminator can suppress the EMI emission but it is at the expense of reduction in signal rise-time and hence SI. Therefore, a balance approach has to be adopted. Using the time-domain circuit simulation on CST Design Studio with CDCV304PV clock driver IBIS and actual PCB Gerbel imported, the circuit shown in Fig. 88 will be simulated. The resulting time-domain signal received at the far-end of the transmission line with different series termination resistors are shown in Fig. 89.
Figure 88 : CST-DS IBIS circuit simulation setup with CDCV304PV clock driver
From EMI emission point of view, it is often easy to use a larger series termination resistor to reduce the emission, as shown in Fig. 89(c). However this comes at the expense of significant reduction in the signal rise time as shown in Fig. 89(d). Such slew in signal rise-time is undesirable especially in high-speed applications.
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(a)
(b)
(c) (d)
Figure 89 : Simulation result (a) Rs=15 (b) Rs=24 (c) Rs=50 (d) receive signal
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hapter 6
6.0 CONCLUSION
With increasing importance of SI in today s high-speed digital circuit design environment, the major challenge is to ensure that the circuit is not only functionally working but also electrically compliance to tighter specifications and design margin.
Source series termination to match the driver output impedance to the PCB trace characteristic impedance to ensure optimal SI performance is one of the most commonly adopted matching techniques used today for its simplicity and effectiveness. To ensure good impedance matching, the output impedance of the driver has to be known before a proper series termination is chosen to match to the PCB interconnection trace with confidence.
6.1 Major Contribution of the Thesis
The major contribution of this thesis is the successful extension of the inductive non- contact two-probe measurement technique to 1GHz. To ensure the accuracy up to 1 GHz, a pre-measurement error elimination process has been developed so that one could accurately characterizing the impedance of a device s output impedance under its intended operating conditions.
The proposed two current probes measurement technique has been described and validated in the characterization of passive components under in-circuit operation with varying biasing conditions. [117] The measured results provide an insight of the impedance behavior of a critical component under its intended biasing condition so that the proper choice of the component can be made in circuit design to achieve
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appropriate and optimal performance. Especially for passive component with non linear behavior, the proposed in-circuit measurement technique has the ability to detect the change in impedance due to varying biasing conditions.
The technique is then extended to determine the output impedance of an in-circuit active device under its intended operating conditions. [118] It is found to be very useful for selecting proper series termination for high-speed clock drivers. With the known extracted output impedance of the driver, a source series termination can be easily chosen to optimize the SI performance as well as to minimize EMI emission. With the proposed technique, it eliminates unnecessary trial-and-error for manual tuning the series termination value.
The proposed in-circuit measurement method can be further extended in many potential applications. For example, it allows the characterization of unknown power supply output impedance and a noisy digital module input impedance for designing an EMI filter systematically [119,120].
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6.2 Limitations and Recommended Future Research Work
The proposed approach is not without limitations. The major limitation of this approach is the operating bandwidth of the current probe itself. The upper frequency limit of the current probe determines the maximum frequency of the proposed measurement approach. Hence, better designed high frequency current probe is necessary in order to extend the operating bandwidth further.
In the active device output characterisation, the proposed technique also has its shortfall. Firstly, it is intended for device level characterisation on a standalone dedicated test jig. As illustrated in the active device output characterisation setup, in order to perform the in-circuit characterisation, several provisions in the PCB layout has to be taken into consideration at the design stage for the placement of current probes and bypass resistor. However, this can be kept to a minimum area using surface mount pads. Still this occupies an area in the PCB board, which the designer has to cater for if in-circuit characterisation is truly needed.
Based on the author opinion and his research in this area, the following future works are worth exploring:
a) Modification improvement can be made to the test jigs design to cater for proper device adapters such as chip holders for passive component and IC sockets for active devices. This allows ease of device testing without the need for soldering and de-soldering, hence minimising damage to the DUT. Note that during pre- calibration, the effects of the socket are being taken into consideration and will be eliminated.
b) Currently the results obtained from the VNA are imported into Microsoft Excel spread sheet to generate the graph. It would be useful and practical if programming effort is made to develop the routine to be integrated into full device test software so as to automate this process and the report generation during the characterization procedure.
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c) The two probe measurement approach can be use in the in-circuit characterisation of EMI filter to investigate the impact of loading on the filter attenuation, an area that can be useful for the designer.
d) Another area that is worth exploring is the use of the proposed method to extract the input power supply impedance of an integrated circuit (IC) for the purpose of characterisation of its power distribution network (PDN) impedance for optimal decoupling design. Some preliminary work by the author on the power supply impedance has been reported in [119,120].
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AUTHOR S PUBLICATIONS
Author s Publications
Journal Papers
1) Weng-Yew Chang, Wei-Shan Soh, Kye-Yak See and Lin-Biao Wang, Extraction of Clock Driver Output Impedance for Signal Integrity Design , IEEE Transactions on Instrumentation and Measurement, Vol. 53, No. 4, pp. 1034-1039, November 2011.
2) Weng-Yew Chang, Kye-Yak See and Hu Bo, Characterization of component under DC biasing condition using an inductive coupling approach , IEEE Transactions on Instrumentation and Measurement, Vol. 59, No. 8, pp. 2109-2114, August 2010.
3) Hu Bo, Kye-Yak See and Weng-Yew Chang, Measurement of EMI suppression of a ferrite core under realistic operating conditions , IEEE EMC Society Newsletters, No. 218, pp. 60-65, Summer Issue 2008.
4) Vuttipon Tarateeraseth, Kye Yak See, Flavio G. Canavero and Weng-Yew Chang, Systematic electromagnetic interference filter design based on information from in- circuit impedance measurement , IEEE Transactions on Electromagnetic Compatibility, Vol. 52, No. 3, pp. 588-598, August 2010.
Conference Papers
5) Wei-Shan Soh, Weng-Yew Chang and Kye-Yak See, Wee-Jin Koh, Manish Oswal, Study of Power/Ground Plane Separation on Radiated Emission Suppression , Proc. on Electrical Design of Advanced Packaging and System Symposium, pp. 35-38, 10-7- 9 December 2010, Singapore.
6) Wei-Shan Soh, Weng-Yew Chang and Kye-Yak See, Filter design for suppression of noise coupling from PCB to DC power supply , Proc. on Asia-Pacific Symposium and Exhibition on Electromagnetic Compatibility, pp. 633-636, 12-16 April 2010, Beijing, China.
7) Lin-Biao Wang, Kye-Yak See, Weng-Yew Chang, Chee-Wai Lu and Say Tyam Ng, Electromagnetic shielding analysis of printed flexible meshed screens , Proc. on Asia-Pacific Symposium and Exhibition on Electromagnetic Compatibility, pp. 965- 968, 12-16 April 2010, Beijing, China.
8) Weng-Yew Chang, Kye-Yak See and Wei-Shan Soh, Measurement of output driver impedance for signal integrity design consideration , Proc. on Asia-Pacific Microwave Conference, pp. 665-668, 7-10 December 2009, Singapore.
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AUTHOR S PUBLICATIONS
9) Wei-Shan Soh, Kye-Yak See, Weng-Yew Chang, Oswal Manish and Lin-Biao Wang, Comprehensive analysis of serpentine line design , Proc. on Asia-Pacific Microwave Conference, pp. 1285-1288, 7-10 December 2009, Singapore.
10) Weng-Yew Chang, Kye-Yak See, Wei-Shan Soh, Manish Oswal and Lin-Biao Wang, High-speed signal termination analysis using a co-simulation approach , Proc. on 12th International Symposium on Integrated Circuits, pp. 623-626, 14-16 December 2009, Singapore.
11) Weng-Yew Chang, Kye-Yak See and Hu Bo, In-circuit impedance measurement based on a two-probe approach , Proc. on Electrical Design of Advanced Packaging and System Symposium, pp. 35-38, 10-12 December 2008, Seoul, Korea.
12) Wei-Shan Soh, Kye-Yak See and Weng-Yew Chang, Experimental study of radiated emission from high speed power plane , Proc. on Electrical Design of Advanced Packaging and System Symposium, pp. 49-52, 10-12 December 2008, Seoul, Korea.
13) Weng-Yew Chang, Kye-Yak See, Yang-Long Tan, Impacts of bends and ground return vias on interconnects for high speed GHz designs , Proc. on Asia Pacific Symposium on Electromagnetic Compatibility, pp. 502-505, 19-23 May 2008, Singapore.
14) Lin-Biao Wang, Kye-Yak See, Weng-Yew Chang and Zhi-Gang Phang, Comprehensive study of crosstalk isolation for high-speed digital board , Proc. on Asia Pacific Symposium on Electromagnetic Compatibility, pp. 867-870, 19-23 May 2008, Singapore.
15) Weng-Yew Chang, Kye-Yak See and Eng-Kee Chua, Comprehensive analysis of the impact of via design on high-speed signal integrity , Proc. on 9th Electronics Packaging Technology Conference, pp. 262-266, 10-12 December 2007, Singapore.
16) Eng-Kee Chua, Er-Ping Li, Kye-Yak See and Weng-Yew Chang, The effects of signal trace s termination on ground bounce and common-mode radiation , IEEE International Symposium on Electromagnetic Compatibility, pp.1-5, 9-13 July 2007, Honolulu, Hawaii, USA
17) Eng-Kee Chua, Kye-Yak See, Er-Ping Li and Weng-Yew Chang, Investigation of relationship between ground bounce and common-mode , Proc. on 8th Electronics Packaging Technology Conference, pp. 610-614, 6-8 December 2006, Singapore.
Page 117
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[117] Weng-Yew Chang, Kye-Yak See and Hu Bo, Characterization of component under DC biasing condition using an inductive coupling approach , IEEE Transactions on Instrumentation and Measurement, Vol. 59, No.8, pp. 2109-2114, August 2010.
[118] Weng-Yew Chang, Wei-Shan Soh, Kye-Yak See and Lin-Biao Wang, Extraction of Clock Driver Output Impedance for Signal Integrity Design , IEEE Transactions on Instrumentation and Measurement, accepted for publication, June 2011.
[119] Wei-Shan Soh, Weng-Yew Chang and Kye-Yak See, Filter design for suppression of noise coupling from PCB to DC power supply , Proc. on Asia-Pacific Symposium and Exhibition on Electromagnetic Compatibility, pp. 633-636, April 2010, Beijing, China.
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Page 127
AUTHOR S BIOGRAPHY
Author s Biography
Chang Weng Yew, Richard
PhD Student Nanyang Technological University School of Electrical & Electronic Engineering, Division of Circuits & Systems (NTU/EEE2) Integrated System Research Lab (S2-B2A-04) Project Engineer (SMTS) DSO National Laboratories Guided Systems Division, Guided System Lab 2 (GS/GS2) 20 Science Park Drive Email (DSO): [email protected]; Email (NTU): [email protected]
Weng-Yew Chang obtained his Diploma in Electrical and Electronics (Merit) from Ngee Ann Polytechnic in March 1987. He received his B.Eng and M.Sc degree from Nanyang Technological University (NTU) in 1994 and 2001, respectively. He joined DSO National Laboratories (formally Defence Science Organization) since 1994. He began his career as a hardware designer under the Weapon Electronics Lab designing airborne embedded digital processing system. Subsequently, he became Project Lead in numerous hardware designs involving embedded DSP digital systems and airborne radar digital system. His last appointment was the Group Head for Airborne Radar Digital Electronics Team under the Division of Guided Systems (GS).
He was awarded the Defence Technology Prize (Team Category) in 2000 and DSO Group Performance Award in 2004 for his contribution in Radar System. He was awarded a DSO Scholarship in 2005 to pursuit his PhD study in NTU under the supervision of Assoc. Prof. See Kye Yak. His research interests are signal integrity for high speed digital circuit design, high-speed measurements, design techniques for EMI/EMC compliance and airborne embedded digital electronics design. He has co-authored more than 17 technical papers published in international referenced journals and conference proceedings.
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APPENDIX
Appendix A: List of EDA Vendors and Tools
Company : Ansoft Corporation (1984) Product : Ansoft HFSS v11 (June 07) 3D High Frequency EM Field simulator, : SIWave v3.5, Q3D Extractor v7, TPAv5, Nexxim v3.5, Ansoft Designer v3.5, : DesignerS1 v3.5, Maxwell-2D&3D v11, Simplorerv7, PExprt, RMxprt, ePhysics Website : http://www.ansoft.com
Company : Agilent EEsof EDA (1993) Product : Advanced Design System ADS 2006u3 High Frequency RF design software : Electromagnetic Design System EMDS (2006C) 3D EM simulator : Antenna Modeling Design System AMDS (2007) 3D EM Antenna design tool : Momentum 2005A HF 3D planar EM simulator : Genesys, SystemVue, RF DE, IC-CAP, GoldenGate Website : http://eesof.tm.agilent.com
Company : QuickWave Software for Electromagnetic Design -QWED (1997) Product : QuickWave-3D (v6.5 April, 2007) : QW-editor, QW-Simulator, VF-modeler, QW-V2D & QWCX Website : http://www.qwed.com.pl/index.html
Company : Vector Fields Ltd - Software for Electromagnetic Design (1984) Product : Opera-2D & 3D, ConcertoAS(low-cost), 2D, ES(essential) & PR (professional) : Parametric Modeling, Advance Optimization, create 2D and 3D models and : Simulation choice of 3 methods, comprehensive post processing Website : http://www.vectorfields.com/
Company : Computer Simulation Technology CST (1992) Product : CST Studio Suite (2008), CST DE Design Environment : CST MWS Microwave Studio - HF 3D EM simulator (Intro 1998) : CST DS Design Studio, CST EM Studio, CST PS Particle Studio : MAFIA 4.2 - Multipurpose ECAD system for 3D EM problems (Intro 1989) Website : http://www.cst.com
Company : Zealand Software, Inc (1992) Product : IE3D 12.12 (Mar 07) - Full wave, 3D MoM based EM simulator : FIDELITY - Time domain full wave 3D FDTD EM simulator : MDSPICE, COCAFIL, FilterSyn, SpiralSyn, LineGauge, : ADIX-Layout format converter, LinCAD-Layout format converter, : LINMIC +/N Linear and Nonlinear Circuit simulation package Website : http://www.zeland.com
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APPENDIX
Company : ComSol Group (1997) Product : ComSol Multiphysic 3.3 2006 : Include AC/DC, Acoustics, CAD import, Heat transfer, RF, MEMS and : Structure Mechanics : PDE Toolbox release in 1995, FEMLAB in 1998, ComSol Multiphysic 2005 Website : http://www.comsol.com
Company : Mentor Graphics Corporation (1981) Product : Scalable Verification, IC Nanometer Design, PCB-FPGA system design : System Level Design, Embedded systems (EDGE, Nuclues), DFT, : System Modeling, Electrical System design and harness engineering : IP (USB, Ethernet, PCI Express, Serial ATA, Peripheral, Mixed signal) : Modelsim Digital simulation, ADVance MS/RF mixed signal simulator : Hyperlynx Ext/GHz - Board level SI, crosstalk and EMC analysis suite : ICX - advance electrical driven design and board/system level verification : DxSim & DxDesigner - Board simulation and verification environment : QuietExpert - Rule based PCB SI, EMC and layout verification system Website : http://www.mentor.com
Company : Cadence Design Systems, Inc (1988) Product : Cadence Encounter - Digital IC (nm Soc) design platform : Cadence Virtuoso - Custom IC silicon design platform : Cadence Allegro System - IC-PKG-PCB Interconnect co-design platform : Cadence SiP - System level Digital/RF SiP co-design with advance packing : Cadence Incisive - Functional verification platform for large complex chips : Cadence Orcad, DFT and Cadence Kits & IP : Website : http://www.cadence.com
Company : Applied Wave Research Inc (1994) Product : MWO 2007 Microwave Office - Microwave/RF design platform : ACE Automated Circuit Extractor : VSS 2007 Visual System Simulator - Complete, end-end comms system design : Analog Office Open RFIC design platform : AWR SI 2006 Cross Domain Signal Integrity Co-chip/pkg/module Solution : AXIEM 3D planar EM simulator (soft launch Sep2007) Website : http://web.appwave.com
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