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Foreword John L. Hennessy, Founder, MIPS Technolagies Inc. Frederick Emmons Terman Dean of Engineering, Stanford University am very pleased to see this new book on the MIPS architecture at such an Iinteresting time in the 15-year history of the architecture. The MIPS archi- tecture had its beginnings in 1984 and was first delivered in 1985. By the late 1980s, the architecture had been adopteda variety of workstation and server companies, including Silicon Graphics and Digital Equipment Corpo- ration. The early 1990s saw the introduction of the R4000, the first 64-bit microprocessor, while the mid 1990s saw the introduction of the R10000 — at the time of its introduction, the most architecturally sophisticated CPU ever built. The end of the 1990s heralds a new era for the MIPS architecture: its emergence as a leading architecture in the embedded processor market. To date, over 100 million MIPS processors have been shipped in applications ranging from video games and palmtops, to laser printers and network routers, to emerging markets, such as set-top boxes. Embedded MIPS processors now ournumber MIPS processors in general-purpose computers by more than 1,000 to 1. This growth of the MIPS architecture in the embedded space and its enormous potential led to the spinout of MIPS Technologies (from Silicon Graphics) as an independent company in 1998. Thus, this book focusing on the MIPS architecture in the embedded mar- ket comes at a very propitious time. Unlike the well-known MIPS architecture handbook, which is largely a reference manual, this book is highly readable and contains a wealth of sage advice to help the programmer to avoid pitfalls, to understand some of the tradeoffs among MIPS implementations, and to optimize performance on MIPS processors. The coverage is extreme.Iy broad, discussing not only the basics of the MIPS architecture, but issues such as memory management and systems instructions, cache organizations and control, and the floating point instructions set. (Although some embedded users will be uninterested in the floating point, such instructions are heav- ily used in graphics-intensive applications, such as video games and set-top boxes.) i ii Several of the chapters are unique in that the author shares his experience in programming the MIPS architecture. These chapters cover topics that are critical to the embedded systems programmer, such as C programming con- ventions (e.g., for register use and procedure linkage), how to write portable MIPS code, and how to obtain the best performance. The coverage of excep- tion handling guides the programmer, by the use of example code sequences, while including a description of the complete exception architecture. As important as the technical content of this book is its readability. Simply stated, this is book fun to read. Dominic Sweetman’s insights and presenta- tion help entice the reader. In my view, this book is the best combination of completeness and readability of any book on the MIPS architecture, and is far better than most on other architectures. In closing, let me mention that Sweetman’s insights into the development of the MIPS architecture are truly exceptional. As a 15-year contributor to the MIPS architecture, I am astounded by the perceptiveness of the author in his explanations of the rationale for both the MIPS architecture and the specific implementations. I am confident that readers interested in understanding or programming the MIPS architecture will learn what they need to know from this book, and that they will enjoy reading it. As a founder of MIPS, a contributor to both the first MIPS implementation (the R2000) and several subsequent implementations, I’m delighted that the author became a MIPS convert and chose to write this book! Contents Foreword i Preface xv 0.1 Style and Limits ............................ xvii 0.2 Conventions .............................. xviii 0.3 Acknowledgments ........................... xviii 1 RICSs and MIPS 1 1.1 Pipelines ................................. 2 1.1.1 What Makes a Pipeline Inefficient? ............. 3 1.1.2 The Pipeline and Caching ................... 4 1.2 The MIPS Five-Stage Pipeline ..................... 5 1.3 RISC and CISC ............................. 7 1.4 Great MIPS Chips of the Past and Present ................................. 7 1.4.1 R2000 to R3000 ........................ 7 1.4.2 R6000: A Diversion ...................... 8 1.4.3 The R4000 Revolution ..................... 9 1.4.4 R5000 and R10000 ...................... 9 1.5 MIPS Compared with CISC Architectures ............. 12 1.5.1 Constraints on Instructions ................. 12 1.5.2 Addressing and Memory Accesses .............. 13 1.5.3 Features You Won’t Find ................... 14 1.5.4 A Feature You Might Not Expect ............... 16 1.5.5 Programmer-Visible Pipeline Effects ............. 16 iii iv Contents 2 MIPS Architecture 19 2.1 A Flavor of MIPS Assembly Language ................ 20 2.2 Registers ................................ 21 2.2.1 Conventional Names and Uses of General- Purpose Registers ....................... 23 2.3 Integer Multiply Unit and Registers ................. 25 2.4 Loading and Storing: Addressing Modes .............. 27 2.5 Data Types in Memory and Registers ................ 27 2.5.1 Integer Data Types ....................... 28 2.5.2 Unaligned Loads and Stores ................. 28 2.5.3 Floating-Foint Data in Memory ................ 29 2.6 Synthesized Instructions in Assembly Language ................................ 30 2.7 MIPS I to MIPS IV 64-Bit (and Other) Extensions ......... 32 2.7.1 To 64 Bits ............................ 33 2.7.2 Who Needs 64 Bits? ...................... 33 2.7.3 Regarding 64 Bits and No Mode Switch: Data in Registers 34 2.7.4 Other Innovations in MIPS III ................ 35 2.8 Basic Address Space .......................... 39 2.8.1 Addressing in Simple Systems ................ 39 2.8.2 Kernel vs. User Privilege Level ................ 40 2.8.3 The Full Picture: The 64-Bit view of the Memory Map .. 40 2.9 Pipeline Hazards ............................ 41 3 Coprocessor 0: MIPS Processor Control 45 3.1 CPU Control Instructions ....................... 48 3.2 What Registers Are Relevant When? ................. 49 3.3 Encodings of Standard CPU Control Registers ................................ 50 3.3.1 Processor ID (PRId) Register ................. 51 3.3.2 Status Register (SR) ...................... 52 3.3.3 Cause Register ......................... 57 3.3.4 Exception Return Address (EPC) Register ......... 58 Contents v 3.3.5 Bad Virtual Address (BadVaddr) Register .......... 58 3.4 Control Registers for the R4000 CPU and Followers ....... 59 3.4.1 Count/Compare Registers: The R4000 Timer ....... 60 3.4.2 Config Register: R4x00 Configuration ............ 60 3.4.3 Load-Linked Address (LLAddr) Register ........... 63 3.4.4 Debugger Watchpoint (WatchLo/ WatchHi) Registers ....................... 63 4 Caches for MIPS 65 4.1 Caches and Cache Management ................... 65 4.2 How Caches Work ........................... 66 4.3 Write-Through Caches in Early MIPS CPUs ............ 69 4.4 Write-Back Caches in Recent MIPS CPUs ............. 69 4.5 Other Choices in Cache Design ................... 71 4.6 Managing Caches ........................... 77 4.7 Secondary and Tertiary Caches ................... 77 4.8 Cache Configuration for MIPS CPUs ................ 77 4.9 Programming R3000-Style Caches ................. 77 4.9.1 Using Cache Isolation and Swapping ............ 79 4.9.2 Initializing and Sizing ..................... 80 4.9.3 Invalidation ........................... 80 4.9.4 Testing and Probing ...................... 82 4.10Programming R4000-Style Caches ................. 82 4.10.1CacheERR, ERR, and ErrorEPC Registers: Cache Error Handling ..................... 84 4.10.2The Cache Instruction ..................... 85 4.10.3Cache Sizing and Figuring Out Configuration ....... 85 4.10.4Initialization Routines ..................... 85 4.10.5Invalidating or Writing Back a Region of Memory in the Cache .............................. 85 4.11Cache Efficiency ............................ 85 4.12Reorganizing Software to Influence Cache Efficiency ....... 93 4.13Write Buffers and When You Need to Worry ............ 95 vi Contents 4.13.1Implementing wbfiush ..................... 97 4.14More about MIPS Caches ....................... 98 4.14.1Multiprocessor Cache Features ............... 98 4.14.2Cache Aliases .......................... 98 5 Exceptions, Interrupts, and Initialization 101 5.1 Precise Exceptions ........................... 103 5.2 When Exceptions Happen ...................... 104 5.3 Exception Vectors: Where Exception Handling Starts ...... 105 5.4 Exception Handling: Basics ..................... 109 5.5 Returning from an Exception ..................... 110 5.6 Nesting Exceptions .......................... 110 5.7 An Exception Routine ......................... 111 5.8 Interrupts ................................ 111 5.8.1 Interrupt Resources in MIPS CPUs ............. 112 5.8.2 Implementing Interrupt Priority ............... 114 5.8.3 Atomicity and Atomic Changes to SR ............ 116 5.8.4 Critical Regions with Interrupts Enabled: Semaphores the MIPS Way .......................... 117 5.9 Starting Up ............................... 119 5.9.1 Probing and Recognizing Your CPU ............. 121 5.9.2 Bootstrap Sequences ..................... 122 5.9.3 Starting Up an Application .................. 123 5.10Emulating Instructions ........................ 124 6 Memory Management and the TLB 125