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DDR3 SDRAM Memory Controller N.Purnachand1, K Hari Kishore2, K.V.Pavankalyan3, K.Divya4, A.Karthik5, Khadar Bhasha6 1,2,3,4,5,6D

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DDR3 SDRAM Memory Controller N.Purnachand1, K Hari Kishore2, K.V.Pavankalyan3, K.Divya4, A.Karthik5, Khadar Bhasha6 1,2,3,4,5,6D International Journal of Pure and Applied Mathematics Volume 115 No. 7 2017, 507-512 ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version) url: http://www.ijpam.eu Special Issue ijpam.eu DDR3 SDRAM Memory Controller N.Purnachand 1, K Hari Kishore 2, K.V.Pavankalyan 3, K.Divya 4, A.Karthik 5, Khadar Bhasha 6 1,2,3,4,5,6 Department of ECE, K L University, Vaddeswaram, Guntur, A.P. India 1Pvn122.k@gmail.com, 2kakarla.harikishore@kluniversity.in Abstract:To overcome the problem of latency in particular memory location. The DDR SDRAM SDRAM, data rate schemes were introduced. In these Controller architecture is shown in Figure 2. scheme the data will worked in according with clock It consists of three modules: pulses such that it automatically adjusts the latency. Till 1) Main control module now Double data rate (DDR) based SDRAM, DDR2- 2) Signal generation module SDRAM and DDR3-SDRAM were implemented. In 3) Data path module. our condition modified DDR3-SDRAM was The main control module has two state machines and a implemented. To enhance the latency of the system and refresh counter. The two state machines are for area utilization. This design will overcome the issues initialization of the SDRAM and for generating the such as data rate interference, high delay and limited commands to the SDRAM. They generate iState and period offence. DDR3 SDRAM controller helps cState outputs according to the system interface control memory interfacing and reduces the problem of signals. The signal generation module now generates synchronization. This high performance RAM the address and command signals depending upon the overcomes the limitations and further can be extended iState and cState. The data path module performs the other memory accessing applications such as CAM, read and writes operations between the bus master and TCAM. The performance of DDR3 were compared DDR. Following are some of the important features of with DDR and helps in identifying the efficiency of the DDR SDRAM Controller: scheme. i. The DDR SDRAM Read and Write operations are simplified by the controller. 1. Introduction ii. For initializing the DDR SDRAM controller, Synchronous DRAM (SDRAM) is preferred in separate state machines are designed internally. embedded system memory design because of its speed iii. The access time for read and the write cycle is and pipelining capability. In high-end applications, like optimised based on the CAS latency and burst length of microprocessors there will be specific built in the DDR SDRAM. peripherals to provide the interface to the SDRAM. But iv. The auto refresh for the DDR SDRAM is done by for other applications, the system designer must design the controller. a specific memory controller to provide command The main control module consists of three sub signals for memory refresh, read and write operation modules: and initialization of SDRAM. "Synchronous switch", 1) Initialization FSM module (INIT_FSM). tells about the behavior of the DRAM kind. In late 2) Command FSM module (CMD_FSM) 1996, SDRAM commenced appearing in systems. 3) Counter module. Unlike preceding technology, SDRAM is designed to In this paper, the SDRAM controller, located between synchronize itself with the timing of the CPU. This the SDRAM and the bus master, minimizes the effort to enables the reminiscence controller to realize the deal with the SDRAM memory by providing a simple precise clock cycle when the asked records might be system to interact with the bus master. Figure 1 is the prepared, so the CPU does not have to wait between block diagram of the DDR SDRAM Memory reminiscence accesses. For example, PC66 SDRAM Controller that is connected between the bus master and runs at 66 MT/s, PC100 SDRAM runs at 100 MT/s, SDRAM. PC133 SDRAM runs at 133 MT/s, and so on. SDRAM’s are classified based on their data transfer rates. In Single data rate SDRAM, the data is 2. Methodology transferred on every rising edge of the clock whereas in double data rate (DDR) SDRAM’s the data is 2.1 DDR-SDRAM transferred on every rising edge and every falling edge DDR SDRAM Controller module receives addresses of the clock and as a result the throughput is increased. and control signals from the BUS Master. The DDR SDRAM Controllers are faster and efficient than Controller generates command signals and based on its counterparts. They allow data transfer at a faster rate these signals the data is either read or written to a without much increase in clock frequency and bus width. Same Commands as for Standard SDRAM 507 International Journal of Pure and Applied Mathematics Special Issue • READ In the i_PRE state, the main control module will • WRITE generate the PRECHARGE command. The • ACTIVATE PRECHARGE command generated during this state • PRECHARGE will be applied to all the banks in the device. Once the • REFRESH PRECHARGE command is generated by the • MRS (Mode Register Set) initialization FSM, it will switch to the next state. The Added next state in the design of initialization FSM is two • EMRS (Extended MRS) AUTO REFRESH commands. These refresh • Phase Shift the Data Strobe commands are generated to refresh the DRAM • Resynchronize the Data memory. After the two refresh state, the initialization A. Main control module FSM will switch to i_MRS state. During this state LOAD MODE REGISTER command is generated to The DDR SDRAM Controller has to undergo configure the DDR SDRAM to a specific mode of an initialization process by a sequence of command operation. signals before the normal memory access . The After satisfying the i_tMRD timing delay the initialization finite state machine in the main control initialization FSM will switch to i_ready state. The module is responsible for the initialization of the DDR initialization FSM will remain in the i_ready state for SDRAM controller. Figure shows the state diagram of normal memory access. And also, when the the initialization FSM (INIT_FSM). Whenever reset initialization FSM switches to i_ready state signal signal is high, the initialization FSM will switch to sys_INIT_DONE is set to high to indicate that DDR i_IDLE state. Once the reset signal goes low, the SDRAM controller initialization is completed. The controller has to wait for 200us clock stabilization i_PRE, i_AR1, i_AR2, i_EMRS and i_MRS states are delay. This is constantly checked by sys_dly_200us used for issuing DDR commands. signal and a high on the sys_dly_200us will indicate CMD_FSM handles the read, write and refresh of that the clock stabilization delay is complete. The DDR the SDRAM. The CMD_FSM state machine is initialization sequence will begin immediately after the initialized to c_IDLE during reset. After reset, clock/power stabilization is complete and then the CMD_FSM stays in c_IDLE as long as INIT_FSM will change its state from i_IDLE to i_NOP sys_INIT_DONE is low which indicates the SDRAM state. From the i_NOP state, the initialization FSM will initialization sequence is not yet completed. When the switch to the i_PRE state on the next clock cycle. sys_INIT_DONE is high, it indicates the system initialization is complete. The controller will now wait for latch_ref_req, sys_INIT_DONE signals and will enter auto refresh, read and write mode depending upon these signals. When the initialization is complete and when the latch_ref_req goes high the controller will refresh by entering into refresh state. After the refresh is complete, when the latch_ref_req and sys_ADSn signal goes low, the controller will go to active state. The ACTIVE command will be issued for each read or write access to open the row. 2.2 Ddr3-Sdram Double statistics charge kind 3 SDRAM (DDR3 Figure 1: DDR SDRAM controller system SDRAM) is a type of synchronous dynamic random-get right of entry to reminiscence (SDRAM) with a high bandwidth ("double records fee") interface, and has been in use considering 2007. It is the higher-pace successor to DDR and DDR2 and predecessor to DDR4 synchronous dynamic random-get admission to memory (SDRAM) chips. DDR3 SDRAM is neither forward nor backward compatible with any earlier form of random-access memory (RAM) due to specific signaling voltages, timings, and other factors. Figure 2. Clock pulses command operations of DDR3 is a DRAM interface specification. The real DDRSDRAM DRAM arrays that store the records are much like in advance kinds, with comparable performance. 508 International Journal of Pure and Applied Mathematics Special Issue The primary gain of DDR3 SDRAM over its on the DDR commands that helps in selecting strobe and spot predecessor, DDR2 SDRAM, is its capability to chip selection in our approach are Mode Register Set, transfer information at two times the fee (8 instances Refresh, PRECHARGE, calibration. From this we the speed of its inner memory arrays), permitting better access different states Intialise, Idle, Read, Write and bandwidth or height statistics quotes. With transfers in pause modes. keeping with cycle of a quadrupled clock sign, a sixty four-bit wide DDR3 module may attain a switch price (in megabytes consistent with 2nd, MB/s) of as much as 64 instances the memory clock pace (in MHz). With statistics being transferred sixty four bits at a time in keeping with reminiscence module, DDR3 SDRAM gives a switch price of (reminiscence clock fee) × four (for bus clock multiplier) × 2 (for information rate) × 64 (number of bits transferred) / eight (quantity of bits/byte). Thus with a reminiscence clock frequency of 100 MHz, DDR3 SDRAM offers a maximum switch fee of 6400 MB/s. The DDR3 popular lets in DRAM chip capacities of up to eight gibibits, and up to 4 ranks of 64 bits every for a complete most of 16 GiB in keeping with DDR3 DIMM. Because of a hardware challenge no longer constant till Ivy Bridge-E in 2013, maximum older Intel CPUs simplest aid up to 4 gbit chips for 8 Figure 4 operations of DDR3SDRAM GiB DIMMs (Intel's Core 2 DDR3 chipsets best aid up to 2 gbits).
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