DRIVING FORCES ON PACKAGING: 5 PHYSICAL INTERCONNECTS
The single most important element of the package and interconnect that influences the system clock speed, the performance density, and often the cost of a system, is how close together the devices can be placed. The term that best describes this is packaging efficiency. The three fabri- cation and assembly issues that constrain the packaging efficiency are:
¥ the I/O off the chipÑthe number, the form factor, the pitch ¥ the I/O off the packageÑthe number, the form factor, the pitch ¥ the interconnect substrateÑthe pad pitch, the via pitch, the line pitch, the number of layers
Pin Count Requirements and RentÕs Rule
As the number of gates on a single die has increased, the number of I/Os required to interface them to the outside world has also increased. In 1960, E.F. Rent of IBM identified a definite empir- ical relationship between the number of gates in a block, Ngates, and the number of I/Os they required, NI/O. This relationship, since coined RentÕs Rule, has been extended and generalized to encompass a variety of chip types and module sizes.
Figure 5-1 is a plot of the signal I/Os required for various gate arrays and microprocessors. In general, for every 4 to 10 signal I/Os, one power or one ground is used. As the clock frequency goes up, a higher fraction of power and ground pads are required to keep switching noise at acceptable levels. For clock frequencies over 250MHz, the ratio is closer to 3:1 signal to power/ground pads.
Empirically, the RentÕs Rule relationship between total signal I/Os required and gate count is:
NkN= p I/O gates where k and p are constants that depend on the architecture and the partitioning. RentÕs Rule graphically shows the ever greater demand for more I/Os as the number of gates increases.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-1 Driving Forces on Packaging: Physical Interconnects
For the case of microprocessors: k = 0.82 p = 0.45
For the case of already committed gate arrays: k = 1.9 p = 0.5
The original values that Rent found applicable for his systems were: k = 2.5 p = 0.61
104
Bipolar Gate Array CMOS Gate Array Microprocessor SRAM DRAM 103
2
Number of Signal Pins 10
101 102 103 104 105 106 Number of Gates or Bits
Source: University of Arizona/ICE, "Roadmaps of Packaging Technology" 13651A
Figure 5-1. I/O Pin Count Versus Complexity
RentÕs Rule is a loose, empirical rule of thumb that can be used to roughly predict the number of I/Os a chip or module will need as the number of committed gates increases. Care must be exer- cised in using it. There is an explicit assumption that the partitioning will remain the same as the gate count increases. Of course, at some point, the functionality must reach the point where the I/O count decreases. After all, even the largest computer has at most a few hundred system-level I/Os for disk drive and keyboard access. The point at which the I/O requirements begin to fall under RentÕs Rule is a measure of the degree of partitioned functionality.
5-2 INTEGRATED CIRCUIT ENGINEERING CORPORATION Driving Forces on Packaging: Physical Interconnects
Decreasing the I/O count off chip without resorting to multiplexing or degrading signal integrity, will always increase the performance density per unit cost, if only by reducing the component and assembly costs. Partitioning of gates and chips into functional units that will bring the I/O count under RentÕs Rule is a critically important step in the design cycle. Integrating more functional- ity on chip will most often increase the performance/cost.
As the gate count available on gate arrays increases, the required I/O count will increase. From 2 the gate density, Dgate, in gates/in , the required I/O count for any die size can be calculated with RentÕs Rule. For gate arrays, the equation would be:
N = k D • A = 1.9 • N I/O gates chip gates
In Figure 5-2, this estimate of required I/O count is compared with a few representative examples of late 1980s vintage gate array families. It is clear that a consequence of smaller design rules and denser gates is more I/O required for the same size chips! This means either finer pitch periph- eral I/O or switching to the more efficient area array I/O.
2,000 1000K Gates/in2
1,500 500K Gates/in2 (486 density) Future Generation 1,000 250K Gates/in2 200K Gates/in2
I/O Required on CMOS Density 100K Gates/in2 500 One Micr
10K Gates/in2 0 0.0 0.2 0.4 0.6 0.8 1.0 √Die Size (inches)
Source: ICE, "Roadmaps of Packaging Technology" 15793
Figure 5-2. I/O Required Increases with Gate Density
For gate arrays fabricated with deep submicron design rules, the integration levels are high enough, and bussed I/O are sufficiently prevalent that RentÕs Rule no longer applies. For exam- ple, the 1996 generation ASICs, at 0.35 micron design rules, have a gate density of roughly 0.4M/cm2. The largest ASIC, 18mm on a side, would have about 3.2M gates, and by RentÕs Rule, require 3,400 I/O!
By comparison, the LSI Logic G10 family of gate arrays, at 0.35 micron design rules and slightly under 18mm on a side, has a maximum usable number of gates of about 2.5 million. However, it has a capacity of only about 800 I/O. This is significantly lower than the prediction from RentÕs
INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-3 Driving Forces on Packaging: Physical Interconnects
Rule. Part of the reason is that 800 I/O were all that could be practically interconnected with cur- rent generation wirebonding equipment. This family is pad limited. Even so, there would never be designs requiring 3,400 I/O because of the high integration levels and the high level of func- tionality. Designs of greater than 200,000 gates are approaching the system-on-a-chip, and begin to fall significantly under RentÕs Rule.
The coefficients for RentsÕ rule have been derived empirically based on a study of gate arrays built in the 1970s and 1980s. The predictions using these coefficients are a measure of the number of signal I/O to fully utilize all the gates as part of a larger ÒrandomÓ logic system. When there is significant integration and mostly busses as the interface, RentÕs Rule should be used as an upper limit of the required number of I/O. Chips with this high an integration level do not have the same interconnect requirements as random logic.
The SIA roadmap for pin count takes into account the impact from higher integration levels and the implementation of bussed I/O. Figure 5-3 contrasts the SIA prediction for I/O with RentÕs Rule prediction, based on the SIA values for chip size and gate density. The large and growing discrepancy is a measure of the impact from the two factors of integration functionality and bussing. Even so, the off- chip I/O count is predicted to grow considerably.
80,000
70,000
Rent's Rule I/O 60,000 SIA Prediction SIA Rent's Rule
50,000
40,000 I/O Off-Chip 30,000
20,000
10,000
0 1994 1996 1998 2000 2002 2004 2006 2008 2010 Year of Introduction Source: ICE, "Roadmaps of Packaging Technology" 22196
Figure 5-3. SIA Off-Chip I/O Compared to RentÕs Rule
5-4 INTEGRATED CIRCUIT ENGINEERING CORPORATION Driving Forces on Packaging: Physical Interconnects
Based on the SIA roadmap predictions, we can estimate the new values for RentÕs Rule that match the SIA roadmap. A good approximation is obtained using:
k = 0.2 p = 0.5
The match to the projected SIA predictions with these coefficients to RentÕs Rule is also shown in Figure 5-3.
IMPLEMENTING OFF CHIP INTERCONNECTS
There are two configurations for I/Os off a chip:
1. a single row or two staggered rows around the periphery 2. an array of pads on a grid over the surface of the die
The maximum number of pads, Npads, on a chip is constrained by the pad pitch and perimeter for peripheral I/O,
4L N = chip pads P pads and the grid pitch and chip area for area array,
L2 N = chip pads P2 pads
This is diagrammed in Figure 5-4. The number of pads constrained by these two approaches is shown in Figure 5-5 for various pitches and for one and two rows of pads.
Using the die sizes and pin count predictions of the SIA roadmap, the pad pitches that would be needed can be estimated. For example, if a single peripheral row is used, a pad pitch of 80 microns is required for current generation ASICs. This is right at the capability of 1996 wirebonding in volume production. To meet future ASIC needs, this pitch must steadily decrease.
In contrast, if the I/O were to be on an area array, the pitch would only have to be 600 microns, or 24mils, a much more realistic effort. This is a strong driving force for area array off chip I/O. In addition to accommodating a higher I/O count without heroic mechanical feats, area array also offers the opportunity for better electrical performance by allowing more power and ground pads distributed over the surface of the chip, where they are needed the most.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-5 Driving Forces on Packaging: Physical Interconnects
N gates PERIPHERAL PADS Chip
Lchip
4 L chip N = pads P pads P pads
AREA ARRAY PADS P pads
2 L chip N = pads 2 P pads Lchip
N gates = Number of available gates P = Pitch of the pads pads Lchip = Length of one side of the die
N I/O = Number of I/O required for the gates
N pads = Number of pads constrained by the geometry N gate D = Density of the gates = gates 2 L chip Source: ICE, "Roadmaps of Packaging Technology" 15794
Figure 5-4. Chip Pad Terms
INTERCONNECT DENSITY: REQUIREMENTS
Various factors will contribute to how closely the chips can be mounted on a board. This next level in the packaging hierarchy, the interconnect substrate, is a planar substrate that interconnects the chips either as bare dice, as in a multichip module or chip-on board (COB), or as packaged dice. Once placed, all the leads from all the chips will have to be interconnected.
5-6 INTEGRATED CIRCUIT ENGINEERING CORPORATION Driving Forces on Packaging: Physical Interconnects
5mil Area Array 10 4 10mil Area Array
(Current IBM C4) 2mil Peripheral MCA4 3mil Peripheral 10 3 4mil Peripheral 6mil Peripheral
MCA3
Number of I/O 10 2 25mil Area Array
10 1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 √Die Size (inches) Source: ICE, "Roadmaps of Packaging Technology" 15795
Figure 5-5. How the Pad Pitch Constrains the Number of Possible I/O
In CAD terminology, each lead is called a node. The electrically connected nodes form one net. A generic board is diagrammed in Figure 5-6. The relevant terms are:
L total trace = total length of all the traces required Nnets = number of nets in the net list for the chips Nleads = number of leads per chip that must be interconnected Nfanout = number of input leads connected to one output Nchips = number of chips in the collection Pfootprint = pitch between chips on the board
There are many ways of describing the interconnect needs for a collection of chips. The method that offers the most generality and is easiest to understand uses the total length of trace, Ltotal trace, as the metric for interconnect. From this, other parameters such as inter- connect density and number of traces per linear inch can be derived.
The average number of nodes attached to a single net is roughly Nfanout+1. If there are three other leads to which an output driver goes, then the net consists of a total of four nodes: the output driver and the three input leads. Used in this way, the fanout number is a rough measure of the degree of bussing. If there is a lot of bus interconnect, Nfanout can be as high as 20. In general, for random logic, without knowing anything else about the architecture, a reasonable value of Nfanout is three.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-7 Driving Forces on Packaging: Physical Interconnects
Single-Chip Package
Net Node Node Substrate (area, A)
Node Node
P Footprint
Source: ICE, "Roadmaps of Packaging Technology" 15797
Figure 5-6. A Net with 4 Nodes
The electrical design may influence the fanout number or the distribution of trace lengths. For example, in a transmission line environment, multiple nodes are connected as a daisy chain rather than a star. With a near-end, series terminated net, such as with the Motorola MCAIII STECL arrays, second incident switching is often used, and there is a greater use of point-to-point inter- connect to avoid excessive wiring delays.
Each fanout will require one interconnect trace segment. By definition, each of these traces will be electrically connected, and be contained on one net. Among the collection of Nchips, there will be a total of Nchips x Nleads nodes. The total number of nets among the collection of chips is given by:
N • N = chips leads Nnets Nfanout + 1
The total length of traces required by these nets will be the product of the number of interconnect trace segments per net, the total number of nets, and the average length of the trace segments,
5-8 INTEGRATED CIRCUIT ENGINEERING CORPORATION Driving Forces on Packaging: Physical Interconnects
IBMÕs studies suggest that a useful way to measure the average interconnect length,
< L >= R • P trace footprint
The average number of chip pitches of an interconnect trace segment, R, will obviously depend on the chip placement, routing algorithm, and interconnect architecture. IBMÕs studies indicate a rough approximation can be obtained using R = 1.5 chip pitches as an average trace length. This indicates that with proper layout, most of the routing runs to adjacent chips on a board.
The total length of interconnect required becomes:
N L = fanout N • N • (1.5) • P total trace N + 1 chips leads footprint fanout
The interconnect density required, Dinterconnect.R, is the length of trace required per unit area of the substrate to perform the required interconnect. For a collection of chips, the substrate area that contains all the traces, Asubstrate, is:
A = N • P2 substrate chips footprint
The interconnect density required is given by:
N 1 D = fanout • N • 1.5 interconnect.R N + 1 leads P fanout footprint
This relationship points out the important terms. It shows that the interconnect density required grows with the number of leads coming off each chip and increases as the footprint is reduced, as when the chips are moved closer together.
For the simple case when all the leads are on the periphery of the footprint, with a pitch of Pleads, the interconnect density required can be approximated by:
= 4 = 6 Dinterconnect.R 1.5 Pleads Pleads
INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-9 Driving Forces on Packaging: Physical Interconnects
For example, to interconnect an array of 50mil pitch chip carriers, the interconnect density required is about 120in/in2. For the case of 11mil pitch leads, such as the outer leads of the single- chip packages of the now extinct ETA10 super computer, the required interconnect density is 540in/in2. This relationship is shown graphically in Figure 5-7, compared with a few examples of the interconnect density required in certain systems.
10 4
10 3 DEC Motorola
hes/sq in) Modules ETA/Honeywell 2 Packages (inc 10 25mil APS Chip 50mil
connect Density Required nChip Carrier Chip 100mil Modules Carrier Chip Carrier Inter 10 1 1 10 100 Peripheral Lead Pitch (mils) Source: ICE, "Roadmaps of Packaging Technology" 15798
Figure 5-7. Selected Interconnect Densities Required
INTERCONNECT DENSITY: IMPLEMENTATIONS
The earliest interconnect substrate, the printed circuit board, was stimulated by the need to reduce the cost of hand wiring vacuum tubes. The introduction of the first transistors in early 1950, with their finer pitch pins also accelerated the implementation of the printed circuit board. It has become conventional to call the bare board, before any components are assembled on it, a printed wiring board (PWB). After the components have been added, it is called a printed circuit board (PCB).
A variety of interconnect substrates have evolved over the last 50 years. Through the introduction of new design concepts, new materials, and new manufacturing processes, the complexity and value of the interconnect substrates have increased dramatically. In addition to the traditional FR4 (epoxy-glass) PWBs, there are substrates with multilayers composed of:
¥ thick-film polymer ¥ thick-film ceramic ¥ high temperature cofired ceramic ¥ low temperature cofired ceramic ¥ and thin-film metal, polymer or glass inner layer dielectrics, substrates.
5-10 INTEGRATED CIRCUIT ENGINEERING CORPORATION Driving Forces on Packaging: Physical Interconnects
All of these variations are described in later chapters.
With all their differences, the interconnect capabilities of all the substrates can be described with the following terms:
Nlayers = the number of metal layers with signal traces Pvias = the closest center-to-center pitch between vias Ntracks = the maximum number of signal traces that will fit between vias at their closest spacing
An ultimate interconnect density can be defined, Dinterconnect ultimate, based on the total length of trace that can be patterned in the metallization per unit area. Based on these definitions, the ultimate interconnect density capability of an interconnect substrate is:
N • N = layers tracks Dinterconnect ultimate Pvias
For example, a low cost, double sided printed circuit board, with vias on 100mil centers, and having a line pitch such that two traces can fit between the via holes, will have an ultimate inter- connect density of 20 inches of trace per square inch of board area, per side, or 40in/in2. If a square inch were to be cut out of the board, and all the traces peeled off and placed end to end, they would extend 40 inches. Another way of looking at this is if all the traces were going in the same direction and a cut were to be made through the board, across the traces, it would cut through 40 traces per inch of cut.
More advanced circuit boards, commonly used for low end PC motherboards, typically use four metal layers. The inner two are power and ground and the outer two are signal layers. The via grid pitch is 50mils, with two tracks of conductors between them, at 5mil line and space. This board has an ultimate interconnect density of 40 inches/in2, with the added benefit of lower noise and lower EMI.
In contrast, at the other extreme of fine lines, the interconnect density on a chip, with a via pitch of 1 micron and one track routing on two metal layers would be 50,000in/in2.
The above analysis is based on the use of every routing channel possible. In practice, both rout- ing algorithms and technology choices limit the actual interconnect density capability, Dinterconnect.C, to no more than 50 percent of this ultimate:
N • N = • layers tracks Dinterconnect.C 0.5 Pvias
INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-11 Driving Forces on Packaging: Physical Interconnects
In Figure 5-8, the interconnect density capabilities of various technologies are shown. There is a dramatic jump in density from a 12 signal layer PWB, with two tracks on a 100mil via pitch grid, having 120in/in2, to a thin-film substrate, with two signal layers, at one track on a 3mil via pitch grid, having 330in/in2. The latter interconnect density, which is quite large, is required to inter- connect a collection of bare dice closely spaced.
/in) 2,000 2 1,800 32 Layers- Traces 1,600 24 Layers- Traces 1,400
1,200 Fujitsu 1,000 nChip VP2000 12 Layers- IBM, 800 Traces TCM 600 8 Layers- Traces 400 2 Layers-
connect Density Capability (in 12 Signal Layer, 200 Traces DEC, 2 Track, High APS
Inter Performance PWB 0 0 1 2 10 10 10 Via Grid Pitch (mils) Source: ICE, "Roadmaps of Packaging Technology" 15799
Figure 5-8. Interconnect Density and Via Grid Pitch
Some technologies are less efficient than this. In interconnect substrates with only fixed through-hole vias, such as PWBs, using more than two tracks means that when a middle track makes contact with a via grid point, it will block the routing channel for some traces on other layers, which cannot use this via, thereby dropping the interconnect density capability, as the layer count grows.
INTERCONNECT DENSITY: PRICE
Each of the different interconnect technologies, printed wiring board, thick film, cofired ceramic, multilayer thin film, and on-chip multilayer, have a different interconnect density capability, a dif- ferent manufacturing cost, and a different level of maturity.
The associated prices for a particular technology are both dynamic and complex. Market forces affect prices as much as technical capability. Prices drop as products move up the learning curve, competition from multiple suppliers increases, and alternative technologies develop. Estimating prices is thus prone to be based on generalities, and should not be trusted to yield better than order of magnitude trends.
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George Messner has analyzed the prices of printed wiring boards. At the low end, a double-sided board with 50in/in2 of interconnect is priced at roughly $0.1/in2. This corresponds to roughly $0.002/in of trace. A four-layer board, with 100in/in2, is priced at $0.004/in of trace. As the board complexity increases, the price per inch of interconnect increases as well. A 14 signal layer board, for example, has a price of around $0.02/in of trace. These are summarized in Figure 5-9.
104 Multi-Chip Silicon Modules Interconnect Confired
Thin Film
18 Layer
103 Microwire 2S
14 Layer Confired 2S
Microwire 1S
1986 Priceline
1984 10 Layer Priceline IC Area (BPA) 8 Layer 102
d Cost (0.01/sq in)
4 Layer
Boar
1992 Priceline (0.2¢/Inch)
Two-Sided Thick Film PWB 10 7.5 PTF
5 One-Sided PWB PTF 2.5
1 10 20 40 60 80 100 200 400 600 1,000 2,000 4,000 6,000 Available Interconnect (in/sq in) Source: ICE, "Roadmaps of Packaging Technology" 12960A
Figure 5-9. Board Cost/Interconnect Density Relationships
In thin-film multilayer interconnects, with a 3mil line pitch and two signal layers, the possible interconnect density is about 330in/in2. Estimates of the price of these substrates, once they have proceeded farther up the learning curve, are about $10/in2. This corresponds to about $0.03/in of trace.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-13 Driving Forces on Packaging: Physical Interconnects
It is remarkable that these last two interconnect technologies offer about the same prices per inch of trace when utilized at their capacity. As a very rough rule of thumb, all high density intercon- nects cost about $0.01/in. The number of gates that will be contained in a system will define the number of nets and the number of individual traces needed to perform all the interconnection. The total interconnect price will clearly be lower if the interconnects are made as short as possible.
It is useful to compare off-chip interconnect prices to the interconnect on the chip. IC technology with five micron pitch and two signal layers offers about 10,000in/in2 interconnect density. It is difficult to estimate the cost of making just the interconnect on the IC. Much of the capital costs associated with IC fabrication is related to patterning the sub-micron gate features. The cost to process a one micron, CMOS, 125mm wafer is about $200, with a usable area of 15in2. If we esti- mate that the interconnect represents about half this value, then the interconnect cost per area is about $7/in2. The price per inch of trace is about twice the cost, $14/10,000in. or $0.0014/in.
This is significantly below the price of high density interconnect substrates, and reflects the pos- sible price curve for thin film multilayer technology. It also points out the cost-conscious strategy: drive the interconnects onto the chip when ever possible.
When volume can absorb the NRE (non-recurring engineering) costs associated with a gate array or FPGA (field programmable gate array) design, the interconnect costs will be minimized by putting as much interconnect as possible on the chip, or using a packaging methodology that results in the smallest sized system.
Driving toward a denser system will also minimize the length of the interconnects and drive toward lower manufacturing costs. In other words, ÒDenser is cheaper.Ó
VIA DENSITY: REQUIREMENTS
The key feature in multilayer interconnects is the ability to perform three-dimensional wiring with the use of multiple planes of interconnect, separated by insulating dielectrics and interconnected with conducting vias.
As the interconnect density requirements increase, the via density required to interconnect the traces increases as well. In general, a simple estimate is that for each trace that connects a pair of pads, there will be a minimum of three vias required; to connect from the first pad to the x layer, to the y layer, and then up to the second pad. This is illustrated in Figure 5-10. This number can range up to 5 vias per pair of pads when there are many nets and escape traces required.
For surface mount devices, each pad requires a via in the vicinity of the package to connect to an x or y routing layer. At the very least, there must be a via per pad within the footprint of the pack- age. At worst case, two vias are needed within the footprint of the package. One via from the sur- face pad to the escape trace, and a second via from the escape trace to a routing channel.
5-14 INTEGRATED CIRCUIT ENGINEERING CORPORATION Driving Forces on Packaging: Physical Interconnects
= a via pad
Minimum routing between Y layer pads using 3 vias
X layer
X escape
Typical routing between Y layer 2 pads requiring escape traces, using 5 vias
Y escape
X layer Source: ICE, "Roadmaps of Packaging Technology" 22197
Figure 5-10. Number of Vias Required to Route a Pair of Surface Pads
This relationship points out that, in general, for every lead off a package, at worst case, two vias must fit within the footprint area associated with the package. This condition defines the effec- tive footprint of the device on the board. Within the region required to connect the device to the routing channels, no other device can be placed.
Exactly as our intuition would predict, if the effective footprint is to be no larger than the physi- cal package footprint, the required via density would have to increase as the pitch of the leads decreases. For the special case where all the leads are on the periphery of the package and the footprint is equal to the length of one side of the package, the via density required is:
= 32 Dvias.R 2 Nleads Pleads since:
= Nleads • Pfootprint Pleads 4 for a peripherally leaded package.
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The via densities required to interconnect peripherally leaded packages with various pitches are shown in Figure 5-11. For example, for 50mil pitch chip carriers, having 160 leads (two inches per side), the via density required is 320 vias/4in2 = 80/in2. For a 308 pin PQFP, on 25mil centers, the via density required goes up to 166/in2.
10 5
10 4 6mil 8mil 12mil 10 3 Bare Chip umber/sq in) (TAB or Wirebonded) 10 2 25mil
50mil Single Chip 10 1 100mil Package Via Density (n
10 0 0 200 400 600 800 1000
Number of Leads Source: ICE, "Roadmaps of Packaging Technology" 15800
Figure 5-11. Via Density Required to Interconnect Peripheral Leaded Devices
In the case of a pad- or pin-grid array, the via density required is roughly:
= 2 Dvias.R 2 Pleads since:
P = N • P footprint leads leads for an array-leaded package.
This is shown in Figure 5-12. For a pin pitch of 100mils, the via density required is roughly 200/in2. For a BGA with 50mil centers, the via pitch is 800/in2. Because this is higher than most boards can practically accommodate, the effective footprint of BGA packages is often larger than the physical package size, and there is a limit to how closely they can be spaced, constrained by the available via density. For this reason, to minimize the need for escape traces, the inner balls of a BGA are often excluded, leaving typically 4-6 rows of balls on the periphery. An example of the footprint of a large BGA is shown in Figure 5-13.
5-16 INTEGRATED CIRCUIT ENGINEERING CORPORATION Driving Forces on Packaging: Physical Interconnects
10 7
10 6 umber/sq in) 10 5
10 4 NEC FTC Package Surface Mount BGA 3 IBM C4 10 Chips 100 mil PGA
Via Density Required (n 10 2 0 10 20 30 40 50 60 70 80 90 100 Component Grid Pitch (mils) Source: ICE, "Roadmaps of Packaging Technology" 15801A
Figure 5-12. Via Density Required in the Interconnect
Courtesy of ASAT/ 22198 Source: ICE, “Roadmaps of Packaging Technology”
Figure 5-13. 352 Ball Tape Ball Grid Array Package
VIA DENSITY: CONSTRAINTS
In all planar interconnect technologies, there are two types of vias: those that go through the entire board, typically used in PWB technology, called plated through-holes (PTHs), and vias that inter- connect only a few selected layers. These are called buried vias and blind vias. Buried vias are used exclusively in all other planar interconnect technologies such as thick film, cofired ceramic, and multilayer thin film, which are fabricated layer by layer or sequentially.
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There are two main limitations with PTH vias. In general, the more layers in the board, the wider the hole must be and the farther apart adjacent vias have to be positioned. This means lower via density. Secondly, only one via can exist at each surface location. This is a severe constraint. An example of a PTH via in a circuit board is shown in Figure 5-14.
0.15mm Hole Diameter 1.2mm Thick Panel
Source: Electrochemicals/ ICE, “Roadmaps of Packaging Technology” 22174
Figure 5-14. Mechanically Drilled Through Hole in FR-4
For example, with a 100mil via grid, if every possible via site is used, there can be no more than 100 vias/in2. The use of through-hole components requires a 100mil grid, at least in the region of the components. A 50mil grid of PTHs, common in surface-mount boards, allows 400 vias/in2.
With PTH technology, the via density is constrained to D vias.C , given by:
= 1 Dvais.C 2 Pvias
Buried via technology can allow vias that connect different sequential layers to occupy the same grid point and can be fabricated on a tighter pitch. The via density given immediately above is a lower limit. Buried vias between more than two sequential layers are either stacked one on top of the other, or staggered from layer to layer. In general, if the metallization pattern is fabricated by an additive process such as screen printing or pattern plating, stacked vias can be fabricated. If the patterning uses a subtractive process, only staggered vias can be produced. Examples of these types of vias are shown in Figure 5-15.
5-18 INTEGRATED CIRCUIT ENGINEERING CORPORATION Driving Forces on Packaging: Physical Interconnects
Source: Advanced Packaging Systems
Staggered vias in a thin-film multilayer substrate
Source: IBM
Stacked vias in a cofired ceramic substrate Source: ICE, “Roadmaps of Packaging Technology” 16086
Figure 5-15. Buried Via Examples
For similarly dimensioned vias, stacked vias can be placed closer together than staggered. In a staggered via arrangement, two pads are required on each intermediate layer, one for contact with the lower layer, and one as a landing pad for the upper layer.
The via density possible will depend on the via pitch and the number of layer pairs. The real den- sity advantage of buried vias comes from the much lower pitch possible. For example, with a via grid pitch of 4mils and just one via per grid point, typical of multilayer thin-film technologies, the via density possible is 40,000/in2. This number so far exceeds any near-term requirement that the difference between stacked or staggered vias is insignificant.
This example also points out the very significant difference between thin film technologies with non mechanically drilled vias and traditional laminate technologies. Though linewidths may be close, thin film technologies offer much finer via pitch and much higher via densities. This is of
INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-19 Driving Forces on Packaging: Physical Interconnects
value when fine pitch area array devices are to be interconnected, as for example 25mil pitch micro BGAs. The required via pitch, not exceeding the body side, is 3,200/in2, easily possible with non- mechanically drilled vias.
Pad Density
For every pad on a package, there must be between one to two vias in the board, depending on the routing complexity. For this reason, the surface pad density is a measure of the required via density in the board, with the condition of not increasing the package attach effective footprint over its physical size.
As package pin count increases, and package size decreases, the pad density required on a board increases and the via density required will increase. Figure 5-16 shows the historical trend of the pad density on a circuit board for a variety of systems. Surface pad densities and via densities will always be driven to higher values, as functional density increases.
600 NEMI Roadmap 500 h
400 State-of-the-Art 300 Leading Edge er Square Inc 200
ads P 8 1/2 Years Commodity Product P 100 10 Years 0 1980 1985 1990 1995 2000 Year Source: Prismark/ICE, “Roadmaps of Packaging Technology” 22194
Figure 5-16. PCB Attachment Pad Density Over Time
As shown in Figure 5-11, peripheral packages with course lead pitches require a relatively low pad pitch and via pitch. At fixed lead pitch, the surface pad density actual decreases with higher pin count. However, the packaging efficiency of peripheral devices is relatively low. For example, a conventional 25mil pitch PQFP with 208 pins, having a die with 5mil pad pitch has a packaging efficiency of only 4%. However, even with this low efficiency, it would have a pad density of almost 125 pads/in2. To keep the effective package footprint on the board within the geometrical footprint requires at least 50mil center PTH vias. As the lead pitch decreases, the required via den- sity in the boards increases.
5-20 INTEGRATED CIRCUIT ENGINEERING CORPORATION Driving Forces on Packaging: Physical Interconnects
For area array packages, the pad density on the board is the pad density on the package. If unfilled arrays of balls are used, to minimize the escape routing, only one via per pad may be required. Pad density, as it reflects on via density and trace density, is a measure of the minimum complexity required for a substrate.
BOARD DENSITY REQUIRED FOR AREA ARRAY ÒESCAPESÓ
For the case of pin- or pad-grid arrays, there is an additional requirement on interconnect density and via density. There must be sufficient traces available under the footprint to allow all the inner pads to ÒescapeÓ to the periphery, where they can be interconnected to routing channels to the other chips. For a total number of pins, Npins, arranged in an area array, there must be a suffi- cient number of tracks, Ntracks, and total number of signal layers, Nlayers, so that each interior pin can have a trace that connects the pin to the periphery, whence it can go wherever required.
This condition, diagrammed in Figure 5-17, requires a minimum number for the product, Ntracks x Nlayers, given by: N • > pins − Ntracks Nlayers 2 2( N − 1) pins
......
......
......
......
......
Npins N traces x N layers > Ð 2 2(√Npins Ð1)
Source: ICE, “Roadmaps of Packaging Technology” 15803
Figure 5-17. PGA ÒEscapesÓ
This requirement is shown graphically in Figure 5-18. With 289 pins, the requirement is for seven track layers. With two-track technology, this requires at least four signal layers.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-21 Driving Forces on Packaging: Physical Interconnects
100
s Required 10 er y k-La rac T 1 IBM 289 Pin PGA 3081 TCM Number of 0.1 10 100 1,000 10,000 Number of Pins in PGA
Source: ICE, “Roadmaps of Packaging Technology” 15804
Figure 5-18. PWB Substrate Complexity for PGA ÒEscapesÓ
This requirement on the minimum number of track layers is in addition to the interconnect den- sity required for the routing. The use of even one PGA device on a board will automatically define the minimum complexity of the board. For example, in the IBM 3081, the TCMs, with 1,800 pins in the base are interconnected by a PWB. The formula above suggests that the level of complex- ity must be nearly 20 track layers. In fact, the substrate is 18 signal layers, just to accommodate the pin escapes.
With pin grid arrays, the pins require large vias, which means fewer traces between the holes, and in general, more layers. With surface mount area array devices, the via holes can be smaller and fewer escape layers required. When the board needs to use 10-12 layers anyway to accommodate the inter-chip routing, there may not be a penalty of using area array devices.
CHIP-ATTACH FOOTPRINT: CONSTRAINTS
In addition to the size of the die, two other geometrical factors, the area required for the leads and for the assembly alley way, contribute to the package-attach footprint on the substrate. For peripheral attach, there is often a minimum pitch of the leads, Pleads, that the substrate can accept. In the case of PWBs, for example, this is currently about 10mil pitch routinely, with 8mil pitch available at an added cost. For cofired ceramic, the minimum pitch is currently 8mils. With thin-film substrates, features down to 4mil pitch are routinely processed. These surface features are shown in Figure 5-19.
A space transformer is required to go from the chip pad pitch to the substrate pitch. This is usu- ally the single-chip package, which has an internal leadframe, either as stamped metal, or as a laminated substrate. Both TAB leadframes and wirebonds have also been used for this function.
5-22 INTEGRATED CIRCUIT ENGINEERING CORPORATION Driving Forces on Packaging: Physical Interconnects
Thick Film
Cofired Ceramic
PWB
Thin Film
0 2 4 6 8 10 12 Surface Pad Peripheral Pitch in Mils
Price Standard
Demonstrated Premium Production
Source: ICE, "Roadmaps of Packaging Technology" 15805A
Figure 5-19. Surface Features on Substrates
The surface pitch, Pleads, and the number of leads, Nleads, defines the length of the side of the square the leads occupy on the surface, Lleads:
• = Pleads Nleads Lleads 4
In the case of a grid array, the length of the side of the chip-attach area on the substrate is :
L = P • N leads leads leads
In addition to the surface pad features of the substrate, the assembly method limits the pitch of the leads. As the pitch goes down, the level of sophistication of the automated tools increases and the associated manufacturing costs and infrastructure required goes up. This poses a practical cost constraint, not an engineering constraint.
Both 50mil and 25mil pitch automated assembly lines are common. In 1992, ETA had in place a pick-and-place facility that routinely assembled 11mil pitch chip carriers. In the early 1990s, both Siemens and DEC had facilities to surface-mount 8mil pitch outer lead bonds of TAB chips. For chip-on-board surface mount, 12mil pitch wirebonds are routinely used.
In addition to the surface pad pitch, an assembly alley of width, Lassembly, is often required around the perimeter, which limits the closest approach of an adjacent chip. This is typically on the order of 100mils. The chip-attach footprint on the substrate will define how closely chips can be assembled, which is described by the pitch of the footprint of the attached chips, Pfootprint:
P = L + 2L footprints leads assembly
INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-23 Driving Forces on Packaging: Physical Interconnects
PACKAGING EFFICIENCY
Even at its best with conventional peripheral and area array packages, the packaging efficiency of putting silicon on a board is in general very poor.
Assuming that the silicon die is pad limited and has a total of Npads on the periphery with a pitch, Ppads, the area of the silicon becomes:
N 2 A = pads • P chip pads 4
In a peripheral-leaded package, the area of the package is determined by its lead pitch, Pleads, which is often determined by the assembly technology chosen. The package area becomes:
2 = Nleads • Apackage Pleads 4
In the case of a PGA or BGA package, in the best case, with a cavity-up configuration so that the entire bottom area is covered with pins or pads, the area of the package is:
A = N • P2 package leads leads
The packaging efficiency of the peripheral-leaded package is:
2 A P η = chip = pads A P package leads
Because the areas of the silicon and the package both scale with the number of pads, the packag- ing efficiency is independent of the number of pins. For example, if the chip pitch is 4mils, common in most high end CMOS devices, and the pitch of the leads is 25mils, the highest possi- ble packaging efficiency for a board populated edge to edge with packages is 2.5%.
In the case of a PGA or BGA, the packaging efficiency is:
2 Achip 1 Ppads η = = N A 16 pads P package leads
For example, with the chip having 4mil pitch and a BGA with 50mil pitch and 400 pads, such as a mid performance range ASIC, the efficiency is 16%. However, the via density required to inter- connect the solder balls to the routing channels is 800/in2, if escape tracks are needed. If the sub- strate is not able to provide this, the implemented packaging efficiency may be even lower than
5-24 INTEGRATED CIRCUIT ENGINEERING CORPORATION Driving Forces on Packaging: Physical Interconnects
this. For the same 400-pad chip with 4mil pitch of the pads on the chip, packaged in a 100mil grid PGA, the packaging efficiency is only 9%. This is the absolute best a 100mil grid PGA can do. This difference is one of the motivations for the transition to BGA over PGA.
The packaging efficiencies of single-chip packages with various pitches are shown in Figure 5-20. It is clear that the only way to increase the packaging efficiency is to use much finer pitch periph- eral leads, a finer pitch BGA, or to remove the single-chip package and go directly to a chip-on- board technology.
100
10mil grid DCA (FC)
cent) 25mil grid chip scale package
er 10 50mil grid BGA y (P 100mil interstitial PGA 10mil periphery (COB) 100mil pitch PGA 25mil periphery (PQFP)
ging Efficienc 1
ka 50mil periphery (PQFP) ac P
0.1 0 100 200 300 400 500 600 700 800 900 1,000 Package Pin Count Source: ICE, "Roadmaps of Packaging Technology" 22199
Figure 5-20. Packaging Efficiency for Peripheral and Area Array with 4mil Pad Pitch on the IC
INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-25 Driving Forces on Packaging: Physical Interconnects
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