DRIVING FORCES ON PACKAGING: 5 PHYSICAL INTERCONNECTS The single most important element of the package and interconnect that influences the system clock speed, the performance density, and often the cost of a system, is how close together the devices can be placed. The term that best describes this is packaging efficiency. The three fabri- cation and assembly issues that constrain the packaging efficiency are: ¥ the I/O off the chipÑthe number, the form factor, the pitch ¥ the I/O off the packageÑthe number, the form factor, the pitch ¥ the interconnect substrateÑthe pad pitch, the via pitch, the line pitch, the number of layers Pin Count Requirements and RentÕs Rule As the number of gates on a single die has increased, the number of I/Os required to interface them to the outside world has also increased. In 1960, E.F. Rent of IBM identified a definite empir- ical relationship between the number of gates in a block, Ngates, and the number of I/Os they required, NI/O. This relationship, since coined RentÕs Rule, has been extended and generalized to encompass a variety of chip types and module sizes. Figure 5-1 is a plot of the signal I/Os required for various gate arrays and microprocessors. In general, for every 4 to 10 signal I/Os, one power or one ground is used. As the clock frequency goes up, a higher fraction of power and ground pads are required to keep switching noise at acceptable levels. For clock frequencies over 250MHz, the ratio is closer to 3:1 signal to power/ground pads. Empirically, the RentÕs Rule relationship between total signal I/Os required and gate count is: NkN= p I/O gates where k and p are constants that depend on the architecture and the partitioning. RentÕs Rule graphically shows the ever greater demand for more I/Os as the number of gates increases. INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-1 Driving Forces on Packaging: Physical Interconnects For the case of microprocessors: k = 0.82 p = 0.45 For the case of already committed gate arrays: k = 1.9 p = 0.5 The original values that Rent found applicable for his systems were: k = 2.5 p = 0.61 104 Bipolar Gate Array CMOS Gate Array Microprocessor SRAM DRAM 103 2 Number of Signal Pins 10 101 102 103 104 105 106 Number of Gates or Bits Source: University of Arizona/ICE, "Roadmaps of Packaging Technology" 13651A Figure 5-1. I/O Pin Count Versus Complexity RentÕs Rule is a loose, empirical rule of thumb that can be used to roughly predict the number of I/Os a chip or module will need as the number of committed gates increases. Care must be exer- cised in using it. There is an explicit assumption that the partitioning will remain the same as the gate count increases. Of course, at some point, the functionality must reach the point where the I/O count decreases. After all, even the largest computer has at most a few hundred system-level I/Os for disk drive and keyboard access. The point at which the I/O requirements begin to fall under RentÕs Rule is a measure of the degree of partitioned functionality. 5-2 INTEGRATED CIRCUIT ENGINEERING CORPORATION Driving Forces on Packaging: Physical Interconnects Decreasing the I/O count off chip without resorting to multiplexing or degrading signal integrity, will always increase the performance density per unit cost, if only by reducing the component and assembly costs. Partitioning of gates and chips into functional units that will bring the I/O count under RentÕs Rule is a critically important step in the design cycle. Integrating more functional- ity on chip will most often increase the performance/cost. As the gate count available on gate arrays increases, the required I/O count will increase. From 2 the gate density, Dgate, in gates/in , the required I/O count for any die size can be calculated with RentÕs Rule. For gate arrays, the equation would be: N = k D • A = 1.9 • N I/O gates chip gates In Figure 5-2, this estimate of required I/O count is compared with a few representative examples of late 1980s vintage gate array families. It is clear that a consequence of smaller design rules and denser gates is more I/O required for the same size chips! This means either finer pitch periph- eral I/O or switching to the more efficient area array I/O. 2,000 1000K Gates/in2 1,500 500K Gates/in2 (486 density) Future Generation 1,000 250K Gates/in2 200K Gates/in2 I/O Required on CMOS Density 100K Gates/in2 500 One Micr 10K Gates/in2 0 0.0 0.2 0.4 0.6 0.8 1.0 √Die Size (inches) Source: ICE, "Roadmaps of Packaging Technology" 15793 Figure 5-2. I/O Required Increases with Gate Density For gate arrays fabricated with deep submicron design rules, the integration levels are high enough, and bussed I/O are sufficiently prevalent that RentÕs Rule no longer applies. For exam- ple, the 1996 generation ASICs, at 0.35 micron design rules, have a gate density of roughly 0.4M/cm2. The largest ASIC, 18mm on a side, would have about 3.2M gates, and by RentÕs Rule, require 3,400 I/O! By comparison, the LSI Logic G10 family of gate arrays, at 0.35 micron design rules and slightly under 18mm on a side, has a maximum usable number of gates of about 2.5 million. However, it has a capacity of only about 800 I/O. This is significantly lower than the prediction from RentÕs INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-3 Driving Forces on Packaging: Physical Interconnects Rule. Part of the reason is that 800 I/O were all that could be practically interconnected with cur- rent generation wirebonding equipment. This family is pad limited. Even so, there would never be designs requiring 3,400 I/O because of the high integration levels and the high level of func- tionality. Designs of greater than 200,000 gates are approaching the system-on-a-chip, and begin to fall significantly under RentÕs Rule. The coefficients for RentsÕ rule have been derived empirically based on a study of gate arrays built in the 1970s and 1980s. The predictions using these coefficients are a measure of the number of signal I/O to fully utilize all the gates as part of a larger ÒrandomÓ logic system. When there is significant integration and mostly busses as the interface, RentÕs Rule should be used as an upper limit of the required number of I/O. Chips with this high an integration level do not have the same interconnect requirements as random logic. The SIA roadmap for pin count takes into account the impact from higher integration levels and the implementation of bussed I/O. Figure 5-3 contrasts the SIA prediction for I/O with RentÕs Rule prediction, based on the SIA values for chip size and gate density. The large and growing discrepancy is a measure of the impact from the two factors of integration functionality and bussing. Even so, the off- chip I/O count is predicted to grow considerably. 80,000 70,000 Rent's Rule I/O 60,000 SIA Prediction SIA Rent's Rule 50,000 40,000 I/O Off-Chip 30,000 20,000 10,000 0 1994 1996 1998 2000 2002 2004 2006 2008 2010 Year of Introduction Source: ICE, "Roadmaps of Packaging Technology" 22196 Figure 5-3. SIA Off-Chip I/O Compared to RentÕs Rule 5-4 INTEGRATED CIRCUIT ENGINEERING CORPORATION Driving Forces on Packaging: Physical Interconnects Based on the SIA roadmap predictions, we can estimate the new values for RentÕs Rule that match the SIA roadmap. A good approximation is obtained using: k = 0.2 p = 0.5 The match to the projected SIA predictions with these coefficients to RentÕs Rule is also shown in Figure 5-3. IMPLEMENTING OFF CHIP INTERCONNECTS There are two configurations for I/Os off a chip: 1. a single row or two staggered rows around the periphery 2. an array of pads on a grid over the surface of the die The maximum number of pads, Npads, on a chip is constrained by the pad pitch and perimeter for peripheral I/O, 4L N = chip pads P pads and the grid pitch and chip area for area array, L2 N = chip pads P2 pads This is diagrammed in Figure 5-4. The number of pads constrained by these two approaches is shown in Figure 5-5 for various pitches and for one and two rows of pads. Using the die sizes and pin count predictions of the SIA roadmap, the pad pitches that would be needed can be estimated. For example, if a single peripheral row is used, a pad pitch of 80 microns is required for current generation ASICs. This is right at the capability of 1996 wirebonding in volume production. To meet future ASIC needs, this pitch must steadily decrease. In contrast, if the I/O were to be on an area array, the pitch would only have to be 600 microns, or 24mils, a much more realistic effort. This is a strong driving force for area array off chip I/O. In addition to accommodating a higher I/O count without heroic mechanical feats, area array also offers the opportunity for better electrical performance by allowing more power and ground pads distributed over the surface of the chip, where they are needed the most.