Sponsored by: Supported by: Welcome from the Mayor of San Diego

2 Welcome from ECTC General and Program Chairs

The Executive and Program Committees of the Electronic Components and Technology Conference (ECTC) welcome you to our 62nd conference at the San Diego Sheraton Marina and Resort, San Diego, Calif. This premier international conference is sponsored by the IEEE Components, Packaging and Manufacturing Technology Society (CPMT). The ECTC Program Committee represents a wide range of disciplines and expertise from the electronics industry around the world. We have selected more than 300 high-quality papers to be presented at the conference in 36 oral sessions, four interactive presentation session and one student posters session. The 36 sessions run through the daytime and cover peer-reviewed papers on 3D/TSV, sensors and MEMS, embedded devices, LEDs, co-design, RF packaging, microfluidics, and inkjet, in addition to conventional packaging topics such as advanced packaging technologies, all types and levels of interconnections, materials, assembly manufacturing, system packaging, optoelectronics, reliability, electronic components and simulation. The program committee strives to address new trends as well as ongoing technological issues. Four Interactive Presentation sessions feature technical peer-reviewed presentations presented in a format that enhances and encourages interaction. One student poster session focuses on research conducted in the academia presented by the budding scientists. Authors from companies, research institutes, and universities in nearly 20 countries will present at the ECTC, making it a truly diverse and global conference. In addition to the technical sessions that are held during the day, four panel sessions focusing on crucial topics presented by industry experts enhance the technical program. In the special session titled “Next Generation Packaging and Integration: The Transformed Role of the Packaging Foundry,” session chair Raj Pendse will gather a panel of experts to present and discuss the increased level of integration in the changing landscape and what subcontracted assembly companies are doing to address customer demand. This panel is intended to serve as an excellent roadmap review for the industry where significant portion relies on subcontracted assembly. The Panel Discussion on Tuesday evening at 7:30 pm, chaired by Rolf Aschenbrenner and Ricky Lee and titled “Power Electronics: A Booming Market,” will focus on power electronics from a packaging perspective. The Plenary Session on Wednesday 7:00 pm, chaired by Christopher Bower and titled “Photonics: Expanding Markets and Emerging Technologies,” will unveil the less-known world of photonics research and discuss how it can help improve the semiconductor revenues. Thursday evening starts with the Gala Reception at 6:30 pm and is followed by the CPMT Seminar at 8:00 pm, which is titled “Advanced Coreless Package Substrate and Material Technologies” and chaired by Kishio Yokouchi and Venky Sundaram. The Professional Development Courses (PDC), organized by the PDC Committee chaired by Kitty Pearsall, will be taught on Tuesday (8:00 am-5:30 pm). World-class experts in their fields offer 16 courses on different topics. Participants can catch up on new technology developments and broaden their technical knowledge base. The technical program and professional development courses are supplemented by the Technology Corner Exhibits where leading companies primarily in the electronics components, materials, and packaging fields exhibit their latest technologies and products. The exhibitors invite you to their reception on Wednesday at 5:30 pm. Along with our receptions and coffee breaks every day, luncheons are another great opportunity to network and discuss technical and business matters. It is our pleasure to announce that Greg Bartlett, the CTO of GLOBALFOUNDRIES will be the invited keynote speaker at the ECTC Luncheon on Wednesday. The International Electronics Manufacturing Initiative (iNEMI) will host the North American Workshop to solicit input for the 2013 iNEMI roadmap on Tuesday (8:00 am- 6:00 pm). There is always more than we can explain at the ECTC. Whether you are a manager, engineer, executive or a student, we invite you to experience the exiting developments in electronic components and technology. We would like to take this opportunity to thank our sponsors, exhibitors, authors and speakers, instructors, session chairs, committee members; and arrangement, finance, publication, and publicity chairs, as well as all the volunteers for their support and hard work. We also thank all conference attendees in advance for making the 62nd ECTC a great success. We hope you will like the program and enjoy the conference, and appreciate your feedback.

David McCann Senol Pekin General Chair Program Chair GLOBALFOUNDRIES Intel Corporation

3 Welcome from ECTC Sponsoring Organization

This is 2012! There have been many rigorous procedure ensures the outstanding quality of ECTC predictions about 2012, including the technical proceedings. The other three pillars of ECTC are most devastating one. No matter professional development courses, panels, and industrial which version of predictions you exhibition. Every year these events attract big crowds for believe in, there is one thing for sure: participation. With the conference location in southern the 62nd Electronic Components California, the 62nd ECTC will undoubtedly maintain its and Technology Conference in momentum in these three areas. San Diego will continue the glory Starting in 2011, the IEEE Components, Packaging & from the previous series of ECTC Manufacturing Technology (CPMT) Society has become conferences and achieve a big the sole sponsor to ECTC. This enables an effective and success! consistent operation of the conference. Being the president The core of ECTC is its technical of the sponsoring organization, I would like to extend the program, which typically consists of 36 oral sessions in three warm welcome from IEEE CPMT to all attendees of the full days. Together with two half-day interactive sessions and 62nd ECTC. I also would like to take this opportunity to one student posters session, the whole technical program thank numerous volunteers who contributed to the success accommodates approximately 350 papers from authors/ of the 62nd ECTC. There will be a luncheon hosted by IEEE presenters all over the world in academia and industry. CPMT on Thursday, May 31. Please join us as we extend our These papers were selected from a pool of more than 700 hospitality and appreciation. abstract submissions, which were reviewed by technical See you then! sub-committees that consist of about 150 dedicated experts Ricky Lee worldwide in electronic packaging and manufacturing. Such a President, IEEE CPMT Society

Conference Policies and Guidelines

Badges Conference attendees MUST wear the official conference badge to be admitted to all training courses, sessions, meals, Technology Corner Exhibits and all conference sponsored social functions. Medical Services For emergency medical services, locate any hotel phone, whether in your room or elsewhere in the hotel, and follow its directions for emergencies. Hotel “house” phones have been placed throughout the hotel and conference area for your convenience. If no phone can be located, please locate the nearest hotel staff or ECTC staff for assistance with your emergency. The closest available hotel staff person may be at the front desk. Personal Property The hotel’s safety deposit box is available for storing your valuables, particularly cash and jewelry. If there is a mini-safe in your room, you should consider using it. Smoking Policy The hotel does not allow smoking on it premise. Smoking is also NOT permitted at any ECTC activities including, but not limited to, functions, events, sessions, or seminars as well. Thank you for your consideration and cooperation.

4 Table of Contents

Conference Policies & Guidelines...... 4 Session 18: Innovative Test Methods...... 15 ECTC Luncheon Speaker...... 5 Session 19: Thru Via Technologies...... 16 iNEMI 2013 Roadmap Workshop...... 5 Session 20: Co-Design­ for the 3D Ecosystem...... 16 Registration...... 6 Session 21: Flip Chip Technologies...... 16 PDC Instructors and Proctors Breakfast...... 6 Session Chairs & Speakers Breakfast...... 6 Session 22: Precision Components, Sensors and RF Packaging...... 17 Speaker Prep Room...... 6 Session 23: Assembly Challenges of Area Array Packages...... 17 Companion Hospitality Room...... 6 Session 24: Inkjet Technology and Embedded Devices...... 17 Miscellaneous Information...... 6 Session 25: 3D Integration...... 18 Luncheons...... 6 Session 26: Advanced Wirebonding...... 18 ECTC Panel Discussion...... 7 Session 27: Bonding Materials and Processes...... 18 ECTC Plenary Session ...... 7 Session 28: New Trends in Mechanical Modeling and Characterization.... 19 CPMT Seminar...... 7 Special Session: Next Generation Packaging and Integration - Session 29: Novel Approaches in Wafer Level Manufacturing...... 19 the Transformed Role of the Packaging Foundry...... 7 Session 30: Interconnect Reliability...... 19 Professional Development Courses...... 8 Session 31: Applications with 3D Technologies...... 20 Session Chairs & Speaker Reception...... 8 Session 32: Advanced Substrate and Wafer Level Packaging...... 20 62nd ECTC Gala Reception ...... 8 Session 33: Substrates and Thermal Interface Materials...... 20 Technology Corner Reception ...... 8 Session 34: 3D Systems and Emerging PackagesThermal­ and Thermo­ ECTC Student Reception...... 8 Mechanical Studies...... 21 Continuing Education Units...... 8 2011 ECTC Paper Awards...... 9 Session 35: Optical Interconnects...... 21 Committee Meetings...... 9 Session 36: Integrated Microfluidics...... 21 Session 1: 3D Interconnect: Bonding and Assembly...... 10 Session 37: Interactive Presentations 1 (9:00 a.m. - 11:00 a.m.)...... 22 Session 2: Next Generation Packaging Reliability...... 10 Session 38: Interactive Presentations 2 (2:00 p.m. - 4:00 p.m)...... 22 Session 3: MEMS Integration and Processing...... 10 Session 39: Interactive Presentations 3 (9:00 a.m. - 11:00 a.m.)...... 22 Session 4: Signal and Power Analysis...... 11 Session 40: Interactive Presentations 4 (2:00 p.m. - 4:00 p.m.)...... 23 Session 5: LEDs and Emerging Optoelectronics Integration...... 11 Session 41: Student Posters (8:30 a.m. - 10:30 a.m.)...... 23 Session 6: Novel Interconnections...... 11 Session 7: Interposer Technology...... 12 Technology Corner Booth Layout...... 24 Session 8: 3D Reliability...... 12 Technology Corner Exhibits...... 25-35 Session 9: Sensors and MEMS...... 12 ECTC Executive Committee...... 36 Session 10: Conductive and Non-Conductive­ Adhesives...... 13 ECTC Program Committee...... 36-38 Session 11: Advanced Flip Chip and Underfill Assembly...... 13 63rd ECTC Call for Papers...... 39 Session 12: Solder and Material Characterization...... 13 63rd ECTC Dates and Location...... 40 Session 13: 3D TSV Manufacturing...... 14 Conference Sponsors...... 40-41 Session 14: Flip Chip Interconnect and Electromigration...... 14 Session 15: Innovative Processes and Techniques...... 14 Media Sponsors...... 41 Session 16: 3D Electrical Analysis...... 15 Hotel Layout...... 42 Session 17: Lead Free Solders...... 15 Conference at a Glance...... 43

Conference organizers reserve the right to cancel or change this program without prior notice.

ECTC Luncheon Keynote Speaker 2012 iNEMI Roadmap - Wednesday, May 30, 2012 • Noon Grande Ballroom North American Bridging the Gap between Workshop the Silicon and Packaging Worlds Tuesday, May 29, 2012 Presenter: Gregg Bartlett Chief Technology Officer at GLOBALFOUNDRIES Since 1994, iNEMI (the International Gregg Bartlett is Chief Technology Officer at Electronics Manufacturing Initiative) has GLOBALFOUNDRIES, where he is responsible for the company’s technology strategy, advanced node development, been developing a biennial technology technology partnerships, and alliances. Gregg joined GLOBALFOUNDRIES in 2009 after a 25-year career in technical and management positions roadmap spanning a 10-year horizon. In at Freescale Semiconductor and its predecessor, Motorola’s Semiconductor Products Sector. 2004, iNEMI expanded the initiative to Immediately prior to joining GLOBALFOUNDRIES, Gregg served as Vice President of Design Technology at Freescale, where he was responsible for design methodology and proactively include global input. This the creation of design IP and collateral for advanced solutions across high-performance year ECTC is hosting one of the several networking, automotive, wireless and analog product markets. regional meetings intended to solicit input He is a member of the board of directors of the Semiconductor Research Corporation, as well as various consortium governance committees. Gregg received his bachelor’s degree in for the 2013 iNEMI Roadmap. Open to chemical engineering from Kansas State University. all conference attendees.

5 Registration, Receptions and General Information

Registration Professional Development Course Instructors Breakfast ECTC registration will be open at the ECTC Registration Desk in PDC Instructors and Proctors are required to attend a briefing the Bayview Foyer, Marina Tower of the Sheraton San Diego Hotel breakfast. & Marina. 7:00 a.m. Tuesday – PDC Instructors and Proctor Briefing Monday, May 28, 2012 – 3:00 p.m. - 5:00 p.m. (Room Location: Executive Center 4) (PD Courses & Conference) Session Chairs and Speakers Breakfast Session Chairs and speakers are requested to attend a Tuesday, May 29, 2012 – 6:45 a.m. - 8:15 a.m. complimentary continental breakfast on the morning of their (AM PD Courses & Special Session Only) sessions/presentations. At this time, presentations will be Tuesday, May 29, 2012 – 11:00 a.m. - 1:15 p.m. transferred to the conference PC, which is loaded with Windows (PM PD Courses Only) XP and MS Office 2003. Tuesday, May 29, 2012 – 1:15 p.m. - 5:00 p.m. 7:00 a.m. Wednesday thru Friday (Room Location: Grande Ballroom B) (Conference) Speaker Prep Room Wednesday, May 30, 2012 – 6:45 a.m. - 4:00 p.m. Speakers should prepare and review their digital presentations as Thursday, May 31, 2012 – 7:30 a.m. - 4:00 p.m. follows: 7:00 a.m. – 5:00 p.m., Tuesday – Friday (Room Location: Marina 3) Friday, June 1, 2012 – 7:30 a.m. - 12:00 p.m. (It is extremely important to assure that your presentation, presentation The above schedule for Tuesday will be vigorously enforced to software and computer work flawlessly with the digital projector provided.) prevent students from being late for their courses. Door Registration Fees Companion Hospitality Room Door Registration with Proceedings on USB drive 8:00 a.m. - 4:00 p.m. Wednesday - Thursday Joint ITHERM & ECTC ...... $1,000 (Room Location: 411 & 415 / 4th floor) IEEE Member Full Registration ...... $725 8:00 a.m. - Noon Friday IEEE Member Speaker / Session Chair ...... $625 (Room Location: 411 & 415 /4th floor) IEEE Member One Day ...... $475 IEEE Member Speaker One Day ...... $350 Miscellaneous Information Non-Member Full Registration ...... $870 Hotel Concierge Non-Member Speaker / Session Chair ...... $625 The Hotel Concierge, located in the hotel lobby, can direct you to any Non-Member One Day ...... $475 show or restaurant, or give suggestions for that special night out. The Non-Member Speaker One Day ...... $350 Concierge can help to make your visit to San Diego a memorable one! Student ...... $250 Message Center Student Speaker ...... $250 Please use the hotel switchboard or the ECTC Registration Desk Exhibits Only ...... $20 located at the Bayview Foyer to leave and pickup messages. The hotel number is +1-619-291-2900. Tuesday Professional Development Courses IEEE Members and Non-Members Press Room Tuesday AM or PM Course with luncheon ...... $475 Press interviews will be scheduled on an as-requested basis. Check at the ECTC Registration Desk (Bayview Foyer) to schedule an Tuesday All-Day Courses with luncheon ...... $675 interview while onsite. You may also coordinate an interview with Tuesday Student All-Day Courses with luncheon ...... $125 conference leadership or presenting technical experts by contacting Extra Luncheon Tickets for each day ...... $50 Eric Perfecto at [email protected] or +1-845-894-4400. Extra Proceedings with Registration ...... $100

Luncheons

Tuesday, May 29, 2012 Wednesday, May 30, 2012 Thursday, May 31, 2012 Friday, June 1, 2012 Noon (Grande Ballroom A) Noon (Grande Ballroom A - C) Noon (Grande Ballroom A - C) Noon (Grande Ballroom B - C) The Electronic Components The Electronic Components The IEEE Components, Packaging The ECTC Program Chair will and Technology Conference and Technology Conference and and Manufacturing Technology sponsor a luncheon for conference will sponsor a luncheon for the Lucheon Sponsor ASE will Society will sponsor a luncheon attendees. all Professional Development sponsor a luncheon for conference for conference attendees. The Courses attendees, instructors, attendees. Best and Outstanding CPMT awards will be presented. proctors and PDC committee Papers will be awarded. The guest There will be a raffle for attendees. members. speaker will be Gregg Bartlett of GLOBALFOUNDRIES.

6 Special Session, plenary session, Panel Session and CPMT Session

Special Session ECTC Plenary Session Tuesday, May 29, 2012 • 10:00 AM – Noon Wednesday, May 30, 2012 • 7:00 - 9:00 p.m. Nautilus 1 Harbor Island I & II

Next Generation Packaging and Integration - Photonics: Expanding Markets & Emerging Technologies the Transformed Role of the Packaging Foundry Chair: Christopher Bower, Semprius Inc. Chair: Raj Pendse, STATS ChipPAC, Inc. Speakers: Ashok Krishnamoorthy, Oracle Speakers: Jeff Perkins, Yole Development Robert Darveaux, Amkor Technology Sheng Liu, Huazhong University of Science and Technology Bill Chen, Advanced Semiconductor Engineering (ASE) Alexander Fang, Aurrion Mike Ma, Siliconware Precision Industries (SPIL) Timo Aalto, VTT Technical Research Centre of Finland Steve Anderson, STATS ChipPAC, Inc. Frank Libsch, IBM Corporation Dan Tracy, SEMI

ECTC Panel Session CPMT Seminar Tuesday, May 29, 2012 • 7:30 - 9:30 p.m. Thursday, May 31, 2012 • 8:00 PM - 10:00 PM Harbor Island I & II Harbor Island I & II

Power Electronics - A Booming Market Advanced Coreless Package Substrate & Material Co-chair: Rolf Aschenbrenner, Fraunhofer IZM Technologies Co-chair: Ricky Lee, Hong Kong University of Science and Technology Co-chair: Kishio Yokouchi, Fujitsu Interconnect Technologies Ltd. Co-chair: Venky Sundaram, Georgia Institute of Technology Speakers: Speakers: Dan Kinzer, Fairchild Semiconductor Corp. Yuji Nishitani, Sony Corp. Klaus-Dieter Lang, Fraunhofer IZM Tanaka Kuniyuki, Shinko Electric Industries Co., Ltd. Lionel Cadix, Yole Development Takeshi Eriguchi, Asahi Glass Co., Ltd. Ljubisa Stevanovic, GE Global Research Masateru Koide, Fujitsu Advanced Technologies Ltd. Bernd Roemer, Infineon Technologies AG

These sessions/seminars are open to all conference attendees.

7 ECTC Student Reception Professional Development Courses Tuesday, May 29, 2012 Tuesday, May 29, 2012 5:00 - 6:00 p.m. Morning Courses 8:00 a.m. – Noon Afternoon Courses 1:15 – 5:15 p.m. Executive Center Break Area Host: Eric Perfecto – IBM Corporation Seabreeze Seabreeze 1. Lead-Free Solder Joint Reliability – Material 9. Package Failure Analysis – Failure Analysis Students, have you ever wondered how Consideration and Analytical Tools the ECTC technical committees review Course Leader: Ning-Cheng Lee – Indium Course Leaders: Rajen Dias and Deepak Goyal – and select papers? Or just what subjects, Corporation Intel Corporation content and paper organization make a Harbor Island I Harbor Island I standout ECTC paper? Then please come 2. Multi-Physics Modeling in IC Packaging and 10. Near Junction Remediation of On-Chip to the ECTC Student Reception. You’ll Microsystems Hot Spots Course Leader: Xuejun Fan – Lamar University Course Leaders: Avram Bar-Cohen – University have a chance to enjoy some good food of Maryland; Karl J. L. Geisler – General Dynamics and meet with representatives of each Advanced Information Systems technical subcommittee. Don’t miss this

Marina 2 Marina 2 chance for an inside view of technical 3. Wafer Level Chip Scale Packaging 11. Technology Advances in 3D-TSV Integration subcommittee operations. Sponsored by (WL-CSP) and Packaging of Micro-Nano-Systems the IBM Corporation. Course Leader: Luu Nguyen –Texas Instruments, Inc. Course Leader: James J.Q. Lu – Rensselaer Polytechnic Institute

Marina 4 Marina 4 General Chair’s Speakers Reception 4. 3D Integration: Alternative to Continued 12. 3D IC Packaging & Integration, and 3D Si Tuesday, May 29, 2012 Scaling Integration 6:00 - 7:00 p.m. Course Leader: Philip Garrou – Microelectronic Course Leader: John Lau – Industrial Technology Consultants of NC Research Institute Grande Ballroom A

Invited session chairs and speakers Harbor Island II Harbor Island II 5. Polymers/Nano-Composites-Electronic & 13. Polymers in Electronic Packaging are requested to attend a reception in Photonic Packaging: Recent Advances Course Leader: Jeffrey Gotro – InnoCentrix, LLC Grande Ballroom A. Course Leaders: C.P. Wong – Georgia Institute of Technology; Daniel Lu – Henkel Corporation

Harbor Island III Harbor Island III Technology Corner Reception 6. Analog and Power Electronics Packaging 14. Flip Chip Technology Wednesday, May 30, 2012 Course Leader: Yong Liu – Fairchild Semiconductor Course Leader: Eric Perfecto – IBM Corporation 5:30 - 6:30 p.m. Corporation An Exhibitor Sponsored Reception will be

held in the Pavilion, located in the white Marina 6 Marina 6 7. Fundamental Concepts of Reliability & 15. Design for Package Reliability tented area just outside the Bayview Mechanics in Electronic Packaging Course Leaders: Darvin Edwards and Yaoyu Pang – Foyer. All attendees and guests are Course Leaders: Shubhada Sahasrabudhe and Texas Instruments, Inc. Sandeep Sane – Intel Corporation invited.

Spinnaker Spinnaker 62nd ECTC Gala Reception 8. Methods for Efficient High-Frequency 16. IC Package Design Signal & Power Thursday, May 31, 2012 Modeling and Optimization of Integrity & EMC Interconnections in Electronic Packaging 6:30 p.m. Course Leader: Sam Karikalan – Broadcom Course Leaders: Ivan Ndip and Michael Toepper – Corporation Fraunhofer IZM All badged attendees and guests are invited to attend a reception outside on Refreshment Breaks – 10:00 - 10:20 a.m. & 3:00 - 3:20 p.m. the Bayview Lawn area. The rain backup Harbor Island Foyer will be Grande Ballroom B - C.

Continuing Education Units The IEEE Components, Packaging and Manufacturing Technology Society (CPMT) has been authorized to offer Continuing Education Units (CEUs) by the International Association for Continuing Education and Training (IACET) for all Professional Development Courses that will be presented at the 62nd ECTC. CEUs are recognized by employers for continuing professional development as a formal measure of participation and attendance in “non-credit” self-study courses, tutorials, symposia and workshops. IEEE CPMT CEUs can be applied towards the “IEEE CPMT Professional Development Certificate.” Complete details, including voluntary enrollment forms, will be available at the conference. All costs associated with ECTC Professional Development Courses CEUs will be underwritten by the conference, i.e. there are no additional costs for Professional Development Courses attendees to obtain CEU credit.

8 2011 ECTC Paper Awards

Best of Conference Papers – 2011 Outstanding Papers – 2011 The Electronic Components and Technology Conference is proud The winning authors for Conference Outstanding Session and to announce the “Best of Conference” papers selected from the Poster Papers receive a personalized plaque commemorating their 61st ECTC proceedings. The authors of the Best Session Paper achievement and will share a check for US $1,000. share a check for US $2,500 and the authors of the Best Poster Paper share a check for US $1,500. The winning authors also Outstanding Session Paper receive a personalized plaque commemorating their achievement. (Session 7, paper 4) Advanced Reliability Study of TSV Interposers and Best Session Paper Interconnects for the 28nm Technology FPGA (Session 32, paper 4) Bahareh Banijamali, Suresh Ramalingam, Kumar Nagarajan, Characterization and Failure Analysis of TSV and Raghu Chaware – Xilinx, Inc. Interconnects: From Non-Destructive Defect Localization to Material Analysis with Nanometer Outstanding Poster Paper Resolution (Session 38, paper 14) Michael Krause, Frank Altmann, Christian Schmidt, and Maximum Channel Density in Multimode Optical Matthias Petzold – Fraunhofer IWM; D. Malta and D. Temple – Waveguides for Parallel Interconnections RTI International Takaaki Ishigure, Ryota Ishiguro, Hisashi Uno, and Hsiang-Han Hsu – Keio University Best Poster Paper (Session 39, paper 9) Conformal Atomic Layer Deposition (ALD) of Intel Best Student Paper – 2011 Alumina on High Surface-Area Porous Copper The winning student receives a personalized plaque and a check for Electrodes to Achieve Ultra-High Capacitance $2,500. The following paper was selected based on the Intel Best Density on Silicon Interposers Student Paper competition conducted at the 61st ECTC: Hongtao Kanika Sethi, Himani Sharma, P. Markondeya Raj, (Session 16, Paper 3) Venky Sundaram, and Rao Tummala – Georgia Institute of Aging Aware Constitutive Models for SnAgCu Solder Alloys Technology S. Chavali, Y. Singh, P. Kumar, G. Subbarayan, I. Dutta and D. R. Edwards – Purdue University

Committee Meetings • Associated Committee Members Only

Tuesday, May 29, 2012 Wednesday, May 30, 2012 Thursday, May 31, 2012 Friday, June 1, 2012 9:00 a.m. – 5:00 p.m. 7:00 a.m. – 8:00 a.m. 6:45 a.m. – 7:45 a.m. 7:00 a.m. – 8:00 a.m. iNEMI Meeting CPMT Materials TC CPMT Transactions Editors / AEs CPMT RF & Wireless TC Nautilus 3 Meeting Room 514, 5th floor Marina 2 Marina 2

9:00 a.m. – 5:30 p.m. 7:00 a.m. – 8:00 a.m. 7:00 a.m. – 8:00 a. m. 7:00 a.m. – 8:00 a.m. ITRS Assemblies & Packaging CPMT High-Density Board Packaging CPMT Education TC CPMT Nano Packaging TC Technology Committee TC Meeting Room 514, 5th floor Meeting Room 514, 5th floor Executive Center 1 Meeting Room 511, 5th floor 5:30 p.m. – 6:30 p.m. 1:30 p.m. – 4:30 p.m. 5:00 p.m. – 7:00 p.m. 4:30 p.m. – 5:30 p.m. ECTC 2013 Program Committee ECTC Executive Committee CPMT Region 8 Advisory Committee CPMT Technical Committee Chairs Meeting Executive Center 3B Meeting Room 514, 5th floor Meeting Room 518, 5th floor Harbor Island III

9:00 p.m. – 10:30 p.m. 6:00 p.m. – 7:00 p.m. 8:00 p.m. ECTC OPTO Committee Program Subcommittee Chairs & 62nd ECTC Governing/Executive Marina 6 Assistant Chairs Reception Committee Reception General Chair’s Suite General Chair’s Suite (by invitation only) (by invitation only)

9 Program Sessions: Wednesday, May 30, 8:00 a.m. - 11:40 a.m.

Session 1: 3D Interconnect: Session 2: Next Generation Packaging Session 3: MEMS Integration and Bonding and Assembly Reliability Processing

Committee: Committee: Committees: Emerging Technologies / Interconnections Applied Reliability Electronic Components & RF

Harbor Island II Harbor Island I Harbor Island III

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Changqing Liu – Loughborough University Sridhar Canumalla – Microsoft Corporation John Cunningham – Oracle James Lu – Rensselaer Polytechnic Institute Jeffrey Suhling – Auburn University P. Markondeya Raj – Georgia Institute of Technology

1. 8:00 a.m. – Structural Design, Process, and 1. 8:00 a.m. – Board Level Solder Joint Assembly 1. 8:00 a.m. – Electronic Packaging of Sensors Reliability of a Wafer-Level 3D Integration and Reliability for Ultra Thin BGA Packages for Lower Limb Prosthetics Scheme with Cu TSVs based on Micro-Bump/ Mohammad M. Hossain, Srinivasa R. Aravamudhan, J. Kelly Lee and Nancy Stoffel – College of Nanoscale Adhesive Hybrid Wafer Bonding Marilyn Nowakowski, Xiaoqing Ma, Satyajit S. Walwadkar, Science and Engineering; Kevin Fite – Clarkson C.T. Ko, Z.C. Hsiao, P.S. Chen, J.H. Huang, H.C. Fu, Y.J. Vijay Kulkarni, and Sriram Muthukumar – Intel University Huang, C.W. Chiang, C.K. Lee, H.H. Chang, W.L. Tsai, Corporation and Y.H. Chen – ITRI; Y.J. Chang – National Chiao Tung University

2. 8:25 a.m. – Evaluation of 3D Interconnect 2. 8:25 a.m. – Safe Working Process Strain Limits 2. 8:25 a.m. – Cost Effective Thin Film Packaging Routing and Stacking Strategy to Optimize for Large Area Array Packages: Observations for Wide Area MEMS High Speed Signal Transmission for Memory from Spherical Bend Testing J.L. Pornin, D. Saint-Patrice, C. Gillot, E. Lagoutte, M. Pellat, on Logic John McMahon, Brian Gray, and Brian P. Standing – and S. Fanget – CEA-LETI J. Roullard, S. Capraro, T. Lacrevaz, C. Bermond, G. Celestica Houzet, and B. Flechet – Université de Savoie; A. Farcy – STMicroelectronics; J. Charbonnier, C. Fuchs, C. Ferrandon, and P. Leduc – CEA-LETI

3. 8:50 a.m. – Study of Low Temperature and 3. 8:50 a.m. – Board Level Drop Test Modeling 3. 8:50 a.m. – Low Temperature Sealing Process High Heat-Resistant Fluxless Bonding via Masazumi Amagai and Jang Seungmin – Texas for Vacuum MEMS Encapsulation Nanoscale Thin Film Control toward Wafer- Instruments, Inc. D. Saint-Patrice, J.L. Pornin, B. Savornin, G. Rodriguez, S. Level Multiple Chip Stacking for 3D LSI Danthon, and S. Fanget – CEA-LETI Eiji Morinaga, Yuichi Oka, Hiroaki Nishimori, Haruhiko Miyagawa, Ryohei Satoh, Yoshiharu Iwata, and Ryota Kanezaki – Osaka University

Refreshment Break: 9:15 a.m. – 10:00 a.m. (Pavilion)

4. 10:00 a.m. – High Density Metal-Metal 4. 10:00 a.m. – Methods for Reliability 4. 10:00 a.m. – On-Chip THz 3D Antennas Interconnect Bonding with Pre-Applied Assessment of MEMS Devices – Case Studies Paolo Nenzi, Francesco Tripaldi, Volha Varlamava, Fabrizio Fluxing Underfill of a MEMS Microphone and a 3-Axis MEMS Palma, and Marco Balucani – University of Rome Christopher Gregory, Matthew Lueck, Alan Huffman, Gyroscope John M. Lannon, Jr., and Dorota S. Temple – RTI J. Hokka, J. Raami, H. Hyvönen, M. Broas, J. Makkonen, J. Li, International T. Mattila, and M. Paulasto-Kröckel – Aalto University

5. 10:25 a.m. – Characterization of a Novel 5. 10:25 a.m. – Stress Evolution in an 5. 10:25 a.m. – A CMOS Embedded RF-MEMS Fluxless Surface Preparation Process for Die Encapsulated MEMS Package Due to Tunable Capacitor for Multi-Band/Multi- Interconnect Bonding Viscoelasticity of Packaging Materials Mode Smartphones Eric F. Schulte, Keith A. Cooper, and Matthew Phillips – Seungbae Park, Dapeng Liu, Yeonsung Kim, and Hohyung Y. Kurui, H. Yamazaki, Y. Shimooka, T. Saito, E. Ogawa, T. SET North America; Subhash L. Shinde – Sandia National Lee – SUNY Binghamton; Sam Zhang – Analog Devices, Ogawa, T. Ikehashi, Y. Sugizaki, and H. Shibata – Toshiba Laboratory Inc. Corporation

6. 10:50 a.m. – Development of Anhydride- 6. 10:50 a.m. – Reliability Analyses on a TSV 6. 10:50 a.m. – High Power Laminate MEMS RF Based NCFs for Cu/Sn-Ag Eutectic Bonding Structure for CMOS Image Sensor Switch and Process Optimization for Fine Pitch TSV Ben-Je Lwo and Chung-Yen Ni – National Defense Sung Jun Kim, Yang Zhang, Minfeng Wang, Mark Bachman, Chip Stacking University and G.P. Li – University of California, Irvine Ji-Won Shin, Yong-Won Choi, Young Soon Kim, and Kyung-Wook Paik – KAIST; Un Byung Kang, Young Kun Jee, and Ji Hwan Hwang – Samsung Electronics Company, Ltd.

7. 11:15 a.m. – “Dual-Purpose” Remateable 7. 11:15 a.m. – Dynamic Bending Test Analysis 7. 11:15 a.m. – A Novel Electrostatic Radio Conductive Ball-in-Pit Interconnects for Chip of Inkjet-Printed Conductors on Flexible Frequency Micro Electromechanical Systems Powering and Passive Alignment in Proximity Substrates (RF MEMS) with Prognostics Function Communication Enabled Multi-Chip Eerik Halonen, Aki Halme, Tapio Karinsalo, Pekka Iso- Yunhan Huang, Michael Osterman, and Michael Pecht – Packages Ketola, Matti Mäntysalo, and Riku Mäkinen – Tampere University of Maryland Hiren D. Thacker, Ivan Shubin, Ying Luo, Kannan Raj, University of Technology James G. Mitchell, Ashok V. Krishnamoorthy, and John E. Cunningham – Oracle 10 Program Sessions: Wednesday, May 30, 8:00 a.m. - 11:40 a.m.

Session 4: Signal and Power Analysis Session 5: LEDs and Emerging Session 6: Novel Interconnections Optoelectronics Integration

Committee: Committee: Committee: Modeling & Simulation Optoelectronics Interconnections

Nautilus 1 Nautilus 3 Nautilus 5

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Henning Braunisch – Intel Corporation Alex Rosiewicz – EM4 James E. Morris – Portland State University Michael Lamson – Consultant Hiren Thacker – Oracle Labs, Oracle Tom Gregorich – MediaTek

1. 8:00 a.m. – The Design of Higher-Order 1. 8:00 a.m. – High Power LED Subassemblies 1. 8:00 a.m. – Metal-Coated Mono-Sized Reference Voltage Generation Circuits for for Automotive Front Light Application Polymer Core Particles for Fine Pitch Flip- Single-Ended Memory Interfaces G. Elger, B. Spinger, R. Peters, N. Benter, H. Willwohl, Chip Interconnects Wendem T. Beyene – Rambus, Inc. S. Honma, U. Bohnenkamp, A. Stolarski, M. Sikkens, A. Mark W. Sugden, Changqing Liu, David Hutt, and David Emmerich, and H. Gijsbers – Philips Technology GmbH; Whalley – Loughborough University; Helge Kristiansen N. Lesch – Philips Lumileds – Conpart A.S.

2. 8:25 a.m. – Efficient and Accurate Modeling 2. 8:25 a.m. – Application Specific LED 2. 8:25 a.m. – THz Ribbon Waveguides using of Effective Medium for Interconnects in Packaging for Automotive Forward-Lighting Polymer-Ceramic Nanocomposites Lossy Shielded Layered Medium using Fast Application and Design of Whole Lamp Xianbo Yang and Premjeet Chahal – Michigan State Convergent Series Module University Sidharath Jain and Jiming Song – Iowa State University; Fei Chen, Zhangming Mao, Xing Fu, Cao Li, Mengxiong Telesphor Kamgaing and Yidnekachew Mekonnen – Intel Zhao, and Sheng Liu – Huazhong University of Science Corporation and Technology; Kai Wang – Guangdong Real Faith Optoelectronics, Inc.

3. 8:50 a.m. – System-Level SoC Near-Field 3. 8:50 a.m. – Index Matched Fluidic Packaging 3. 8:50 a.m. – Thermocompression Bonding of (NF) Emissions: Simulation to Measurement of High Power UV LED Clusters on Aluminum Ag-MWCNTs Nanocomposite Films as an Correlation Substrates for Improved Optical Output Alternative Die-Attach Solution for High- Rajen Murugan, Souvik Mukherjee, Minhong Mi, Lionel Power Temperature Packaging of SiC Devices Pauc, and Claudio Girardi – Texas Instruments, Inc.; Marc Schneider, Benjamin Leyrer, Christian Herbold, Vanessa Smet, Mamun Jamal, Alan Mathewson, and Kafil Dipanjan Gope, Daniel de Araujo, Swagato Chakraborty, Stefan Maikowske, and Jürgen Brandner – Karlsruhe M. Razeeb – Tyndall National Institute and Vikram Jandhyala – Nimbic Inc. Institute of Technology

Refreshment Break: 9:15 a.m. – 10:00 a.m. (Pavilion)

4. 10:00 a.m. – Statistical Analysis of Inter- 4. 10:00 a.m. – Advanced Thin Glass Based 4. 10:00 a.m. – Novel Interconnect Symbol-Interference and Crosstalk for Photonic PCB Integration Methodologies for Ultra-Thin Chips on Foils Coding Buses Henning Schröder and Lars Brusberg – Fraunhofer IZM; A. Sridhar, H. Fledderus, R.H.L. Kusters, and J. van den Yu Chang, Dan Oh, and Ralf Schmitt – Rambus, Inc. Norbert Arndt-Staufenbiel and Klaus-Dieter Lang – TU Brand – TNO/Holst Centre; M. Cauwe – IMEC Berlin; Karim Richlowski and Christian Ranzinger – Contag GmbH

5. 10:25 a.m. – Simulation Challenges in 5. 10:25 a.m. – A Laminate Cantilever 5. 10:25 a.m. – Gold Passivated Mechanically Designing High Speed Serial Links Waveguide Optical Switch Flexible Interconnects (MFIs) with High Arun Reddy Chada – Missouri University of Science and Jonas Tsai, Arthur Yang Zhang, G.P. Li, and Mark Bachman Elastic Deformation Technology; Bhyrav Mutnury, Douglas Wallace, Douglas – University of California, Irvine Chaoqi Zhang, Hyung Suk Yang, and Muhannad S. Bakir – Winterberg, and Minchuan Wang – Dell Inc.; Antonio Georgia Institute of Technology Ciccomancini Scogna – CST of America, Inc.

6. 10:50 a.m. – A New Approach to Deriving 6. 10:50 a.m. – Pick and Align–High Precision 6. 10:50 a.m. – Microsolder/Adhesive Hybrid Packaging System Statistical Eye Diagram Active Alignment of Optical Components Joints for High-Density, High-Power, Based on Parallel Non-Linear Transient Michael Leers, Matthias Winzen, Erik Liermann, Heinrich High-Reliability, and Reworkable Module Simulations using Multiple Short Signal Bit Faidel, Thomas Westphalen, Joern Miesner, Joerg Interconnection in Mobile Phones Patterns Luttmann, and Dieter Hoffmann – Fraunhofer Institute Kiwon Lee and Kyung-Wook Paik – KAIST; Ilkka J. Zhaoqing Chen, Wiren Dale Becker, and George Katopis for Laser Technology ILT Saarinen and Lasse Pykari – Nokia Corporation – IBM Corporation

7. 11:15 a.m. – Optimizing the Timing Center 7. 11:15 a.m. – Fabrication of Low Cost Wafer- 7. 11:15 a.m. – Hybrid Au-Underfill Resin for High-Speed Parallel Buses Level Micro-Lens Arrays with Spacers using Bonding with Lock-and-Key Structure Dan Oh, Arun Vaidyanath, Chris Madden, and Yohan Glass Molds by Combining a Chemical Foaming Masatsugu Nimura, Jun Mizuno, and Shuichi Shoji Frans – Rambus, Inc.; Woopoung Kim – Qualcomm, Inc. Process (CFP) and a Hot Forming Process (HFP) – Waseda University; Akitsu Shigetou – National Shunjin Qin, Jintang Shang, Tingting Wang, Wenlin Kuai, Institute for Materials Science; Katsuyuki Sakuma – IBM and Wenlong Wei – Southeast University; Li Zhang and Corporation; Hiroshi Ogino and Tomoyuki Enomoto – Chiming Lai – Jiangyin Changdian Advanced Packaging Nissan Chemical Industries Co. Ltd.; Siyuan Lv – Nanjing Foreign Language School 11 Program Sessions: Wednesday, May 30, 1:30 p.m. - 5:10 p.m.

Session 7: Interposer Technology Session 8: 3D Reliability Session 9: Sensors and MEMS

Committee: Committees: Applied Reliability / Committee: Advanced Packaging Interconnections Advanced Packaging

Harbor Island II Harbor Island I Harbor Island III

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Christopher Bower – Semprius, Inc. Vikas Gupta – Texas Instruments, Inc. Ricky Lee – Hong Kong Univ. of Science & Technology John Knickerbocker – IBM Corporation Wei-Chung Lo – ITRI James Zhang – Micron Technology, Inc.

1. 1:30 p.m. – Integrating Through-Silicon Vias 1. 1:30 p.m. – High-Frequency Measurements of 1. 1:30 p.m. – Assembly and Packaging with Solder Free, Compliant Interconnects for TSV Failures Technologies for High Temperature SiC- Novel, Large Area Interposers Joohee Kim, Daniel Jung, Jonghyun Cho, Jun So Pak, and Sensors Ivan Shubin, Alex Chow, Hiren D. Thacker, Kannan Raj, Joungho Kim – KAIST; Jong Min Yook and Jun Chul Kim Roderich Zeiser, Phillipp Wagner, and Jürgen Wilde – Ashok V. Krishnamoorthy, James G. Mitchell, and John – Korea Electronics Technology Institute University of Freiburg E. Cunningham – Oracle; Eugene M. Chow and Dirk DeBruyker – Palo Alto Research Center (PARC); Koji Fujimoto – DNP America, LLC

2. 1:55 p.m. – Process Integration and Testing 2. 1:55 p.m. – Electrical Characterization 2. 1:55 p.m. – Drop Impact Reliability of MEMS of TSV Si Interposers for 3D Integration Method to Study Barrier Integrity in 3D Inertial Sensors with Membrane Suspensions Applications Through-Silicon Vias for Mobile Phones J. Lannon Jr., A. Hilton, A. Huffman, M. Lueck, E. Vick, S. Y.L. Li, D. Velenis, T. Kauerauf, M. Stucchi, Y. Civale, A. Jong Woon Kim, Heung Woo Park, Min Kyu Choi, Goodwin, G. Cunningham, D. Malta, C. Gregory, and D. Redolfi, and K. Croes – IMEC Won Kyu Jeung, and Jung Won Lee – Samsung Electro- Temple – RTI International Mechanics Company, Limited

3. 2:20 p.m. – High Density and Low-Cost 3. 2:20 p.m. – Outstanding and Innovative 3. 2:20 p.m. – Chip on Board Development for Silicon Interposer using Thin-film and Organic Reliability Study of 3D TSV Interposer and a Novel MEMS Accelerometer for Seismic Lamination Processes Fine Pitch Solder Micro-Bumps Imaging Jong-Min Yook, Jun Chul Kim, Se-Hoon Park, Jong-In Bahareh Banijamali, Suresh Ramalingam, Henley Liu, and Zhuqing Zhang, Jennifer Wu, Sheldon Bernard, and Ryu, and Jong Chul Park – Korea Electronics Technology Myongseob Kim – Xilinx, Inc. Robert G. Walmsley – Hewlett Packard Company Institute

Refreshment Break: 2:45 p.m. - 3:30 p.m. (Pavilion)

4. 3:30 p.m. – Assembly and Reliability 4. 3:30 p.m. – Chip Package Interaction in 4. 3:30 p.m. – Failsafe Wafer-Level Packaging of Challenges in 3D Integration of 28nm FPGA Micro Bump and TSV Structure a Piezoelectric MEMS Actuator Die on a Large High Density 65nm Passive Ha-Young You, Yuchul Hwang, Jun-Woo Pyun, Young- M.A. Matin, K. Ozaki, D. Akai, K. Sawada, and M. Ishida – Interposer Gyun Ryu, and Hyoung-Sub Kim – Samsung Electronics Toyohashi University of Technology Raghunandan Chaware, Kumar Nagarajan, and Suresh Co., Ltd. Ramalingam – Xilinx, Inc.

5. 3:55 p.m. – TSV Technology for 2.5D IC 5. 3:55 p.m. – Effect of Intermetallic Formation 5. 3:55 p.m. – Hermetic Wafer-Level Packaging Solution on Electromigration Reliability of TSV- for RF MEMs: Effects on Resonator Meng-Jen Wang, Chang-Ying Hung, Chin-Li Kao, Pao-Nan Microbump Joints in 3D Interconnect Performance Lee, Chi-Han Chen, Chih-Pin Hung, and Ho-Ming Tong – Yiwei Wang, Tengfei Jiang, Jay Im, and Paul S. Ho – M. David Henry, K. Douglas Greth, Janet Nguyen, Advanced Semiconductor Engineering, Inc. University of Texas, Austin; Seung-Hyun Chae, Rajiv Christopher D. Nordquist, Randy Shul, Mike Wiwi, Dunne, Yoshimi Takahashi, Kazuaki Mawatari, Philipp Thomas A. Plut, and Roy H. Olsson III – Sandia National Steinmann, and Tom Bonifield – Texas Instruments, Inc. Laboratories

6. 4:20 p.m. – Development of Substrates 6. 4:20 p.m. – Electromigration Behavior of 3D- 6. 4:20 p.m. – 3D MEMS High Vacuum Wafer for Through Glass Vias (TGV) For 3DS-IC IC TSV Interconnects Level Packaging Integration Thomas Frank and Lorena Anghel – STMicroelectronics; S. Nicolas, S. Caplet, F. Greco, M. Audoin, X. Baillin, and S. Aric Shorey, Scott Pollard, Alex Streltsov, Garrett Piech, Stephane Moreau, Lucile Arnaud, Patrick Leduc, and Fanget – CEA-LETI and Robert Wagner – Corning, Inc. Aurelie Thuaire – CEA-LETI; Cedrick Chappaz – STMicroelectronics

7. 4:45 p.m. – Low-Cost and Low-Loss 3D 7. 4:45 p.m. – In-Depth Raman Spectroscopy 7. 4:45 p.m. – Investigation of a Unified LTCC- Silicon Interposer for High Bandwidth Logic- Analysis of Various Parameters Affecting the Based Micromachining and Packaging to-Memory Interconnections without TSV in Mechanical Stress near the Surface and Bulk Platform for High Density/Multifunctional the Logic IC of Cu-TSVs Microsystem Integration Venky Sundaram, Qiao Chen, Gokul Kumar, Fuhan Liu, Ingrid De Wolf, Veerle Simons, Vladimir Cherman, Riet Min Miao, Yufeng Jin, Hua Gan, Jing Zhang, Yunsong Qiu, and Rao Tummala – Georgia Institute of Technology; Yuya Labie, Bart Vandevelde, and Eric Beyne – IMEC Yang Zhang, Yangfei Zhang, Rui Cao, Zhensong Li, and Suzuki – Zeon Corporation Chengchen Gao – Peking University; Zhengyi Wang and Fangqing Mu – 43rd Institute of China Electronics Technology Group Corporation 12 Program Sessions: Wednesday, May 30, 1:30 p.m. - 5:10 p.m.

Session 10: Conductive and Session 11: Advanced Flip Chip and Session 12: Solder and Material Non-Conductive Adhesives Underfill Assembly Characterization

Committee: Committee: Committee: Materials & Processing Assembly & Manufacturing Technology Applied Reliability

Nautilus 1 Nautilus 3 Nautilus 5

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Stephanie Potisek – Dow Chemical Wei Koh – Powertech Technology, Inc. Lakshmi N. Ramanathan – Microsoft Corporation Lejun Wang – Medtronic, Inc. Tom Poulin – Aerie Engineering Dongming He – Qualcomm, Inc.

1. 1:30 p.m. – NCF for Pre-Applied Process in 1. 1:30 p.m. – Differential Heating/Cooling Chip 1. 1:30 p.m. – Investigation of Phosphorous Higher Density Electronic Package Including Joining Method to Prevent Chip Package Impact on Lead-Free BGA Solder Joint and 3D-Package Interaction Issue in Large Die with Ultra Failure Mechanism Kazutaka Honda, Akira Nagai, Makoto Satou, Shinsuke Low-k Technology Ming Sun, Muh-Ren Lin, Tim Chaudhry, and Robert Lutze Hagiwara, Satoru Tuchida, and Hidenori Abe – Hitachi Katsuyuki Sakuma, Kurt Smith, Krishna Tunga, Eric – Broadcom Corporation Chemical Co., Ltd. Perfecto, Thomas Wassick, Frank Pompeo, and Jae- Woong Nah – IBM Corporation

2. 1:55 p.m. – Non-Conductive Film and 2. 1:55 p.m. – Advanced Flip-Chip Package 2. 1:55 p.m. – Aging Impact on the Accelerated Compression Molding Technology for Self- Solution for 28nm Si Node and Beyond Thermal Cycling Performance of Lead-Free Assembly-Based 3D Integration C.S. Liu, C.S. Chen, C.H. Lee, H.Y. Tsai, H.P. Pu, M.D. BGA Solder Joints in Various Stress Conditions T. Fukushima, Y. Ohara, J. Bea, M. Murugesan, K.W. Lee, T. Cheng, T.H. Kuo, H.W. Chen, C.Y. Wu, M.J. Lii, and Tae-Kyu Lee and Hongtao Ma – Cisco Systems, Inc. Tanaka, and M. Koyanagi – Tohoku University Doug C.H. Yu – Taiwan Semiconductor Manufacturing Company, Ltd.

3. 2:20 p.m. – Effect of NCF Design for the 3. 2:20 p.m. – Development of Large Die Fine 3. 2:20 p.m. – High Strain Rate Behaviour Assembly of Flip Chip and Reliability Pitch Flip Chip BGA using TCNCP Technology of Lead-Free Solders Depending on Alloy Satomi Kawamoto, Masaki Yoshida, Shin Teraki, and Yanggyoo Jung, Minjae Lee, Sunwoo Park, Dongsu Composition and Thermal Aging Hidenori Iida – NAMICS Corporation Ryu, Youshin Jung, Chanha Hwang, Choonheung Lee, K. Meier and K.J. Wolter – TU Dresden; F. Kraemer – Sungsoon Park, and Miguel Jimarez – Amkor Technology; Saarland University Myung-June Lee – Altera Corporation

Refreshment Break: 2:45 p.m. - 3:30 p.m. (Pavilion)

4. 3:30 p.m. – Highly Conductive, Flexible, Bio- 4. 3:30 p.m. – Low Temperature Touch Down 4. 3:30 p.m. – Effect of Microstructure Evolution Compatible Poly-Urethane based Isotropic and Suppressing Filler Trapping Bonding on Pb-Free Solder Joint Reliability in Conductive Adhesives for Flexible Electronics Process with Wafer Level Pre-Applied Thermomechanical Fatigue Zhuo Li, Rongwei Zhang, Yan Liu, and Taoran Le – Underfilling Film Adhesive Liang Yin and Michael Meilunas – Universal Instruments Georgia Institute of Technology; C.P. Wong – Georgia Toshihisa Nonaka, Shoichi Niizeki, Noboru Asahi, and Corporation; Babak Arfaei, Luke Wentlent, and Peter Institute of Technology, Chinese University of Hong Koichi Fujimaru – Toray Industries, Inc. Borgesen – SUNY, Binghamton Kong

5. 3:55 p.m. – Low Temperature Curable 5. 3:55 p.m. – Mixed Pitch BGA (mpBGA) 5. 3:55 p.m. – Sensitivity of Grain Structure and Anisotropic Conductive Films (ACFs) with Packaging Development for High Bandwidth- Fatigue Reliability of Pb-Free Solder Joint on Photo-Active Curing Agent (PA-ACFs) High Speed Networking Devices the Position in PBGA Packaging Assembly Il Kim and Kyung-Wook Paik – KAIST John Savic, Mohan Nagar, Weidong Xie, Mudasir Ahmad, Huili Xu, Woong Ho Bang, and Choong-Un Kim – David Senk, and Anurag Bansal – Cisco Systems, Inc.; University of Texas, Arlington; Tae-Kyu Lee – Cisco Nokibul Islam, Gun Oh Park, Raj Pendse, HangChul Systems, Inc. Choi, and SangHo Lee – STATS ChipPAC, Ltd.

6. 4:20 p.m. – Novel Interconnect Materials 6. 4:20 p.m. – Copper Pillar Bumped 6. 4:20 p.m. – Creep Behavior of Joint-Scale for High Reliability Power Converters with Sapphire Flip Chip on Leadframe Package Sn1.0Ag0.5Cu Solder Shear Samples Operation Temperatures above 150°C Development Cillian Burke, Jeff Punch, and Maurice Collins – Susanne Duch, Thomas Krebs, Yvonne Loewer, Wolfgang John Yang – Peregrine Semiconductor University of Limerick Schmitt, and Muriel Thomas – Heraeus Materials Technology GmbH & Co.

7. 4:45 p.m. – Usability of ECA Materials in 7. 4:45 p.m. – Ultrasonic-Assisted Thermo- 7. 4:45 p.m. – Improved Predictions of Lead Free High Temperature Sensor Applications Compression Bonding Method for High- Solder Joint Reliability that Include Aging Sanna Lahokallio and Laura Frisk – Tampere University Performance Solder Anisotropic Conductive Effects of Technology Film (ACF) Joints Mohammad Motalab, Zijie Cai, Jeffrey C. Suhling, Jiawei Yoo-Sun Kim, Kiwon Lee, and Kyung-Wook Paik – Zhang, John L. Evans, Michael J. Bozack, and Pradeep Lall KAIST – Auburn University

13 Program Sessions: Thursday, May 31, 8:00 a.m. - 11:40 a.m.

Session 13: 3D TSV Manufacturing Session 14: Flip Chip Interconnect and Session 15: Innovative Processes and Electromigration Techniques

Committee: Committee: Committee: Assembly & Manufacturing Technology Interconnections Materials & Processing

Harbor Island II Harbor Island I Harbor Island III

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Andy Tseng – Advanced Semiconductor Engineering, Inc. Lou Nicholls – Amkor Technology, Inc. Bing Dang – IBM Corporation Hirofumi Nakajima – Renesas Electronics Co. Bernd Ebersberger – Intel Mobile Communications Hongtao Ma – Bridgelux, Inc.

1. 8:00 a.m. – Challenges and Improvements for 1. 8:00 a.m. – Novel Design and Integration 1. 8:00 a.m. – Metrology and Inspection 3D-IC Integration using Ultra Thin (25µm) Enhancements in the Final Polymeric Requirements for 3D Stacking of IC’s Devices Passivation for Improved Mechanical Sandip Halder, Andy Miller, Mireille Maenhoudt, Gerald A. La Manna, T. Buisson, M. Detalle, K.J. Rebibis, D. Velenis, Performance and C4 Electromigration in Pb- Beyer, Bart Swinnen, and Eric Beyne – IMEC; David W. Zhang, and E. Beyne – IMEC Free C4 Products Grant, David Marx, Russ Dudley, and Maurice Ford – E. Misra, T. Daubenspeck, T. Wassick, K. Tunga, G. Tamar Technology Lafontant, D. Questad, G. Osborne, and T. Sullivan – IBM Corporation; G.J. Scott – Amkor Technology

2. 8:25 a.m. – Development of Cost-Effective 2. 8:25 a.m. – High Current-Carrying and 2. 8:25 a.m. – Characterization of the Annealing Wafer Level Process for 3D-Integration with Highly-Reliable 30µm Diameter Cu-Cu Area- Behavior for Copper-Filled TSVs Bumpless TSV Interconnects Array Interconnections without Solder P. Saettler and K.J. Wolter – TU Dresden; M. Boettcher K. Fujimoto, N. Maeda, H. Kitada, Y.S. Kim, S. Kodama, and Sadia A. Khan, Nitesh Kumbhat, Pulugurtha Raj, Venky – FhG ASSID T. Ohba – University of Tokyo; T. Nakamura – Fujitsu Sundaram, and Rao Tummala – Georgia Institute Laboratories Ltd.; K. Suzuki – Dai Nippon Printing Co., of Technology; Abhishek Goyal – Indian Institute of Ltd. Technology Roorkee; Kodai Okoshi – Namics Corporation; Georg Meyer-Berg – Infineon Technologies AG

3. 8:50 a.m. – High Aspect Ratio TSVs Fabricated 3. 8:50 a.m. – Reliability Study of Lead-Free 3. 8:50 a.m. – Locally Induced Stress in Stacked by Magnetic Self-Assembly of Gold-Coated Flip-Chips with Solder Bumps Down to 30 Ultrathin Si Wafers: XPS and Micro-Raman Nickel Wires µm Diameter Study A.C. Fischer, S.J. Bleiker, N. Somjit, N. Roxhed, T. Stefan Härter, Andreas Reinhardt, and Jörg Franke – M. Murugesan, T. Fukushima, and M. Koyanagi – NICHe; Haraldsson, G. Stemme, and F. Niklaus – KTH Royal University of Erlangen-Nuremberg; Rainer Dohle and H. Nohira – Tokyo City University; H. Kobayashi – ASET; Institute of Technology Jörg Goßler – Micro Systems Engineering GmbH T. Tanaka – Tohoku University

Refreshment Break: 9:15 a.m. – 10:00 a.m. (Pavilion)

4. 10:00 a.m. – Assembly Process and Reliability 4. 10:00 a.m. – Effect of Joule Heating on 4. 10:00 a.m. – Process Development for High- Assessment of TSV/RDL/IPD Interposer with Electromigration Reliability of Pb-Free Current Electrochemical Deposition of Multi-Chip-Stacking for 3D IC Integration Interconnect Copper Pillar Bumps SiP Minhua Lu, Steven L. Wright, Gerard McVicker, and Sri M. Wei Koh – Pacrim Technology; Barry Lin – Powetech C.J. Zhan, P.J. Tzeng, J.H. Lau, M.J. Dai, H.C. Chien, C.K. Sri-Jayantha – IBM Corporation Technology Inc. Lee, S.T. Wu, K.S. Kao, S.Y. Huang, C.W. Fan, S.C. Chung, and Y.W. Huang – ITRI

5. 10:25 a.m. – A CMOS Compatible Chip-to- 5. 10:25 a.m. – Mechanically Compliant Lead- 5. 10:25 a.m. – Wafer Bumping, Assembly, and Chip 3D Integration Platform Free Solder Metallurgy: The Key Element in Reliability Assessment of µbumps with 5µm Yuksel Temiz, Michael Zervas, Carlotta Guiducci, and Enabling Extreme Low-K Large-Die Flip Chip Pads on 10µm Pitch for 3D IC Integration Yusuf Leblebici – École Polytechnique Fédérale de Devices C.K. Lee, C.J. Zhan, J.H. Lau, Y.J. Huang, H.C. Fu, J.H. Lausanne Mengzhi Pang, Matt Kaufmann, Henry Sze, Reza Sharifi, Huang, Z.C. Hsiao, S.W. Chen, S.Y. Huang, C.W. Fan, Y.M. Keith Tan, Chong Wei Neo, Ram Ramakrishna, Sam Lin, and K.S. Kao – ITRI Karikalan, and Reza Khan – Broadcom Corporation

6. 10:50 a.m. – A New Carrier Structure for TSV 6. 10:50 a.m. – 40µm Ag-AgIn Flip-Chip 6. 10:50 a.m. – In-Situ Strain Measurement with Thin Wafer Handling Interconnect Process at 180ºC Metallic Thin Film Sensors Ming-Chih Chen, Frank Hsieh, and Dyi-Chung Hu – Wen P. Lin, Chu-Hsuan Sha, and Chin C. Lee – University Christine Taylor and Suresh K. Sitaraman – Georgia Unimicron Technology, Inc. of California, Irvine Institute of Technology

7. 11:15 a.m. – Electrical Testing of Blind 7. 11:15 a.m. – Electromigration Behavior in 7. 11:15 a.m. – Environmentally Friendly Dry Through-Silicon Via (TSV) for 3D IC Low Temperature Flip Chip Bonding De-Smear of Fine-Via by Ultra High Density Integration Kei Murayama and Mitsutoshi Higashi – Shinko Electric Nonequilibrium Atmospheric Pressure Plasma Jui-Feng Hung, John H. Lau, Peng-Shu Chen, Shih-Hsien Industries Co., Ltd.; Taiji Sakai and Nobuaki Imaizumi – Yoshiyuki Iwata and Hajime Sakamoto – Ibiden Co., Ltd.; Wu, Shinn-Juh Lai, Ming-Lin Li, Shyh-Shyuan Sheu, Pei-Jer Fujitsu Laboratories Ltd. Keigo Takeda and Masaru Hori – Nagoya University Tzeng, Zhe-Hui Lin, Tzu-Kun Ku, Wei-Chung Lo, and Ming-Jer Kao – ITRI

14 Program Sessions: Thursday, May 31, 8:00 a.m. - 11:40 a.m.

Session 16: 3D Electrical Analysis Session 17: Lead Free Solders Session 18: Innovative Test Methods

Committee: Committee: Committee: Modeling & Simulation Materials & Processing Applied Reliability

Nautilus 1 Nautilus 3 Nautilus 5

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Wendem Beyene – Rambus Mikel Miller – Draper Laboratory Darvin R. Edwards – Texas Instruments, Inc. Daniel de Araujo – Nimbic, Inc. Dong Wook Kim – Qualcomm, Inc. Tim Chaudhry – Broadcom Corporation

1. 8:00 a.m. – Fast Electrical-Thermal Co- 1. 8:00 a.m. – Electromigration Performance of 1. 8:00 a.m. – A New Physical Model for Life- Simulation using Multigrid Method for 3D Printed Sn0.7Cu Bumps with Immersion Tin Time Prediction of Pb-Free Solder Joints in Integration Surface Finishing for Flip Chip Applications Electromigration Tests Jianyong Xie and Madhavan Swaminathan – Georgia Kuei Hsiao Kuo, Jason Lee, Stan Chen, F.L. Chien, Rick Tian Tian, Jung-Kyu Han, Daechul Choi, and King-Ning Tu Institute of Technology Lee, and John Lau – Siliconware Precision Industries – University of California, Los Angeles; A.M. Gusak and Co., Ltd. O. Yu Liashenko – Cherkasy National University

2. 8:25 a.m. – Accurate Electrical Simulation 2. 8:25 a.m. – The Dependence of the Sn 2. 8:25 a.m. – Generalized Method for and Design Optimization for Silicon Grain Structure of Pb-Free Solder Joints on Characterizing Mechanical Loads in Mobile Interposer Considering the MOS Effect and Composition and Geometry Devices Eddy Currents in the Silicon Substrate Gregory Parks, Babak Arfaei, Michael Benedict, and Eric Ari Lumbantobing and Sanjay Tiku – Microsoft Jing Zhou, Lixi Wan, Fengwei Dai, Huijuan Wang, Cotts – Binghamton University; Minhua Lu and Eric Corporation Chongshen Song, Tianmin Du, Yanbiao Chu, Maoyun Pan, Perfecto – IBM Corporation Daniel Guidotti, Liqiang Cao, and Daquan Yu – Chinese Academy of Sciences

3. 8:50 a.m. – Characterization and Modeling 3. 8:50 a.m. – Influence of IMCs Volume Ratio in 3. 8:50 a.m. – Interfacial Fracture Properties of of Si-Substrate Noise Induced by RF Signal Microscale Solder Joints on their Mechanical Cu-EMC Interfaces at Pressure Cooker Test Propagating in TSV of 3D-IC Stack Integrity Conditions M. Brocard, P. Le Maître, P. Bar, A. Farcy, P. Coudrain, and Zhiwen Chen, Bing An and Yiping Wu – Huazhong M. Sadeghinia, K.M.B Jansen, and L.J. Ernst – Delft N. Hotellier – STMicroelectronics; C. Bermond and T. University of Science & Technology; Changqing Liu and University of Technology; H. Pape – Infineon Lacrevaz – Université de Savoie; R. Anciant, P. Leduc, H. Rob Parkin – Loughborough University Technologies AG Ben Jamaa, and S. Chéramy – CEA-LETI

Refreshment Break: 9:15 a.m. – 10:00 a.m. (Pavilion)

4. 10:00 a.m. – PDN Impedance and Noise 4. 10:00 a.m. – Chemical Reactions of Silver and 4. 10:00 a.m. – Measurement of Die Stresses in Simulation of 3D SiP with a Widebus Indium at 180°C Annealing Microprocessor Packaging Due to Thermal Structure Yuan-Yun Wu, Wen P. Lin, and Chin C. Lee – University of and Power Cycling Hiroki Takatani, Yosuke Tanaka, Yoshiaki Oizono, Yoshitaka California, Irvine Jordan Roberts, Mohammad Motalab, Safina Hussain, Nabeshima, Takafumi Okumura, and Toshio Sudo – Jeffrey C. Suhling, Richard C. Jaeger, and Pradeep Lall – Shibaura Institute of Technology; Atsushi Sakai, Shiro Auburn University Uchiyama, and Hiroaki Ikeda – Association of Super- Advanced Electronics Technologies

5. 10:25 a.m. – Development of an Optimized 5. 10:25 a.m. – Soldering Reactions under Space 5. 10:25 a.m. – Flip Chip Power Cycling System Power Delivery System for 3D IC Integration Confinement for 3D IC Applications Development and Lead Free Bump Power with TSV Silicon Interposer C.R. Kao, H.Y. Chuang, W.M. Chen, T.L. Yang, M.S. Kuo, Y.J. Cycling Reliability Zhe Li, Hong Shi, John Xie, and Arif Rahman – Altera Chen, J.J. Yu, and C.C. Li – National Taiwan University M.K.C. Wu, H.Y. Pan, L. Lin, C. Chiu, T. Chou, G. Lu, P. Liu, Corporation G. Wu, H.P. Pu, H.Y. Tsai, K. Wu and B. Kiang – Taiwan Semiconductor Manufacturing Company, Ltd.

6. 10:50 a.m. – Modeling of Power Delivery into 6. 10:50 a.m. – Systematic Investigation of Sn- 6. 10:50 a.m. – Development of Early Process 3D Chips on Silicon Interposer Ag and Sn-Cu Modified by Minor Alloying Control Indicators for Reliability Drop Test Zheng Xu, Xiaoxiong Gu, Michael Scheuermann, Element of Titanium Performance of eWLB Products Buckwell C. Webb, and John U. Knickerbocker – IBM W.M. Chen and C.R. Kao – National Taiwan University; Alexandre Azevedo, André Cardoso, Jorge Teixeira, Oriza Corporation; Kenneth Rose and Jian-Qiang Lu – S.K. Kang – IBM Corporation Tavares, and Rui Marques – Nanium SA Rensselaer Polytechnic Institute

7. 11:15 a.m. – Effects of On-Chip Decoupling 7. 11:15 a.m. – Synthesis and Characterization 7. 11:15 a.m. – Microstructure and Stress Capacitors and Silicon Substrate on Power of Nanoscaled Solder Material Characterization around TSV using In-Situ Distribution Networks in TSV-Based 3D-ICs Andrej Novikov and Mathias Nowottnick – University PIT-in-SEM Kiyeong Kim, Jun So Pak, and Joungho Kim – KAIST; of Rostock Gyujei Lee – Hynix Semiconductor, Inc.; Seoul National Hyungdong Lee – Hynix Semiconductor, Inc. University; Min-Jae Choi, Suk-Woo Jeon, and Kwang-Yoo Byun – Hynix Semiconductor, Inc.; Dongil Kwon – Seoul National University

15 Program Sessions: Thursday, May 31, 1:30 p.m. - 5:10 p.m.

Session 19: Thru Via Technologies Session 20: Co-Design for the 3D Session 21: Flip Chip Technologies Ecosystem

Committee: Committee: Committee: Advanced Packaging Interconnections Advanced Packaging

Harbor Island II Harbor Island I Harbor Island III

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Rozalia Beica – Lam Research AG Gilles Poupon – CEA-LETI-MINATEC Raj N. Master – Microsoft Corporation Sam Karikalan – Broadcom Corporation Voya Markovich – Endicott Interconnect Technologies, Inc. Daniel Baldwin – Engent, Inc.

1. 1:30 p.m. – Robust TSV Via-Middle and Via- 1. 1:30 p.m. – Effects of Silicon Substrate 1. 1:30 p.m. – Low Cost Cu Column fcPoP Reveal Process Integration Accomplished Coupling Phenomena on Signal Integrity for Technology through Characterization and Management RF or High Speed Communications in 3D-IC Hamid Eslampour, YoungChul Kim, SeongWon Park, and of Sources of Variation E. Eid, T. Lacrevaz, G. Houzet, C. Bermond, and B. Fléchet TaeWoo Lee – STATS ChipPAC, Inc. N. Kumar, S. Ramaswami, J. Dukovic, J. Tseng, R. Ding, N. – Université de Savoie; A. Farcy – STMicroelectronics; Rajagopalan, B. Eaton, R. Mishra, R. Yalamanchili, Z. Wang, F. Calmon – Institute des Nanotechnologies de Lyon; P. S. Xia, and K. Sapre – Applied Materials, Inc. Leduc – CEA-LETI

2. 1:55 p.m. – A Novel Scallop Free TSV Etching 2. 1:55 p.m. – Nonlinear Effects of TSV and 2. 1:55 p.m. – Reliability of Large Die Ultra Method in Magnetic Neutral Loop Discharge Harmonic Generation Low-k Lead-Free Flip Chip Packages Plasma Jonghyun Cho, Joohee Kim, Jun So Pak, and Joungho Kim Laurene Yip – Xilinx, Inc. Yasuhiro Morikawa, Takahide Murayama, Toshiyuki – KAIST; Junho Lee, Hyngdong Lee, and Kunwoo Park – Sakuishi, Manabu Yoshii, and Koukou Suu – Ulvac, Inc. Hynix Semiconductor, Inc.

3. 2:20 p.m. – Electrical and Morphological 3. 2:20 p.m. – The Size Dependency of Full IMC 3. 2:20 p.m. – Preferred Orientation of 30um Assessment of Via Middle and Backside Solder Joint for 3D Interconnection Fine Pitch Sn2.5Ag Micro-Bumps Studied Process Technology for 3D Integration Liping Mo, Fengshun Wu and Weisheng Xia – Huazhong by Synchrotron Polychromatic X-Ray Laue Jean-Philippe Colonna, Gennie Garnier, Pascal Chausse, University of Science & Technology; Changqing Liu – Microdiffraction Roselyne Segaud, Amandine Jouve, Catherine Brunet- Loughborough University Tian Tian and King-Ning Tu – University of California, Manquat, Severine Cheramy, and Nicolas Sillon – CEA- Los Angeles; Kai Chen, Martin Kunz, and Nobumichi LETI; Perceval Coudrain, Christophe Aumont, Nicolas Tamura – Lawrence Berkeley National Laboratory; Hotellier, and Thomas Frank – STMicroelectronics Chau-Jie Zhan and Tao-Chih Chang – ITRI Refreshment Break: 2:45 p.m. - 3:30 p.m. (Pavilion)

4. 3:30 p.m. – Process Modeling of Dry Etching 4. 3:30 p.m. – GTL High Speed I/O in 3D ICs 4. 3:30 p.m. – Cu Pillar Exposed-Die Molded for the 3D-Integration with Tapered TSVs for TSV and Interconnect Signal Integrity FCCSP for Mobile Devices Martin Wilke, Michael Töpper, Hue Quoc Huynh, and Characterization Albert Chang-Yi Lan, C.S. Hsiao, John Lau, Erik So, and Klaus Dieter Lang – Fraunhofer IZM Hyunho Baek and William R. Eisenstadt – University of B.H. Ma – Siliconware Precision Industries Co., Ltd. Florida; Shadi Harb – Intel Corporation

5. 3:55 p.m. – All-Wet Cu-Filled TSV Process 5. 3:55 p.m. – Electrical Characterization of 5. 3:55 p.m. – Coreless Substrate Technology using Electroless Co-Alloy Barrier and Cu Through Silicon Vias (TSVs) with an On Chip Investigation for Ultra-Thin CPU BGA Seed Bus Driver for 3D IC Integration Packaging Fumihiro Inoue, Tomohiro Shimizu, Hiroshi Miyake, S.S. Sheu and S.H. Wu – National Central University; Z.H. Mathew Manusharow, Sriram Muthukumar, Emily Zheng, Ryohei Arima, and Shoso Shingubara – Kansai University Lin, C.S. Lin, J.H. Lau, S.H. Lee, K.L. Su, T.K. Ku, J.F. Hung, P.S. Asim Sadiq, and Cliff Lee – Intel Corporation Chen, S.J. Lai, and W.C. Lo – ITRI

6. 4:20 p.m. – Thermal effects on Through- 6. 4:20 p.m. – Co-Design and Optimization of 6. 4:20 p.m. – Evaluation and Verification Silicon Via (TSV) Signal Integrity a 256-GB/s 3D IC Package with a Controller of Enhanced Electrical Performance of Manho Lee, Jonghyun Cho, Joohee Kim, Jun So Pak, and and Stacked DRAM Advanced Coreless Flip-Chip BGA Package Joungho Kim – KAIST; Hyungdong Lee, Junho Lee, and David Secker, Mandy Ji, John Wilson, Scott Best, Ming Li, with Warpage Measurement Data Kunwoo Park – Hynix Semiconductor, Inc. and Julia Cline – Rambus Inc. GaWon Kim, JiHeon Yu, ChulWoo Park, SeoungJoon Hong, JinYoung Kim, Glenn Rinne, and ChoonHeung Lee – Amkor Technology Korea, Inc.

7. 4:45 p.m. – Enhanced Barrier Seed 7. 4:45 p.m. – Electrical Analyses of TSV-RDL- 7. 4:45 p.m. – fcCuBE Technology: A Pathway to Metallization for Integration of High-Density Bump of Interposers for High-Speed 3D IC Advanced Si-Node and Fine Pitch Flip Chip High Aspect-Ratio Copper-Filled 3D Through- Integration Hamid Eslampour, Mukul Joshi, KeonTaek Kang, HyunIl Silicon Via Interconnects Tseshih Sung, Kevin Chiang, Daniel Lee, and Mike Ma – Bae, and YoungChul Kim – STATS ChipPAC, Inc. Yann Civale, Silvia Armini, Harold Philipsen, Augusto Siliconware Precision Industries Co., Ltd. Redolfi, Dimitrios Velenis, Kristof Croes, Nancy Heylen, Zaid El-Mekki, Kevin Vandersmissen, Gerald Beyer, Bart Swinnen, and Eric Beyne – IMEC 16 Program Sessions: Thursday, May 31, 1:30 p.m. - 5:10 p.m. Session 22: Precision Components, Session 23: Assembly Challenges of Session 24: Inkjet Technology and Sensors and RF Packaging Area Array Packages Embedded Devices

Committee: Committee: Committees: Electronic Components & RF / Electronic Components & RF Assembly & Manufacturing Technology Emerging Technologies

Nautilus 1 Nautilus 3 Nautilus 5

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Amit P. Agrawal – Cisco Systems, Inc. Paul Houston – Engent Rockwell Hsu – Cisco Systems, Inc. Lih-Tyng Hwang – National Sun Yat-Sen University Sylvain Ouimet – IBM Corporation Karlheinz Bock – Fraunhofer EMFT

1. 1:30 p.m. – Integration of Precision Resistors 1. 1:30 p.m. – Assembly Yield Improvement of an 1. 1:30 p.m. – System Integration of Smart and Capacitors with Near-Zero Temperature Asymmetric Surface Mountable Transformer Packages using Printed Electronics Coefficients in Silicon and Organic Packages Lejun Wang, Chunho Kim, Scott Sleeper, Gavin Hall, Julie Matti Mäntysalo – Tampere University of Technology; Li P. Markondeya Raj, K.P. Murali, Saumya Gandhi, and Rao Dobbins, and Molly McGuire – Medtronic Xie, Fredrik Jonsson, Yi Feng, Ana López Cabezas, and Tummala – Georgia Institute of Technology; Kirk Slenes Li-Rong Zheng – KTH Royal Institute of Technology and Nathan Berg – TPL Inc.

2. 1:55 p.m. – Low Cost QFN Package Design 2. 1:55 p.m. – Low-Cost and Fine-Pitch Micro- 2. 1:55 p.m. – Inkjet-Printed Graphene-Based for Millimeter-Wave Applications Ball Mounting Technology for WLCSP Wireless Gas Sensor Modules Yi-Chieh Lin, Yu-Chih Lin, Tzyy-Sheng Horng, and Y.H. Lin, Frank Kuo, Y.F Chen, C.S. Ho, J.Y. Lai, Stan Chen, Taoran Le, Vasileios Lakafosis, Ziyin Lin, C.P. Wong, and Lih-Tyng Hwang – National Sun Yat-Sen University; F.L. Chien, Rick Lee, and John Lau – Siliconware Precision M.M. Tentzeris – Georgia Institute of Technology Chi-Tsung Chiu and Chih-Pin Hung – Advanced Industries Co., Ltd. Semiconductor Engineering

3. 2:20 p.m. – A Novel U-Shaped Magnetic 3. 2:20 p.m. – Investigation of the Assembly 3. 2:20 p.m. – Inkjet Printed Flexible User Shield for Perpendicular MRAM Reflow Process and PCB Design on the Interface Module Takahito Watanabe and Shintaro Yamamichi – Renesas Reliability of WLCSP Santtu Koskinen and Matti Mäntysalo – Tampere Electronics Corporation Yong Liu, Qiuxiao Qian, Shichun Qu, Stephen Martin, and University of Technology; Lasse Pykäri – Nokia Oseob Jeon – Fairchild Semiconductor Corporation

Refreshment Break: 2:45 p.m. - 3:30 p.m. (Pavilion)

4. 3:30 p.m. – Behavior Model of Switching DC- 4. 3:30 p.m. – Systematic Studies of Second 4. 3:30 p.m. – Modeling and Design of an Ultra- DC Converter for Improving Power Delivery Level Interconnection Reliability of Edge Miniaturized WLAN Sub-System with Chip- Network Design and Corner Bonded Lead-Free Array-Based Last Embedded PA and Digital Dies Seungyong Baek, Philip Pun, and Amit Agrawal – Cisco Packages under Mechanical and Thermal Gokul Kumar, Srikrishna Sitaraman, Vivek Sridharan, Systems, Inc. Loading Nithya Sankaran, Fuhan Liu, Nitesh Kumbhat, Venky Hongbin Shi and Toshitsugu Ueda – Waseda University; Sundaram, and Rao Tummala – Georgia Institute of Daquan Yu – Chinese Academy of Sciences Technology; Vijay Nair and Telesphor Kamgaing – Intel Corporation; Frank Juskey – TriQuint Corporation

5. 3:55 p.m. – Planar Surface Plasmonic 5. 3:55 p.m. – Assessment of Non-Uniform 5. 3:55 p.m. – Scalable Modeling and Wideband Structures for Terahertz Circuits and Sensors Temperature Effect on BGA De-Component Measurement Techniques for a Signal TSV Premjeet Chahal, Joshua Myers, Kyoung Youl Park, Process Surrounded by Multiple Ground TSVs for RF/ Collin Meierbachtol, and Naveen Nair – Michigan State Kun Tang, Fubin Song, S.W. Ricky Lee, and Jeffery, C.C. Lo High-Speed Applications University – Hong Kong University of Science & Technology Kuan-Chung Lu and Tzyy-Sheng Horng – National Sun Yat-Sen University; Hsin-Hung Lee, Kung-Chin Fan, Tzu- Yuan Huang, and Chun-Hsun Lin – Siliconware Precision Industries Co., Ltd.

6. 4:20 p.m. – Optimized SAW Chemical Sensor 6. 4:20 p.m. – Voltage In-Situ Electrical 6. 4:20 p.m. – A 77 GHz SiGe Single-Chip Four- with Microfluidic Packaging Metrology for Test-to-Failure BGA Channel Transceiver Module with Integrated Robert W. Brocato, Terisse A. Brocato, Joel R. Wendt, Component Shock Margin Assessment Antennas in Embedded Wafer- Level BGA Carlos A. Sanchez, and Larry G. Stotts – Sandia National Ramgopal Uppalapati, Sanjay Goyal, Mike Williams, and Package Laboratories Satish Parupalli – Intel Corporation M. Wojnowski, R. Lachner, J. Böck, G. Sommer, and K. Pressel – Infineon Technologies AG; C. Wagner – DICE GmbH & Co. KG

7. 4:45 p.m. – A Surface Micromachined High 7. 4:45 p.m. – Validated Methodology for Short- 7. 4:45 p.m. – Ultralow Impedance Analysis and Directivity GPS Patch Antenna with a Four- Design-Cycle Chip, Package and System Evaluation of Power Distribution Network for Leaf Clover Shape Metamaterial Slab Interaction Decoupling Capacitor Embedded Interposers Cheolbok Kim, Kyoung Tae Kim, and Yong-Kyu Yoon – Mudasir Ahmad, Qiang Wang, and Weidong Xie – Cisco of 3-D Integrated LSI System University of Florida; Kyung-Hoon Lee – ETRI; Sangrok Systems, Inc. Katsuya Kikuchi and Masahiro Aoyagi – National Lee – ShinHeung College Institute of Advanced Industrial Science and Technology (AIST); Chihiro Ueda and Kanji Otsuka – Meisei University; Toshio Gomyo and Toshikazu Ookubo – Association of Super-Advanced Electronic Technologies 17 Program Sessions: Friday, June 1, 8:00 a.m. - 11:40 a.m. Session 25: 3D Integration Session 26: Advanced Wirebonding Session 27: Bonding Materials and Processes

Committee: Committee: Committee: Advanced Packaging Interconnections Materials & Processing

Harbor Island II Harbor Island I Harbor Island III

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Subhash L. Shinde – Sandia National Laboratory Flynn Carson – STATS ChipPAC, Inc. Kwang-Lung Lin – National Cheng Kung University Luu T. Nguyen – Texas Instruments William Chen – Advanced Semiconductor Engineering, Inc. C Robert Kao – National Taiwan University

1. 8:00 a.m. – Addressing Bandwidth Challenges 1. 8:00 a.m. – Pd-Coated Cu Wire Bonding 1. 8:00 a.m. – Fluxless Tin Bonding of Silicon in Next Generation High Performance Technology: Chip Design, Process Chips to Aluminum Substrates Network Systems with 3D IC Integration Optimization, Production Qualification Shou-Jen Hsu, Chu-Hsuan Sha, and Chin C. Lee – Li Li, Peng Su, Jie Xue, and Mark Brillhart – Cisco and Reliability Test for High Reliability University of California, Irvine Systems, Inc.; John Lau, P.J. Tzeng, C.K. Lee, C.J. Zhan, M.J. Semiconductor Devices Dai, H.C. Chien, and S.T. Wu – ITRI Inderjit Singh and Shin Low – Xilinx, Inc.; Ivy Qin, Cuong Huynh, Horst Clauberg, and Bob Chylak – Kulicke and Soffa Industries, Inc.; Hui Xu and Viola L. Acoff – University of Alabama

2. 8:25 a.m. – 3D Multi-Stacking of Thin 2. 8:25 a.m. – Evaluation of Back End of Line 2. 8:25 a.m. – Low-Temperature, Surface- Dies based on TSV and Micro-Inserts Structures Underneath Wirebond Pads in Compliant Wafer Bonding using Sub-Micron Interconnections Ultra Low-k Device Gold Particles for Wafer-Level MEMS J. Souriau and L. Castagné – CEA-LETI; J. Liotard – Toyohiro Aoki, Takashi Hisada, Keishi Okamoto, John C. Packaging STMicroelectronics; K. Inal, J. Mazuir, and F. Le Texier Malinowski, Keith F. Beckham, and Shinichi Harada – IBM Hiroyuki Ishida and Takuya Yazaki – Suss MicroTec; – ENSM.SE/CMP-GC; G. Fresquet – Fogale; M. Varvara Corporation; Yong-Seok Yang and Joon-Su Kim – Amkor Toshinori Ogashiwa and Yukio Kanehira – Tanaka and N. Launay – SPTS Technologie sas.; B. Dubois and T. Technology, Korea Kikinzoku Kogyo; Shin Ito and Jun Mizuno – Waseda Malia – Gemalto University

3. 8:50 a.m. – Polyimide Based Temporary Wafer 3. 8:50 a.m. – Low Cost Pd Coated Ag Bonding 3. 8:50 a.m. – Electron Microscopy Study on Bonding Technology for High Temperature Wire for High Quality Fab in Air Intermetallic Compound Formation in Cu-Al Compliant TSV Backside Processing and Thin Suresh Tanna, Jairus L. Pisigan, and John Persic – Bond Interface Device Handling Microbonds, Inc.; W.H. Song, Christopher Halmo, and In-Tae Bae and Dae Young Jung – SUNY Binghamton; K. Zoschke, T. Fischer, M. Toepper, T. Fritzsch, and H. Oppermann Michael Mayer – University of Waterloo Yong Du – Advanced Semiconductor Engineering – Fraunhofer IZM; O. Ehrmann and K.D. Lang – TU Berlin; T. Itabashi – Hitachi Chemical DuPont MicroSystems Ltd.; M. Zussman – HD MicroSystems; M. Souter – Tamarack Scientific Refreshment Break: 9:15 a.m. - 10:00 a.m. (Harbor Island Foyer)

4. 10:00 a.m. – Development of a Stacked 4. 10:00 a.m. – An Evaluation of Effects of 4. 10:00 a.m. – Evaluation of the Crystallinity of WCSP Package Platform using TSV (Through Molding Compound and Substrate Material Grain Boundaries of Electronic Copper Thin Silicon Via) Technology Properties on Reliability of Cu Wire BGA Films for Highly Reliable Interconnections Rajiv Dunne, Yoshimi Takahashi, Kazuaki Mawatari, Components Naoki Saito, Naoakazu Murata, Kinji Tamakawa, Ken Masamitsu Matsuura, Tom Bonifield, Philipp Steinmann, Peng Su – Cisco Systems, Inc.; Hidetoshi Seki, Yoshinori Suzuki, and Hideo Miura – Tohoku University and David Stepniak – Texas Instruments, Inc. Nishitani, Chen Ping, Shin-ichi Zenbutsu, and Shingo Itoh – Sumitomo Bakelite Co. Ltd.; Louie Huang, Nicholas Liao, Bill Liu, Curtis Chen, Winnie Tai, and Andy Tseng – ASE

5. 10:25 a.m. – 2.5D and 3D Technology 5. 10:25 a.m. – Cu Wire and Pd-Cu Wire 5. 10:25 a.m. – Evaluation of Self-Assembled Challenges and Test Vehicle Demonstrations Package Reliability and Molding Compounds Monolayer Treatment for Wire Bonding with J.U. Knickerbocker, P.S. Andry, E. Colgan, B. Dang, T. Hidenori Abe – Hitachi Chemical Company, Ltd.; Dong ENEPIG Surface Finish Dickson, X. Gu, C. Haymes, C. Jahnes, Y. Liu, J. Maria, R.J. Chul Kang, Takashi Yamamoto, Takashi Yagihashi, Yoshinori Jeremy Palmer, Dahwey Chu, and Lu Fang – Sandia Polastre, and C.K. Tsang – IBM Corporation Endo, Hiroyuki Saito, Takahiro Horie, Hironori Tamate, National Laboratories Yoshinori Ejiri, and Naoki Watanabe – Hitachi Chemical Company., Ltd.

6. 10:50 a.m. – 3D-TSV Vertical Interconnection 6. 10:50 a.m. – Copper Wire Bond Analysis: Pad 6. 10:50 a.m. – Silver Alloy Wire Ball Bonding Method using Cu/SnAg Double Bumps and Design Effects and Process Considerations Liao Jun Kai, Liang Yi Hung, Li Wei Wu, Men Yeh B-Stage Non-Conductive Adhesives (NCAs) John D. Beleran, Yong Bo Yang, Hyman G. Robles, and Chiang, Don Son Jiang, C.M. Huang, and Yu Po Wang – Yongwon Choi, Jiwon Shin, and Kyung-Wook Paik – Antonino Milanes – United Test And Assembly Center, Siliconware Precision Industries Co., Ltd. KAIST Ltd. (UTAC); Alfred Yeo and Chan Kai Chong – Global Foundries, Ltd.

7. 11:15 a.m. – Numerical and Experimental 7. 11:15 a.m. – Effect of EFO Settings on 7. 11:15 a.m. – Low Cost Palladium Coating Characterization of the Thermal Behavior of Microstructure and Hardness in the FAB of Process and Its Effect on Free-Air-Ball a Packaged DRAM-on-Logic Stack Copper Bonding Wire Softness and Second Bond Strength of Cu H. Oprins, V.O. Cherman, B. Vandevelde, G. Van der Plas, P. Dong Liu, Haibin Chen, and Jingshen Wu – Hong Kong Bonding Wires Marchal, and E. Beyne – IMEC University of Science & Technology; Fei Wong, Kan Lee, John Persic, Jairus L. Pisigan, Suresh Tanna, and Yong and Ivan Shiu – NXP Semiconductors Hong Kong, Ltd. Guo – Microbonds, Inc.; W.H. Song and Michael Mayer – University of Waterloo

18 Program Sessions: Friday, June 1, 8:00 a.m. - 11:40 a.m. Session 28: New Trends in Mechanical Session 29: Novel Approaches in Wafer Session 30: Interconnect Reliability Modeling and Characterization Level Manufacturing

Committee: Committee: Committee: Modeling & Simulation Assembly & Manufacturing Technology Applied Reliability

Marina 6 Seabreeze Spinnaker

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: L. J. Ernst – Delft University of Technology Shichun Qu – Fairchild Semiconductor S.B. Park – Binghamton University Bruce Kim – The University of Alabama Jie Xue – Cisco Systems, Inc. Scott Savage – Medtronic Microelectronics Center

1. 8:00 a.m. – Modeling for Critical Design 1. 8:00 a.m. – Wafer Level Underfill for Area 1. 8:00 a.m. – Effects of Surface Finish and Performance of Wafer Level Chip Scale Array Cu Pillar Flip Chip Packaging of Ultra Conditions on Interfacial Reaction Package Low-k Chips on Organic Substrates Characteristics and Mechanical Reliability of Yong Liu, Qiuxiao Qian, Matt Ring, Jihwan Kim, and Dan Jae-Woong Nah, Michael Gaynes, Eric Perfecto, and Novel Sn-1.2Ag-0.7Cu-0.4In Solder Bump Kinzer – Fairchild Semiconductor Corporation Claudius Feger – IBM Corporation Jae-Myeong Kim, Byung-Hyun Kwak, and Young-Bae Park – Andong National University; Myeong-Hyeok Jeong and Sehoon Yoo – Korea Institute of Industrial Technology

2. 8:25 a.m. – Prediction of Tin-Whiskers 2. 8:25 a.m. – Metrology for Characterization 2. 8:25 a.m. – Micro-Interconnection Reliability: Generation during Thermal Cycle Test using of Wafer Thickness Uniformity during 3DS-IC Thermal, Electrical and Mechanical Stress Stress and Mass-Diffusion Analysis Processing S.L. Wright, C.K. Tsang, J. Maria, B. Dang, R. Polastre, P. Takeshi Terasaki, Takahiko Kato, Tomio Iwasaki, Yasutaka Tom Dunn, Chris Lee, Mark Tronolone, and Aric Shorey Andry, and J. Knickerbocker – IBM Corporation Ookura, and Masato Nakamura – Hitachi, Ltd.; Hideki – Corning, Inc. Ishii and Kenji Yamamoto – Renesas Electronics Corp.

3. 8:50 a.m. – Finite Element Modeling of 3. 8:50 a.m. – Novel Sidewall Interconnection 3. 8:50 a.m. – Effects of UBM Structure/ Anomalous Moisture Diffusion with Dual using Perpendicular Circuit Die with Non- Material on the Reliability Performance of Stage Model Solder Bumps for 3D Chip Stack 3D Chip Stacking with 30um-Pitch Solder Xuejun Fan and Vishal Nigaraj – Lamar University Sun-Rak Kim, Il Kim, and Seung S. Lee – KAIST; Jae Hak Micro Bump Interconnections Lee – KIMM Shin-Yi Huang, Chau-Jie Zhan, Yu-Wei Huang, Yu-Min Lin, Chia-Wen Fan, Su-Ching Chung, Kuo-Shu Kao, Jing-Yao Chang, Mei-Lun Wu, John H. Lau, and Tai-Hung Chen – ITRI; Tsung-Fu Yang – Topco Scientific Co., Ltd.

Refreshment Break: 9:15 a.m. - 10:00 a.m. (Harbor Island Foyer)

4. 10:00 a.m. – Modeling and Reliability 4. 10:00 a.m. – Advanced Low Profile PoP 4. 10:00 a.m. – Electromigration of SnAg Bump Characterization of Area-Array Electronics Solution with Embedded Wafer Level PoP with Ni UBM on Various Substrate Pad Subjected to High-G Mechanical Shock Up (eWLB-PoP) Technology Finishes with SnCu Presolder to 50,000G Seung Wook Yoon, Jose Alvin Caparas, Yaojian Lin, and Tung-Chin Yeh, Tsung-Fu Tsai, Larry Lin, Roger Hsieh, and Pradeep Lall, Kewal Patel, and Ryan Lowe – Auburn Pandi C. Marimuthu – STATS ChipPAC, Ltd. Kenneth Wu – Taiwan Semiconductor Manufacturing University; Mark Strickland, Jim Blanche, Dave Geist, Company, Ltd. and Randall Montgomery – NASA Marshall Space Flight Center

5. 10:25 a.m. – Design and Assembly of a 5. 10:25 a.m. – Temporary Wafer Bonding 5. 10:25 a.m. – Isothermal Shear Fatigue Double-Sided 3D Package with a Controller Defect Impact Assessment on Substrate Mechanism of Lead Free Solder Joints and a DRAM Stack Thinning: Process Enhancement through Huili Xu, Woong Ho Bang, and Choong-Un Kim – Xi Liu and Suresh K. Sitaraman – Georgia Institute Systematic Defect Track Down University of Texas, Arlington; Hong-Tao Ma, Tae-Kyu Lee, of Technology; Ming Li, Don Mullen, and Julia Cline – A. Phommahaxay, G. Verbinnen, S. Suhard, P. Bex, J. and Kuo-Chuan Liu – Cisco Systems, Inc. Rambus, Inc. Pancken, M. Lismont, A. Van den Eede, A. Jourdain, and B. Swinnen – IMEC; T. Woitke, P. Bisson, and W. Spiess – Suss MicroTec

6. 10:50 a.m. – Establishing Mode Mix 6. 10:50 a.m. – Novel Approaches of Wafer Level 6. 10:50 a.m. – Electromigration Measurements Dependency of Fracture Toughness in Packaging for MEMS Devices in Thin-Film IPD and eWLB Interconnections Microelectronic Components with Reduced Cheng-Hsiang Liu, Hong-Da Chang, Hsin-Yi Liao, Kuo- Robert Frye – RF Design Consulting, LLC; Kai Liu, Experimental Effort Hsiang Li, Chen-Han Lin, Wei-Yu Chen, and Tse-Yuan Lin KyawOo Aung, and M. Pandi Chelvam – STATS H. Pape, I. Maus, and H.S. Nabi – Infineon Technologies; – Siliconware Precision Industries Co., Ltd. ChipPAC, Ltd. L.J. Ernst – Delft University of Technology; B. Wunderle – TU Chemnitz

7. 11:15 a.m. – Failure Prediction in Fully 7. 11:15 a.m. – Silicon-Based System in 7. 11:15 a.m. – Effect of High Strain-Rate Coupled Thermal and Deformational Fields Packaging for Light Emitting Diodes on Mechanical Properties of SAC105 and with Peridynamics Bin Cao, Shan Yu, Huai Zheng, and Sheng Liu – Huazhong SAC305 Lead-Free Alloys Abigail Agwai – Intel Corporation; Ibrahim Guven and University of Science & Technology Pradeep Lall, Sandeep Shantaram, and Jeff Suhling – Erdogan Madenci – University of Arizona Auburn University; Dave Locker – US AMRDEC

19 Program Sessions: Friday, June 1, 1:30 p.m. - 5:10 p.m. Session 31: Applications with Session 32: Advanced Substrate and Session 33: Substrates and Thermal 3D Technologies Wafer Level Packaging Interface Materials

Committees: Interconnections / Committee: Committee: Emerging Technologies Advanced Packaging Materials & Processing

Harbor Island II Harbor Island I Harbor Island III

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Akitsu Shigetou – National Institute for Materials Science Young-Gon Kim – IDT Don Frye – Polyera Corp. Nancy Stoffel – GE Global Research Altaf Hasan – Intel Corporation Tieyu Zheng – Intel Corporation

1. 1:30 p.m. – Via Last Technology for Direct 1. 1:30 p.m. – Application of Coreless Substrate 1. 1:30 p.m. – Evaluation of Raw Substrate Stacking of Processor and Flash to Package on Package Architectures Variation from Different Suppliers and R. Puschmann, M. Boettcher, I. Bartusseck, F. Windrich, Robert Nickerson, Reynaldo Olmedo, Russell Processes, and their Impact on Package C. Fiedler, P. John, C. Manier, K. Zoschke, J. Grafe, H. Mortensen, Choong Kooi Chee, Sanjay Goyal, Ai Ling Warpage Oppermann, and M.J. Wolf – Fraunhofer IZM; M. Low, and Charles Gealer – Intel Corporation Wei Lin, Shengmin Wen, Akito Yoshida, and JeongMin Ziesmann – NXP Semiconductors Shin – Amkor Technology

2. 1:55 p.m. – 3D-Interconnect Approach for 2. 1:55 p.m. – Chip-Last Fan-Out Package 2. 1:55 p.m. – Low Cost System-in-Package High End Electronics with Embedded Power ICs in Ultra-Thin Module using Next Generation Low Loss Rabindra N. Das, Frank D. Egitto, John Lauffer, Barry Laminates Organic Material Bonitz, Bill Wilson, Francesco Marconi, Mark D. Poliks, Nitesh Kumbhat, Koushik Ramachandran, Fuhan Liu, Yuya Suzuki, Srikrishna Sitaraman, Abhilash Goyal, Fuhan and Voya R. Markovich – Endicott Interconnect Brent Wagner, Venky Sundaram, and Rao Tummala – Liu, Nitesh Kumbhat, Venky Sundaram, and Rao Tummala Technologies, Inc. Georgia Institute of Technology – Georgia Institute of Technology; Masakazu Hashimoto, Toshihiko Jimbo, and Ryota Mori – Zeon

3. 2:20 p.m. – TSV-Based Decoupling Capacitor 3. 2:20 p.m. – Low Warpage Coreless Substrate 3. 2:20 p.m. – Enhancement of Barrier Schemes in 3D-IC for Large-Size LSI Packages Properties of Encapsulants for Harsh Eunseok Song, Jun So Pak, and Joungho Kim – KAIST Mamoru Kurashina, Daisuke Mizutani, Masateru Koide, Environment Applications Manabu Watanabe, Kenji Fukuzono, and Hitoshi Suzuki T. Braun, J. Bauer, K.F. Becker, M. Koch, and R. – Fujitsu Aschenbrenner – Fraunhofer IZM; L. Georgi and K.D. Lang – TU Berlin

Refreshment Break: 2:45 p.m. - 3:30 p.m. (Harbor Island Foyer)

4. 3:30 p.m. – Enabling Technologies for 4. 3:30 p.m. – Innovative Fan-Out Wafer Level 4. 3:30 p.m. – Thermal Performance Advanced Wafer Level Camera Integration Package using Lamination Process and Characterization of Nano Thermal Interface C. Bouvier, S. Bolis, D. Saint-Patrice, A. Pouydebasque, F. Adhered Si Wafer on the Backside Materials after Power Cycling Jacquet, C. Bridoux, S. Moreau, G. Simon, and N. Sillon – H.S. Hsu, David Chang, Kenny Liu, Nicholas Kao, Mark Shuangxi Sun – Shanghai University; Luo Xin and CEA-LETI; E. Vigier-Blanc – STMicroelectronics SAS Liao, and Steve Chiu – Siliconware Precision Industries Johan Liu – Shanghai University, Chalmers University Co., Ltd. of Technology; Carl Zandén and Björn Carlberg – Chalmers University of Technology; Lilei Ye – SHT Smart High-Tech AB

5. 3:55 p.m. – Low Cost 3D Multilevel 5. 3:55 p.m. – Development and 5. 3:55 p.m. – Structural Functionality Analysis Interconnect Integration for RF and Characterization of Next Generation eWLB of Nanostructured Thermal Interface Microwave Applications (Embedded Wafer Level BGA) Packaging Materials Ayad Ghannam and David Bourrier – LAAS-CNRS; Yonggang Jin, Jerome Teysseyre, and Xavier Baraton – Xiangdong Xue, Chris Bailey, Hua Lu, and Ohidul Alam – Lamine Ourak, Christophe Viallon, and Thierry Parra – STMicroelectronics; S.W. Yoon, Yaojian Lin, and Pandi C. University of Greenwich LAAS-CNR, University of Toulouse Marimuthu – STATS ChipPAC, Ltd.

6. 4:20 p.m. – A Low-Cost Approach to High-k 6. 4:20 p.m. – Optical Characteristics and 6. 4:20 p.m. – Single/Few-Layer Boron Nitride- Thin Film Decoupling Capacitors on Silicon Reliability Evaluation of Wafer Level White Based Nanocomposites for High Thermal and Glass Interposers LED Package Conductivity Underfills Saumya Gandhi, Shu Xiang, P. Markondeya Raj, Venky Akiya Kimura, Susumu Obata, Toshiya Nakayama, Ryuichi Ziyin Lin, Yagang Yao, Andrew Mcnamara, and Kyoung-Sik Sundaram, Madhavan Swaminathan, and Rao Tummala – Togawa, Takayoshi Fujii, Hiroshi Koizumi, Kazuhito Moon – Georgia Institute of Technology; C.P. Wong – Georgia Institute of Technology Higuchi, Yosuke Akimoto, Miyuki Shimojuku, and Akihiro Georgia Institute of Technology, Chinese University of Kojima – Toshiba Corporation Hong Kong

7. 4:45 p.m. – Fine Pitch Copper PoP for Mobile 7. 4:45 p.m. – Wafer Level Compression Molding 7. 4:45 p.m. – Nano-Micro Particle Filled Applications Compounds Thermal Interface Materials: Towards Philip Damberg, Ilyas Mohammed, and Reynaldo Co – Taku Hasegawa, Hidenori Abe, and Takatoshi Ikeuchi – Materials Development, Characterization, Invensas, Inc. Hitachi Chemical Co., Ltd. Assembly, and Performance Evaluation Rabindra N. Das, Evan Chenelly, Erich Kopp, Dave Alcoe, Mark D. Poliks, and Voya R. Markovich – Endicott Interconnect Technologies, Inc.

20 Program Sessions: Friday, June 1, 1:30 p.m. - 5:10 p.m. Session 34: 3D Systems and Emerging Packages- Session 35: Optical Interconnects Session 36: Integrated Microfluidics Thermal and Thermo-Mechanical Studies

Committee: Committee: Committee: Modeling & Simulation Optoelectronics Emerging Technologies

Marina 6 Seabreeze Spinnaker

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Yong Liu – Fairchild Semiconductor Corporation Andrew Shapiro – JPL Mark Bachman – University of California, Irvine Xuejun Fan – Lamar University Kannan Raj – Sun Labs, Oracle Joana Maria – IBM Corporation

1. 1:30 p.m. – A Finite Element Analysis of Board 1. 1:30 p.m. – Terabit/Sec 48-Channel Fiber- 1. 1:30 p.m. – Characteristics of Blood Flow Level Temperature Cycling Reliability of Coupled Optical Module based on Holey in Microchannels and Relevant Impact Embedded Wafer Level BGA (eWLB) Package CMOS Transceiver IC on Modelling Blood Behaviour in Biochip Seng Guan Chow, Yaojian Lin, Eric Ouyang, and Billy Ahn Fuad E. Doany, Benjamin G. Lee, Alexander V. Rylyakov, Separators – STATS ChipPAC, Inc. Daniel M. Kuchta, Christopher Jahnes, Christian Baks, Xiangdong Xue – University of Greenwich; Xueyong Frank Libsch, and Clint L. Schow – IBM Corporation Wei – University of Cambridge

2. 1:55 p.m. – Hybrid Thermal Solution for 2. 1:55 p.m. – Cost-Effective Low-Loss Flexible 2. 1:55 p.m. – Integration of On-Chip Glass 3D-ICs: Using Thermal TSVs with Placement Optical Engine with Microlens-Imprinted Microfluidic System by a Chemical Foaming Algorithm for Stress Relieving Structures Film for High-Speed On-Board Optical Process (CFP) Jui-Hung Chien, Yung-Fa Chou, and Ding-Ming Kwai Interconnection Jintang Shang, Xinhu Luo, Shunjin Qin, Yu Zou, Xiao Xie, – ITRI; Hao Yu, Nien-Yu Tsai, and Shih-Chieh Chang – Takashi Shiraishi, Takatoshi Yagisawa, Tadashi Ikeuchi, and Junwen Liu – Southeast University; Wei Lin and C.P. National Tsing Hua University; Chiao-Ling Lung – ITRI, Satoshi Ide, and Kazuhiro Tanaka – Fujitsu Laboratories, Wong – Georgia Institute of Technology National Tsing Hua University; Chin-Chi Hsu and Ping- Ltd. Hei Chen – National Taiwan University

3. 2:20 p.m. – Development of Through Silicon 3. 2:20 p.m. – Small-Aperture Guided-Mode- 3. 2:20 p.m. – Plastic Injection Micromolding of Via (TSV) Interposer for Memory Module Flip Resonance Filter with Cavity Resonators THz Circuits and Microfluidic Sensors Chip Package Shogo Ura, Tatsuya Majima, Koji Hatanaka, Junichi Inoue, Kyoung Youl Park, Nophadon Wiwatcharagoses, Cecilia Nicholas Kao, Eason Chen, Daniel Lee, and Mike Ma – Kenzo Nishio, and Yasuhiro Awatsuji – Kyoto Institute Acosta Silveira, and Premjeet Chahal – Michigan State Siliconware Precision Industries Co., Ltd. of Technology; Kenji Kintaka – National Institute of University Advanced Industrial Science and Technology

Refreshment Break: 2:45 p.m. - 3:30 p.m. (Harbor Island Foyer)

4. 3:30 p.m. – Interlayer Dielectric Cracking in 4. 3:30 p.m. – Scaling Hybrid-Integration of 4. 3:30 p.m. – Combination of Channel- and Back End of Line (BEOL) Stack Silicon Photonics in Freescale130nm to TSMC Droplet-Based Microfluidics for Complex Sathyanarayanan Raghavan and Suresh K. Sitaraman 40nm-CMOS VLSI Drivers for Low Power PoC-Devices – Georgia Institute of Technology; Ilko Schmadlak – Communications Erik Jung, Jörg Bauer, Tanja Braun, and Victoria Schuldt Freescale Semiconductor J.E. Cunningham, I. Shubin, H.D. Thacker, J.H. Lee, G.L. Li, – Fraunhofer IZM; Leopold Georgi – TU Berlin; Khaled X. Zheng, J. Lexau, R. Ho, J.G. Mitchell, Y. Luo, J. Yao, and K. Metwally, Laurent Robert, and Chantal Khan-Malek – Raj – Oracle CNRS FEMTO Innovation

5. 3:55 p.m. – Prognostication of Accrued 5. 3:55 p.m. – Demonstration of High- 5. 3:55 p.m. – Silicon Integrated Micro Batteries Damage in Board Assemblies under Thermal Bandwidth Data Transmission above 240 based on Deep Reactive Ion Etching and and Mechanical Stresses Gbps for Optoelectronic Module with Low- Through Silicon Via Technologies Pradeep Lall and Ryan Lowe – Auburn University; Kai Loss and Low-Crosstalk Polynorbornene R. Hahn, K. Markquardt, M. Thunmann, M. Töpper, M. Goebel – NASA Ames Research Center Waveguides Wilke, M. Ferch, Q.H. Huynh, and K.D. Lang – Fraunhofer Yuka Ito, Shinsuke Terada, Mayank Kumar Singh, Shinya IZM Arai, and Koji Choki – Sumitomo Bakelite Co., Ltd.

6. 4:20 p.m. – Generic Thermal Analysis for 6. 4:20 p.m. – Single-Mode Glass Waveguide 6. 4:20 p.m. – Using Polymer and Ionic Liquid Phone and Tablet Systems Platform for DWDM Chip-to-Chip as Liquid Droplet Study in Single-Plate Siva P. Gurrum, Darvin R. Edwards, Thomas Marchand- Interconnects Electrowetting System Golder, Jotaro Akiyama, Satoshi Yokoya, Jean-Francois Lars Brusberg and Henning Schröder – Fraunhofer IZM; Edward K.L. Chan and Matthew M.F. Yuen – Hong Kong Drouard, and Franck Dahan – Texas Instruments, Inc. Marco Queisser and Klaus-Dieter Lang – TU Berlin University of Science & Technology

7. 4:45 p.m. – Cohesive Zone Modeling of 7. 4:45 p.m. – Ultralow EMI Interconnection 7. 4:45 p.m. – Microfluidic Thermal Component 3D Delamination in Encapsulated Silicon Module for Mobile Devices using 3D-Flexible for Integrated Microfluidic Systems Devices Hybrid Multi-Fin Optoelectronic FPC Sarkis Babikian, Liang Wu, G.P. Li, and Mark Bachman – Siow Ling Ho, Shailendra P. Joshi, and Andrew A.O. Tay – Hiroshi Uemura, Kentaro Kobayashi, Kohei Hiyama, University of California, Irvine National University of Singapore Hideto Furuyama, Yoshiaki Sugizaki, and Hideki Shibata – Toshiba Corporation

21 Interactive Presentations: Wednesday, May 30 and Thursday, May 31, 9:00 a.m. - 11:00 a.m. and 2:00 p.m. - 4:00 p.m.

Wednesday, May 30 16. Coating Techniques for 3D-Packaging Applications Thursday, May 31 Session 37: Interactive Presentations 1 M. Töpper, M. Wilke, J. Röder, T. Fischer, and Ch. Lopper – Session 39: Interactive Presentations 3 9:00 a.m. - 11:00 a.m. Fraunhofer IZM 9:00 a.m. - 11:00 a.m. Committee: Interactive Presentations 17. Void Formation during Reflow Soldering Committee: Interactive Presentations Thomas D. Ewald – Robert Bosch GmbH, TU Dresden; Pavilion Norbert Holle – Robert Bosch GmbH; Klaus-Jürgen Pavilion Session Co-Chairs: Wolter – TU Dresden Session Co-Chairs: Mark Poliks – Endicott Interconnect Technologies, Inc. Ibrahim Guven – University of Arizona Ibrahim Guven – University of Arizona Wednesday, May 30 Nam Pham – IBM Corporation 1. Newly Developed Ultra Low CTE Materials for Thin Session 38: Interactive Presentations 2 1. Aspects of Scaling to Mesoscale Models Derived Core PKG 2:00 p.m. - 4:00 p.m. from the Molecular Scale for Understanding Epoxy Masato Miyatake, Hikari Murai, Shin Takanezawa, Shinji Committee: Interactive Presentations Interfaces Tsuchikawa, Masaaki Takekoshi, Tomohiko Kotake, and Nancy Iwamoto – Honeywell Performance Materials Masahisa Ose – Hitachi Chemical Co., Ltd. Pavilion and Technologies 2. Fabrication and Electrical Characterization of Session Co-Chairs: 2. A Compact Thermal Model to Predict the Junction Embedded Actives and Passives for System Level Swapan Bhattacharya – Georgia Institute of Temperature of High Power Light Emitting Diode Analysis: Towards Size, Weight and Power (SWaP) Technology Package Reduction Run Hu, Zhangming Mao, Huai Zheng, Quan Chen, Rao Bonda – Amkor Technology Rabindra N. Das, Steven G. Rosser, Robert Welte, John Sheng Liu, and Xiaobing Luo – Huazhong University of M. Lauffer, Richard Kelly, Mark D. Poliks, and Voya R. 1. The Study of Silicon Passivation Polymer Adhesion Science & Technology Markovich – Endicott Interconnect Technologies, Inc. to Epoxy Mold Compound Through Button Shear 3. Channel Design Methodology for 28Gbps 3. Polyhedral Oligomeric Silsesquioxanes (POSS)- Strength SerDes FPGA Applications with Stacked Silicon Filled Underfill with Excellent High Temperature Shin Low and Inderjit Singh – Xilinx, Inc.; Takeshi Mori – Interconnect Technology Performance Sumitomo Bakelite Co. Ltd.; Hironari Mori – Sumitomo Namhoon Kim, Daniel Wu, Jack Carrel, Joong-Ho Kim, Ziyin Lin and Kyoung-sik Moon – Georgia Institute of Plastics America, Inc. and Paul Wu – Xilinx, Inc. Technology; Shunyi Lau – Chinese University of Hong 4. Design, Modeling, and Fabrication of mm3 Three- 2. A General Co-Design Approach to Multi-Level Kong; C.P. Wong – Georgia Institute of Technology, Dimensional Integrated Antennas Package Modeling based on Individual Single-Level Chinese University of Hong Kong Peter Gadfort and Paul D. Franzon – North Carolina 4. Package-on-Package for Chip Cooling with Package Full-Wave S-Parameter Modeling Including State University Embedded Fluidics Signal and Power/Ground Ports 5. Decoupling Optimization for IC-Package and Tiffany Chua, Sarkis Babikian, Liang Wu, G.P. Li, and Mark Zhaoqing Chen – IBM Corporation PCB Systems Considering High Performance Bachman – University of California, Irvine 3. Sustained Damage and Remaining Useful Life Microprocessor Core and Signal Interface 5. A Study on the Chip-Package-Interaction for Assessment in Lead-Free Electronics Subjected to Interactions Advanced Devices with Ultra Low-k Dielectric Sequential Multiple Thermal Environments Om P. Mandhana – Sigrity, Inc. Seok Won Lee, Byoung Wook Jang, Jong Kook Kim, Yoon Pradeep Lall, Mahendra Harsha, and Jeff Suhling – Auburn 6. Extraction of Electrical Properties of Nanomagnetic Ha Jung, Young Bae Kim, Ho Geon Song, Sa Yoon Kang, University; Kai Goebel – NASA Ames Research Center Materials through Meander-Shaped Inductor and Young Min Kang, San Man Lee, Ki Chul Park, Chi Sun Ju, 4. Development of Micro-Alloying Method for Cu Inverted-F Antenna Structures and Gun Rae Kim – Samsung Electronics Company, Ltd. Pillar Solder Bump by Solid Liquid Interaction Kyu Han, Madhavan Swaminathan, P. Markondeya Raj, 6. Ultra Low-Cost Through-Silicon Holes (TSHs) Wen Yin, Fengwei Dai, Chongshen Song, Zhang Bo, and Himani Sharma, K.P. Murali, and Rao Tummala – Georgia Interposers for 3D IC Integration SiPs Lixi Wan – Chinese Academy of Sciences; Daquan Yu – Institute of Technology; Vijay Nair – Intel Corporation Sheng-Tsai Wu, John H. Lau, Heng-Chieh Chien, Jui-Feng Chinese Academy of Sciences, Jiangsu R&D Center for 7. Reverse Wire Bonding and Phosphor Printing for Hung, Ming-Ji Dai, Yu-Lin Chao, Ra-Min Tain, Wei-Chung Internet of Things; Han Yu and Jiangyan Sun – Shanghai LED Wafer Level Packaging Lo, and Ming-Jer Kao – ITRI Sinyang Semiconductor Materials Co., Ltd. Jeffery C.C. Lo, S.W. Ricky Lee, Rong Zhang, and Mei Li – 7. Fabrication and Characterization of Wafer-Level Hong Kong University of Science & Technology 5. Factors Affecting Pb-Free Flip Chip Bump Reliability Deep TSV Arrays 8. Multiple Voltage-Supplies in TSV-Based Three- Modeling for Life Prediction Michael Zervas, Yuksel Temiz, and Yusuf Leblebici – École Dimensional (3D) Power Distribution Networks Polytechnique Fédérale de Lausanne Ahmer Syed, Gil Sharon, and Robert Darveaux – Amkor Zheng Xu, Xiaoxiong Gu, Michael Scheuermann, 8. Impact of the Winding Area of Enameled Wire on Technology Buckwell C. Webb, and John U. Knickerbocker – IBM Packaging Performance of a Closed Loop Hall 6. Optimized Reliability Test Design to Reduce Corporation; Kenneth Rose and Jiang Qiang Lu – Effect Current Sensor Uncertainties in Reliability Assessment Rensselaer Polytechnic Institute Fu’an Li, Xiaobing Luo, Xingguo Cheng, and Sheng Liu – Daeil Kwon and Alan E. Lucero – Intel Corporation 9. Comprehensive, Scalable Design Guidance for Huazhong University of Science and Technology 7. Design, Fabrication, and Calibration of Stress Serpentine Time Delay Variation in Digital System 9. MEMS Gyroscope Yield Simulation Based on Monte Sensors Embedded in a TSV Interposer in a 300mm Jaemin Shin and Timothy Michalka – Qualcomm, Inc. Carlo Method Wafer 10. Investigation of Integrated Passive Device with Zhang Luo and Sheng Liu – Huazhong University of P.J. Tzeng, J.H. Lau, M.J. Dai, S.T. Wu, H.C. Chien, Y.L. Chao, Through-Silicon Via Science & Technology; Xiaoping Wang – FineMEMS Inc.; C.C. Chen, S.C. Chen, C.Y. Wu, C.K. Lee, C.J. Zhan, and Kai Liu, MaPhooPwint Hlaing, YongTaek Lee, HyunTai Min Jin – Hunan University J.C. Chen – ITRI Kim, Gwang Kim, and Billy Ahn – STATS ChipPAC, Inc.; 10. High-Density Capacitors with Conformal High-K 8. Highly-Reliable Silicon and Glass Interposers- Robert Frye – RF Design Consulting Dielectrics on Etched-Metal Foils to-Printed Wiring Board SMT Interconnections: 11. A New Methodology for Board-Level Harmonic Parthasarathi Chakraborti, Himani Sharma, P. Modeling, Design, Fabrication and Reliability Analysis of Multi-Level Packages Markondeya Raj, and Rao Tummala – Georgia Institute Xian Qin, Nitesh Kumbhat, Venky Sundaram, and Rao Cheng-fu Chen – University of Alaska, Fairbanks of Technology 12. Surface Plasmon-Assisted Terahertz Imaging Array Tummala – Georgia Institute of Technology 11. 3D Stacked Microfluidic Cooling for High Kyoung Youl Park, Collin S. Meierbachtol, Nophadon Performance 3D Ics 9. Development of Damage-Less Wet-Chemical Wiwatcharagoses, and Premjeet Chahal – Michigan State Yue Zhang, Ashish Dembla, Yogendra Joshi, and Silicon-Wafer Thinning Process for Three- University Muhannad S. Bakir – Georgia Institute of Technology Dimensional Integration 13. Modular Assembly of Diode Lasers in a Compact 12. Copper Conductive Adhesives for Printed Circuit Naoya Watanabe and Masahiro Aoyagi – AIST; Takumi and Reliable Setup for a Wide Range of Interconnects Miyazaki and Kazuhiro Yoshikawa – PRE-TECH AT Co., Applications Siyuan Qi, Robert Litchfield, David A. Hutt, Bala Ltd. A. Sahm, C. Fiebig, S. Spießberger, E. Luvsandamdin, K. Vaidhyanathan, and Changqing Liu – Loughborough 10. Nano Filler Dispersion in Polymer Composites for Paschke, G. Erbert, and G. Tränkle – Ferdinand Braun University; Patrick Webb – Manufacturing Technology Electronic Packaging Institute; M. Schiemangk – Humboldt-Universität zu Centre; Stephen Ebbens – University of Sheffield Zhuo Li, Yi Gao, Kyoung-Sik Moon, and Allen Berlin 13. Low Temperature Bonding using Non-Conductive Tannenbaum – Georgia Institute of Technology; C.P. 14. Refined but Handy Electrical Models of TSV Adhesive for 3D Chip Stacking with 30mm-Pitch Wong – Georgia Institute of Technology, Chinese Useable from Low to High Density and for RF or Micro Solder Bump Interconnections University of Hong Kong Fast Digital Signals in 3D-IC Yu-Min Lin, Chau-Jie Zhan, Kuo-Shu Kao, Chia-Wen Fan, 11. Topology Bandpass Filter with Spiral Capacitors L. Fourneaud, T. Lacrevaz, C. Bermond, Y. Gaeremynck, Su-Ching Chung, Yu-Wei Huang, Shin-Yi Huang, Jing-Yao Young K. Song, Chu Hsuan Sha, and Chin C. Lee – and B. Flechet – Université de Savoie; J. Charbonnier and Chang, John H. Lau, and Tai-Hung Chen – ITRI; Tsung-Fu University of California, Irvine C.. Fuchs – CEA-LETI; A. Farcy – STMicroelectronics Yang – Topco Scientific Company, Ltd. 12. Flexible System for Real-Time Plasma 15. Thermal Evaluation and Analyses of 3D IC 14. Plasma Etch and Low Temperature PECVD Integration SiP with TSVs for Network System Decapsulation of Copper Wire Bonded IC Packages Processes for Via Reveal Applications Applications Dave Thomas, Keith Buchanan, Hefin Griffiths, Kath J. Tang, J.B.J. Schelen, and C.I.M. Beenakker – Delft Heng-Chieh Chien, John H. Lau, Yu-Lin Chao, Ming-Ji Dai, Crook, Mark Carruthers, Oliver Ansell, and Dan Archard University of Technology and Ra-Min Tain – ITRI; L. Li, P. Su, J. Xue, and M. Brillhart – SPTS Technologies 13. High Productivity and Damage-Free Ultrasonic – Cisco Systems, Inc. 15. A Mobile TV/GPS Module by Embedding a GPS IC Anisotropic Conductive Film (ACF) Bonding for 16. The Effect of Sintering Profile and Printed in Printed-Circuit-Board Touch Screen Panel (TSP) Assemblies Layer Variations with Inkjet-Printed, Large-Area Jong-In Ryu, Se-Hoon Park, Dongsu Kim, Jun-Chul Kim, Seung-Ho Kim and Kyung-Wook Paik – KAIST; Young- Applications and Jong-Chul Park – Korea Electronics Technology Jae Kim and Ho Joon Park – Samsung Electro-Mechanics Vesa Pynttäri, Eerik Halonen, Matti Mäntysalo, and Riku Institute Company, Limited Mäkinen – Tampere University of Technology

Wednesday & Thursday Refreshment Breaks: 9:15 a.m. - 10:00 a.m. and 2:45 p.m. - 3:30 p.m. • See pages 10-17 for location. 22 Interactive Presentations: Wednesday, May 30 and Thursday, May 31, 9:00 a.m. - 11:00 a.m. and 2:00 p.m. - 4:00 p.m.

17. Efficient Parametric Modeling and Analysis for 13. Microfluidic Chips Fabrication from UV Curable 9. Double Stub Matching in Multilayered Printed Circuit Backplane Channel Characterization Adhesives for Heterogeneous Integration Board using Vias Xiaoxiong Gu, Michael Cracraft, Renato Rimolo V.R.S.S. Mokkapati – National University of Singapore; Andreas Hardock, Renato Rimolo-Donadio, Heinz-Dietrich Donadio, and Young Kwark – IBM Corporation; Ki Jin Ole Bethge – Technical University of Vienna; Rainer Brüns, and Christian Schuster – TU Hamburg-Harburg Han – IBM Corporation, Ulsan National Institute of Hainberger and Hubert Brueckl – Austrian Institute of 10. Highly Compact Surface Micromachined Science and Technology Technology Metamaterial Circuits using Multilayers of Low-Loss 18. Non-Causal Behavior: The Cause for Concern 14. Cost Trade-Off Analysis of PoP versus 3D TSV Benzocyclobutene for Microwave and Millimeter Wave Wesley Martin, Jerry Bartley, Matt Doyle, Richard Chet A. Palesko and Alan C. Palesko – SavanSys Applications Ericson, and George Zettles – IBM Corporation Solutions, LLC; E. Jan Vardaman – TechSearch David E. Senior – University of Florida, Universidad Tecnológica de Bolívar; Xiaoyu Cheng and Yong-Kyu Yoon – 19. Characterization of Al Wire Wedge Bonding in International, Inc. University of Florida Power Electronics Package 15. High Density Compliant Contacting Technology for Integrated High Power Modules in Automotive 11. 40µm Ag/Au Composite Flip-Chip Interconnect using Yumin Liu, Yong Liu, Daren Keller, Suresh Belani, and Solid State Atomic Bonding at 200°C Michael Dube – Fairchild Semiconductor Corporation Applications Paolo Nenzi, Rocco Crescenzi, Nicola Pio Belfiore, and Wen P. Lin, Chu-Hsuan Sha, and Chin C. Lee – University of Marco Balucani – University of Rome; Alexander Dolgyi, California, Irvine Alexy Klyshko, and Vitaly Bondarenko – Belarussian 12. Nanomanufacturing of Large Area Carbon Nanofibers Thursday, May 31 State University of Informatics and Radioelectronics using Tube Nozzle Electrospinning (TNE), Lithography Session 40: Interactive Presentations 4 16. Development of Ultra Dense Edge Interconnects for and Carbonization Processes Die to Die Connections based on Immersion Solder Pit Fee Jao, Sheng-Po Fang, David E. Senior, Kyong Tae Kim, 2:00 p.m. - 4:00 p.m. and Yong-Kyu Yoon – University of Florida Committee: Interactive Presentations Bridging Dahwey Chu and Lauren E.S. Rohwer – Sandia National 13. Embedded Actives for Terahertz Circuit Applications: Pavilion Laboratories Imaging Array Xianbo Yang and Premjeet Chahal – Michigan State Session Co-Chairs: 17. A Cost-Effective and Compact 28-Gb/s ROSA Module using a Novel TO-CAN Package University Rao Bonda – Amkor Technology 14. Vertically Aligned Nickel Nanowire/Epoxy Composite Sae-Kyoung Kang, Joon Ki Lee, Joon-Young Huh, Jyung Patrick Thompson – Texas Instruments, Inc. for Electrical and Thermal Conducting Material Chan Lee, and Kwangjoon Kim – Electronics and Hyeong-Gi Lee and Kyung-Wook Paik – KAIST 1. Remedies to Control Electromigration: Effects of Telecommunications Research Institute 15. A Compact 100 MHz to 7 GHz Frequency Equalizer CNT Doped Sn-Ag-Cu Interconnects 18. A New Approach towards an Optimum Design based on Distributed Passive Circuits Sha Xu and Y.C. Chan – City University of Hong Kong; and Manufacture of Microfluidic Devices based Xiaoyu Cheng, David E. Senior, and Yong-Kyu Yoon – Xiaoxin Zhu, Hua Lu, and Chris Bailey – University of on Ex Situ Fabricated Hydrogel based Thin Films’ University of Florida Greenwich; Hiren Kotadia and Samjid H. Mannan – Integration 16. Low Latency High Throughput Memory-Processor King’s College London Weiwei Zhao and Changqing Liu – Loughborough Interface 2. Cu and Al-Cu Composite-Material Interconnects for University; Tommaso Santaniello – Loughborough Qidong Wang, Daniel Guidotti, Jie Cui, Liqiang Cao, Tianchun Power Devices University, University of Milan; Patrick Webb – Ye, and Lixi Wan – Chinese Academy of Sciences; Fujiang Lin Jamin Ling, Tao Xu, Raymond Chen, Orlando Valentin, and Manufacturing Technology Centre; Cristina Lenardi – and Guang Zhu – University of Science and Technology of Christoph Luechinger – Kulicke and Soffa Industries, Inc. University of Milan, Fondazione Filarete China; Qian Wang – Tsinghua University 3. Compliant Interconnects for Reduced Cost of a 19. Design and Fabrication of Low-Loss, Horizontal 17. Metamaterial-Inspired Miniaturized Microwave Ceramic Ball Grid Array Carrier and Vertical Interconnect Links using Air-Clad Sensing Probes Maaike M.V. Taklo, Andreas Larsson, and Astrid-Sofie Transmission Lines and Through Silicon Vias Nophadon Wiwatcharagoses, Kyoung Youl Park, and Vardøy – SINTEF ICT; Helge Kristiansen – Conpart AS; Rohit Sharma, Erdal Uzunlar, Vachan Kumar, Rajarshi Premjeet Chahal – Michigan State University Saha, Xinyi Yeow, Azad Naeemi, and Paul Kohl – Georgia Lars Hoff – Vestfold University College; Knut Waaler – 18. Active Cooling Analysis of the Micro Pump used in Institute of Technology; Rizwan Bashirullah – University WesternGeco AS IGBT Power Module of Florida 4. Novel Low-Volume Solder-on-Pad (SoP) Material Ling Xu, Yang Zhou, Yang Zhang, Bulong Wu, Mingxiang Chen, and Process for Flip Chip Bonding using Au Stud Xiaobing Luo, and Sheng Liu – Huazhong University of Science & Technology Bumps Friday, June 1 Session 41: Student Posters 19. Liquid Encapsulation for Monochromatic LED Kwang-Seong Choi, Ho-Eun Bae, Su-Jeong Jeon, Hyun- Emitter Packages: Enhancement of Thermal-Optical Cheol Bae, and Yong-Sung Eom – ETRI 8:30 a.m. - 10:30 a.m. Performance and Reliability 5. Design and Process Development of a Stacked Committee: Interactive Presentations Jiun Pyng You, Yu-Chou Shih, Yeong-Her Lin, Bohan Yan, and SRAM Memory Chip Module with TSV Grande Ballroom A Frank G. Shi – University of California, Irvine Interconnection 20. A Novel Wafer-Level Metal/BCB Interconnection Shenglin Ma, Xin Sun, Yunhui Zhu, Zhiyuan Zhu, Qinghu Session Co-Chairs: between Both Sides of Wafer using TSV and Its Cui, Meng Chen, Yongqiang Xiao, Jing Chen, Wengao Lu, Mark Eblen – Kyocera Microwave Performance and Yufeng Jin – Peking University; Min Miao – Peking Patrick Thompson – Texas Instruments, Inc. Jiajie Tang, Xiao Chen, Gaowei Xu, and Le Luo – Chinese University, Beijing Information Science & Technology 1. High-Efficient Optics for Different LED Packaging Academy of Sciences University Types in Forward-Lighting Application 21. An Investigation on Structure and Materials of 6. Bio-Inspired Surface Treatment on Touch Screen Fei Chen and Sheng Liu – Huazhong University of Laminated Organic Solar Cell Packaging Panels (TSPs) for Adhesion Enhancement Science and Technology; Kai Wang – Guangdong Real Xing Chen, Simin Wang, Zhang Luo, Shengzhi Zhang, Il Kim, Seung-Ho Kim, Inseong You, Haeshin Lee, and Faith Optoelectronics Inc. Zhicheng Lv, Hao Jiang, and Sheng Liu – Huazhong Kyung-Wook Paik – KAIST 2. Metamaterial Transmission Line Based University of Science & Technology 7. Low Slow-Wave Effect and Crosstalk for Low-Cost Reconfigurable X-Band Phase Shifter Design 22. Robust, Novel, and Low Cost Superhydrophobic ABF-Coated TSVs in 3D IC Interposer Nophadon Wiwatcharagoses, Kyoung Youl Park, and Nanocomposites Coating for Reliability Improvement of Microelectronics Yu-Jen Chang, Tai-Yu Zheng, Hao-Hsiang Chuang, Chuen- Premjeet Chahal – Michigan State University Yan Liu, Ziyin Lin, and Kyoung-sik Moon – Georgia Institute De Wang, Yi-Chang Lu, Yih-Peng Chiou, and Tzong-Lin 3. Phosphor Size Dependence of Lumen Efficiency of Technology; C.P. Wong – Georgia Institute of Technology, and Spatial CCT Uniformity for Typical White LED Wu – National Taiwan University; Peng-Shu Chen, Tzu- Chinese University of Hong Kong Emitters Ying Kuo, Chau-Jie Zhan, Shih-Hsien Wu, and Wei-Chung 23. ZnO Quantum Dots-Filled Encapsulant for LED Lo – ITRI Yun Shuai, Nguyen T. Tran, Jiun Pyng You, and Frank G. Shi Packaging 8. Study of Pd Mixing during Pd-Cu Wire Ball – University of California, Irvine Yan Liu, Ziyin Lin, Xueying Zhao, and Kyoung-sik Moon Formation and Impact on Wire Bond Quality 4. Assembly and Alignment of Proximity – Georgia Institute of Technology; Sehoon Yoo – Korea Flynn Carson, Jae Hak Yee, Soo San Park, and Edward Communication Enabled Multi-Chip Packages using Institute of Industrial Technology (KITECH); C.P. Wong – Fontanilla – STATS ChipPAC Elastomeric Bump Interposers Georgia Institute of Technology, Chinese University of Hong 9. Vertical Tree 3-Dimensional TSV Clock Distribution Hyung Suk Yang – Georgia Institute of Technology; Hiren Kong Network in 3D IC D. Thacker, Ivan Shubin, John E. Cunningham, and James 24. Combination of Translucent Eu:YAG Glass Ceramic Dayoung Kim, Joohee Kim, Junso Pak, and Joungho Kim G. Mitchell – Oracle with LED Chip – KAIST; Hyungdong Lee, Junho Lee, and Kunwoo Park 5. The Process and Reliability Tests of Glass-to-Glass Liang Yang, Zhicheng Lv, Mingxiang Chen, and Sheng Liu – Laser Bonding for Top-Emission OLED Device – Hynix Semiconductor Inc. Huazhong University of Science & Technology Yuneng Lai, Zunmiao Chen, Yuanhao Huang, and Jianhua 10. Design of a Liquid Bridge Heat Switch System based 25. The Role of Friction Coefficient on the Stitch Zhang – Shanghai University on the Liquid Bridge Control for the Electronics Bondability in Pd Coated Cu and Bare Cu Wire 6. 60 GHz Tapered-Helix Antenna for WPAN Bonding Cooling Applications Su-Heon Jeong, Sung-Ki Nam, and Sun-Kyu Lee – A. Rezvani, C. Nan, and M. Mayer – University of Waterloo; I. Paolo Nenzi, Francesco Tripaldi, Frank Silvio Marzano, Qin – Kulicke and Soffa, Inc. Gwang-ju Institute of Science and Technology; Wataru Fabrizio Palma, and Marco Balucani – University of 26. Novel Core-Shell Nanocomposites for RF Embedded Nakayama – Thermtech International Rome Capacitors: Processing and Characterization 11. Broad-Side Crosstalk Mitigation in Dual-Stripline 7. Resonance-Based Addressing in Laminate MEMS Warda Benhadjala, Isabelle Bord, Laurent Béchou, and Design Devices Yves Ousten – Université de Bordeaux; Ephraim Suhir Jimmy Hsu and Kai Xiao – Intel Corporation Minfeng Wang, Yang Zhang, G.P. Li, and Mark Bachman – – University of California, Santa Cruz; Matthieu Buet and 12. Chip to Wafer Direct Bonding Technologies for High University of California, Irvine Fabien Rougé – Polyrise SAS Density 3D Integration 8. A Study on the Intermetallic Growth of Fine- 27. Reliability and Microstructural Studies of Sn-Ag-Cu L. Sanchez, L. Bally, B. Montmayeul, F. Fournel, J. Pitch Cu Pillar/SnAg Solder Bump for 3D-TSV Lead-Free Solder Joints in Pulse-Heated Reflow Dafonseca, E. Augendre, L. Di Cioccio, V. Carron, and Interconnection Soldering T. Signamarcheix – CEA-LETI; R. Taibi and S. Mermoz – Yong-Sung Park, Ji-Won Shin, Yong-Won Choi, and M. Mostofizadeh, K. Kokko, and L. Frisk – Tampere University STMicroelectronics; G. Lecarpentier – SET Kyung-Wook Paik – KAIST of Technology Wednesday & Thursday Refreshment Breaks: 9:15 a.m. - 10:00 a.m. and 2:45 p.m. - 3:30 p.m. • See pages 10-17 for location. 23 Technology Corner Booth and Poster Layout Technology Corner Exhibits Wednesday, May 30, 2012 • 9:00 a.m. - Noon & 1:30 p.m. - 6:30 p.m. Thursday, May 31, 2012 • 9:00 a.m. - Noon & 1:30 p.m. - 4:00 p.m.

Interactive Presentation Sessions Wednesday, May 30, 2012 morning Interactive Presentations • 9:00 a.m. - 11:00 a.m. Wednesday, May 30, 2012 afternoon Interactive Presentations • 2:00 p.m. - 4:00 p.m. Thursday, May 31, 2012 morning Interactive Presentations • 9:00 a.m. - 11:00 a.m. Thursday, May 31, 2012 afternoon Interactive Presentations • 2:00 p.m. - 4:00 p.m.

24 Technology Corner Exhibitors

3D Glass Solutions AI TECHNOLOGY, INC. Amkor Technology, Inc. 4343 Pan American Freeway NE 70 Washington Road 1900 S. Price Road Albuquerque, NM 87107 Princeton Junction, NJ 08550 Chandler, AZ 85286 Phone: +1-866-559-8982 Phone: +1-609-799-9388 Phone: +1-480-821-5000 ext.7891 Fax: +1-866-561-0975 Fax: +1-609-799-9308 Fax: +1-480-821-8263 www.3dglassSolutions.com www.aitechnology.com www.amkor.com Contact: Roger Cook Contact: Richard Amigh Contact: Deborah Patterson Email: [email protected] Email: [email protected] Email: [email protected] Booth 206 Booth 405 Booth 311 3D Glass Solutions provides glass interposer, AI Technology is an ISO9001 certified facility and man- Amkor Technology, Inc. is one of the world’s largest Through-Glass (TGV) and complete glass micro- ufactures flexible “Stress-free” adhesives, films, pastes providers of advanced semiconductor assembly device fabrication services and products to a variety and thermal films, gels/grease. Products are available and test services. Founded in 1968, Amkor has of markets including semiconductor 2.D and 3D SIP, in syringes, jars, premixed and frozen or separated in become a strategic manufacturing partner for many BEOL, RF, MEMS, MOEMS, optoelectronics, lab- Part A and Part B for ambient storage. Film based of the world’s leading semiconductor companies on-a-chip, microfluidics and a variety of others. Our adhesives with tack for ease of use can be shipped and electronics OEMs, providing a broad array of services include design, process development, full in sheets or in performs. Adhesives are electrically advanced package design, assembly and test solutions. prototyping and fabrication services for micro-devices conductive or insulating and applicable for die-attach, Amkor’s operational base encompasses more than 5 in glass, fused silica and ceramic .Capabilities include lid sealing, BGA, multichip modules, and wafer lamina- million square feet of manufacturing facilities, product photo-lithography, thin films, etch, metrology and full tion. Solder-Sub™ and Chip-Coupler™ applications development centers, and sales & support offices in 3D surface structuring. Our patent pending photo- available. Asia, Europe and the United States. Amkor offers structurable APEX™ GLASS enables us to produce a suite of services, including electroplated wafer Our Insulating Metal Substrate uses our proprietary these 3D structured parts in a high volume batch bumping, probe, assembly and final test. Amkor is a flexible thermal dielectric insulating layer resulting in process. leader in advanced copper pillar bump and packaging stress and warp-free thermal copper-clad laminates. technologies which enables next generation flip chip We also have a variety of Thermal Insulating Materials 3D Systems Packaging Research Center (PRC) interconnect. which will improve performance. Both of these prod- Georgia Institute of Technology ucts have shown improvements in LED performance. 813 Ferst Drive, NW ANSYS, Inc Atlanta, GA 30332-0560 275 Technology Drive ALLVIA, Inc. Phone: +1-404-894-9097 Canonsburg, PA 15317 657 N. Pastoria Ave. Fax: +1-404-894-3842 Phone: +1-866-267-9724 Sunnyvale, CA 94085 www.prc.gatech.edu www.ansys.com Phone: +1-408- 212-3200 Contacts: Dr. Rao Tummala, Dr. Venky Booth 402 Fax: +1-408-720-3334 Sundaram ANSYS provides the engineering and design process www.allvia.com Email: [email protected] insight to help you be first to market with products Contact: Phil Marcoux Booth 411 that realize their promise and revolutionize your Email: [email protected] The 3D Systems Packaging Research Center (PRC) business. We develop, market and support engineering Booth 600 at the Georgia Institute of Technology is an Industry- simulation software used to predict how products will ALLVIA, Inc. provides Silicon Interposer and Through- Centric Global Academic Center dedicated to behave and how manufacturing processes will operate Silicon Via (TSV) foundry services to Semiconductor, leading-edge research and education in the System-on- in real-world environments. We offer the most Optoelectronics and MEMS industries meeting the a-Package (SOP) concept to enable highly miniaturized, comprehensive suite of simulation solvers in the world demands of advanced vertical interconnects, 2.5D, multi- to mega-functional systems in a single package. so that we can confidently predict your product’s 3D and System-in-Package (SiP) solutions. ALLVIA, Led by Prof. Rao Tummala, the PRC has developed a success. a leader in TSV development, provides design unique and integrated approach to research, education and processing for front side (filled) and backside and industry collaborations using its comprehensive ASE Group (conformal plated) through silicon vias. With its full 300 mm SOP panel facilities, involving cross-disciplinary 1255 E. Arques Ave. line of in-house processing equipment, ALLVIA offers research, academic faculty and students. The Center’s Sunnyvale, CA 94085 services for prototyping as well as volume production research encompasses a full spectrum of the most Phone: +1-408.636.9500 runs. advanced 3D systems packaging technologies including; Fax: +1-408.636.9485 design and test; ultra-thin and ultra-high density www.aseglobal.com Alpha Novatech, Inc. organic packages; glass and silicon interposers ; Contact: Patricia MacLeod 473 Sapena Ct. #12 thin film passives for power and signal conditioning Email: [email protected] Santa Clara, CA 95054 applications; all enabled by leading advances in design, Booth 613 Phone: +1-408-567-8082 materials and processes, interconnections, assembly, ASE Group is the world’s largest provider of Fax: +1-408-567-8053 reliability and thermal management. The PRC offers independent semiconductor manufacturing services www.alphanovatech.com a variety of industry partnerships that include one- in assembly and test. With over twelve facilities Contact: Glenn Summerfield on-one contracts, and an extensive array of consortia worldwide, ASE is meeting the industry’s evolving Email: [email protected] research programs involving OEMs, IDMs, foundries, demand for critical IC features such as smaller Booth 208 OSATs, substrate and module makers, materials footprint, lower power, and higher performance. Alpha Novatech, Inc. is your partner for thermal and tool suppliers, thus creating a global ecosystem ASE’s broad portfolio of technology and solutions solutions. We offer a wide variety of standard heat for advanced packaging technology innovations, encompass IC test program design, front-end sinks and accessories. Our product line includes commercialization and, global connectivity. Benefits engineering test, wafer probe, wafer bump, natural convection, forced convection, and active heat include intellectual property rights, technology substrate design and supply, wafer level package, sinks. We also offer various attachment methods transfer, access to students for recruiting, one-on- flip chip, system-in-package, final test and electronic and hardware for almost any application. In addition, one company-to-faculty relationships, state-of-the-art manufacturing services. The Group generated sales we can offer free heat sink thermal simulations. R&D facilities, advanced technology prototypes (new), revenues of $4.0 billion in 2010 and employs over Standard or custom heat sinks in prototype to and more. For more information about the consortia 34,000 people worldwide. For more information on production quantities. Quick and easy customization and membership programs, research areas or other the ASE portfolio including our proven copper wire without NRE fees, while featuring short lead times. information, we invite you to visit our website at bond capabilities and our advances in 3D & TSV Standard parts are carried in stock. Lead time for www.prc.gatech.edu. technologies, please visit www.aseglobal.com. custom parts of 1-2 weeks is possible for initial quantities.

25 Bergquist Company, The CoreTech System (Moldex3D) Co., Ltd. CPS Technologies Corporation 18930 West 78th Street Moldex3D North America Sales & Support 111 South Worcester Street Chanhassen, MN 55317 Center Norton, MA 02766 Phone: +1-952-835-2322 Farmington Hills Corporate Center I Phone: +1-508-222-0614 Fax: +1-952-835-0430 21800 Haggerty Road, Suite 109 Fax: +1-508-222-0220 www.bergquistcompany.com Northville, MI, 48167 www.alsic.com Email: [email protected] Phone: +1-248-946-4570 Contact: Bo Sullivan, Senior Account Manager Booth 500 Fax: +1-248-928-2270 Email: [email protected] The Bergquist Company is the industry leader in the CoreTech System (Moldex3D) Co., Ltd. Booth 113 design and manufacturing of high performance thermal Headquarters CPS Technologies Corporation is the worldwide lead- management materials used to cool electronic compo- Tai Yuen Hi-Tech Industrial Park er in the design and high-volume production of AlSiC nents. Bergquist supplies the world with some of the 8F-2, No.32, Taiyuan St., Chupei City (aluminum silicon carbide) for high thermal conductiv- best-known brands in the business: Sil-Pad® thermally- Hsinchu County 302, Taiwan ity and device compatible thermal expansion. AlSiC conductive interface materials, Gap Pad® electrically Phone: +886-3-560-0199 thermal management components manufactured by insulating and non-insulating gap fillers, Hi-Flow® phase Fax: +886-3-560-0198 CPS include hermetic electronic packaging, heat sinks, change grease replacement materials, Bond-Ply® ther- www.moldex3d.com microprocessor flip chip heat spreader lids, thermal mally-conductive adhesive tapes, and Thermal Clad® Contact: Kenny Lu substrates, IGBT base plates for motor controllers, insulated metal substrates for surface-mount applica- Email: [email protected] cooler baseplates, Pin Fin baseplates for Hybrid Elec- tions. Bergquist also designs and manufactures 5-Wire Booth 209 tric Vehicles (HEV) and System in Package (SiP) Heat resistive touch screens, and HeatSeal® membrane CoreTech System (Moldex3D) Co., Ltd. has been Spreader Lids that address multiple IC’s on a PCB with switches. The company’s patented HeatSeal process providing the professional CAE analysis solution for a single lid design. thermally bonds switch layers together, creating a seal the plastic injection molding industry since 1995. impervious to moisture, temperature extremes and Moldex3D Chip Encapsulation provides innovative CST of America, Inc. cleaning chemicals. HeatSeal also provides superior and complete tools for users to gain the sights of 492 Old Connecticut Path, Suite 505 protection against ESD events that can ruin ordinary plastic encapsulation processes. The filling and curing Framingham, MA 01701 membrane switches that are bonded with pressure processes of the thermoset resins, along with all the Phone: +1-508-665-4400 sensitive adhesive (PSA). critical characteristics including warpage, wire sweep Fax: +1-508-665-4401 and paddle shift can all be visualized by the software. www.cst.com Chip Scale Review From Moldex3D Chip Encapsulation, you can benefit Contact: Debra Gasser PO Box 9522 on: Direct Phone: +1-508-665-4412 San Jose, CA 95157-0522 Email: [email protected] 1. Package and mold design validation and optimization Phone: +1-408-429-8585 Booth 204 to reduce manufacturing cost and design cycle time. Fax: +1-408-429-8605 CST of America, Inc. is the leading supplier of 3D www.ChipScaleReview.com 2. Simulation-driven-design of complex and innovative electromagnetic simulation tools in North America. Contact: Kim Newman, Publisher IC packages. CST’s products aid in the microwave/RF and high Email: [email protected] speed design of many consumer, industrial, aerospace CoreTech is committed to provide the advanced Booth 112 and research level components and systems including technologies and solutions for industrial demands; Chip Scale Review is the leading international test, interconnects, packages, materials, wireless devices, CoreTech has extended the worldwide sales and assembly, and packaging magazine for WLP, and vehicles. The software has an excellent 3D service network to provide local, immediate and TSVs, 2D/3D device packaging and high-density interface with robust imports from all the major CAD professional service. interconnection of microelectronics, ICs, MEMS, RF/ and EDA vendors. Huge cost savings are possible, by wireless, optoelectronic and other wafer-fabricated reducing or eliminating the hardware prototype stage CORWIL Technology Corporation devices for the 21st century. Chip Scale Review is of a design. Key results can be analyzed and optimized 1635 McCarthy Blvd. published six times in print and digital and publishes based on user goals. Milpitas, CA 95035 in-depth packaging related editorial with exclusive state Phone: +1-408-321-6404 of the art technical editorial, news, and commentary DISCO Hi-Tec America, Inc. Fax: +1-408-321-6407 on critical and topical industry matters. CSR 3270 Scott Boulevard www.CORWIL.com co-sponsors the visionary 9th annual International Santa Clara, CA 95054-3011 Contact: Rosie Medina Wafer-Level Packaging Conference (IWLPC) with Phone: +1-408-987-3776 Email: [email protected] SMTA being held Nov 5-8, 2012 in San Jose, California Fax: +1-408-987-3785 Booth 101 (www.iwlpc.com). Renew or sign up for a one year www.discousa.com CORWIL was founded in 1990 to provide high subscription online at www.ChipScaleReview.com Contact: Devin Martin quality and responsive IC assembly and test services Email: [email protected] to the semiconductor, OEM electronics, military CoolClouds, Inc. Booth 207 and aerospace, and medical industries. CORWIL is a 75 5th St., Suite 200 DISCO Corporation is the world leader in cutting, diversified provider of various services, including wafer Atlanta, GA 30308 grinding, and polishing technology. With more than thinning and dicing, optical/manual inspection, and full Phone: +1-770-670-1345 40 years of experience in precision processing a assembly (wirebond & flip chip) and testing of IC’s in coolclouds.net wide variety of materials, DISCO has amassed a QFN, ceramic, and BGA packages, as well as complex Contact: Ven Holalkere vast knowledge base in these core competencies. modules. CORWIL is a high volume subcontractor Email: [email protected] Along with providing related equipment and tooling, of wafer dicing, visual inspection, and die pick & place Pavillion tabletop DISCO offers a variety of services including process services with experience in exotic wafer materials CoolClouds specializes in modular design and optimization, joint development initiatives, and such as sapphire, gallium nitride, gallium arsenide, development of high performance thermal consultative services. Additionally, next generation indium phosphate, and silicon germanium. CORWIL management products, based on fluidic and hybrid product prototyping and small run product output is is certified QML (Q & V), ISO 9001:2000 & ITAR cooling concepts. The company focuses on solutions available at the Development Center in Santa Clara, registered. for chips, and equipment that ranges from personal CA. For more information, please contact DISCO at computers to data centers. Founders of the company (408) 987-3776. have worked on research projects with several companies, including Intel, IBM, Fujitsu, DegreeC and National Semiconductor.

26 Dow Corning Corporation Enzotechnology silicon-on-insulator (SOI), compound semiconductor 2200 W. Salzburg Road 14776 Yorba Ct. and silicon-based power-device solutions. Midland, MI 48686 Chino, CA 91710 Founded in 1980, EVG is headquartered in St. Phone: +1-989-496-6647 Phone: +1-909-993-5140 Florian, Austria, and operates via a global customer Fax: +1-989-496-6824 Fax: +1-909-993-5141 support network, with subsidiaries in Tempe, AZ.; www.dowcorning.com/electronics www.enzotech.com Albany, NY; Yokohama and Fukuoka, Japan; Seoul, Contact: Melanie Oliver www.enzotechnology.com Korea and Chung-Li, Taiwan. The company’s unique Email: [email protected] Contact: Richard Yu Triple i-approach (Invent - Innovate - Implement) is Booth 106 Email: [email protected] supported by a vertical integration, allowing EVG to Dow Corning Electronics, headquartered in Booth 100 respond quickly to new technology developments, Midland, MI, is a leading supplier of silicon-based Founded in 1982, Enzotech has been striving to pro- apply the technology to manufacturing challenges and materials for wire-bond, flip chip and advanced vide cooling solutions for a variety of servers that expedite device manufacturing in high volume. packaging applications. In addition to our current require high efficiency and 24-hour power stability. product line of encapsulants, die attach adhesives, With the on-going innovation and challenges in the ficonTEC (USA) Corporation lid seal adhesives, and thermal interface materials, computer industry, Enzotech has become a leading 25 Calle Canela Dow Corning is investing in the development of new innovator in designing unique material forming technol- San Clemente, CA 92673 materials technology to meet the challenging needs ogy. Along with its OEM experiences with companies Phone: +1-949-388-5800 of emerging applications. Dow Corning leads by such as AMD and Intel, we also have the reputation as Fax: +1-949-388-1489 delivering innovative products, application technologies, being one of the world’s most advanced high-perfor- www.ficontec.com and reliable global supply, making it easy to do business mance heat sink manufacturer. Enzotech is committed Contact: Soon Jang and win in your markets. to provide customers with world-class high quality Email: [email protected] products that are delivered in a cost effective manner, Booth 108 Dow Electronic Materials resulting in a win-win situation for all. ficonTEC is a global, premier supplier of micron- and 455 Forest Street submicron-precision automation solution systems for Marlborough, MA 01752 Esterline Connection Technologies device assembly and testing applications. Given its Phone: +1-508-481-5970 SOURIAU PA&E unique capabilities, ficonTEC has become a strategic www.dow.com 434 Olds Station Rd. manufacturing partner and a provider of various Contact: Bob Forman Wenatchee, WA automated assembly and test solutions for many of Direct Phone: +1-425-785-9817 Phone: +1-509-667-5480 the world’s leading device manufacturers and OEMs. Email: [email protected] Fax: +1-509-663-5039 Such applications range from semi-automated and Booth 501 www.pacaero.com automated submicron-precision eutectic and epoxy die Dow Electronic Materials, a global supplier of mate- www.esterline.com bonding and LDB soldering, six (6) axis micro-optics rials and technologies to the electronics industry, Booth 203 alignment and assembly, micro-OE and fiber-optic brings innovative leadership to the semiconductor, SOURIAU PA&E specializes in the design and device assembly, among many. The solution is uniquely interconnect, finishing, display, photovoltaic, LED and manufacture of hermetic DC/RF/fiber optic provided through a collaborative engineering effort optics markets. From advanced technology centers connectors, electronic packaging and EMI filters for with ficonTEC from the development to production worldwide, teams of talented Dow research scientists use in harsh-environment applications where absolute phases, captured in a semi-customized system product. and application experts work closely with customers, reliability is a must. We employ unique materials Customers’ system solutions are supported by providing solutions, products and technical service and processes to help our aerospace and defense ficonTEC’s acclaimed worldwide Customer Service necessary for next-generation electronics. Dow’s port- customers address a range of technical challenges and Support department. folio includes metallization and lithography materials including: size/weight reduction, electrical performance, for advanced semiconductor packaging applications, thermal conductivity and more. We offer a range of Finetech such as bumping, pillars, redistribution, passivation and manufacturing capabilities - machining, plating, vacuum 8380 S. Kyrene Road, Suite 110 UBM used for the latest WLCSP, flip chip, SiP, and 3D brazing, laser welding, and more – at a single location. Tempe, AZ 85284 chip packages. This integrated manufacturing approach can reduce Phone: +1-480-893-1630 complexity and risk on your next project. We have Fax: +1-480-893-1632 DuPont Wafer Level Packaging Solutions a talented staff of application engineers with deep www.finetechusa.com 14 T.W. Alexander Drive experience in developing and manufacturing custom Contact: Neil O’Brien Research Triangle Park, NC 27709 solutions for extreme environments who are ready to Email: [email protected] Phone: +1-510-784-7514 assist you with your next project. Booth 612 www.wlpsolutions.dupont.com Finetech offers precision bonders for flip chip, Chip Contact: Karen D. Willwerth EV Group, Inc. to Wafer (300mm), laser bars & diodes, photonics Email: [email protected] 7700 South River Parkway packaging, VCSELs, MEMs, and sensors. Thermo-com- Booths 406 & 408 Tempe, AZ 85284 pression, thermo-sonic, eutectic, epoxy, ACF & Indium DuPont Wafer Level Packaging Solutions will highlight Phone: +1-480-305-2400 bonding. Process flexibility within one bonder is ideal materials and process technologies for WLP and Fax: +1-480-305 - 2401 for R&D or prototyping. Manual and fully-automated 3D/TSV applications, including dry film photoresists, www.evgroup.com models are available with placement accuracy down to photoresist removers and redistribution dielectrics Contact: Carl Mann +/- 0.5 micron. Our customers benefit from industry- from HD Microsystems. DuPont is also showcasing Email: [email protected] leading machine specifications and process know-how new temporary adhesives, permanent adhesives, and Booth 603 built over years of application experience. surface preparation materials for wafer bonding. EV Group (EVG) is a world leader in wafer- processing solutions for semiconductor, MEMS ElectronicsCooling and nanotechnology applications. Through close ITEM Publications collaboration with its global customers, the company 1000 Germantown Pike, Suite F2 implements its flexible manufacturing model to develop Plymouth Meeting, PA 19462 reliable, high-quality, low-cost-of-ownership systems Phone: +1-484-688-0300 that are easily integrated into customers’ fab lines. Fax: +1-484-688-0303 Key products include wafer bonding, lithography/ www.electronics-cooling.com nanoimprint lithography (NIL) and metrology Contact: Paul Salotto, Publisher equipment, as well as photoresist coaters, cleaners and Email: [email protected] inspection systems. Booth 109 In addition to its dominant share of the market for ElectronicsCooling is dedicated to engineers responsible wafer bonders, EVG holds a leading position in NIL for thermal management of electronics. The magazine and lithography for advanced packaging and MEMS. is a source of useful information directly applicable Along these lines, the company co-founded the EMC- to real thermal design problems in today’s electronic 3D consortium in 2006 to create and help drive equipment. We are the only publication solely dedi- implementation of a cost-effective through-silicon-via cated to the specific needs of the thermal community. (TSV) process for chip packaging and MEMS/sensors. Stop by our booth during the show and pick up the Other target semiconductor-related markets include latest issue of ElectronicsCooling.

27 Fraunhofer Center for Applied Microstructure FRT of America High Connection Density, Inc. (HCD) Diagnostics CAM 1101 S. Winchester Boulevard, L-240 820A Kifer Road Heideallee 19 San Jose, CA 95128 Sunnyvale, CA 94086 06120 Halle (Saale) Phone: +1-408-261-2632 Phone: +1-408-743-9700 Germany Fax: +1-408-261-1173 Fax: +1-408-743-9701 Phone: +49 (0) 345- 55 89 130 www.frtofamerica.com www.hcdcorp.com Fax: +49 (0) 345- 55 89 101 Contact: Paul Flynn Contact: Charlie Stevenson www.iwm.fraunhofer.de Email: [email protected] Email: [email protected] Contact: Prof. Dr. Matthias Petzold Booth 102 Booth 409 Email: [email protected] FRT is recognized as a valued partner for non-contact, High Connection Density, Inc. (HCD) is a premier Booth 607 optical metrology systems. FRT of America serves you supplier of board-to-board, flex-to-board, and Fraunhofer CAM is a leading service provider of fail- by providing high-quality automated measuring tools package-to-board solderless connectors for BGA, ure diagnostics and material assessment for industry that fulfill your research, inspection and process verifi- LGA and socket applications. HCD’s SuperButton® including semiconductor technologies, microelectronic cation needs. Delivering increased manufacturing yield, and SuperSpring® technology-based products are components, microsystems and nanostructured mate- enhanced productivity, improved quality and product the perfect solution for projects requiring high rials. Within Fraunhofer CAM, we consider the entire performance, because that’s what it’s about at the end frequency, high current and low resistance. Designed work flow from non-destructive defect localization of the day. The MicroProf TTV measures wafer thick- for manufacturability, HCD offers its innovative over high precision target preparation to cutting edge ness, TTV, bow and warp for full thickness, thinned proprietary technology at competitive prices. nanoanalytics supplemented by micro-mechanical test- and bonded wafers. The WLI PI is for measuring high ing, finite element modeling and numerical simulation. aspect ratio TSV and bumped wafers. The CWL IR is Huntsman Advanced Materials Our research results are aiming at supporting our for measuring silicon thickness on bonded wafers. The 10003 Woodloch Forest Dr. cooperation partners introducing innovative materials MicroSpy Topo DT is a high resolution microscope The Woodlands, TX 77380 and new technologies, improving manufacturing pro- with confocal and interferometric measuring modes. Phone: +1-888-564-9318 cess steps, securing reliable field use of components, Fax: +1-281-719-4032 analyzing field returns, and consequently optimizing Fujipoly America Corporation www.huntsman.com/advanced_materials manufacturing yield, product quality, reliability, and 900 Milik Street Contact: Mangesh Rajadhyaksha cost efficiency. Carteret, NJ 07008 Email: [email protected] Phone: +1-732-969-0100 Booth 610 Due to our close collaboration with leading microelec- Fax: +1-732-969-3311 Huntsman Advanced Materials is a leading global tronics manufacturers, within Fraunhofer CAM we are www.fujipoly.com supplier of synthetic and formulated polymer systems also able to support test and diagnostics equipment Contact: Frank Hobler for customers requiring high performance materials suppliers in exploring and evaluating upcoming mar- Email: [email protected] which outperform the properties, functionality and kets, new customer segments and future application Booth 608 durability of traditional materials. In the electronics fields. We provide our partners innovative hard- and Fujipoly is a globally positioned manufacturing company market, we provide advanced organic protective software components, problem-adapted analysis work specializing in electronic packaging components such solutions to build, structure and assemble printed flows and industry-compatible application strategies. as Zebra® Elastomeric Connectors, Sarcon® Thermal circuit boards and to encapsulate, insulate and bond Progress in signal evaluation and hardware develop- Interface Materials, as well as complex silicone rubber electrical and electronic components. Our brands, ment is used to improve defect detection and material extrusions and co-extrusions. With nine locations in such as Araldite® adhesive and laminating systems, analysis by lock-in thermography, scanning acoustic North America, Europe, and Asia, Fujipoly’s global net- Probimer® solder masks and Euremelt® hot melt microscopy or electron microscopy. work is designed to supply products to our customers adhesives, are pioneers in the industry, serving quickly at the local level. customers for more than 50 years. Our customers Fraunhofer Institute for Reliability and Microin- benefit from sound technical expertise and products tegration IZM Heraeus Materials Technology GmbH & Co. that are tailor-made to meet their requirements. Gustav-Meyer-Allee 25 Kg 13355 Berlin Heraeusstr 12-14 IBM Microelectronics - Packaging Development Germany Hanau 63459 2070 Route 52 Phone: +49 (0) 30-464-03-100 Germany Hopewell Jct. NY 12533 Fax: +49 (0) 30-464 03-111 Phone: +496181755465 Phone: +1-845-892-0660 www.izm.fraunhofer.de www.heraeus-contactmaterials.com Fax: +1-845-892-6256 Contact: Georg Weigelt Contact: Julia Hoefling www-03.ibm.com/technology/ Email: [email protected] Email: [email protected] Contact: Barry Hochlowski Booth 309 Booth 304 Email: [email protected] Invisible – but indispensable – nowadays nothing Worldwide Suppliers of Material for the Electronics Booth 110 works without highly integrated microelectronics and Assembly Market – Heraeus supplies solder paste, IBM Microelectronics - a world leader in microsystem technology. Reliable and cost-effective fluxes, soft solder wire, solder spheres, thermally and semiconductor and packaging technology - has assembly and interconnection technologies are the electrically conductive adhesives and variety of other formed a Packaging Joint Development Ecosystem foundation of integrating these in products. Fraunhofer adhesives to the package and component assembly with leading assembly, materials, and equipment IZM, a worldwide leader in the development and markets. The Contact Materials Division offers a wide providers. This ecosystem leverages IBM’s research reliability analysis of electronic packaging technologies, range of innovative products to address your assembly and development resources with synergistic skills from provides its customers with tailor-made system material requirements. From the world’s newest high partner companies to solve shared challenges and integration technologies on wafer, chip and board Pb solder replacement to our economical and reliable drive industry leadership in semiconductor flip chip level. Our research also ensures that electronic family of “green” solders, fluxes and adhesives that packaging; enhancements in technology development systems are more reliable, so that we can accurately meet cutting edge, 21st century requirements in the (design, performance and reliability); improvements predict life-cycle. assembly materials arena – Heraeus is your answer. in time to market; and definition of new industry standards. IBM’s semiconductor packaging technologies raise the bar on product performance, power efficiency, integration and reliability. Our products are becoming increasingly intelligent, interconnected and instrumented. Advances in semiconductor device performance and the transition to environmentally friendly interconnects drive complexity in the design and implementation of appropriate packaging solutions. Increased use of multi-core processors that drive larger die size, greater I/O counts and enhanced cooling requirements have made the co-development of silicon and packaging solutions essential to the successful implementation of both. It’s time to differentiate your semiconductor packaging technology….Smarter technology for a Smarter Planet. 28 Industrial Technology Research Institute Interconnect Systems, Inc. JSR Micro, Inc. Bldg. 17, No. 195, Sec. 4 Chung Hsing Rd. 759 Flynn Road 1280 N. Mathilda Ave. Chutung, Hsinchu, Taiwan Camarillo, CA 93012 Sunnyvale, CA 94089 Phone: +886 3 5917024 Phone: +1-805-482-2870 Phone: +1-408-543-8800 Fax: +886 3 5917193 Fax: +1-805-482-8470 Fax: +1-408-543-8964 www.itri.org.tw www.isipkg.com www.jsrmicro.com/ Contact: Dr. Robert Lo Email: [email protected] Contact: James Chung Email: [email protected] Booth 312 Email: [email protected] Booth 502 ISI specializes in microelectronic Modules, Custom Booths 507 & 509 Industrial Technology Research Institute (ITRI), found- Packaging and Interconnect solutions including High JSR’s unique THB series of negative tone resists ed in 1973, is a non-profit organization conducting in Performance Computing (HPC) Modules, 3D Over- address the needs of metal plating and bumping applied research and technological services. Electronics Molded Modules, High Density 3D Memory Packaging processes. Excellent plating tolerance and ease of and Optoelectronics Research Laboratories (EOL) is and FPGA Systems design. ISI holds 29 patents for stripping allow for fast processing with excellent one of the core labs , devoting to advanced researches products and designs. Our broad set of capabilities exposure throughput and superior process margins. in semiconductor technologies and optoelectronics includes high density PCB Design, fine pitch SMT, Flip THB cross-links on exposure and is developable in developments. Chip and Wirebond Assembly, and design-in Packaging. standard TMAH yielding high aspect ratio profiles We have unique Module Interconnect solutions includ- for film thicknesses from 5 to 100um. JSR’s WPR EOL has played a key role in Taiwan’s prominent elec- ing BGA, Leadframe, PGA and Micro-PGA. Our HiLo is a thick photosensitive dielectric that is ideal tronic and optoelectronic industries by staying tuned Interconnect System is used for high performance for redistribution layers, stress buffer layers and with global trends of technology. EOL has successfully BGA Socketing and Board-to-Board Interconnect. passivation. Available in positive and negative tone, empowered domestic industries in further enhancing Products include IC Packages, Cost Reduction Mod- WPR is patternable and aqueous developable and their competitiveness in manufacturing technologies ules, IC Footprint Conversion Adapters, Flex Circuit provides for low residual stress and low cure and product developments. Assemblies, and Bare Die to PCB or Flex. ISI’s multiple temperature. The core competences of EOL are briefly introduced capabilities and fast-track Process Development pro- below: vide a superior level of integration for System Design- Kyocera America • Nano-electronics Technology ers at an unprecedented speed-to-market. 1401 Route 52, Suite 203 • Flexible electronics Technology Fishkill, NY 12524 • Bio-photonic system Technology Intermark (USA), Inc. Phone: +1-845-896-0480 • 3D Imaging Technology 1310 Tully Rd., Ste#117 Contact: Tony Soldano, National Sales • Optoelectronic Semiconductor Technology San Jose, CA 95122 Manager – Organic Products • 3DIC Packaging Technology. Phone: +1-408-971-2055 Email: [email protected] • TSV Plating Fax: +1-408-971-6033 Booth 404 • Ultra thin wafer handling www.intermark-usa.com Kyocera America, Inc. (KAI) offers an extensive • Stacked Die Assembly Email: [email protected] array of semiconductor packages and high frequency • Electrical & Thermal Design Pavillion tabletop complex modules including mmW, RF, T/R modules, Intermark USA is your EMI, thermal, and vibration BGAs, SiPs, and High Power GaN packages in a Insidix one-stop shop. Difficulty passing FCC’s EMI standards, variety of ceramic and organic material sets. KAI has 24 rue du Drac application too hot to handle, or need to protect state-of-the-art electrical design, modeling / simulation Seyssins application from shock or rattle Intermark has the capability in-house to maximize package and circuit France 38 180 solution. Intermark offers solutions to issues that performance in your application. Our Assembly Phone: +33 (0)4 38 12 42 80 hinder applications from hitting the market. Intermark’s Technology Division accepts prototype to medium Fax: +33 (0)4 38 12 03 22 EMI absorbers, ferrite solution, EMI shielding tapes, volume production orders for flip chip, wirebond, www.insidix.com gaskets, cable shielding jackets, EMI window shielding, wafer dicing / bumping, vacuum soldering, test and Contact: Joe Thomas and grounding material will correct most EMI emission burn-in. Email: [email protected] or immunity issues coming from PCB level, from cable, Booth 505 and enclosure. Intermark’s wide range of Silicone Mini-Systems, Inc. (MSI) TDM (Topography and Deformation Measurement) is based or silicone free thermal pads, thermal and 20 David Road a patented INSIDIX technology that helps the develop- EMI dual function sheets, thermal tapes, or thermal North Attleboro, MA 02760 ment engineer increase the reliability of his products, spreaders will correct most thermal management Phone: +1-508-695-0203 from simple components to highly complex packaging, issues within an application. Intermark’s selection of Fax: +1-508-695-6076 and allows the failure analysis engineer to understand multiple grade GEL sheets and bushing will correct www.Mini-SystemsInc.com more accurately the root causes of failures observed most vibration, noise, or shock solution needed. With Contact: Craig Tourgee in operations. The TDM operating system combines requirement standards getting tighter Intermark’s wide Email: [email protected] a powerful, internally developed heating/cooling range of materials will provide a solution for you to get Booth 407 sequence with a sophisticated optical set-up for 3D your application into the market. For over 40 years MSI has been delivering superior topography analysis/warpage measurement under quality products. Absolute tolerances starting at 0.01% thermal stress of all kinds of materials, components Invensas and TCRs at ±2ppm/°C. Case Sizes start at 0101. and sub-systems. TDM can impose the same thermal 2702 Orchard Parkway Standard deliveries start in just 2 WEEKS! MSIs manu- profiles and cycles on the devices that they will actually San Jose, CA 95134 factured products consist of precision: experience during the production process and dur- Phone: +1-408-324-5100 • Thin/Thick film Chip Resistors ing normal use. Throughout the thermal cycle, TDM Fax: +1-408-324-5101 • QPL Resistors to MIL-PRF-55342 measures the 3D deformation and warpage related to www.invensas.com • MOS Chip Capacitors the imposed thermal stress, thus revealing faults that Contact: Phil Damberg • Chip Networks would likely occur during normal production and use. Email: [email protected] • Chip Attenuators Booth 107 • QPL Jumpers to MIL-PRF-32159/Mounting Pads Invensas was created in 2011 with one mission: to • Hermetic Packages enable tomorrow’s semiconductor technologies • Three divisions located in MA. through inventive solutions today. We do this by Applications include Medical implantables, Military, inventing, productizing and acquiring intellectual Aerospace, Microwave/RF and Telecommunications property (IP). Collaborative interdisciplinary teams of technologists create novel products and find solutions to critical industry roadmap problems, or “choke-points”. Highly experienced engineers and PhD technologists build and debug products on front- end and back-end semiconductor production lines to perfect and qualify products for market. Skilled experts and industry veterans mine, analyze, acquire and aggregate patents into valuable portfolios to provide broader and more complete solutions for our customers.

29 MI-Seojin,Inc. NAGASE & CO., LTD. and Nagase ChemteX CO. Newport Corp. B-210 SK Twin Tower 5-1, Nihonbashi-Kobunacho, Chuo-ku, 101 Billerica Ave. 345-9 Gasan-dong, Geumcheon-gu Tokyo, 103-8355 Japan N. Billierica, MA 01862 Seoul 153-773, Korea Phone: +81-3-3665-3300 Phone: +1-978-667-9449 Phone: +82-2-915-0390 Fax: +81-3-3665-3950 www.newport.com Fax: +82-2-6085-0770 www.nagase.co.jp/english/index Contact: Dan Crowley www.mett-innovation.com www.nagasechemtex.co.jp/english/index Email: [email protected] Contact: Seokyong Choi Contact: Nobuo Ogura Booth 611 Email: [email protected] Email: [email protected] Newport is a leading supplier of high precision Booth 210 dispense and assembly equipment for the Booth 604 Nagase ChemteX is a leading company for semicon- MI-Seojin has exclusively patented technologies on ductor encapsulant of epoxy resin. Our line-up prod- semiconductor and microelectronics industry offering eco-friendly TED based cooling modules and we are ucts and applications are as follow, Non-Conductive systems for the manufacture of Microwave, Optical, exploring high efficient LED business on the basis of Paste(NCP) for Fine pitch FC-PKG, Underfill for MCM’s and MEM’s devices. With over two decades of accumulated know-how on cooling solution area. We Pb-free, Liquid Molding Compound(LMC) for FO- advanced packaging application experience, Newport provide TED(Thermoelectric Device), SCHM-TED PKG like e-WLB and Wafer Process Encapsulated products support multiple interconnect technologies, (Car Seat Heating and Cooling Module), TED Cooling Film(WPEF) for 3D PKG. We can developing for the including epoxy die bonding, eutectic attach and flip Module, TED Car air-conditioning system, Heat sink, package of Ultra Low K, Cu Post and 3D(CoW, TSV chip. The ultra-precision Newport MRSI-M3 with 3 Heat pipe, TIM, Prepare for cooling solution and and TMV). micron accuracy, MRSI-M5 with 5 micron accuracy Projection LED Package, High Efficiency LED Lamp for and MRSI-605 Assembly Work Cells specialize in thin new LED business. Our strength is that we can design NAMICS Technologies, Inc. die handling and 3D packaging and the Newport MRSI- and make products as for your special demands. We 2055 Gateway Place, Suite 480 175Ag Epoxy Dispenser is the leader for high precision are ready to cooperate with your special development San Jose, CA 95110 conductive epoxy dispensing including 125 micron dots project. Phone: +1-408-516-4611 Fax: +1-408-516-4617 Nikon Metrology, Inc. MJS Designs, Inc. www.namics.co.jp 12701 Grand River Avenue Contact: Brian Schmaltz 4130 E. Wood St., Ste. 100 Brighton, MI 48116 Email: [email protected] Phone: +1-810-220-4360 Phoenix, AZ 85040 Booth 300 Phone: +1-602-437-5068 NAMICS CORPORATION is a leading source for Fax: +1-810-220-4300 Fax: +1-800-445-9442 underfills, encapsulants, adhesives, and insulating www.nikonmetrology.com www.mjsdesigns.com and conductive materials used by producers of Contact: Cali Schwartzly Contact: Elizabeth Gale semiconductor devices, passive components and Email: [email protected] Email: [email protected] solar cells. NAMICS subsidiary, DIEMAT, Inc. Booth 202 Booth 605 located in Byfield, MA, specializes in the development Nikon Metrology offers the most complete metrology Electronics Solutions on a Fast Track of innovative thermally conductive adhesives and product portfolio, including X-ray and Computed For design, engineering, assembly or testing of printed sealing glasses. Headquartered in Niigata, Japan with Tomography inspection systems and state-of-the-art circuit boards, cables, sub-assemblies, box-builds, and subsidiaries in the USA, Europe, Singapore, Korea and vision measuring instruments featuring optical and system builds—for quantity 1 to 2,000–we have quick- China, NAMICS serves its worldwide customers with mechanical 3D metrology solutions. These innovative turn turnkey perfected for outsourcing needs. Since enabling products for leading edge applications. metrology solutions respond to the advanced 1976, as an electronics manufacturer services (EMS) inspection requirements of manufacturers active in provider for many Fortune 500 companies, some have NANIUM S.A. aerospace, electronics, automotive, medical, consumer given us awards for outstanding results on their behalf. Avenida 1º de Maio 801 and other industries. On-site, sophisticated PCB diagnostic equipment is 4485-629 Vila do Conde Portugal available, including flying probe, 3-D X-ray, and bound- Phone: +351 252 24 6000 ary scan. Additionally, the MJS engineering and design Fax: +351 252 24 6001 teams provide a broad spectrum of expertise, includ- www.nanium.com ing RoHS compliance, digital and RF, in electronic, Contact: Mr. Antonio Barny, Business mechanical & software design, with end-to-end sup- Development Manager port from conceptualization through manufacturing Email: [email protected] and fulfillment. Booth 114 NANIUM is dedicated to provide package and system Momentive Performance Materials Inc. design, development, manufacturing, testing and 22 Corporate Woods Blvd. engineering services in the semiconductor business, Albany, NY 12211 from prototypes and samples to small, medium and Phone: +1-800-295-2392 high volume. The service portfolio ranges from wafer www.momentive.com test, wafer pre-assembly, wafer level and component Contact: Kim Le level assembly, package and product test and board Emails: [email protected] or level assembly and test to assembly and test of special [email protected] customized package solutions and systems. This is Booth 200 complemented by fully equipped in-house reliability and failure analysis laboratories and capabilities for Momentive’s SilCool* low thermal resistance fast development feedback and product qualification. adhesives, SilCool* thermal interface grease, SilFas die NANIUM is operating mainly in Wafer Level Packaging attach adhesives, encapsulation materials for power (WLP), Fan-In type Wafer Level Chip Size Package electronics and InvisiSil* LED and optical encapsulants (WLCSP) and Fan-Out type embedded Wafer Level provide design freedom and enable greater Ball Grid Array (eWLB), both up to 300mm wafer productivity in electronics applications. Momentive diameter. Being at home in the “More-than-Moore” is a global leader in silicones and advanced materials, domain of heterogeneous integration of different with a 70-year heritage of being first to market with functionalities at package level and being recognized performance applications for major industries that as leading edge provider of Fan-Out WLP technology, support and improve everyday life. The company NANIUM offers System-in-Package (SiP) solutions on delivers science-based solutions, by linking custom wafer level. NANIUM also offers over-mold package technology platforms to opportunities for customers. solutions based on laminated organic substrate Additional information is available at www.momentive. interposers, concentrating on more complex and com. *SilFas, SilCool, InvisiSil are trademarks of sophisticated package solutions like SiP and Multichip Momentive Performance Materials Inc. Packages (MCP). With more than 15 years of experience in the semiconductor industry, NANIUM has a highly qualified, competent, well experienced and motivated team of 520 people as well as state-of-the- art facilities and equipment, ready to provide services beyond its customers’ expectations. The company is located in Porto, Portugal, at Europes’ west coast. More information: www.nanium.com

30 Nordson DAGE Palomar Technologies QualiTau 48065 Fremont Boulevard 2728 Loker Ave. West 950 Benecia Ave. Fremont, CA 94538 Carlsbad, CA 92010 Sunnyvale, CA 94085 Phone: +1-510-683-3930 Phone: +1-760-931-3600 Phone: +1-408-522-9200 Fax: +1-510-933-2966 Fax: +1-760-931-5191 Fax: +1-408-522-8110 www.nordsondage.com www.palomartechnologies.com www.qualitau.com Contact: Aram Kardjian Contact: Jessica Sylvester Email: [email protected] [email protected] Email: [email protected] Booth 307 Booth 212 Booth 504 QualiTau offers a variety of reliability and Nordson DAGE is the market leading provider Palomar Technologies, a former subsidiary of Hughes parametric test equipment for the characterization of award winning test and inspection systems for Aircraft, is the global leader of automated high- and development of new materials used in the destructive and non-destructive mechanical testing accuracy, large work area die attach and wire bond manufacture of Integrated Circuits. The DSPT 9012 of electronic components and is recognized as the equipment and precision contract assembly services. (Desktop Semiconductor Parametric Tester) is a PC industry standard. Nordson DAGE continues to Customers utilize the products, services and solutions Controlled SMU test instrument built specifically for invest significantly in research and development to from Palomar Technologies to meet their needs for semiconductor device characterization and testing. remain at the cutting edge of bond testing technology. optoelectronic packaging, complex hybrid assembly The MIRA, Infinity, ACE, and Multi-Probe reliability The 4000PLUS platform compliments the range of test systems for both traditional and the more specialist and micron-level component attachment. test systems perform tests for Hot Carrier Injection, applications such as ribbon pull, BGA sphere and Dielectric Breakdown, Solder Bump at up to 8 Amps, package fatigue, PCB 3 point bend testing, and hot Plexus Corp. and Electromigration at test temperatures up to bump pull for PCB pad cratering testing in accordance One Plexus Way 450°C. with IPC9708.The 4000HS high speed bondtester, Neenah, WI 54957 capable of testing solder bumps in high speed shear Phone: +1-920-751-3202 Quik-Pak and high speed cold bump pull modes, is becoming Fax: +1-920-751-5395 10987 Via Frontera a viable alternative to board level drop testing. In www.plexus.com San Diego, CA 92127 addition to highly accurate force measurements, the Contact: Mark Wolfgram Phone: +1-858-674-4676 4000HS provides bond energy results, including total Email: [email protected] Fax: +1-858-674-4681 and fractional values. Bond energy values are proving Booth 606 www.icproto.com invaluable for failure mode analysis, particularly in the Plexus has delivered optimized Product Realization Contact: Julie Adams detection of lead-free brittle fractures. Furthermore, solutions through a unique customer focused Email: [email protected] they can be used to evaluate various materials (alloys, service model since 1979. With more than 7 years Booth 308 UBM, finish, substrate) and to monitor bumping of Microelectronic experience, Plexus enables Quik-Pak, a division of Delphon Industries, provides IC production processes. The tool has applications in creative, secure sub-systems solutions and delivers packaging and assembly services. The company’s new- development, failure analysis, QA and production. comprehensive end-to-end solutions to customers est offering is its OmPP package. These pre-molded Nordson DAGE also provides 2D and CT X-ray by seamlessly integrating product conceptualization, QFN packages are cost-effective, come in a variety inspection systems, including the flagship, award- design, commercialization, manufacturing, fulfillment of sizes and are ideal for prototype or production winning XD7600NT Diamond FP, which have been and sustaining services. volume applications. Quik-Pak also specializes in a specifically and ergonomically designed for the printed variety of services that together provide a full turn-key circuit board (PCB) and semiconductor industries. PURE TECHNOLOGIES solution including wafer preparation, die/wire bonding, These X-ray inspection systems provide high 177 US Hwy # 1, No. 306 remolding and marking/branding. Custom assembly resolution nano-focus analysis not only within failure Tequesta, FL 33469 services are also offered for Flip Chip, Ceramic Pack- analysis laboratories but also within the production Phone: +1-404-964-3791 ages, Chip-on-Board, Stacked Die, MEMS, etc environment. The unique Nordson DAGE NT sealed- Fax: +1-877-738-8263 transmissive type of X-ray tube is at the heart of the Int’l Fax: +1-973-273-2132 RTI International - Center for Materials & Elec- Nordson DAGE NT X-ray inspection systems. It supersedes and out-performs the closed and open www.puretechnologies.com tronic Technologies tube types that are available in earlier systems. The Contact: Jerry Cohn 3040 Cornwallis Road, Adv Tech Bldg sealed-transmissive tube is the only way to genuinely Email: [email protected] P.O. Box 12194 improve X-ray image resolution whilst still providing Booth 503 RTP, NC 27709 Pure Technologies manufactures low (0.02, 0.01 cph/ Phone: +1-919-248-1801 true high power and all without compromising the 2 2 resolution and magnification. The new X-Plane™ cm ), ultra-low (0.005, 0.002 cph/ ) and super ultra- www.rti.org/microsystem 2 Analysis system option allows X-ray inspection in any low (<0.001 cph/cm ) alpha emitting Tin (Sn), Lead- Contact: Alan Huffman plane without cutting the board. Free (including all SAC) alloys, Pb and Pb/Sn alloys. Email: [email protected] These ALPHALO® products are available in various Booth 310 PAC TECH USA – Packaging Technologies, Inc. shapes and sizes – ingots, anodes, slugs, pellets, foil, RTI International’s Center for Materials and Electronic 328 Martin Avenue rods, bricks, PbO and SnO powder, etc. for wafer- Technologies is a world leader in advanced intercon- Santa Clara, CA 95050 level packaging, interconnects, and sphere and powder/ nect and packaging technologies. RTI provides access Phone: +1-408-588-1925 x 202 paste manufacturing. ALPHA-LO® reduces or eliminates to state of the art wafer bumping and WLP technolo- Fax: +1-408-588-1927 soft errors from alpha particle emissions from gies, supporting small and mid-volume customers as www.pactech.com solders, enhances performance reliability and reduces well as developmental applications. As a recognized Contact: Dr. Thorsten Teutsch corporate liability. All materials are guaranteed and leader in 3D integration, RTI has developed a com- Email: [email protected] certified to be at secular equilibrium and are tested prehensive platform of technologies and works with Booth 401 and retested over time before shipping to insure that commercial, government, and academic clients from Pac Tech is one of the leading subcontractor houses the alpha emission rate is stable and will not increase around the world to develop and implement solutions. for wafer bumping. The emphasis is concentrated over time. In addition to its focus on advanced interconnect tech- on a low cost electroless bumping process on wafer nologies, RTI also conducts research and development level, based on Ni/Au as an Under Bump Metallization in sensors and actuators, electronic material character- (UBM) and solder application (eutectic PbSn or lead- ization, and novel device microfabrication. The Center free) by stencil printing. This process is suitable for 4, is staffed with full time engineers and researchers 5, 6, 8 and 12 inch wafers with Al- or Cu-metallization. developing new technologies and solutions in conjunc- Pac Tech offers also manual and fully automatic equip- tion with our clients. Fully integrated fabrication and ment for electroless Ni/Au bumping on Al and Cu analytical facilities allow RTI to support a diverse proj- metallization, as well as completes turnkey solutions which include the transfer of the technology and deliv- ect base, from process development, proof of concept ery of chemicals. Furthermore, Pac Tech builds laser and prototyping, to small-scale production. based bumping (SB2) and Flip-Chip assembly (Laplace) RTI International is a non-profit research institute equipment. The SB2 equipment is suitable for fluxless offering innovative research, technical expertise, and solder jetting on R&D for CSP, BGA, Flip Chip, HDD fabrication capabilities to governments and businesses and MEMS as well as for automated production envi- worldwide. ronments. The Laplace (Laser Placer) FlipChip bonder offers low stress assembly solutions for flex and rigid substrates, like LCD drivers, RFID labels, MEMS and optical devices, SIP applications.

31 Semiconductor Equipment Corporation Shinko Electric America Sonnet Software 5154 Goldman Avenue 2880 Zanker Road, Suite 204 100 Elwood Davis Road Moorpark, CA 93021 San Jose, CA 95134 North Syracuse, NY 13212 Phone: +1-805-529-2293 Phone: +1-408-232-0482 Phone: +1-315- 453-3096 or +1-877-7SONNET Fax: +1-805-529-2193 Fax: +1-408-955-0368 Fax: +1-315-451-1694 www.semicorp.com www.shinko.co.jp Contact: Robert O’Rourke Contact: Don Moore Contact: Rick McDonald Email: [email protected] Email: [email protected] Email: [email protected] Booth 602 Booth 303 Booth 609 Sonnet software is dedicated to the development Semiconductor Equipment Corporation produces Shinko Electric Industries Co., LTD. is a leading of high-frequency electromagnetic analysis software. manual, semiautomatic, and automatic equipment manufacturer of a wide variety of materials used Sonnet’s software is aimed at today’s demanding for the Photonics, Semiconductor, MEMS, SMT and in the packaging of integrated circuits such as: design challenges involving predominately 3D planar Hybrid Industries. Products include flip-chip bonders, Organic Substrates, Leadframes, TO-Headers and circuits and antennas, including microstrip, stripline, die bonders, diode laser bonders, eutectic die bonders, Heatspreaders. With headquarters located in Nagano, co-planar waveguide, PCB (single and multiple layers) manual pick & place, die rework, dicing tape, manual Japan and offices worldwide, Shinko strives to and RF packages incorporating any number of layers of and automatic dicing tape applicators, heat release provide the ultimate in service and solutions for our metal traces embedded in stratified dielectric material. tape, backgrinding tape, backgrinding tape applicators, customers. For more about Shinko please visit our For more information on the Sonnet Suites visit www. and die ejectors. website at www.shinko.com. sonnetsoftware.com

SET – Smart Equipment Technology SIGRITY, INC. Sonoscan, Inc. 131, impasse Barteudet 900 E. Hamilton Avenue, Suite 500 2149 E. Pratt Blvd. 74490 Saint Jeoire, France Campbell, CA 95008 Elk Grove Village, IL 60007 Phone: +33 (0) 450-35-83-92 Phone: +1-408-688-0145 Phone: +1-847-437-6400 Fax: +33 (0) 450-35-88-01 Fax: +1-408-688-0144 Fax: +1-847-437-1550 www.set-sas.fr www.sigrity.com www.sonoscan.com Contact: Gilbert Lecarpentier Contact: Leslie Landers, VP Sales & Mkt. Contact: Bryan Schackmuth Email: [email protected] Email: [email protected] Email: [email protected] Booth 601 Booth 403 Booth: 306 SET, Smart Equipment Technology (Former Suss SIGRITY provides software tools and technical ser- Founded in 1973 and headquartered in Chicago, IL, MicroTec Device Bonder Division) is a world leading vices for power, ground and signal integrity analysis Sonoscan®, Inc. is a worldwide leader and innovator in supplier of High Accuracy Assembly and Nano Imprint of high performance IC packages and printed circuit Acoustic Micro Imaging (AMI) technology. Sonoscan Lithography Solutions. As a supplier of semiconductor boards. SIGRITY analysis tools utilize a fast electro- manufactures and markets acoustic microscope equipment dedicated to high-end applications for over magnetic field solver that takes into account coupling instruments and accessories to nondestructively 30 years and with more than 300 Device Bonders between vias, reflection from edges, resonance, power inspect and analyze products. Our C-SAM® scanning installed worldwide, SET is globally renowned for the and ground voltage fluctuations, and electromagnetic acoustic microscope provides unmatched accuracy unsurpassed bonding accuracy (± 0.5 µm) and the high radiation. SIGRITY’s package physical design products and robustness setting the standard in AMI for the flexibility of its die and flip-chip bonders. SET’s product provide eDriven capability and facilitate design reuse. inspection of products for hidden internal defects such portfolio ranges from manual loading versions to fully Worldwide leading companies as well as high-tech as poor bonding, delaminations between layers, cracks automated operation. The SET systems cover a wide start-ups have successfully adopted SIGRITY’s software and voids. In addition, Sonoscan offers analytical range of bonding applications and offer the unique abil- tools for applications in various pre- and post-layout services through regional testing laboratories in Asia, ity to handle both fragile and small components onto power and signal integrity analyses. Europe and the U.S. and educational workshops for substrates up to 300mm. beginners to advanced on AMI technology. SIMULIA Shin-Etsu MicroSi, Inc. 166 Valley Street SPTS Technologies 10028 S. 51st Street Providence, RI 02909-2499 1150 Ringwood Court Phoenix, AZ 85044 Phone: +1-401-276-4400 San Jose, CA 95131-1726 Phone: +1-480-893-8898 Fax: +1-401-276-4408 Phone: +1-408-571-1400 Fax: +1-480-893-8637 www.simulia.com Fax: +1-408-715-0267 www.microsi.com Contact: Mike Sasdelli www.spts.com Email: [email protected] Email: [email protected] or Mike. Contact: Lisa Mansfield Booth 510 [email protected] Email: [email protected] Shin-Etsu Microsi, Inc. is a wholly owned subsidiary of Booth 211 Booth 201 Shin-Etsu Chemical Ltd. Shin-Etsu MicroSi is a world SIMULIA is the Dassault Systèmes brand that makes SPTS Technologies designs, manufactures, sells, class supplier of packaging materials for the semi- realistic simulation an integral business practice and supports etch, PVD, CVD and thermal capital conductor industry. With a global support network, improving product performance, reducing physical equipment and process technologies for the global which includes Sales Engineers, R&D, Manufacturing, prototypes, and driving innovation. SIMULIA semiconductor and micro-device industries, providing Quality Assurance, and Logistics, we are able to quick- solutions include Abaqus Unified Finite Element advanced wafer processing solutions to MEMS, ly develop and provide new technologies to benefit Analysis solutions, multiphysics solutions for insight advanced packaging, LED, high speed RF device, and our customers. This allows our clients to meet their into challenging engineering problems, and SIMULIA power management markets. ever changing technical, commercial and environmental SLM for managing simulation data, processes, and needs by implementing Shin-Etsu MicroSi’s technology. intellectual property. Shin-Etsu MicroSi is known for supplying high perfor- mance Thermal Interface Materials, Underfills, Molding Smoltek AB Compounds, High Purity Silicone Encapsulants, and Regnbagsg. 3 Die Attach Materials. 417 55 Gothenburg SWEDEN Phone: +46 708 393 693 www.smoltek.com Contact: Anders Johansson Email: [email protected] Booth 205 Smoltek AB offers a proprietary and versatile conductive nano-scale carbon technology tailored to support the future needs of the semiconductor industry. Applications ranges from Thermal Management Solutions to Micro-Bumps and Interconnects. The business idea is to license our IP’s and Process Technology to our customers - directly or through partnerships with selected vendors of semiconductor processing tools.

32 STATS ChipPAC Tamar Technology TechSearch International Inc. 47400 Kato Road 996 Lawrence Drive #202 4801 Spicewood Springs Rd., Suite 150 Fremont, CA 94538 Newbury Park, CA 91320 Austin, TX 78759 Phone: +1-510-979-8000 Phone: +1-805-480-3358 Phone: +1-512-372-8887 Fax: +1-510-979-8001 Fax: +1-805-498-7644 Fax: +1-512-372-8889 www.statschippac.com www.tamartechnology.com www.techsearchinc.com Contact: Lisa Lavin Contact: Russ Dudley Contacts: E. Jan Vardaman, Becky Travelstead Email: [email protected] Email: [email protected] Email: [email protected] Booth 213 Booth 111 Booth 400 STATS ChipPAC is a leading service provider of Tamar Technology develops and manufactures high- TechSearch International, Inc. was founded in 1987 as semiconductor packaging design, bump, probe, speed non-contact metrology solutions for 3DIC a market research and consulting company specializing assembly, test and distribution solutions. A trusted advanced packaging and related processes for MEMS, in emerging semiconductor packaging trends. partner to leading semiconductor companies CMOS image sensors, compound semiconductors, Multi- and single-client services encompass market worldwide, STATS ChipPAC provides fully integrated, LED, and other market areas. research, technology trends, strategic planning, and multi-site, end-to-end packaging and testing solutions technology licensing. Research topics include wafer Tamar’s proprietary sensor technology offers that bring products to market faster. With advanced level packaging, flip chip interconnect, CSPs, BGAs, maximum flexibility and includes their Optical Stylus process technology and a global manufacturing 3D integration with TSVs, manufacturing in China Probe (OSP), Wafer Thickness Sensor (WTS), and presence spanning Singapore, South Korea, China, and India, multichip packages (MCPs) such as stacked Visible Thickness Sensor (VTS) to support a variety of Malaysia and Thailand, STATS ChipPAC offers a full die CSPs and System-in-Package (SiP), embedded applications. range of backend turnkey services for a wide variety components, microvia substrates, LED assembly, and of electronics applications. STATS ChipPAC has a The measurement capability provided by these sensors Pb-free manufacturing. Market forecasts and trends in leadership position in advanced package technology include through silicon via (TSV) depth with unlimited advanced semiconductor packages and materials are such as fan-in and fan-out wafer level packaging, flip aspect ratio, wafer thickness and total thickness available. In conjunction with SavanSys Solutions, wire chip interconnect, Through Silicon Via, 2.5D and 3D variation (TTV) for single and multi-layer wafers, bond, flip chip and WLP trade-off cost models are integration to meet the increasing market demand remaining silicon thickness (RST), wafer shape, thin Si offered. TechSearch International professionals have for next generation devices with higher levels of thickness, thick films and polymer thickness, and other an extensive network of more than 15,000 contacts performance, increased functionality and compact critical measurement requirements. in North America, Asia, and Europe and travel sizes. extensively, visiting major electronics manufacturing Tamar’s WaferScan system is modular in design so operations and research facilities worldwide. the user can configure it with one or more sensors to SUSS MicroTec Inc. maximize the measurement flexibility and value. The A SÜSS MicroTec AG Company Tokyo Ohka Kogyo Co., Ltd. system can be configured for semi or fully automated 430 Indio Way TOK America, Inc. operation and the high speed data rates allow the user Sunnyvale CA 94085 190 Topaz St. the flexibility to integrate the measurement technology Phone: +1-408-940-0300 Milpitas, CA 95035 in-line to monitor production real-time depending on Fax: +1-408-940-0350 Phone: +1-408-956-9901 process requirements. www.suss.com Fax: +1-408-956-9995 Contact: Hosgoer Sarioglu www.tok.co.jp/en/index.php Tamarack Scientific Co. Inc. Email: [email protected] Contact: Satoshi Teranish 220 Klug Circle Booth 508 Email: [email protected] Corona, CA 92880 SUSS MicroTec - Shaping the Future Booth 302 Phone: +1-951-817-3700 With over 60 years of engineering experience and For over 50 years TOK has been supplying Fax: +1-951-817-0640 thousands of active systems installed worldwide, superior quality chemicals and equipment to the www.tamsci.com SUSS MicroTec is amongst the leading suppliers of microelectronics and semiconductor manufacturers Contact: Matt Souter process equipment for semiconductors and related of the world. TOK is now offering materials and Email: [email protected] markets. The solution portfolio covers all performance equipment to enable fabrication of 3DIC with TSVs. Booth 506 steps for photomask and wafer processing ranging These products include photoresists for plating (Au, Manufacturer of LASER SYSTEMS, UV STEPPERS, from cleaning, coating, baking, developing, aligning, to Ni, Cu, Pb/Sn, SN/Ag), photo definable insulators, and UV SCANNERS and MASK ALIGNERS. Tamarack wafer bonding and is complemented by micro-optical the “Zero Newton” system, an innovative turn-key supplies photolithography and laser micromachining components. solution for temporary wafer handling that can be systems. We specialize in applications including: LASER tailored to meet the demanding needs of companies From Advanced Packaging to 3D Integration DEBONDING 3D TSV; WLFO & WLCSP; Solar on the forefront of 3DIC packing technology. Please SUSS MicroTec has been at the forefront of Cells, Organic Electronics, MEMS, Medical Devices and visit our booth to learn more about TOK’s products companies supporting the advanced packaging industry HDI. Our Excimer and Solid State ablation systems are and how TOK can help you solve your most with dedicated lithography solutions. With the trend ideal for direct pattern etching thin metals from wafers challenging advanced packaging requirements. leading towards 3D architectures for IC integration to seed layer removal or other electronic circuits. In and packaging, we support 3D Packaging and 3D addition, laser drill RDL Vias and Trenches for WLCSP Toray Engineering Co., Ltd. Interconnect processes with precision equipment with selective material removal, down to 1um. Systems 1-45,Oe 1-chome, Shiga, for thick resist and high topography applications, designed for 300mm, Roll-to-Roll, Reel-to-Reel 520-2141 Japan Through-Silicon-Via (TSV) manufacturing, bonding and and Sheet handling. Resolution capabilities to 1um. Phone: +81-77-544-6221 de-bonding solutions, stacking technologies as well as Machines designed for 24/7 production environments. Fax: +81-77-544-1940 products for the production of CMOS image sensors. www.toray-engl.co.jp MEMS and Compound Semiconductor Manufacturing Toray Engineering Co., Ltd. With a full range of wafer-processing equipment 411 Borel Avenue, Suite 520 and extensive experience in warped wafer handling San Mateo, CA 94402 solutions, SUSS MicroTec has positioned itself as Phone: +1-408-313-2408 the leader in high-volume Micro-Electro-Mechanical- Contact: Kyoji Ishikawa Systems (MEMS) manufacturing. Our equipment Email: [email protected] is specifically designed to handle non-standard Booth 301 substrates like fragile compound semiconductors and Toray Engineering Co., Ltd provides Flip Chip Bond- incorporates specialized hardware such as coaters, ing Equipment for Semiconductor Packaging (FC aligners and bonders optimized for LED manufacturing. 2000), Optoelectronics (OF2000) and LCD devices (CL2000FW, OS2000). Also, Vacuum Encapsulation Equipment (VE500) and various Flexible substrates (TCP,interposer) manufacturing equipment such as resist coater, proximity exposer, etching, developing line are available.

33 Torrey Hills Technologies, LLC XYZTEC YOLE DEVELOPPEMENT 6370 Lusk Blvd., Suite F-111 5843 Cajon Way Le Quartz – 75 cours Emile Zola San Diego, CA 92121 Gilroy, CA 95020 69100 Lyon-Villeurbanne Phone: +1-858-558-6666 Phone: +1-408-846-5475 FRANCE Fax: +1-858-630-3383 Fax: +1-408-852-4011 Phone: +33-472-83-01-80 www.torreyhillstech.com www.xyztec.com Fax: +33-472-83-01-83 Contact: Joyce Zhang Contact: Cynthia Blank www.yole.fr Email: [email protected] Email: [email protected] Contact: Camille Favre Booth 105 Booth 513 Email: [email protected] Torrey Hills Technologies, LLC is a leader in XYZTEC, a leading global supplier of bond test Booth 104 developing and delivering quality yet affordable equipment, offers the most flexible bond testing Beginning in 1998 with Yole Développement, we have component parts and production equipment for platform on the market today! The Condor series grown to become a group of companies providing multiple industries. Its wide range of products include features a single platform with multiple test capabilities market research, technology analysis, strategy tungsten-copper, molybdenum-copper, Cu/Mo/Cu, Cu/ allowing end-users the added flexibility of performing consulting, media in addition to finance services. With Mo70Cu/Cu heat sinks, and fast fire and infrared belt many types of tests all on one system. In addition a solid focus on emerging applications using silicon furnaces that can work in a variety of atmospheres to standard bond testing applications such as wire and/or micro manufacturing Yole Développement serving both electronics and solar cell industries. pull, ball shear, die shear, the Condor series has the group has expanded to include more than 40 Headquartered in San Diego, CA, its mission is to help capability to perform peel testing, push testing, high associates worldwide covering MEMS, MedTech, customers achieve higher profitability by the provision impact testing, fatigue testing, and creep testing. Advanced Packaging, Compound Semiconductors, of innovative products and services. Power Electronics, LED, and Photovoltaics. The group XYZTEC is the only bond test supplier that offers a supports companies, investors and R&D organizations Revolving Measurement Unit, featuring four different USHIO America worldwide to help them understand markets and measurement sensors to address 80% of your test 5440 Cerritos Ave. follow technology trends to develop their business. requirements. The joysticks are ergonomically Cypress, CA 90630 friendly, easily move the XY stage to the desired CUSTOM STUDIES Phone: +1-800-838-7446 position, and feature 12 logically arranged buttons • Market data, market research and marketing analysis Fax: +1-800-776-3641 for increased operator efficiency. The Condor EZ • Technology analysis www.ushioamerica.com software features onboard graphics and intelligent • Reverse engineering and reverse costing Contact: Toru Fujinami wizards, providing intuitive operator control as well • Strategy consulting Email: [email protected] as sophisticated SPC software thus ensuring complete • Corporate Finance Advisory (M&A and fund raising) Booth 103 documentation of the test protocol. Check out our Ushio America, a leading global supplier of semicon- TECHNOLOGY & MARKET REPORTS new web site at www.xyztec.com. ductor fabrication equipment, subsystems and com- • Collection of reports ponents, has engaged in development, manufacturing • Players & market databases Yield Engineering Systems, Inc. and sales in a wide range of product fields. As a world • Manufacturing cost simulation tools 203-A Lawrence Drive premier photolithography light source provider, the • Component reverse engineering & costing analysis Livermore, CA 94551 Ushio Group leverages the industry’s most advanced More information on www.yole.fr Phone: +1-925-373-8353 or +1-888-YES-3637 development capabilities to meet the increasingly Fax: +1-925-373-8354 MEDIA sophisticated and divergent product requirements of www.yieldengineering.com • Critical news, Bi-weekly: Micronews, the magazine the global semiconductor industry. Contact: Bill Moffat • In-depth analysis & Quarterly Technology Magazines: Ushio offers wide range lithography systems, including Email: [email protected] MEMS Trends– 3D Packaging – iLED – Power Dev’ the full-field projection exposure equipment, UX4-3Di Booth 305 • Online disruptive technologies website: www.i- FFPL300, WLP stepper UX7-3Di STEP300 and stepper Yield Engineering Systems (YES) provides a wide micronews.com for organic substrate, UX5-3Di STEP500. Subsystems variety of processing equipment including high • Exclusive Webcasts and components solutions for Nano Imprints Lithog- reliability polymer processing tools for WLP type CONTACTS raphy templates cleaning subsystems, mask cleaning processes and plasma systems for underfill treatment. For more information about: subsystems, UV LED components, EUV Lithography YES manufactures quality equipment for the • Services : Jean-Christophe Eloy ([email protected]) Source subsystems as well as the industry-bench- Semiconductor, Photovoltaic, FPD, MEMS, Medical, • Reports: David Jourdan ([email protected]) marked superior UV lamps are also available. Nanotech Industries and more. • Media : Sandrine Leroy ([email protected]) Ushio provides manufacturing solutions for a wide Our tool line features high temperature vacuum cure range of semiconductor process applications including ovens, chemical vapor deposition (CVD) systems and 2.5D and 3D packaging, EUV lithography, NGL, LEDs plasma etch/clean tools. Our products are used for and compound semiconductors. precise surface modification, surface cleaning, underfill processing and thin film coating of semiconductor wafers, semiconductor and MEMS devices, biosensors and medical slides. Applications include high vacuum applications for MEMS, low-k dielectric repair, polyimide and BCB bake, copper anneal, anti-corrosive coating, photoresist adhesion or stripping, silane/surface adhesion promotion, MEMS coating to reduce stiction and image reversal.

34 Zeon Corporation / Zeon Chemicals L.P. technology leading devices. ”Ultra-Low Loss Build-Up Zymet, Inc. 5 Centerpointe Drive, 4th Floor, Suite 401 Film” provides high density, high speed, and reliable IC 7 Great Meadow Lane Lake Oswego, OR 97035 or GPU packages with properties such as low CTE, E. Hanover, NJ 07936 Phone: +1-408-817-0135 4/4um L/S, low dielectric constant, low loss tangent, Phone: +1-973-428-6245 Fax: +1-971-204-0240 and low moisture absorption. In addition to those Fax: +1-973-428-5244 www.zeon.co.jp/business_e/enterprise/imagelec/ properties, it allows forming very fine copper lines www.zymet.com imagelec.html on high smooth surfaces, with its Ra around 70nm Contacts: Sean Sandage and Karl Loh www.zeonchemicals.com while maintaining superior peel strength performance. Email: [email protected] Contact: Chris Blatt Ultra-Low Loss PCB Materials: Both prepreg and Booth 410 Email: [email protected] copper-clad laminate are available to form multilayer Adhesives and encapsulants for electronics and Booth 511 printed-circuit board with the strength of extremely optoelectronics assembly. Products include electrically Zeon Corporation, a leading Japanese technology low loss tangent, high modulus, 20/20um or even conductive and thermally conductive adhesives, ultra- polymer company, and subsidiary Zeon Chemicals less L/S with ultra-smooth surface, and either high low stress adhesives, ACPs and NCPs, UV curable L.P., USA have developed two innovative state-of-the- or low dielectric constant depending on the desired glob top encapsulants, and underfill and reworkable art packaging materials: 1) “Ultra-Low Loss Build-Up application. The low k variety is ideal for high- underfill encapsulants for flip chips, WLPs, CSPs, Film” used for Build-Up substrate for IC packages, performance servers, as well as milli-wave applications BGAs, and POPs. GPU, WLP, Si Interposer and any application requiring where conventional products fall short either in signal superior electrical properties, and 2) “Ultra-Low Loss integrity or challenges in high cost processing. The high PCB Materials” low-loss laminate for both high k and k version is an ideal replacement for LTCC where high low k applications such as milli-wave radars, high-speed performance and miniaturization are roadmap items. servers and circuits, and RF/mobile applications for

®

35 2012 Executive Committee Arrangements Chair E. Jan Vardaman Lisa Renzi TechSearch International, Inc. General Chair David McCann Renzi & Company, Inc. James Jian Zhang GLOBALFOUNDRIES [email protected] Micron Technology, Inc. [email protected] +1-940-383-3059 Applied Reliability Chair +1-518-305-6317 CPMT Representative Keith Newman Vice-General Chair C. P. Wong Hewlett Packard Wolfgang Sauter Georgia Institute of Technology [email protected] IBM Corporation [email protected] +1-408-276-7193 [email protected] +1-404-894-8391 Assistant Chair +1-802-769-3634 Scott Savage 2011 Program Committee Program Chair Medtronic Microelectronics Center Senol Pekin Advanced Packaging [email protected] Intel Corporation Chair +1-480-303-4749 [email protected] Joseph W. Soucy Jo Caers +1-480-552-4898 Draper Laboratory Royal Philips [email protected] Assistant Program Chair +1-617-258-2953 Sridhar Canumalla Beth Keser Microsoft Corporation Assistant Chair Qualcomm, Inc. Harry K. Charles Raj N. Master [email protected] The Johns Hopkins University APL Microsoft Corporation +1-858-658-3332 [email protected] Tim Chaudhry Jr. Past General Chair +1-650-693-0849 Broadcom Corporation Rajen Dias Daniel Baldwin Darvin R. Edwards Intel Corporation Engent, Inc. Texas Instruments, Inc. [email protected] Deepak Goyal +1-480-554-5202 Charles Banda Laboratory for Physical Sciences Intel Corporation Sr. Past General Chair Vikas Gupta Rozalia Beica Jean Trewhella Texas Instruments, Inc. LAM Research AG IBM Corporation Dongming He [email protected] Christopher Bower Qualcomm, Inc. +1-845-894-3974 Semprius, Inc. Donna M. Noctor Exhibits Chair Paul M. Harvey Siemens Industry, Inc. Bill Moody IBM Corporation John H. L. Pang B. Moody & Associates, Inc. Altaf Hasan Nanyang Technological University [email protected] Intel Corporation +1-302-478-4143 S.B. Park Erik Jung Binghamton University Finance Chair Fraunhofer IZM Lakshmi N. Ramanathan Patrick Thompson Sam Karikalan Microsoft Corporation Texas Instruments, Inc. Broadcom Corporation [email protected] Ephraim Suhir +1-972-995-7660 Beth Keser University of California, Santa Cruz Qualcomm, Inc. Publications Chair Jeffrey Suhling Auburn University Steve Bezuk Young-Gon Kim Qualcomm CDMA Technologies IDT Dongji Xie [email protected] John Knickerbocker nVidia Corporation +1-858-651-2770 IBM Corporation Charles Zhang Publicity Chair Jeffrey A. Knight Intel Corporation Eric D. Perfecto Elliot Manufacturing Assembly & Manufacturing Technology IBM Corporation John H. Lau Chair [email protected] ITRI +1-845-894-4400 Hirofumi Nakajima S. W. Ricky Lee Renesas Electronics Corporation Web Administrator Hong Kong University of Science and [email protected] Alan Huffman Technology +81-44-435-1137 RTI International Luu T. Nguyen Assistant Chair [email protected] Texas Instruments, Inc. Paul Houston +1-919-248-9216 Engent Raj Pendse Professional Development [email protected] STATS ChipPAC, Inc. +1-678-990-3320 ext. 229 Courses Chair Kitty Pearsall Sudipta K. Ray Sai Ankireddi IBM Corporation IBM Corporation Intersil, Inc. [email protected] Subhash L. Shinde Sharad Bhatt +1-512-286-7957 Sandia National Laboratory Shanta Systems, Inc.

36 Claudius Feger Lih-Tyng Hwang C. S. Premachandran IBM Corporation National Sun Yat-Sen University Global Foundries Singapore Pte. Ltd. Jerry Lu Mahadevan K. Iyer Koneru Ramakrishna Intel Corporation Texas Instruments, Inc. Anveshak Technology & Knowledge Solutions Vijay Khanna Timothy G. Lenihan IBM Corporation TGL Consulting Nancy Stoffel GE Global Research Wayne Koh Li Li Powertech Technology .Inc. Freescale Semiconductor, Inc. Klaus Juergen Wolter Technische Universitaet Dresden Choon Heung Lee Sebastian Liau Amkor Technology Korea ITRI Enboa Wu Mali Mahalingam Hong Kong Applied Science and Lianjun Liu Technology Research Institute Freescale Semiconductor, Inc. Everspin Technologies Debendra Mallik Allison Xiao Albert Lu National Starch and Chemical Company Intel Corporation Singapore Institute of Manufacturing Sylvain Ouimet Technology Interconnections IBM Corporation Chair Nanju Na Bernd Ebersberger Kitty Pearsall IBM Corporation Intel Mobile Communications IBM Corporation Andrea Paganini [email protected] Sande Petty-Weeks IBM Corporation +49-89-998853-53281 Skyworks Solutions, Inc. Markondeya R. Pulugurtha Assistant Chair Tom Poulin Georgia Institute of Technology Gilles Poupon Aerie Engineering CEA LETI - MINATEC Albert F. Puttlitz [email protected] Shichun Qu Mechanical Eng. Consultant +33-4-38-78-53-99 Fairchild Semiconductor Thomas G. Reynolds, III Flynn Carson Shawn Shi T3 Group, LLC STATS ChipPAC, Inc. Medtronic Corporation Clemens Ruppel William Chen Tom Swirbel EPCOS AG ASE-US, Inc. Motorola, Inc. Hideki Sasaki Rajen Dias Sean Too Renesas Electronics Corporation Intel Corporation Microsoft Corporation Grit Sommer Tom Gregorich Andy Tseng Infineon Technologies AG MediaTek Advanced Semiconductor Engineering, Inc. Frank Theunis Alan Huffman Shaw Fong Wong EPCOS AG RTI International Intel Corporation Emerging Technologies Li Li Jie Xue Chair Cisco Systems, Inc. Cisco Systems, Inc. Karlheinz Bock Changqing Liu University of Berlin and Fraunhofer EMFT Jin Yang Loughborough University Intel Corporation [email protected] +49-89-54759-506 Wei-Chung Lo Electronic Components & RF ITRI Chair Assistant Chair Rockwell M. Hsu Bernd K. Appelt James Lu Cisco, Inc. ASE, Inc. Rensselaer Polytechnic Institute [email protected] [email protected] Voya Markovich +1-480-838-7435 +1-408-768-8533 Endicott Interconnect Technologies, Inc. Assistant Chair Isaac Robin Abothu David McCann Manos M. Tentzeris Consultant GLOBALFOUNDRIES Georgia Institute of Technology [email protected] Vasudeva P. Atluri James E. Morris +1-404-385-6006 Renavitas Technologies Portland State University Amit P. Agrawal Mark Bachmann Lou Nicholls Cisco Systems, Inc. University of California, Irvine Amkor Technology, Inc. Eric Beyne John Cunningham Prema Palaniappan IMEC Oracle Texas Instruments, Inc. Prem Chahal Rabindra N. Das Senol Pekin Michigan State University Endicott Interconnect Technologies, Inc. Intel Corporation Craig Gaw Steve Greathouse Wolfgang Sauter Freescale Semiconductor, Inc. Plexus Corporation IBM Corporation Abhilash Goyal Joana Maria Lei Shan Oracle IBM Corporation IBM Corporation T. S. Horng Goran Matijasevic Akitsu Shigetou National Sun Yat-Sen University University of California, Irvine National Institute for Materials Science C. P. Hung Dave Peard Matthew Yao Advanced Semiconductor Engineering, Inc. Henkel Corporation Rockwell Collins

37 Materials & Processing Modeling & Simulation Fuad Doany Chair Chair IBM Corporation Chin C. Lee Bruce Kim Kannan Raj University of California, Irvine The University of Alabama [email protected] Sun Labs, Oracle [email protected] +1-205-348-4972 +1-949-824-7462 Masanobu Okayasu Assistant Chair Opnext Assistant Chair Suresh K. Sitaraman Diptarka Majumdar Georgia Institute of Technology Michael Leers Sun Chemical Corporation [email protected] Fraunhofer ILT +1-404-894-3405 [email protected] Ping Zhou +1-201-933-4500 x1258 Ramachandra Achar LDX Optronics, Inc. Carleton University Rajen Chanchani Shogo Ura Daniel de Araujo Consulant Kyoto Institute of Technology Nimbic, Inc. Choong Kooi Chee Soon Jang Intel Corporation Wenden Beyene Rambus FiconTEC USA Tim Chen Henning Braunisch Stefan Weiss Darbond Electronic Materials Co., Ltd. Intel Corporation Oclaro Switzerland AG Bing Dang Zhaoqing Chen Yi-Jen Chan IBM Corporation IBM Corporation ITRI Don Frye L. J. Ernst Z. Rena Huang Delft University of Technology Polyera Corp. Rensselaer Polytechnic Institute Robert Kao Xuejun Fan Lamar University Interactive Presentations National Taiwan University Chair Pradeep Lall Nam Pham Dong Wook Kim Auburn University Qualcomm IBM Corporation Michael Lamson [email protected] Yi-Shao Lai Consultant +1-512-286-8011 Advanced Semiconductor Engineering, Inc. Sheng Liu Assistant Chair Grace Yi Li Huazhong University of Science and Mark Poliks Intel Corporation Technology Endicot Interconnect Technology Yong Liu Kwang-Lung Lin [email protected] Fairchild Semiconductor Corporation National Cheng Kung University +1-607-755-2064 Erdogan Madenci Daniel D. Lu University of Arizona Swapan Bhattacharya Henkel Corporation Georgia Institute of Technology Tony Mak Hongtao Ma Middlesex Community College Rao Bonda Cisco Systems, Inc. Gamal Refai-Ahmed Amkor Technology Mikel Miller PreQual Tech Corporation Ibrahim Guven Draper Laboratory Sandeep Sane University of Arizona Intel Corporation Kyung-Wook Paik Mark Eblen KAIST Madhavan Swaminathan Kyocera America, Inc. Georgia Institute of Technology Mark Poliks Patrick Thompson Andrew A. O. Tay Endicott Interconnect Technologies, Inc. National University of Singapore Texas Instruments, Inc. Stephanie Potisek Jie-Hua Zhao Professional Development Dow Chemical Apple Courses Chair Yoichi Taira Optoelectronics IBM Corporation Chair Kitty Pearsall Andrew Shapiro IBM Corporation Quinn Tong JPL [email protected] Henkel Corporation [email protected] +1-512-286-7957 +1-818-393-7311 Yutaka Tsukada Assistant Chair i-PACKS Assistant Chair Jeffrey Suhling Henning Schroeder Auburn University Lejun Wang Fraunhofer IZM Medtronic, Inc. [email protected] [email protected] +1-334-844-3332 Myung Jin Yim +49-30-46403-277 Broadcom Corporation Harry G. Kellzi Eddie Kobeda Teledyne Microelectronic Technologies IBM Corporation Tieyu Zheng Intel Corporation Gee-Kung Chang Albert F. Puttlitz Georgia Institute of Technology Mechanical Eng. Consultant

38 63rd ECTC Call for Papers

First Call For Papers 63rd Electronic Components and Technology Conference www.ectc.net To be held May 28 - May 31, 2013 Cosmopolitan of Las Vegas, Las Vegas, Nevada, USA The Electronic Components and Technology Conference (ECTC) is the premier international electronics symposium that brings together the best in packaging, components and microelectronic systems science, technology and education in an environment of cooperation and technical exchange. ECTC is sponsored by the Components, Packaging and Manufacturing Technology (CPMT) Society of the IEEE. You are invited to submit abstracts that provide non-commercial information on new developments, technology and knowledge in the areas including, but not limited to as given below under each technical subcommittee name. Authors are encouraged to review the sessions of the previous ECTC programs to determine the committee selection for their abstracts.

Advanced Packaging: ing, wafer-level packaging, advanced wirebond interconnections, 3D integration, embedded, and wafer level packaging, flip chip, non-solder interconnections and connectors. advanced substrates, novel assembly technologies, interposers, TSVs, MEMS & sensors, optoelectronic & photovoltaic device Materials & Processing: packaging. Adhesives and adhesion, lead free solder, novel materials and processing; underfills, mold compounds, and dielectrics, emerg- Applied Reliability: 3D package reliability, characterization and test methods, ing materials and processing for 3D. interconnection reliability; solder and material characterization, and next generation/novel packaging reliability. Modeling & Simulation: Thermal, mechanical, electrical modeling and related measure- Assembly and Manufacturing Technology: ments, 3D/TSV design and modeling, fracture and warpage in Assembly challenges and solutions, manufacturing aspects of packages, and high-speed interconnects. 3D/TSV, manufacturing challenges of wafer thinning and flip chip processing. Optoelectronics: Optical system integration and photonic system-in-package, Electronic Components & RF: power efficient optical subsystems, fiber optical interconnects, Components (including embedded components) and optical-PCB, active optical cables, optical transceivers, modules for RF/THz systems and bio applications, metamaterials, wireless sensors, RFID, RF MEMS, flexible & optoelectronic assembly and reliability, high-efficiency LEDs and printed electronics, “green” RF electronics, wireless power high power lasers, integrated optical sensors, silicon photonics, transmission, power scavenging components, nano-based RF polymer and thin glass based waveguide technology. structures, and low-power RF designs. Interactive Presentations (formerly Posters): Emerging Technologies: Papers may be submitted on any of the listed major topics Emerging packaging concepts and technologies, emerging 3D and presentation of papers in an interactive format is highly packaging concepts, novel approaches to packaging, organic IC encouraged at ECTC. Interactive presentation papers allow & TFT, microfluidics and MEMs, anti-counterfeiting packaging, significant interaction between the presenter and attendees, and packaging for biosensing. and are especially suited for material that benefits from more explanation than is practical for oral presentations. Highly Interconnections: Design, structure, processes, performance, reliability (including rated abstracts not fitting into topic of an oral session, highly electromigration), and test of first- and second-level intercon- rated abstracts that are submitted specifically for interactive nections. Interconnections for 3D integration including TSV presentation, or abstracts that are selected at the discretion of and silicon interposers; interconnections in substrates, PCBs the program chair are included in the Interactive Presentation and systems. Solder bumping and Cu-pillar for flip chip packag- sessions.

You are invited to submit a <750-word abstract that describes the scope, Professional Development Courses content, and key points of your proposed paper via the website at www.ectc.net. In addition to abstracts for papers, proposals are solicited from individuals interested If you have any questions, contact: in teaching educational professional development courses (4 hours) on topics described in the Call for Papers. Using the format “Course Objectives/Course Beth Keser, 63rd ECTC Program Chair Outline/Who Should Attend,” 200-word proposals must be submitted via the Qualcomm, Inc. website at www.ectc.net by October 8, 2012. If you have any questions, contact: 5775 Morehouse Road San Diego, CA, USA Kitty Pearsall, 63rd ECTC Professional Development Courses Chair Phone: +1-858-658-3332 IBM Corporation Email: [email protected] IMAD 2C-40/Bldg 045 11400 Burnet Road Abstracts must be received by October 8, 2012. All abstracts must be submitted Austin, TX 78758 electronically at www.ectc.net. You must include the mailing address, business Phone: +1-512-286-7957 telephone number and email address of presenting author(s) and affiliations of all Fax: +1-512-973-4111 authors with your submission. Email: [email protected]

39 63rd Electronic Components & Technology Conference

The Cosmopolitan of Las Vegas Las Vegas, NV • May 28 - 31, 2013 The spectacular city of Las Vegas awaits you in 2013. As the entertainment capital of the world, there are over 100 spectacular live shows and entertainment venues to see daily. Las Vegas also touts world-class cuisine with an array of restaurants by world famous chefs. One of the newest attractions to Las Vegas is The Cosmopolitan hotel itself. Located directly adjacent to the world-renown Bellagio and its famed fountain show, the Cosmopolitan is of the newest hotels in Vegas. The hotel itself is a $4 billion stunning architectural statement with a chandelier bar that spans two stories. It also has some of the country’s top chefs, three distinctive pools, and 44,000 square feet of salon, spa, and fitness areas. Should you want to put aside Vegas’ bright lights and casinos, visit many of the natural wonders that surround this city. Over five major parks and wonders are in close proximity. From Red Rock Canyon to Death Valley or Hoover Dam to Grand Canyon National Park, there is so much to do and see.

Conference Sponsors Gala Reception Gold Sponsors

www.globalfoundries.com www.nanium.com Gala Reception Silver Sponors

www.amkor.com www.microsoft.com/Hardware www.murataamericas.com Program Sponsors

www.appliedmaterials.com www.corning.com www.globalfoundries.com

40 Conference Sponsors Luncheon Sponsor Tote Bags Sponsor Thumb Drive Sponsor

www.aseglobal.com www.allvia.com www.pactech.com

Media Sponsors Badge Lanyard Sponsor Internet Kiosk Sponsor Official Media Sponsor

wlpsolutions.dupont.com www.chipscalereview.com www.puretechnologies.com

Additional Media Sponsors Student Paper Sponsor Student Reception

www.electronics-cooling.com www.intel.com www.ibm.com

Refreshment Break Sponsors www.3dincites.com

www.engentaat.com http://www.inemi.org www.memsjournal.com

www.jsrmicro.com www.mediatek.com www.meptec.com

www.edacafe.com www.microsoft.com/Hardware www.namics.co.jp/e/

www.electroiq.com/semiconductors.html www.qualcomm.com www.semi.org

taptimes.com www.spil.com.tw www.statschippac.com

www.yole.fr www.tokamerica.com

As of May 7, 2012 41 SHERATON SAN DIEGO HOTEL & MARINA, SAN DIEGO, CALIFORNIA

42 Conference At A Glance

Monday, 5:00 p.m. – 6:00 p.m. 5:30 p.m. – 6:30 p.m. 6:30 p.m. – 7:30 p.m. May 28, 2012 ECTC Student Reception Technology Corner Reception Gala Reception Executive Center Break Area Pavilion 3:00 p.m. – 5:00 p.m. Bayview Lawn Area Rain Backup: Registration – Bayview Foyer 6:00 p.m. – 7:00 p.m. 7:00 p.m. – 9:00 p.m. Grande Ballroom B - C Marina Tower General Chair’s Speakers Plenary Session Reception (by Invitation) Harbor Island I & II Tuesday, Grande Ballroom A 8:00 p.m. – 10:00 p.m. May 29, 2012 Thursday, CPMT Seminar 7:30 p.m. – 9:00 p.m. Harbor Island I & II 6:45 a.m. – 8:15 a.m. Panel Session May 31, 2012 AM PD Courses Harbor Island I & II 7:00 a.m. – 5:00 p.m. Registration Only Speakers Prep Friday, Registration – Bayview Foyer, Wednesday, Marina 3 June 1, 2012 May 30, 2012 Marina Tower 7:00 a.m. – 5:00 p.m. 6:45 a.m. – 4:00 p.m. 7:00 a.m. – 7:45 a.m. Speakers Prep Today’s Speaker’s Breakfast 7:00 a.m. – 7:45 a.m. Conference Registration Marina 3 PD Courses Instructor and Bayview Foyer, Marina Tower Grande Ballroom B Proctors Briefing & Breakfast 7:00 a.m. – 7:45 a.m. Executive Center 4 7:00 a.m. – 7:45 a.m. 7:30 a.m. – 4:00 p.m. Today’s Speaker’s Breakfast Conference Registration Today’s Speaker’s Breakfast Grande Ballroom B 7:00 a.m. – 5:00 p.m. Bayview Foyer, Marina Tower Grande Ballroom B Speakers Prep – Marina 3 7:00 a.m. – 5:00 p.m. 8:00 a.m. – 4:00 p.m. 7:30 a.m. – Noon Speakers Prep – Marina 3 8:00 a.m. – Noon Companion Hospitality Room Conference Registration Rooms 411 and 415 (5th Floor) AM PD Courses 8:00 a.m. – 4:00 p.m. Bayview Foyer See page 8 for locations Companion Hospitality Room Marina Tower Rooms 411 and 415 (5th Floor) 8:00 a.m. – 11:40 a.m. Sessions 13, 14, 15, 16, 17, 18 9:00 a.m. – 5:00 p.m. 8:00 a.m. – Noon 8:00 a.m. – 11:40 a.m. See pages 14 thru 15 for iNEMI Roadmap Meeting Companion Hospitality Room Sessions 1, 2, 3, 4 , 5, 6 Locations Nautilus 3 See pages 10 thru 11 for Rooms 411 and 415 (5th Floor) Locations 9:00 a.m. – 11:00 a.m. 10:00 a.m. – Noon Session 39: Interactive 8:00 a.m. – 11:40 a.m. Special Session 9:00 a.m. – 11:00 a.m. Presentations 3 Sessions 25, 26, 27, 28, 29, 30 Nautilus I Session 37: Interactive Pavilion See pages 18 thru 19 for Presentations 1 Locations 10:00 a.m. – 10:20 a.m. Pavilion 9:00 a.m. – Noon AM PD Course Break Technology Corner Exhibits 8:30 a.m. – 10:30 a.m. Harbor Island Foyer 9:00 a.m. – Noon Pavilion Technology Corner Exhibits Student Poster Session Pavilion 11:00 a.m. – 1:15 p.m. 9:15 a.m. – 10:00 a.m. Grande Ballroom A Refreshment Break Conference Registration 9:15 a.m. – 10:00 a.m. 9:15 a.m. – 10:00 a.m. PM PD Courses Registration Only Refreshment Break Pavilion Bayview Foyer, Marina Tower Pavilion Refreshment Break Noon Southern Hemisphere Ballroom Noon Noon CPMT Luncheon Harbor Island Foyer PD Courses Luncheon ECTC Luncheon Grande Ballroom A - C Grande Ballroom A Grande Ballroom A - C Noon 1:30 p.m. – 4:00 p.m. Program Chair Luncheon 1:30 p.m. – 6:30 p.m. Technology Corner Exhibits 1:00 p.m. – 5:00 p.m. Technology Corner Exhibits Pavilion Grande Ballroom B - C Technology Corner Set-up Pavilion Pavilion 1:30 p.m. – 5:10 p.m. 1:30 p.m. – 5:10 p.m. 1:30 p.m. – 5:10 p.m. Sessions 19, 20, 21, 22, 23, 24 Sessions 31, 32, 33, 34, 35, 36 1:15 p.m. – 5:00 p.m. Sessions 7, 8, 9, 10, 11, 12 See pages 16 thru 17 for See pages 20 thru 21 for Conference Registration See pages 12 thru 13 for Locations Locations Bayview Foyer, Marina Tower Locations 2:00 p.m. – 4:00 p.m. 2:00 p.m. – 4:00 p.m. 2:45 p.m. – 3:30 p.m. 1:15 p.m. – 5:15 p.m. Session 40: Interactive Session 38: Interactive Refreshment Break PD PM Courses Presentations 4 Presentations 2 Harbor Island Foyer See page 8 for locations Pavilion Pavilion

3:00 p.m. – 3:20 p.m. 2:45 p.m. – 3:30 p.m. 2:45 p.m. – 3:30 p.m. *All ECTC events will be taking PM PD Course Break Refreshment Break Refreshment Break place in the Sheraton San Harbor Island Foyer Pavilion Pavilion Diego Hotel & Marina * 43 Sponsored by: Supported by: