Falcon Lib.Falcon(Sch 1):Page1 Schematic Rev Pcba Number Rev Bom Release Date

CR-1 : @FALCON_LIB.FALCON(SCH_1):PAGE1 SCHEMATIC REV PCBA NUMBER REV BOM RELEASE DATE

1.0 X8XXXXX-001 D XX/XX/06 PAGE CONTENTS PAGE CONTENTS [1] COVER PAGE [34][33] SB, SB, SMC PCIEX + SMM GPIO + JTAG [2] CLOCK DIAGRAM [3] RESET/ENABLE DIAGRAM [35] SB, FLASH + USB + SPI [4] CPU, CLOCKS + EEPROM + STRAPPING [37][36] SB, SB, STANDBY ETHERNET POWER + +AUDIO DECOUPLE + SATA [5] CPU, FSB [38] SB, MAIN POWER + DECOUPLE [6] CPU, FSB POWER + PLL POWER [39] SB OUT, ETHERNET [7] CPU, CORE POWER [8] CPU, POWER [40] SB OUT, AUDIO [9] CPU, DECOUPLING [41] SB OUT, FLASH FALCON [10] CPU, DECOUPLING [42] SB OUT, FAN + INFRARED + BUTTONS [11] CPU, DECOUPLING [43] CONN, AVIP [44] CONN, RJ45 + USB COMBO RETAIL [12] GPU, FSB [13] GPU, VIDEO + PCIEX + EEPROM [14][15] GPU, MEMORY CONTROLLER AC + DB [45][46] CONN, MISC, GAME V_5P0 PORTS DUAL, + MEMORY DEBUG PORTS MAPPING REV 1.0 [16] GPU, PLL POWER + FSB POWER [47] CONN, ODD AND HDD [17] GPU, CORE POWER + MEM POWER [48] CONN, ARGON + POWER FAB D [49] VREGS, INPUT + OUTPUT FILTERS [18] GPU, DECOUPLING [50] VREGS, CPU CONTROLLER [19] MEMORY, A (TOP) [51] VREGS, GPU OUTPUT PHASE 1,2,3 [20] MEMORY, A MIRRORED (BOTTOM) [21] MEMORY, B (TOP) [52] VREGS, GPU CONTROLLER [53][54] VREGS, GPUSWITCHED OUTPUT 1.8, PHASE 5.0V 1,2 [22] MEMORY, B MIRRORED (BOTTOM) [23] MEMORY, C (TOP) [24] MEMORY, C MIRRORED (BOTTOM) [55][56] VREGS, XDK, LINEAR DEBUG REGULATORS CONN [25] MEMORY, D (TOP) [57][58] DEBUG DEBUG BOARD, BOARD, CPU CPU + GPU CONN BREAKOUT [27][26] HANA, MEMORY, CLOCKS D MIRRORED + STRAPPING (BOTTOM) [59] DEBUG BOARD, CPU CONN + TERM [28] HANA, VIDEO + FAN + JTAG [60] DEBUG BOARD, CPU TERM [30][29] HANA, CONN, POWER HDMI + DECOUPLING [61] DEBUG BOARD, TITAN + YETI CONN [31] HANA, POWER + DECOUPLING [62][63] DEBUG XDK, BOARD, LEDS, GPU BDCM CONN PHY + TERM [32] POWER TRACE EMI CAPS [64] LABELS AND MOUNTING, PCI SWIZ [65-6] MEM QUAL BOARDS RULES: (APPLIED WHEN POSSIBLE) 2.)1.) WHENMSB TO POSSIBLE: LSB IS TOP INPUTS TO BOTTOM ON LEFT, OUTPUTS ON RIGHT FALCON 3.) ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING 4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS PLEASE REFER TO THE XENON DESIGN SPEC 6.)5.) TRANSIMITTERLANED SIGNALS NAME ARE GROUPEDUSED AS ONPREFIX SYMBOLS WITH RX AND TX CONNECTIONS 7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES 8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS BOM RELEASE DATE XX/XX/06 PB NUMBER X80XXXX-00X 9.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE 10.) SUFFIX _N FOR ACTIVE LOW OR N JUNCTION SIGNATURE DATE 12.) SUFFIX _P FOR P JUNCTION DRN BY MICROSOFT XBOX 13.) SUFFIX _EN FOR ENABLE 14.) 'CLK' FOR CLOCKS, 'RST' FOR RESETS CHK BY TITLE 15.) PWRGD FOR POWER GOOD ENGR SCH, PBA, FALCON DRAWING APVD PROJECT NAME PAGE REV FALCON_FABD APVD MICROSOFT Tue May 08 18:21:43 2007 FALCON_RETAIL 1/82 1.0 [PAGE_TITLE=COVER PAGE] APVD CONFIDENTIAL CR-2 : @FALCON_LIB.FALCON(SCH_1):PAGE2

RJ45/USB AVIP CONN CONN POWER FAN * THIS IS OUT OF DATE * CONN CONN

ENET_CLK(25MHZ) ENET CLOCK DIAGRAM PHY

I2S_MCLK(12.288MHZ) AUDIO ANA_XTAL_IN(27MHZ) I2S_BCLK(3.072MHZ) DAC

GPU VR DEBUG CONN ANA ANA BCKUP GPU VR STBY_CLK(48MHZ) CNTL SATA_CLK_REF(25MHZ) SB SATA_CLK_DP/DN(100MHZ) DVD PCIEX_CLK_DP/DN(100MHZ) SATA AUD_CLK(24.576MHZ) CONN CPU_CLK_DP/DN(100MHZ) RISCWATCH PIX_CLK_OUT_DP/DN(100MHZ) CONN GPU_CLK_DP/DN (100MHZ)

DVD PWR CONN MC_CLK1_DP/DN(800MHZ) ANA MC_CLK0_DP/DN(800MHZ) BCKUP MEM MD_CLK1_DP/DN(800MHZ) GPU CPU CPU VR CLAM C+D MD_CLK0_DP/DN(800MHZ)

1P8 VR

FLSH

HDD CONN

TITAN JTAG 3P3 VR MA_CLK1_DP/DN(800MHZ) MA_CLK0_DP/DN(800MHZ) MB_CLK1_DP/DN(800MHZ) MB_CLK0_DP/DN(800MHZ) CONN

VMEM VR MEM EFUSE VR CLAM A+B CPUCNTL VR 5P0 VR MPORT VR

GAME CONN

EJECT MEM MEM BIND ARGON IR SW CONN CONN SW CONN

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 11:47:32 2007 FALCON_RETAIL 2/82 1.0 CONFIDENTIAL CR-3 : @FALCON_LIB.FALCON(SCH_1):PAGE3

RJ45/USB AVIP CONN CONN POWER CONN CONN

FAN RESET/ENABLE DIAGRAM

ENET PHY ENET_RST_N AUD_CLAMP AUDIO AUD_RST_N DAC PSU_V12P0_EN

GPU VR EXT_PWR_ON_N

HANA_CLK_OEHANA_RST_N HANA VREG_GPU_EN_N GPUCNTL VR SMC_RST_N

VREG_GPU_PWRGD DVD SB EXT_PWR_ON_N SATACONN CPU_CHECKSTOP_N

SB_RST_N CPU_RST_N CPU_PWRGD GPU_RST_N RISCWATCH GPU_RST_DONE CONN DVDPWR CONN

CPU MEM_RST VR MEM_SCAN_EN MEM MEM_SCAN_TOP_EN SMC_DBG_EN CLAM C+D MEM_SCAN_BOT_EN GPU CPU VREG_3P3_EN VREG_CPU_PWRGD

HDD 3P3 CONN VR

MEM_RST MEM_SCAN_EN CPU_PWRGD

MEM_SCAN_TOP_EN MEM_SCAN_BOT_EN TITAN JTAG MEM CONN CONNDEBUG CLAM A+B VREG_1P8_EN_N VMEM VR EFUSE VR CNTL 5P0 VR CPU VR VREG_5P0_EN_N VREG_EFUSE_EN VREG_CPU_EN GAMECONN

EJECT MEM MEM BIND ARGON IR SW CONN CONN SW CONN

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=RESET/ENABLE DIAGRAM] Tue May 08 11:47:32 2007 FALCON_RETAIL 3/82 1.0 CONFIDENTIAL CR-4 : @FALCON_LIB.FALCON(SCH_1):PAGE4

CPU_RST_V1P1_N OUT CPU, CLOCKS + EEPROM + STRAPPING CPU_RST_N 1 R7R4 2 3.92K 1% 34 1 R6D4 2 IN 402 CH 1 CPU_CLK_DP 1 C7R112 IN 1 R7R16 2 0 CPU_CLK_DP_C FT2P1158 360PF 5% 10% 402 CH 6.19K 1% 50V FT2P12 1CPU_PWRGD 402 CH 2 EMPTY FTP 603 1 R7R10 2 34 CPU_PWRGD_V1P1_N 27 IN 1 R6D5 2 INFTP V_GPUCORE CPU_CLK_DN 3.92K 1% 402 CH 0 5% 1 R7R11 2 1 C7R113 402 CH 360PF 6.19K 1% U7D1 1OF10 IC V_GPUCORE 402 CH 50V CPU_CLK_DN_C CPU_CORE_IF_BGR_PLL TP7R1 2 EMPTY 27 LOKI PROBE 2 R6R4 1 603 AG23 CORE_CLK_DNCORE_CLK_DP CORE_IF_BGR_PLL AH15 1 1K 5% TP6D1 AF23 2 1 402 CH VREG_EFUSE_EN 1 PROBE 1 HARD_RESET_B R6R6 AF1 C7 2 POWER_GOOD EFU_POWERON R6R9 10K 2 R6R5 1 AD14 OUT SMT 10K 5% 10% CPU_FSB_HF_CLKOUT_DP 5% 1K 5% SMT FSB_CLK_DN FSB_CLK_DP FSB_HF_CLKOUT_DP EMPTY CH FSB_CLK_DP AH21 AF20 CPU_FSB_HF_CLKOUT_DN CH 402 FSB_CLK_DN FSB_HF_CLKOUT_DN OUT 402 2 AH20 AG20 56 2 CPU_FSB_IMPED_CAL_DP OUT 402 FSB_CLK_SEL FSB_IMPED_CAL_DP CPU_FSB_IMPED_CAL_DN CPU_FSB_CLK_SEL AE16 FSB_IMPED_CAL_DN AH23 EXT_CLK_EN AH22 CPU_EXT_CLK_EN AD16 1 CPU_PLL_BYPASS TP7R3 OUT PLL_BYPASS CPU_RES0_DP PROBE R6R8 AF14 RESISTOR0_DP OUT 1 AH12 CPU_RES0_DN 1 10K RESISTOR0_DN 1 PULSE_LIMIT_BYPASS AH13 2 5% R6R7 CPU_PULSE_LIMIT_BYPASS AG14 EMPTY 10K CHR7R17 TP7R4 5% 10K 1 CPU_VDDS0_DP SMT PROBE 402 2 1 1 5% DB7R2 AF11 1 CH R7D1 VDDS0_DP 402 R7D2 AH10 2 2 10K VDDS0_DN CPU_VDDS0_DN TP7R2 402 5% 10K V_GPUCORE PROBE 2 5% SYS_CONFIG0 AG2 SMT 1 CH CPU_SYS_CONFIG0 VDDS1_DP CPU_VDDS1_DPCPU_VDDS1_DN 402 EMPTY AH3 SYS_CONFIG1 VDDS1_DN AH1 2 2 402 CPU_SYS_CONFIG1 2 AE2 CPU_POST_IN<0..4> SMT DB7R1 0 AF8 POST_IN0 POST_IN1 TP V_GPUCORE 1 1 AG8 PSRO0_OUT CPU_PSRO0_OUT 1 AE14 1 R7R15 2 AH7 R7R8 3 AH8 POST_IN2 100 1 5% 100 AH9 POST_IN3 5% V_CPUCORE EMPTY POST_IN4 R7R9 402 EMPTY OUT 2 402 1 CPU_SPI_CLK OUT 2 4 CPU_SPI_SI SPI_SI 4 IN OUT CH 10K R7T18 C4 SPI_CLK B4 CPU_SPI_EN 4 LAYOUT: MUST BE ACCESSIBLE A3 4 402 5% SPI_SOSPI_EN CPU_SPI_SO 2 2 A4 10K R6E1 CH TEMP_DP CPU_TEMP_P 5%402 CPU_ANL_2 AH18 IN 28 10K CPU_ANL_1 ANL_1 TEMP_DN CPU_TEMP_N 28 2 4 AH19 OUT OUT 5% OUT AE22 ANL_2 CH OUT AD22 VID0 CPU_VREG_APS0 50 402 C5 1 57 A2 SRVID VID1 CPU_VREG_APS1 50 OUT B6 OUT CPU_VGATE AH14 VGATE VID2 A5 CPU_VREG_APS2 50 CPU_SRVID OUT 50 VID3 B5 CPU_VREG_APS3 OUT 50 CPU_TEST_EN AF2 TE VID4 A6 CPU_VREG_APS4 V_GPUCORE V_1P8 OUT VID5 C6 CPU_VREG_APS5 OUT 50

1 R7R1 2 1 1 1 FTP FT7T5 FTP FT7T2 1 R7R14 X806937-001 1 FTP FT7T4 1.40K 1% FTP FT7T1 1 CH 10K 1 FTP FT7T3 402 5% FTP FT7T7 1 1 1 1 1 CH CPU R7R1 R7R2 1 R7R2 2 402 R7R21 R7R12 R7R13 R7R22 R7R23 4 2 LOKI 1.40K 1K V_MEM 10K 10K 10K 10K 10K 1K 1% V_MEM 5% 5% 5% 5% 5% 402 CH ASPEN EMPTY 10K CH CH CH CH CH 402 402 402 402 2 2 2 2 2 402 1 1 V_MEM C6F1 .1UF R7F3 0 1 2 3 4 10% U7E1 EMPTY 6.3V 10K 2 X5R 5% CPU_SPI_CLK AT25020A 402 EMPTY 1 1 1 1 1 R6E2 CPU_SPI_CLK_R 6 SCK VCC 8 402 R7R20 R7R5 R7R3 R7R19 R7R18 CPU_SPI_SO_R 5 2 IN 1K 5% SDI 2 100 2 R7F7 1 10K 10K 10K 10K 10K 402 CH 5% 5% 5% 5% 5% 5% SDO OUT 4 7 HOLD_N* CPU_SPI_SI_R1K 5% CPU_SPI_SI EMPTY 4 EMPTY EMPTY EMPTY EMPTY R7E7 CPU_SPI_EN_R 1 CS_N* 402 CH 402 402 402 402 402 IN 1 2 2 2 2 2 CPU_SPI_SO 1K 5% 3 WP_N* GND 4 FTP 1 4 V_MEM 402 CH R7F4 FT7R4FTP V_MEM 1 3 FT7R6FTP X800552-001 1 2 FT7R2FTP 2 1 CH 1 1 R7E8 FT7R1FTP 1 402 1 0 5% 2 FT7R5 R7U3 10K 4 10K402 402 CH 5%

CH 2 R7F1 1

2 10K 5% R7F2 CPU_SPI_WP_N IN 402 EMPTY IN 1K 5% CPU_SPI_EN 402 CH

FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=CPU, CLOCKS + EEPROM + STRAPPING] Tue May 08 18:24:08 2007 FALCON_RETAIL 4/82 1.0 CONFIDENTIAL DRAWING CR-5 : @FALCON_LIB.FALCON(SCH_1):PAGE5

CPU, FSB

FSB_GP_CP0_CLK_DP U7D1 2OF10 IC FSB_CP_GP0_CLK_DP FSB_GP_CP0_CLK_DN FSB_CP_GP0_CLK_DN LOKI FSB_GP_CP0_FLAG_DP AE27 FSB_CP_GP0_FLAG_DP FSB_GP_CP0_FLAG_DN GP_CP0_CLK_DP CP_GP0_CLK_DP FSB_CP_GP0_FLAG_DN IN V28 GP_CP0_CLK_DN CP_GP0_CLK_DN AE28 IN V27 FSB_GP_CP0_DATA0_DP AB27 AH25 FSB_CP_GP0_DATA0_DP IN GP_CP0_FLAG_DP CP_GP0_FLAG_DP OUT FSB_GP_CP0_DATA0_DN AB28 GP_CP0_FLAG_DN CP_GP0_FLAG_DN AH26 FSB_CP_GP0_DATA0_DN OUT FSB_GP_CP0_DATA1_DP FSB_CP_GP0_DATA1_DP IN FSB_GP_CP0_DATA1_DN AB26 FSB_CP_GP0_DATA1_DN T26 GP_CP0_DATA0_DP CP_GP0_DATA0_DP OUT FSB_GP_CP0_DATA2_DP AB25 FSB_CP_GP0_DATA2_DP OUT IN T25 GP_CP0_DATA0_DN CP_GP0_DATA0_DN OUT 12 FSB_GP_CP0_DATA2_DN T28 GP_CP0_DATA1_DP CP_GP0_DATA1_DP AC27 FSB_CP_GP0_DATA2_DN 12 12 IN OUT 12 IN FSB_GP_CP0_DATA3_DP T27 GP_CP0_DATA1_DN CP_GP0_DATA1_DN AC28 FSB_CP_GP0_DATA3_DP FSB_GP_CP0_DATA3_DN FSB_CP_GP0_DATA3_DN OUT 12 IN U27 GP_CP0_DATA2_DP CP_GP0_DATA2_DP AD28 OUT 12 12 IN FSB_GP_CP0_DATA4_DP U28 AD27 FSB_CP_GP0_DATA4_DP 12 IN GP_CP0_DATA2_DN CP_GP0_DATA2_DN FSB_GP_CP0_DATA4_DN V26 GP_CP0_DATA3_DP CP_GP0_DATA3_DP AD25 FSB_CP_GP0_DATA4_DN 12 FSB_GP_CP0_DATA5_DP V25 AD26 FSB_CP_GP0_DATA5_DP 12 12 IN GP_CP0_DATA3_DN CP_GP0_DATA3_DN OUT 12 IN FSB_GP_CP0_DATA5_DN W27 AF28 FSB_CP_GP0_DATA5_DN 12 IN GP_CP0_DATA4_DP CP_GP0_DATA4_DP OUT 12 12 IN FSB_GP_CP0_DATA6_DP W28 GP_CP0_DATA4_DN CP_GP0_DATA4_DN AF27 FSB_CP_GP0_DATA6_DP OUT 12 Y26 12 FSB_GP_CP0_DATA6_DN GP_CP0_DATA5_DP CP_GP0_DATA5_DP AF25 FSB_CP_GP0_DATA6_DN OUT 12 12 Y25 12 FSB_GP_CP0_DATA7_DP GP_CP0_DATA5_DN CP_GP0_DATA5_DN AF26 FSB_CP_GP0_DATA7_DP OUT 12 IN Y28 12 12 FSB_GP_CP0_DATA7_DN GP_CP0_DATA6_DP CP_GP0_DATA6_DP AG27 FSB_CP_GP0_DATA7_DN OUT 12 IN Y27 12 AG28 OUT 12 IN GP_CP0_DATA6_DN CP_GP0_DATA6_DN OUT 12 IN FSB_GP_CP1_CLK_DP AA27 GP_CP0_DATA7_DP CP_GP0_DATA7_DP AH28 FSB_CP_GP1_CLK_DP 12 12 OUT 12 IN FSB_GP_CP1_CLK_DN AA28 GP_CP0_DATA7_DN CP_GP0_DATA7_DN AH27 FSB_CP_GP1_CLK_DN 12 IN OUT 12 12 E28 M28 OUT 12 12 12 IN FSB_GP_CP1_FLAG_DP E27 GP_CP1_CLK_DP CP_GP1_CLK_DP M27 FSB_CP_GP1_FLAG_DP 12 IN FSB_GP_CP1_FLAG_DN GP_CP1_CLK_DN CP_GP1_CLK_DN FSB_CP_GP1_FLAG_DN 12 12 OUT 12 J26 R28 OUT IN 12 FSB_GP_CP1_DATA0_DP J25 GP_CP1_FLAG_DP CP_GP1_FLAG_DP R27 FSB_CP_GP1_DATA0_DP 12 12 FSB_GP_CP1_DATA0_DN GP_CP1_FLAG_DN CP_GP1_FLAG_DN FSB_CP_GP1_DATA0_DN OUT 12 FSB_GP_CP1_DATA1_DP C26 J28 FSB_CP_GP1_DATA1_DP OUT 12 IN J27 12 12 FSB_GP_CP1_DATA1_DN C25 GP_CP1_DATA0_DP CP_GP1_DATA0_DP FSB_CP_GP1_DATA1_DN 12 IN C28 GP_CP1_DATA0_DN CP_GP1_DATA0_DN K28 OUT FSB_GP_CP1_DATA2_DP K27 FSB_CP_GP1_DATA2_DP OUT 12 IN C27 GP_CP1_DATA1_DP CP_GP1_DATA1_DP 12 FSB_GP_CP1_DATA2_DN L25 FSB_CP_GP1_DATA2_DN OUT 12 IN FSB_GP_CP1_DATA3_DP D27 GP_CP1_DATA1_DN CP_GP1_DATA1_DN FSB_CP_GP1_DATA3_DP 12 12 IN D28 L26 OUT 12 12 IN FSB_GP_CP1_DATA3_DN GP_CP1_DATA2_DP CP_GP1_DATA2_DP FSB_CP_GP1_DATA3_DN 12 E26 L28 OUT 12 IN GP_CP1_DATA2_DN CP_GP1_DATA2_DN 12 FSB_GP_CP1_DATA4_DP E25 L27 FSB_CP_GP1_DATA4_DP OUT 12 IN FSB_GP_CP1_DATA4_DN GP_CP1_DATA3_DP CP_GP1_DATA3_DP N25 FSB_CP_GP1_DATA4_DN OUT 12 12 IN F27 12 FSB_GP_CP1_DATA5_DP GP_CP1_DATA3_DN CP_GP1_DATA3_DN N26 FSB_CP_GP1_DATA5_DP OUT 12 IN F28 OUT 12 12 FSB_GP_CP1_DATA5_DN G26 GP_CP1_DATA4_DP CP_GP1_DATA4_DP N28 FSB_CP_GP1_DATA5_DN 12 12 GP_CP1_DATA4_DN CP_GP1_DATA4_DN N27 OUT 12 IN FSB_GP_CP1_DATA6_DP G25 FSB_CP_GP1_DATA6_DP OUT 12 IN G28 GP_CP1_DATA5_DP CP_GP1_DATA5_DP P28 12 12 FSB_GP_CP1_DATA6_DN FSB_CP_GP1_DATA6_DN OUT 12 IN FSB_GP_CP1_DATA7_DP G27 GP_CP1_DATA5_DN CP_GP1_DATA5_DN P27 FSB_CP_GP1_DATA7_DP 12 IN R25 OUT 12 12 H27 GP_CP1_DATA6_DP CP_GP1_DATA6_DP 12 IN FSB_GP_CP1_DATA7_DN R26 FSB_CP_GP1_DATA7_DN OUT 12 IN H28 GP_CP1_DATA6_DN CP_GP1_DATA6_DN OUT 12 12 IN GP_CP1_DATA7_DP CP_GP1_DATA7_DP OUT 12 GP_CP1_DATA7_DN CP_GP1_DATA7_DN

X806937-001

V_GPUCORE

1 C6R15 1 C6R18 1 C6R14 1 C6R25 1 C6R37 1 C6T19 1 C6T7 1 C6T27 1 C6T33 1 C6T32 1 C6R6 .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 2X5R 2 X5R 2X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 402 402 402 402 402 402 402 402 402 402 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=CPU, FSB] Tue May 08 18:24:09 2007 FALCON_RETAIL 5/82 1.0 CONFIDENTIAL CR-6 : @FALCON_LIB.FALCON(SCH_1):PAGE6

CPU, FSB POWER + PLL POWER

V_1P8 V_GPUCORE V_CPUPLL 4of10 U7D1 IC

FB7R1 1 1 1 C7R115 C7R116 C7R114 LOKI 1 2 VDD_FSB0 AA25 .1UF .1UF .1UF 1K FB 10% 10% 10% VDD_FSB1 AB24 0.2A 6.3V 6.3V 6.3V VDD_FSB2 603 2 X5R 2 X5R 2 X5R AC25 1 0.7DCR 1 402 VDD_FSB3 AD24 C7R1 C7R7 402 402 .1UF 2.2UF VDD_FSB4 AE25 10% 10% VDD_FSB5 AF24 6.3V 6.3V VDD_FSB6 AG25 2 X5R 2 X5R 402 ST7R1 603 VDD_FSB7 AH24 1 2 VDD_FSB8 B11 V_EFUSE VDD_FSB9 CPU_VDDE SHORT VDD_FSB10 B19B15 2 R7T2 1 VDD_FSB11 B23 VDD_FSB12 B27 FB6D1 10K 5% VDD_FSB13 C24 402 CH 1 2 VDD_IO VDD_FSB14 D8 AH4 1K FB VDD_FSB15 D12 0.2A 603 A7 VDDE VDD_FSB16 D16 1 0.7DCR 1 B7 C6D1 C6D4 VDDE_SEC VDD_FSB17 D20 .1UF 2.2UF VDD_FSB18 D25 V_CPU_CORE_HF_VDDA_PLL AG17 10% 10% CORE_HF_VDDA_PLL VDD_FSB19 E24 6.3V 6.3V V_CPU_CORE_HF_GNDA_PLL AF17 2 X5R 2 X5R CORE_HF_GNDA_PLL VDD_FSB20 F25 402 603 VDD_FSB21 G24 AH17 ST6D1 V_CPU_CORE_IF_VDDA_PLL CORE_IF_VDDA_PLL VDD_FSB22 H25 AH16 1 2 V_CPU_CORE_IF_GNDA_PLL CORE_IF_GNDA_PLL VDD_FSB23 J24 VDD_FSB24 K25 AD20 SHORT V_CPU_FSB_HF_VDDA_PLL FSB_HF_VDDA_PLL VDD_FSB25 L24 AE20 M25 V_CPU_FSB_HF_GNDA_PLL FSB_HF_GNDA_PLL VDD_FSB26 VDD_FSB27 N24 FB6R1 AD18 P25 FSB_IF_VDDA_PLL VDD_FSB28 1 2 V_CPU_FSB_IF_VDDA_PLL AE18 R24 FSB_IF_GNDA_PLL VDD_FSB29 1K FB V_CPU_FSB_IF_GNDA_PLL VDD_FSB30 T24 0.2A 603 AH11 U25 VDDA_RNG VDD_FSB31 1 0.7DCR 1 AG11 V24 C6R2 C6R4 V_CPU_VDDA_RNG GNDA_RNG VDD_FSB32 .1UF 2.2UF W25 10% 10% V_CPU_GNDA_RNG VDD_FSB33 Y24 6.3V 6.3V VDD_FSB34 2 X5R 2 X5R 402 ST6R1 603

1 2

SHORT

FB6R2

1 2 1K FB 0.2A 603 1 0.7DCR 1 C6R3 2.2UFC6R5 .1UF 10% 10% X806937-001 6.3V 6.3V 2 X5R 2 X5R 402 603 ST6R2

1 2

SHORT

FB7D1

1 2 1K FB 0.2A 603 0.7DCR C7D1 1 C7D2 1UF 2.2UF 10% 10% 16V 6.3V EMPTY 2 X5R 603 603 ST7D1

1 2

SHORT

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=CPU, FSB POWER + PLL POWER] Tue May 08 18:24:09 2007 FALCON_RETAIL 6/82 1.0 CONFIDENTIAL CR-7 : @FALCON_LIB.FALCON(SCH_1):PAGE7 CPU, CORE POWER

V_CPUCORE V_CPUCORE V_CPUCORE V_CPUCORE V_CPUCORE V_CPUVCS

IC U7D1 IC U7D1 IC 5of10 U7D1 6of10 7of10 LOKI LOKI LOKI P7 B1 AA2 VDD0 VDD48 AE6 K5 VDD96 VDD143 V9 VDD190 VCS0 AA4 VDD1 VDD49 AE8 K7 VDD97 VDD144 P9 V11 VDD191 VCS1 AA6 VDD2 VDD50 AE10 K9 VDD98 VDD145 P11 V13 VDD192 VCS2 B3C1 AA10AA8 VDD3 VDD51 AE12 K11 VDD99 VDD146 P13 V15 VDD193 VCS3 C2 VDD4 VDD52 AF4 K13 VDD100 VDD147 P15 V17 VDD194 VCS4 C3 AF7 K15 V19 D1 AA12 VDD5 VDD53 VDD101 VDD148 P17 VDD195 VCS5 D3 AA14 VDD6 VDD54 AF10 K17 VDD102 VDD149 P19 V21 VDD196 VCS6 D4 AA16 VDD7 VDD55 AF13 K19 VDD103 VDD150 P21 V23 VDD197 VCS7 D5 AA18 VDD8 VDD56 AG3 K21 VDD104 VDD151 P23 W2 VDD198 VCS8 E2 AA20 K23 VDD9 VDD57 AG6 VDD105 VDD152 R2 W4 VDD199 VCS9 AA22 AG9 W6 VCS10 E4 VDD10 VDD58 L2 VDD106 VDD153 R4 VDD200 AB1 W8 E6 VDD11 VDD59 AG12 L4 VDD107 VDD154 R6 VDD201 VCS11 R8 F1 AB3 VDD12 VDD60 G2 L6 VDD108 VDD155 W10 VDD202 VCS12 L8 F7 AB5 VDD13 VDD61 G4 VDD109 VDD156 R10 W12 VDD203 VCS13 F3 AB7 F5 VDD14 VDD62 G6 L10 VDD110 VDD157 R12 W14 VDD204 VCS14 AB9 G8 W16 VDD15 VDD63 L12 VDD111 VDD158 R14 VDD205 VCS15 AB11 R16 W18 VDD16 VDD64 G10 L14 VDD112 VDD159 VDD206 AB13 G12 L16 R18 W20 VDD17 VDD65 VDD113 VDD160 VDD207 AB15 G14 L18 R20 W22 AB17 VDD18 VDD66 VDD114 VDD161 VDD208 G16 L20 R22 Y1 VDD19 VDD67 VDD115 VDD162 VDD209 AB19 G18 L22 T1 Y3 VDD20 VDD68 VDD116 VDD163 VDD210 AB21 G20 M1 T3 Y5 VDD21 VDD69 VDD117 VDD164 AB23 G22 M3 T5 Y7 VDD211 VDD22 VDD70 VDD118 VDD165 AC2 M5 T7 Y9 VDD212 VDD119 VDD166 AC4 VDD23 VDD71 H1 M7 T9 Y11 VDD213 H3 VDD120 VDD167 AC6 VDD24 VDD72 M9 T11 Y13 VDD214 VDD25 H5 VDD121 VDD168 AC8 VDD73 H7 M11 T13 Y15 VDD215 AC10 VDD26 VDD74 H9 VDD122 VDD169 T15 Y17 VDD216 M13 VDD217 AC12 VDD27 VDD75 H11 M15 VDD123 VDD170 T17 Y19 VDD218 AC14 VDD28 VDD76 H13 M17 VDD124 VDD171 T19 Y21 VDD219 AC16 VDD29 VDD77 H15 M19 VDD125 VDD172 T21 Y23 AC18 VDD30 VDD78 H17 M21 VDD126 VDD173 T23 VDD220 VDD31 VDD127 VDD174 AC20 VDD79 H19 M23 U2 VDD128 VDD175 AC22 VDD32 VDD80 H21 N2 U4 AD1 VDD33 VDD81 H23 N4 VDD129 VDD176 U6 VDD130 VDD177 AD3 VDD34 VDD82 J2 N6 U8 AD5 VDD35 VDD83 J4 N8 VDD131 VDD178 U10 AD7 VDD36 VDD84 J6 N10 VDD132 VDD179 U12 AD9 VDD37 VDD85 J8 N12 VDD133 VDD180 U14 V7 AD11 VDD38 VDD86 J10 N14 VDD134 VDD181 U16 AD13 VDD39 VDD87 J12 N16 VDD135 VDD182 U18 AD15 VDD40 VDD88 J14 N18 VDD136 VDD183 U20 AD17 VDD41 VDD89 J16 N20 VDD137 VDD184 U22 AD19 VDD42 VDD90 J18 N22 VDD138 VDD185 V1 AD21 VDD43 VDD91 J20 P1 VDD139 VDD186 V3 AE4AD23 VDD44 VDD92 J22 P3 VDD140 VDD187 V5 AE1 VDD45 VDD93 K1 P5 VDD141 VDD188 VDD46 VDD94 K3 VDD142 VDD189 VDD47 VDD95 X806937-001 X806937-001 X806937-001

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:10 2007 FALCON_RETAIL 7/82 1.0 [PAGE_TITLE=CPU, CORE POWER] CONFIDENTIAL CR-8 : @FALCON_LIB.FALCON(SCH_1):PAGE8

CPU, POWER

IC U7D1 IC U7D1 IC U7D1 9of10 10 of 10 8of10 LOKI LOKI LOKI F22 VSS117 VSS175 L11 T4 VSS233 VSS291 Y20 AA1 VSS0 VSS58 AF3 F24 VSS118 VSS176 L13 T6 VSS234 VSS292 Y22 VSS1 VSS59 AF6 AA3 F26 VSS119 VSS177 L15 T8 VSS235 AA5 VSS2 VSS60 AF9 G1 VSS120 VSS178 L17 VSS236 VSS3 VSS61 AF12 T10 VSS121 VSS179 L19 T12 AA7 VSS4 VSS62 AF15 G3 VSS237 VSS122 VSS180 L21 T14 AA11 VSS5 VSS63 AF16 G5 VSS238 AA9 G7 VSS123 VSS181 L23 T16 AA13 VSS6 VSS64 AF18 VSS239 AA15 AF19 G9 VSS124 VSS182 M2 T18 VSS240 VSS7 VSS65 G11 T20 AA17 AF21 VSS125 VSS183 M4 VSS241 VSS8 VSS66 T22 AA19 AF22 G13 VSS126 VSS184 M6 VSS242 VSS9 VSS67 G15 M8 U1 AA21 AG4 VSS127 VSS185 VSS243 VSS10 VSS68 G17 AA23 AG7 VSS128 VSS186 M10 U3 VSS244 VSS11 VSS69 G19 U5 AA24 AG10 VSS129 VSS187 M12 VSS245 VSS12 VSS70 G21 U7 AA26 AG13 VSS130 VSS188 M14 VSS246 VSS13 VSS71 G23 AG15 VSS131 VSS189 M16 U9 VSS247 AB2 VSS14 VSS72 U11 AB4 AG16 H2 VSS132 VSS190 M18 VSS248 VSS15 VSS73 M20 U13 AB6 AG18 H4 VSS133 VSS191 VSS249 VSS16 VSS74 H6 M22 U15 AB8 AG19 VSS134 VSS192 VSS250 VSS17 VSS75 H8 M24 U17 AB10 AG21 VSS135 VSS193 VSS251 VSS18 VSS76 M26 U19 AB12 H10 VSS136 VSS194 VSS252 VSS19 VSS77 AG22 N1 U21 AB14 H12 VSS137 VSS195 VSS253 VSS20 VSS78 AG24 N3 U23 AB16 H14 VSS138 VSS196 VSS254 VSS21 VSS79 AG26 H16 N5 U24 AB18 B2 VSS139 VSS197 VSS255 VSS22 VSS80 H18 N7 U26 AB20 B9 VSS140 VSS198 VSS256 AB22 VSS23 VSS81 B13 H20 N9 V2 H22 VSS141 VSS199 N11 VSS257 AC1 VSS24 VSS82 B17 V4 H24 VSS142 VSS200 V6 VSS258 VSS25 VSS83 B21 N13 AC3 H26 VSS143 VSS201 N15 V8 VSS259 AC5 VSS26 VSS84 B25 J1 VSS144 VSS202 N17 VSS260 AC7 VSS27 VSS85 B28 V10 VSS145 VSS203 N19 VSS261 AC9 VSS28 VSS86 D2 J3 V12 VSS146 VSS204 N21 VSS262 AC11 VSS29 VSS87 D6 J5 V14 VSS147 VSS205 N23 VSS263 AC13 VSS30 VSS88 D10 J7 V16 VSS148 VSS206 VSS264 AC15 VSS31 VSS89 J9 P2 V18 D14 J11 VSS149 VSS207 V20 VSS265 AC17 VSS32 VSS90 D18 P4 J13 VSS150 VSS208 P6 V22 VSS266 AC19 VSS33 VSS91 D22 J15 VSS151 VSS209 P8 W1 VSS267 AC21 VSS34 VSS92 D24 J17 VSS152 VSS210 VSS268 AC23 VSS35 VSS93 D26 P10 W3 J19 VSS153 VSS211 W5 VSS269 AC24 VSS36 VSS94 E1 P12 J21 VSS154 VSS212 W7 AC26 VSS37 VSS95 P14 VSS270 E3 J23 VSS155 VSS213 P16 W9 VSS271 AD2 VSS38 VSS96 E5 VSS156 VSS214 P18 W11 VSS272 AD4 VSS39 VSS97 E7 K2 VSS157 VSS215 P20 W13 AD6 VSS40 VSS98 E9 K4 VSS273 K6 VSS158 VSS216 P22 W15 VSS274 AD8 VSS41 VSS99 E11 K8 VSS159 VSS217 P24 W17 VSS275 AD10AE3 VSS42 VSS100 E13 K10 VSS160 VSS218 P26 W19 VSS276 AD12AE5 VSS43 VSS101 E15 K12 VSS161 VSS219 R1 W21 VSS277 AE7 VSS44 VSS102 E17 K14 VSS162 VSS220 R3 W23 VSS278 AE9 VSS45 VSS103 E19 K16 VSS163 VSS221 R5 W24 VSS279 AE11 VSS46 VSS104 E21 K18 VSS164 VSS222 R7 W26 VSS280 VSS47 VSS105 E23 K20 VSS165 VSS223 R9 Y2 VSS48 VSS106 F2 VSS281 AE13 K22 VSS166 VSS224 R11 Y4 VSS282 VSS49 VSS107 F4 L9 K24 Y10 AE15 F6 VSS167 VSS225 R13 Y6 VSS283 VSS50 VSS108 K26 R15 Y12Y8 AE17 F8 VSS168 VSS226 VSS284 VSS51 VSS109 L1 R17 Y14 AE19 VSS169 VSS227 Y16 VSS285 VSS52 VSS110 F10 L3 R19 AE21 VSS170 VSS228 Y18 VSS286 VSS53 VSS111 F12 L5 R21 AE23 F14 VSS171 VSS229 VSS287 VSS54 VSS112 L7 R23 AE24 F16 VSS172 VSS230 VSS288 VSS55 VSS113 T2 AE26 F18 VSS173 VSS231 VSS289 VSS56 VSS114 F20 VSS174 VSS232 VSS290 VSS57 VSS115 VSS116 X806937-001 X806937-001 X806937-001

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=CPU, POWER] Tue May 08 18:24:10 2007 FALCON_RETAIL 8/82 1.0 CONFIDENTIAL CR-9 : @FALCON_LIB.FALCON(SCH_1):PAGE9

CPU, DECOUPLING V_CPUCORE

C7T94 C7E6 C7R3 C7R27 C6R7 1 2 1 2 1 2 1 2 1 2

4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 6.3V 6.3V 6.3V 6.3V 6.3V EMPTY X5R X5R X5R X5R 805 805 805 805 805

C7T93 C7D12 C7E1 C7D8 C6R10 1 2 1 2 1 2 1 2 1 2 4.7UF 4.7UF 10% 10% 4.7UF 10% 4.7UF 4.7UF 10% 6.3V 6.3V 6.3V 6.3V 10% 6.3V EMPTY X5R X5R X5R 805 805 805 805 X5R C7R119 805 C7T33 C7D19 1 2 C7D4 C7R28 1 2 1 2 1 2 1 2 4.7UF 10% 4.7UF 10% 4.7UF 10% 6.3V 4.7UF 10% 4.7UF 10% 6.3V 6.3V EMPTY 6.3VX5R 6.3V X5R EMPTY 805 805 805 805X5R 805 C7D18 C7R2 C7D3 C7R90 1 2 C7R29 1 2 1 2 1 2 1 2 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 6.3V 4.7UF 10% 6.3V 6.3V 6.3V EMPTY 6.3V X5R X5R X5R 805 X5R 805 805 805 805

C7E2 C7R120 1 2 C7D7 C7T4 C7E10 1 2 1 2 1 2 1 2 10% 4.7UF 10% 4.7UF 6.3V 4.7UF 4.7UF 10% 4.7UF 10% 6.3V X5R 6.3V 10% 6.3V 6.3V EMPTY 805 X5R X5R EMPTY 805 805 805 805

C7T32 C7E5 C7T83 C7R91 1 2 1 2 1 2 1 2

4.7UF 10% 4.7UF 4.7UF 10% 4.7UF 10% X5R 6.3V805 6.3V 6.3V 6.3V 10%X5R X5R X5R 805 805 805

C7R26 C7D5 C7D11 C7T5 1 2 1 2 1 2 1 2

4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 6.3V 6.3V 6.3V 6.3V X5R EMPTY X5R X5R 805 805 805 805

C7E9 C7R121 C7T84 C7R5 1 2 1 2 1 2 1 2

4.7UF 10% 4.7UF 80510% 4.7UF 10% 4.7UF 10% 6.3V 6.3V 6.3V 6.3V EMPTY EMPTY X5R X5R 805 805 805

C7T1 C7R23 C6T1 C7R4 1 2 1 2 1 2 1 2

4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R 805 805 805 805

C7R30 C7R25 C7T6 C7R24 1 2 1 2 1 2 1 2 4.7UF 10% 4.7UF 10% 4.7UF 10% 4.7UF 10% X5R6.3V 6.3V 805 6.3V 6.3VX5R X5R X5R 805 805 805

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=CPU, DECOUPLING] Tue May 08 18:24:11 2007 FALCON_RETAIL 9/82 1.0 CONFIDENTIAL CR-10 : @FALCON_LIB.FALCON(SCH_1):PAGE10

V_CPUCORE

CPU, DECOUPLING

C7R49 C7T9 C6R44 C7R52 C6T10 C7T21 1 2 1 2 1 2 1 2 1 2 1 2

10% 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF6.3V .1UF 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R X5R 402 402 402 402 402 402

C7R44 C7R22 C6R32 C7R51 C7T22 C6T2 1 2 1 2 1 2 1 2 1 2 1 2 10% .1UF 10% .1UF 10% .1UF .1UF 10% .1UF 10% 10%.1UF 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R 402 402 402 402 402 402 X5R

C6R29 C7R35 C7R102 C7R50 C7T27 C7T10 1 2 1 2 1 2 1 2 1 2 1 2

.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R X5R 402 402 402 402 402 402

C6R28 C7R34 C7R81 C6T6 C7R48 C7R111 1 2 1 2 1 2 1 2 1 2 1 2

.1UF 10% 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 6.3V .1UF6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R 402 402 402 402 402 X5R 402 C6R17 C7R19 C7R68 C6R36 C7T51 1 2 1 2 1 2 1 2 1 2

.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R 402 402 402X5R 402 402

C7R76 C7R43 C7R69 C6R23 C7T37 1 2 1 2 1 2 1 2 1 2

.1UF 10% X5R.1UF 10% .1UF 10% .1UF 10% .1UF 10% 6.3V 4026.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R 402 402 402 402

C6R39 C6R16 C7R57 C7R58 C7R89 .1UF 1 2 1 2 1 2 1 2 1 2 X5R 10% .1UF 10% .1UF 10% .1UF .1UF 6.3V 6.3V 6.3V 6.3V 6.3V 10% X5R X5R X5R 402 X5R402 402 402 10%402

C6R42 C6R19 C6R20 C7R59 C6T25 1 2 1 2 1 2 1 2 1 2

.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R 402 402 402 402 402

C7R67 C7R61 C6R21 C7R60 C7R99 1 2 1 2 1 2 1 2 1 2 X5R 402 .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R 402 10% 402 402 402

C7T3 C6R35 C6T26 C7T2 C7R100 .1UF 1 2 1 2 1 2 1 2 1 2 X5R 402 10% .1UF .1UF 10% .1UF 10% .1UF 10% 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R 402 402 402 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:11 2007 FALCON_RETAIL 10/82 1.0 CONFIDENTIAL

[PAGE_TITLE=CPU, DECOUPLING] CR-11 : @FALCON_LIB.FALCON(SCH_1):PAGE11

V_CPUCORE V_CPUVCS CPU, DECOUPLING

N:EMPTIES

C7R31 C7T25 C7T38 C7T58 C6T17 C7R66 C7T7 C7T29 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R EMPTY X5R X5R X5R402 402 402 402 402 402 X5R 402 X5R C7T54 C6T24 C7R110 C6R24 C7R95402 C6T4 C7T14 C7T30 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

.1UF 10% .1UF 10% .1UF 10% .1UF 10% 10% 10% .1UF 10% .1UF 10% 6.3V 6.3V 6.3V 6.3V .1UF6.3V .1UF6.3V 6.3V 6.3V X5R X5R X5R X5R EMPTY 402X5R 402 402 402 402 402X5R 402 402X5R

C6T16 C6T13 C6T14 C7T56 C6T18 C7T15 C7T12 C7T31 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

.1UF 10% .1UF 10% 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 6.3V 6.3V .1UF6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R EMPTY X5R X5R 402 402 402 402 402 402 402 402

C7R56 C7R20 C7T28 C7T50 C7R101 C7T24 C7T13 1 2 1 2 1 2 1 2 1 2 1 2 1 2 .1UF .1UF 10% .1UF 10% .1UF 10% .1UF 10% 10% .1UF 10% .1UF 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R EMPTY X5R 402 402 402 402 402 402 X5R 402 C6R26 C7R42 C7R14 C7R106 C7T57 C6T11 C7T8 1 2 1 2 1 2 1 2 1 2 1 2 1 2 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R EMPTY X5R 402 402 402 402 402 402 402

C6T9 C7R41 C7T49 C7T11 C7T55 C7R74 C7T16 1 2 1 2 1 2 1 2 1 2 1 2 1 2

10% .1UF 10% 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF6.3V 6.3V .1UF6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R EMPTY X5R 402 402 402 402 402 402 402

C6T3 C7R40 C6T22 C7T40 C7R83 C6R30 C7T17 1 2 1 2 1 2 1 2 1 2 1 2 1 2 10% .1UF 10% .1UF 10% 10% .1UF 10% .1UF10% .1UF 10% .1UF 6.3V 6.3V .1UF6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R X5R 402 402 402 402 402 EMPTY402 402

C7R21 C7R39 C7T41 C7R75 C7T39 C7R82 C7T18 1 2 1 2 1 2 1 2 1 2 1 2 1 2

.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 6.3V 6.3V 6.3V402 6.3V 6.3V 6.3V 6.3V X5R X5R402 X5R X5R X5R EMPTY X5R 402 402 402 402 402

C6R41 C6T21 C7R33 C7T47 C7T26 C7T23 C7T19 1 2 1 2 1 2 1 2 1 2 1 2 1 2

.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R EMPTY X5R 402 402 402 402 402 402 402 10%

C6R13 C6R12 C7R32 C7T46 C7T48 C7R65 C7T20 1 2 1 2 1 2 1 2 1 2 1 2 1 2 X5R .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF .1UF 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R EMPTY X5R 402 402 402 402 402 402 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=CPU, DECOUPLING] Tue May 08 18:24:12 2007 FALCON_RETAIL 11/82 1.0 CONFIDENTIAL CR-12 : @FALCON_LIB.FALCON(SCH_1):PAGE12

V_MEM

V_GPUCORE GPU, FSB MEM SCAN BUFFERS STUFFED EMPTY R2R5: 10K 0OHM

2 R5C12 1 V_MEM 1 R2E5 2 1K 5% 1 402 0 5% 1 1OF12 CH C2E4 402 CH R2R5 1 2 0 R5R1 IC 1K 2 R5C11 1 U4D1 5% 5% GPU Y2 VERSION 1 .1UF 10% CH FSB_BYPCLK_DP U2E2 EMPTY EMPTY 1K 5% FSB_BYPCLK_DN 6.3V 402 402 CH 2 402 B29 FSB_BYPCLK_DP 402 SN74LVC1G125 2 FSB_BYPCLK_SEL MEM_SCAN_EN_BUFF MEM_SCAN_EN A29 FSB_BYPCLK_DN X5R 5 VCC D25 4 25 26 FSB_BYPCLK_SEL 2 FSB_CP_GP0_CLK_DP FSB_GP_CP0_CLK_DP 13 IN IN OUT 19 20 21 22 23 24 1 FSB_CP_GP0_CLK_DN FSB_GP_CP0_CLK_DN 3 GND OE_N 1 IN J34 CP_GP0_CLK_DP GP_CP0_CLK_DP P33 R5R2 FSB_CP_GP0_FLAG_DP J33 FSB_GP_CP0_FLAG_DP IN CP_GP0_CLK_DN GP_CP0_CLK_DN P34 OUT 1 1 1K FSB_CP_GP0_FLAG_DN FSB_GP_CP0_FLAG_DN OUT IN CP_GP0_FLAG_DP GP_CP0_FLAG_DP L34 OUT X801565-001 5% J30 L33 R4F8 R2D11 OUT 5 CH CP_GP0_FLAG_DN GP_CP0_FLAG_DN OUT 5 5 402 FSB_CP_GP0_DATA0_DP J29 FSB_GP_CP0_DATA0_DP 5 1K 1K 5 IN 5 5% 5% 5 FSB_CP_GP0_DATA0_DN M29 T29 FSB_GP_CP0_DATA0_DN 5 2 CP_GP0_DATA0_DP GP_CP0_DATA0_DP OUT CH IN FSB_CP_GP0_DATA1_DP M30 T30 FSB_GP_CP0_DATA1_DP CH 5 CP_GP0_DATA0_DN GP_CP0_DATA0_DN OUT 5 402 IN T31 5 IN FSB_CP_GP0_DATA1_DN L32 CP_GP0_DATA1_DP GP_CP0_DATA1_DP FSB_GP_CP0_DATA1_DN OUT 5 2 2 5 FSB_CP_GP0_DATA2_DP L31 T32 FSB_GP_CP0_DATA2_DP 5 402 5 CP_GP0_DATA1_DN GP_CP0_DATA1_DN 5 5 FSB_CP_GP0_DATA2_DN K33 CP_GP0_DATA2_DP GP_CP0_DATA2_DP R34 FSB_GP_CP0_DATA2_DN 5 5 FSB_CP_GP0_DATA3_DP K34 FSB_GP_CP0_DATA3_DP 5 5 CP_GP0_DATA2_DN GP_CP0_DATA2_DN R33 OUT 5 L30 5 FSB_CP_GP0_DATA3_DN CP_GP0_DATA3_DP GP_CP0_DATA3_DP R29 FSB_GP_CP0_DATA3_DNOUT 5 5 L29 R30 5 5 FSB_CP_GP0_DATA4_DP CP_GP0_DATA3_DN GP_CP0_DATA3_DN FSB_GP_CP0_DATA4_DPOUT 5 5 J31 N34 5 FSB_CP_GP0_DATA4_DN CP_GP0_DATA4_DP GP_CP0_DATA4_DP FSB_GP_CP0_DATA4_DN OUT 5 FSB_CP_GP0_DATA5_DP J32 N33 FSB_GP_CP0_DATA5_DP 5 5 IN CP_GP0_DATA4_DN GP_CP0_DATA4_DN OUT OUT 5 5 K30 P29 5 IN FSB_CP_GP0_DATA5_DN FSB_GP_CP0_DATA5_DNOUT OUT 5 K29 CP_GP0_DATA5_DP GP_CP0_DATA5_DP P30 OUT 5 IN FSB_CP_GP0_DATA6_DP CP_GP0_DATA5_DN GP_CP0_DATA5_DN FSB_GP_CP0_DATA6_DP OUT 5 IN H34 N31 FSB_CP_GP0_DATA6_DN CP_GP0_DATA6_DP GP_CP0_DATA6_DP FSB_GP_CP0_DATA6_DN OUT 5 IN H33 M34N32 FSB_GP_CP0_DATA7_DP 5 V_MEM 5 IN FSB_CP_GP0_DATA7_DP H31 CP_GP0_DATA6_DN GP_CP0_DATA6_DN OUT 1 R2D12 2 5 IN M33 OUT 5 5 FSB_CP_GP0_DATA7_DN CP_GP0_DATA7_DP GP_CP0_DATA7_DP FSB_GP_CP0_DATA7_DN 5 IN H32 0 5% CP_GP0_DATA7_DN GP_CP0_DATA7_DN 5 IN OUT 5 C2R12 402 CH FSB_CP_GP1_CLK_DP AC33 FSB_GP_CP1_CLK_DP 1 2 5 IN V33 FSB_GP_CP1_CLK_DN OUT 5 5 IN FSB_CP_GP1_CLK_DN T33V34 CP_GP1_CLK_DP GP_CP1_CLK_DP AC34 5 5 IN OUT 5 FSB_CP_GP1_FLAG_DP T34 FSB_GP_CP1_FLAG_DP .1UF 10% 5 5 IN CP_GP1_CLK_DN GP_CP1_CLK_DN Y29 OUT 5 6.3V U2D1 EMPTY FSB_CP_GP1_FLAG_DN FSB_GP_CP1_FLAG_DN 5 5 CP_GP1_FLAG_DP GP_CP1_FLAG_DP Y30 5 X5R IN 402 SN74LVC1G125 5 CP_GP1_FLAG_DN GP_CP1_FLAG_DN OUT 5 5 5 IN 5 AC28 5 5 IN FSB_CP_GP1_DATA0_DP FSB_GP_CP1_DATA0_DP OUT 5 VCC AA31 MEM_SCAN_TOP_EN4 IN FSB_CP_GP1_DATA0_DN AA32 CP_GP1_DATA0_DP GP_CP1_DATA0_DP AC29 FSB_GP_CP1_DATA0_DN OUT 5 MEM_SCAN_TOP_EN_BUFF 2 IN OUT 23 5 5 IN 25 FSB_CP_GP1_DATA1_DP CP_GP1_DATA0_DN GP_CP1_DATA0_DN AD29 FSB_GP_CP1_DATA1_DP OUT 3 GND OE_N 1 5 IN Y33 OUT 5 IN FSB_CP_GP1_DATA1_DN Y34 CP_GP1_DATA1_DP GP_CP1_DATA1_DP AD30 FSB_GP_CP1_DATA1_DN 5 1 1 5 OUT 5 OUT IN FSB_CP_GP1_DATA2_DP W30 CP_GP1_DATA1_DN GP_CP1_DATA1_DN AD34 FSB_GP_CP1_DATA2_DP IN FSB_CP_GP1_DATA2_DN OUT R4F7 R2T2 5 CP_GP1_DATA2_DP GP_CP1_DATA2_DP AD33 FSB_GP_CP1_DATA2_DN X801565-001 IN W29 OUT 1K 1K FSB_CP_GP1_DATA3_DP W33 CP_GP1_DATA2_DN GP_CP1_DATA2_DN AB29 FSB_GP_CP1_DATA3_DP 5% 5% IN OUT 13 IN FSB_CP_GP1_DATA3_DN W34 CP_GP1_DATA3_DP GP_CP1_DATA3_DP AB30 FSB_GP_CP1_DATA3_DN CH CH AC32 OUT IN FSB_CP_GP1_DATA4_DP V29 CP_GP1_DATA3_DN GP_CP1_DATA3_DN FSB_GP_CP1_DATA4_DP OUT 402 402 19 21 IN V28 AC31 2 2 IN FSB_CP_GP1_DATA5_DPFSB_CP_GP1_DATA4_DN CP_GP1_DATA4_DP GP_CP1_DATA4_DP FSB_GP_CP1_DATA4_DN OUT U33V31 CP_GP1_DATA4_DN GP_CP1_DATA4_DN AA29 FSB_GP_CP1_DATA5_DP OUT V32 AA30 IN FSB_CP_GP1_DATA5_DN U34 CP_GP1_DATA5_DP GP_CP1_DATA5_DP FSB_GP_CP1_DATA5_DN OUT V_GPUCORE5 U30 AB33 OUT 5 IN FSB_CP_GP1_DATA6_DNFSB_CP_GP1_DATA6_DP CP_GP1_DATA5_DN GP_CP1_DATA5_DN FSB_GP_CP1_DATA6_DP IN U29 CP_GP1_DATA6_DP GP_CP1_DATA6_DP AB34 FSB_GP_CP1_DATA6_DN OUT 5 IN CP_GP1_DATA6_DN GP_CP1_DATA6_DN AA34 IN FSB_CP_GP1_DATA7_DNFSB_CP_GP1_DATA7_DP AA33 FSB_GP_CP1_DATA7_DNFSB_GP_CP1_DATA7_DP 5 IN T28 CP_GP1_DATA7_DP GP_CP1_DATA7_DP CP_GP1_DATA7_DN GP_CP1_DATA7_DN 1 R4R9 2 FSB_IMPED_CAL FSB_IMPED_NCAL AA28 49.9 1% 1 FSB_IMPED_PCAL 402 EMPTY FSB_IMPED_NCAL R5R3 1 V_MEM 4.87K C4R70 1000PF X02125-001 1% V_MEM GPU R5R3 R4R9 10% 1 R2R6 2 CH 2 50V B13L STUFF EMPTY 402 0 5% 2 X7R402 1 1 GUNGA EMPTY STUFF C2D5 402 CH 1 2 R4U6 R2T1 1K 1K .1UF 10% 5% 5% 6.3V U2R1 EMPTY CH X5R CH 402 SN74LVC1G125 402 402 2 2 V_GPUCORE 5 VCC 4 13 MEM_SCAN_BOT_EN_BUFF 2 IN OUT 20 22 24 FSB DECOUPLING OUT 26 3 GND OE_N 1 IN MEM_SCAN_BOT_EN X801565-001 C4R27 C4R33 C4R45 C4T22 C5R18 C4R65 C4R60 C4T13 .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF 10% 10% 10% 10% 10% 10% 10% 10% 6.3VX5R 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 13 IN 402 X5R X5R X5R X5R X5R X5R X5R GPU_SCAN_BUFF_EN_N 402 402 402 402 402 402 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=GPU, FSB] Tue May 08 18:24:13 2007 FALCON_RETAIL 12/82 1.0 CONFIDENTIAL CR-13 : @FALCON_LIB.FALCON(SCH_1):PAGE13

GPU, VIDEO + PCIEX + EEPROM + JTAG

2OF12 PEX_GPU_SB_L1_DP U4D1 C4D1 GPU Y2 VERSION 1 1 2 58 1 GPU_CLK_DP NB_CLK_DP 1 FT2P14FTP IN GPU_CLK_DN A25 IC FTP FT2P13 IN NB_CLK_DN .1UF 10% 27 A24 6.3V X5R GPU_RST_N27 E11 D14 GPU_RST_DONE 34 PEX_SB_GPU_L1_DP RST_IN_N* RST_DONE OUT 402 IN PEX_SB_GPU_L1_DN PEX_GPU_SB_L1_DN OUT B27 PEX_RX1_DP PEX_TX1_DP B26 PEX_GPU_SB_L1_DP_C C4D2 1 2 IN A27 PEX_RX1_DN PEX_TX1_DN A26 PEX_GPU_SB_L1_DN_C OUT 33 58 IN PEX_SB_GPU_L0_DNPEX_SB_GPU_L0_DP 33 B23 PEX_RX0_DP PEX_TX0_DP B22 PEX_GPU_SB_L0_DP_C IN PEX_GPU_SB_L0_DN_C .1UF 10% IN A23 PEX_RX0_DN PEX_TX0_DN A22 6.3V X5R 1 R5D1 2 PEX_PCAL 402 A28 PEX_PCAL 33 1 B28 PEX_GPU_SB_L0_DP 562 1% R5D2 2 PEX_NCAL PEX_NCAL C4D3 1 2 402 CH V_GPUPCIE B21 OUT 33 58 2K 1% PEX_ICAL B14 GPU_PIX_CLK_1X OUT 2834 402 CH D10 PIX_CLK_OUT .1UF 10% B17 PIX_DATA<14..0> OUT 6.3V C10 PIX_CLK_IN_DP 28 1 R4R3 2 A17 14 X5R PEX_ICAL PIX_CLK_IN_DN PIX_DATA14 13 402 1.47K PIX_DATA13 D16 V_MEM B16 12 C4D7 402 CH PIX_DATA12 1 2 OUT 27 ANA_PIX_CLK_2X_DP 11 PEX_GPU_SB_L0_DN 33 58 IN PIX_DATA11 A16 33 27 IN ANA_PIX_CLK_2X_DN D15 10 1 28 C22 PIX_DATA10 .1UF 10% 33 GPU_TEMP_P B15 9 6.3V 28 IN NB_THERMD_P PIX_DATA9 R4D1 GPU_TEMP_N C23 A15 8 1K X5R 33 28 OUT NB_THERMD_N PIX_DATA8 402 EDRAM_TEMP_P G14 A14 7 5% 28 IN ED_THERMD_P PIX_DATA7 OUT EDRAM_TEMP_N G15 D13 EMPTY ED_THERMD_N PIX_DATA6 B13 6 402 5 2 GPU R5D2 R5D1 R4R3 R4T1 R4R8 PIX_DATA5 A13 4 DB4D1 1% 1 PIX_DATA4 B12 3 B13L 2K, 1% 562, 1% 1.47K, 1% 40.2, 1% 40.2, 1% TP PIX_DATA3 A12 1 GUNGA 49.9, 1% EMPTY EMPTY 240, 1% 240, 1% 2 PIX_DATA2 1 R4D2 PIX_DATA1 D11 0 1K PIX_DATA0 OUT 28 5% A11 OUT 1 R3C28 2 GPU_TCLK_R 28 CH IN VSYNC_OUT B11GPU_VSYNC_OUTGPU_HSYNC_OUT 402 1.27K 1% HSYNC_OUT 2 402 CH GPU_SPI_SI IN G16 G17 GPU_SPI_SO SROM_SO SROM_EN_PSRO_OUT GPU_SROM_EN_PSRO_OUTE16 1 R4T1 2 34 MEM_CALA SROM_SI E15 13 SROM_SCLK GPU_SPI_CLKE14 13 40.2 1% SROM_CS OUT 13 402 CH GPU_SPI_CS_N 1 R4R8 2 MEM_CALB OUT OUT 13 19 40.2 1% AG16 AG11 20 21 22 23 24 25 26 V8 AN13 402 CH MEM_CALA MEM_RST MEM_RST OUT 12 MEM_CALB MEM_SCAN_EN G9 G10 12 MEM_SCAN_EN_BUFF OUTOUT 12 E13 MEM_SCAN_OEN_A OUT GPU_TDO D12 MEM_SCAN_TOP_EN_BUFF GPU_TCLK TDOTCLK MEM_SCAN_OEN_B 2 2 GPU_TDI E12 TDI MEM_SCAN_BOT_EN_BUFF G12 TMS R2E1 R4F6 GPU_TRST G11 TRST 1K 1K GPU_TMS 5% 5% V_MEM V_MEM GPU_TRST_ED G13 TRST_ED CH CH 402 402 1 1 1 1 R2E2 R2E4 X02125-001 1.5K 1.5K 1% 1% CH J2D2 CH J5C2 402 402 2X3HDR 2 2X4HDR 2 V_1P8 1 2 GPU_SPI_SI 13 1 2 OUT 3 GPU_SPI_WP_N 13 V_1P8 3 4 OUT 4 5 6 5 6 1 7 8 HDR 1 R4C7 1 13 1 R2D10 HDR 1.5K R2D91.5K R2E3 1 1.5K C5C3 V_MEM 1% 10K V_1P8 .1UF 131% 1% 4025% CH 2 10% CH CH CH 6.3V 402 402 U4C1 EMPTY 2 2 402 X5R VIDEO DECOUPLING 2 2 402 R5C5 GPU_SPI_CLK_R AT25020A 13 6 SCK 8 GPU_SPI_SO_R 5 VCC GPU_SPI_CLK 1K SDI 2 C3C2 C3R9 C4R26 C3R8 IN 402 CH5% SDO OUT X5R 7 4.7UF .1UF .1UF .1UF R5C8 HOLD_N* GPU_SPI_SI 10% 80510% 10% 10% GPU_SPI_CS_N_R 1 CS_N* 6.3V 6.3V 6.3V 6.3V 13 X5R 3 4 2 X5R X5R IN GPU_SPI_SO 1K 5% WP_N* GND 402 402 402 402 CH V_1P8 R4C6 R4C3 X800552-001 10K 5% IN 2 R4C4 1 1K 5% CH 1 GPU_SPI_CS_N1 402 CH 10K 5% 402 1 R5C10 R5P3 402 CH 12 OUT 10K 10K 5% 5% 2 R4C5 1 13 GPU_SCAN_BUFF_EN_N CH CH IN 402 402 10K 5% 2 2 402 EMPTY GPU_SPI_WP_N

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=GPU, VIDEO + PCIEX + EEPROM + JTAG] Tue May 08 18:24:13 2007 FALCON_RETAIL 13/82 1.0 CONFIDENTIAL CR-14 : @FALCON_LIB.FALCON(SCH_1):PAGE14

GPU, MEMORY CONTROLLER 0 PARTITION A & B

3OF12 IC U4D1 4OF12 IC U4D1 GPU Y2 VERSION 1 GPU Y2 VERSION 1

20 19 MA_DQ31 AP19 MA_DQ31 22 21 MB_DQ31 AN27 MB_DQ31 MA_DQ30 AN19 MB_DQ30 AP28 20 19 MA_DQ28 MA_DQ30 22 21 BI MB_DQ30 BI MA_DQ29 AL18 MB_DQ29 AP27 20 19 BI MA_DQ27 MA_DQ29 22 21 BI MB_DQ28 MB_DQ29 20 19 BI MA_DQ26 AN20 MA_DQ28 22 21 BI MB_DQ27 AP29 MB_DQ28 20 19 BI AN18 MA_DQ27 22 21 BI AL25 MB_DQ27 BI BI MB_DQ26 20 19 AM20 MA_DQ26 22 21 AP31 MB_DQ26 BI MA_DQ25 AN17 BI MB_DQ25 AM25 20 19 BI MA_DQ25 22 21 BI MB_DQ25 MA_DQ24 AL20 MB_DQ24 AP32 20 19 BI MA_DQ24 22 21 BI AP30 MB_DQ24 MA_WDQS3 AP20AM18 MB_WDQS3 20 19 OUT MA_WDQS3 22 21 OUT MB_WDQS3 20 19 MA_RDQS3 22 21 MB_RDQS3 AN26 IN MA_DM3 AP18 MA_RDQS3 IN MB_DM3 AP26 MB_RDQS3 20 19 OUT MA_DM3 MA_CLK1_DP 22 21 OUT MB_DM3 AH10 AM33 MA_DQ23 AP15 MA_CLK1_DN MB_DQ23 AM23 MB_CLK1_DP 20 19 MA_DQ23 MA_CLK1_DP AK10 MA_CLK0_DP OUT 20 22 21 BI MB_DQ23 MB_CLK1_DP AM34 22 20 19 MA_DQ22 AN15 AN12 20 22 21 BI MB_DQ22 AP23 MB_CLK1_DN 22 MA_DQ21 MA_DQ22 MA_CLK1_DN MA_CLK0_DN OUT MB_DQ21 MB_DQ22 MB_CLK1_DN AL33 OUT 20 19 BI AM15 AP12 19 22 21 AL23 MB_CLK0_DP 21 BI MA_DQ20 MA_DQ21 MA_CLK0_DP OUT MB_DQ21 MB_CLK0_DP AL34 OUT 20 19 AN14 19 22 21 MB_DQ20 AN23 MB_CLK0_DN OUT 21 BI MA_DQ19 MA_DQ20 MA_CLK0_DN OUT BI MB_DQ19 MB_DQ20 MB_CLK0_DN OUT 20 19 AN16 MA_DQ19 22 21 AN25 BI MA_DQ18 MA_A<12..0> 19 20 BI MB_DQ19 AK32 MB_A<12..0> 21 22 20 19 BI AL13 MA_DQ18 MA_A12 22 21 MB_DQ18 12 OUT MA_DQ17 AN4 12 BI AP22 MB_DQ18 MB_A12 AE29 20 19 BI AP17 MA_DQ17 MA_A11 AP7 11 OUT 22 21 BI MB_DQ17 AP25 11 BI MA_DQ16 MB_DQ17 MB_A11 AE34 20 19 MA_WDQS2 AM13 MA_DQ16 MA_A10 AP4 10 22 21 BI MB_DQ16 AN21 10 BI BI AN22 MB_DQ16 MB_A10 AJ30 20 19 MA_RDQS2 AP14AL15 MA_A9 9 22 21 MB_WDQS2 OUT MA_WDQS2 AP8 8 OUT MB_WDQS2 MB_A9 20 19 22 21 MB_RDQS2 AK33 9 IN AN11 IN AP24 8 MA_DM2 AP16 MA_RDQS2 MA_A8 7 MB_DM2 AN24 MB_RDQS2 MB_A8 AJ33 7 20 19 OUT MA_DM2 AP9 22 21 OUT MA_A7 AN10 MB_DM2 MB_A7 AK34 6 MA_DQ15 MA_A6 AP11 6 MB_DQ15 AH26 MB_A6 AM32 20 19 AH16 MA_DQ15 MA_A5 5 22 21 5 MA_DQ14 AK20 AN9 4 BI MB_DQ14 AN32 MB_DQ15 MB_A5 AJ34 4 20 19 MA_DQ13 MA_DQ14 MA_A4 22 21 BI 20 19 BI AK16 AN8 3 22 21 MB_DQ13 AK26 MB_DQ14 MB_A4 AE30 3 BI MA_DQ12 MA_DQ13 MA_A3 BI 20 19 AH20 AN7 22 21 MB_DQ12 AN31 MB_DQ13 MB_A3 AF28 BI MA_A2 AN5 2 20 19 MA_DQ11 AH17 MA_DQ12 1 22 21 BI MB_DQ11 AN29 MB_DQ12 MB_A2 AE33 21 BI MA_DQ11 MA_A1 AP6 20 19 BI MA_DQ10 AJ19 0 22 21 BI MB_DQ10 AN30 MB_DQ11 MB_A1 AF29 MA_DQ10 MA_A0 BI 0 20 19 BI MA_DQ9 AJ18 22 21 MB_DQ9 AK28 MB_DQ10 MB_A0 BI MA_DQ9 MA_BA<2..0> 19 20 BI MB_BA<2..0> 21 22 MA_DQ8 AH18 AP10 2 OUT MB_DQ8 AK29 MB_DQ9 AH30 2 OUT 20 19 BI MA_DQ8 MA_BA2 22 21 BI MA_WDQS1 AM10 1 MB_WDQS1 AK30 MB_DQ8 MB_BA2 AH33 1 20 19 OUT AK19 MA_WDQS1 MA_BA1 22 21 OUT MA_RDQS1 AK17 AP5 0 MB_RDQS1 MB_WDQS1 MB_BA1 AG30 0 20 19 IN MA_RDQS1 MA_BA0 22 21 IN AN28 MA_DM1 AM17 MB_DM1 AK27 MB_RDQS1 MB_BA0 20 19 OUT MA_DM1 AJ9 22 21 OUT AN6 MA_CKE 19 20 MB_DM1 AG34 MB_CKE 21 22 20 19 MA_DQ7 AK15 MA_CKE MA_WE_NOUT 19 20 22 21 MB_DQ7 AK25 MB_CKE AF33 MB_WE_N OUT 21 22 OUT OUT 20 19 AH11 MA_DQ7 MA_WE_N* AK8 MA_CAS_N 19 20 22 21 MB_DQ6 AH21 MB_DQ7 MB_WE_N* AF32 MB_CAS_N 21 22 BI OUT BI OUT 20 19 MA_DQ6 AH15 MA_DQ6 MA_CAS_N* AK7 MA_RAS_N 20 22 21 BI MB_DQ5 AH25 MB_DQ6 MB_CAS_N* AF31 MB_RAS_N 22 BI AK11 AK9 MA_CS1_NOUT 19 MB_DQ4 AK21 MB_CS1_N OUT 21 20 19 BI MA_DQ5 MA_DQ5 MA_RAS_N* OUT 19 20 22 21 BI MB_DQ5 MB_RAS_N* AH34 OUT 21 22 20 19 BI MA_DQ4 MA_DQ4 MA_CS1_N* AL10 MA_CS0_N 19 22 21 BI MB_DQ3 MB_DQ4 MB_CS1_N* AF34 MB_CS0_N 21 OUT BI OUT 20 19 BI MA_DQ2MA_DQ3 AH13 MA_DQ3 MA_CS0_N* 22 21 MB_DQ2 AH23 MB_DQ3 MB_CS0_N* BI AK12 MA_DQ2 BI AK22 20 19 MA_DQ1 AJ13 22 21 MB_DQ1 AJ23 MB_DQ2 BI MA_DQ1 BI 20 19 AH12 22 21 MB_DQ0 AH22 MB_DQ1 BI MA_DQ0 BI MB_WDQS0 20 19 OUT MA_DQ0 22 21 OUTOUT AM22 MB_DQ0 AM12AJ14 MA_WDQS0 MB_RDQS0 20 19 IN MA_RDQS0MA_WDQS0 22 21 IN MB_WDQS0 AK14 MA_RDQS0 MB_DM0 AJ24 OUT 20 19 22 21 AK24 MB_RDQS0 MA_DM0 MA_DM0 MB_DM0 AK6 AG33 AP13 MA_VREF1 AP21 V_MEM MB_VREF1 MA_VREF0 V_MEM MB_VREF0

1 R4T4 1 549 X02125-001 R5E2 X02125-001 1% 549 V_MEM V_MEM CH 1% V_MEM 402 CH MEMORY CONTROLLER B, DECOUPLING 2 MA_VREF1 402 1 2 1 MB_VREF1 1 R4T7 549 R4T8 1 C4T47 C4T31 C4T34 C5T2 C4T39 C4T40 R4T3 1% 549 4.7UF .22UF .22UF .22UF .22UF 1.27K 1 1% .1UF CH 10% 10% 10% 10% 10% 10% 1% V_MEM 1 CH 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 402 C5E1 R5E1 2 CH 2 1.27K 402 X5R X5R X5R X5R X5R X5R .1UF 2 805 402 402 402 402 402 402 MEMORY CONTROLLER A, DECOUPLING 10% 1% 2 6.3V MB_VREF0 MA_VREF0 2 X5R CH 402 402 2 1 C4R3 C4T29 C4T32 C4T42 C4T44 1 1 1 R4T6 C4T45 4.7UF .22UF .22UF .22UF .22UF R4T5 C4T46.1UF 1.27K .1UF 10% 10% 10% 10% 10% 1.27K 1% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 10% 6.3V X5R X5R X5R X5R X5R 1% 6.3VX5R C4T33 C5T3 C5T4 C5T1 2 805 402 402 402 402 2 CH X5R 402CH 402 .22UF .22UF .22UF .22UF 402 402 10% 10% 10% 10% 2 2 6.3VX5R 6.3V 6.3V 6.3V 402 X5R X5R X5R 402 402 402

TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE C4T35 C4T27 C4T41 C4T43 R4T3, R4T6, R5E1, R4T5, R4R5, R4R2, R4T2, R4R7 .22UF .22UF .22UF .22UF 10% 10% 10% 10% MEM VREF RESISTOR VALUE 6.3V 6.3VX5R 6.3V 6.3V X5R 402 X5R X5R 70% 1.27KOHM THESE ARE THE GPU VREFS NEEDED 402 402 402 72% 1.40KOHM FOR VARIOUS MEMORIES. CONSULT WITH MEM TEAM FOR USAGE. 73% 1.47KOHM 74% 1.54KOHM DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=GPU, MEMORY CONTROLLER A + B] Tue May 08 18:24:14 2007 FALCON_RETAIL 14/82 1.0 CONFIDENTIAL CR-15 : @FALCON_LIB.FALCON(SCH_1):PAGE15

GPU, MEMORY CONTROLLER 1 PARTITION C & D 5OF12 6OF12 U4D1 IC IC GPU Y2 VERSION 1 U4D1 GPU Y2 VERSION 1 MD_DQ30 MC_DQ31 R1 MD_DQ31 AC3 24 23 MC_DQ30 MC_DQ31 MD_DQ29 MD_DQ31 R3 AC4 BI MC_DQ30 26 MD_DQ28 MD_DQ30 24 23 MC_DQ29 R2 BI BI MC_DQ29 BI 26 25 MD_DQ29 24 23 BI MC_DQ28 R4 MD_DQ27 24 23 MC_DQ27MC_DQ26 N4 MC_DQ28 BI 25 MD_DQ28 24 23 BI MC_DQ27 BIMD_DQ2626 25 MD_DQ27 24 23 BI MC_DQ25T2 MC_DQ26 BIMD_DQ2526 25 AE2 MD_DQ26 24 23 BI MC_DQ24 N3 MC_DQ25 BI 26 25 AC1AA2 24 23 BI MC_WDQS3 BI MD_DQ24 MD_DQ25 U1 26 25 AE1 24 23 BI MC_DQ24 BI AD1 MD_DQ24 MD_WDQS326 25 AB1AD2 24 23 MC_WDQS3 MD_RDQS3 MD_WDQS3 OUT MC_RDQS3 P2 OUT 26 25 AC2 24 23 MC_RDQS3 IN MD_DM326 25 MD_RDQS3 MC_DM3 P1 AB2 OUT MC_DM3 OUT 26 25 MD_DM3 24 23 24 MD_CLK1_DP IN L1 26 25 W2 24 23 K4 J1 MC_CLK1_DPMC_CLK1_DN 24 MD_DQ23 AD6 MD_CLK1_DN MC_DQ23 L2 MC_DQ23 MC_CLK1_DP MD_DQ23 MD_CLK1_DP 24 23 MC_DQ22T1 H1 MC_CLK0_DP OUT 23 MD_DQ2226 25 W1 AD5 MD_CLK0_DP 26 BI K3 MC_DQ22 MC_CLK1_DN F1 BI MD_DQ22 MD_CLK1_DN 24 23 MC_DQ21 MC_CLK0_DN OUT 23 MD_DQ2126 25 Y2 AE4 MD_CLK0_DN 26 24 23 BI MC_DQ21 MC_CLK0_DP E1 BI MD_DQ21 MD_CLK0_DP OUT OUT OUT 23 24 MD_DQ2026 25 V4 AE3 OUT 25 26 25 24 23 BI BI OUT BI MC_DQ20MC_DQ19 MC_DQ20 MC_CLK0_DN OUT BI MD_DQ1926 25 Y4 MD_DQ20 MD_CLK0_DN 25 24 23 BI MC_DQ18 MC_DQ19 MC_A<12..0> BI 26 25 MD_DQ19 MD_A<12..0> 24 23 K2 MC_A12 A10 12 OUT MD_DQ18 V1 12 OUT BI MC_DQ17 MC_DQ18 BI 26 25 MD_DQ18 MD_A12 AK5 N1 MC_A11 A7 11 AA1 11 24 23 BI MD_DQ1726 25 AL2 MC_DQ16 J2N2 MC_DQ17 B10 10 BI V2 MD_DQ17 MD_A11 10 MC_WDQS2 MC_A10 BI MD_DQ1626 25 AM2 24 23 MC_DQ16 MD_DQ16 MD_A10 MD_WDQS226 25 V3 BIOUT MC_WDQS2 MC_A9 OUT MD_WDQS2 MD_A9 AF5 24 23 MC_RDQS2 M1 D1 89 MD_RDQS226 25 Y1 89 24 23 MC_RDQS2 MC_A8 B6 IN MD_DM2 MD_RDQS2 MD_A8 AE5 MC_DM2 M2 MC_DM2 A5 7 26 25 Y3 AF2 7 24 23 OUTIN K1 MC_A7 A4 OUT MD_DM2 MD_A7 J6 6 W6 AF7 6 24 23 MC_DQ15 MC_A6 MD_DQ1526 25 MD_A6 MC_DQ14 N6 MC_DQ15 MC_A5 C1 AE7 24 23 26 25 MD_DQ15 MD_A5 24 23 BI J5 MC_DQ14 MC_A4 B5 5 MD_DQ14 AC7 AG2 45 4 26 25 BI MC_DQ13 A6 3 BI MD_DQ13 W5 MD_DQ14 MD_A4 AM1 3 24 23 BI MC_DQ12 MC_DQ13 26 25 24 23 N7 MC_A3 B7 2 BI MD_DQ12 AC6 MD_DQ13 MD_A3 AJ2 2 BI MC_DQ12 23 24 BI 26 25 25 26 24 23 L5 MC_A2 A9 1 AA5 MD_DQ12 MD_A2 AM3 1 BI MC_DQ11 MC_DQ11 MC_A1 BI MD_DQ1126 25 24 23 B8 MD_DQ10 AB5 AK2 MC_DQ10 M5 MC_DQ10 MC_A0 BI 26 25 MD_DQ11 MD_A1 24 23 L7 BI MD_DQ9 AA7 MC_DQ9 MC_DQ9 0 26 25 MD_DQ10 MD_A0 0 24 23 M3K5 MC_BA<2..0> OUT BI MD_DQ826 25 AB3 MD_DQ9 AG5 MD_BA<2..0> OUT BI MC_DQ8 MC_DQ8 MC_BA2 B4 BI 2 23 24 26 25 2 BI MC_WDQS1 A3 1 MD_WDQS1 AB7 MD_DQ8 MD_BA2 AH2 1 24 23 OUT M7 MC_WDQS1 MC_BA1 23 24 OUT BI 0 MD_RDQS126 25 Y5 AJ5 0 24 23 MC_RDQS1 MC_RDQS1 MC_BA0 B9 23 24 IN MD_WDQS1 MD_BA1 MC_DM1 K7 MD_DM1 Y7 MD_RDQS1 MD_BA0 25 26 24 23 OUTIN MC_DM1 23 24 OUT 26 25 25 26 24 23 A8 MC_CKE 23 24 MD_DM1 AK1 MD_CKE F2 26 25 25 26 24 23 MC_DQ7 H2 E7 MC_WE_NOUT 23 MD_DQ7 V7 AH1 MD_WE_N OUT MC_DQ7 MC_CKE 26 25 MD_CKE 25 26 24 23 BI MC_DQ6 B2 MC_WE_N* E8 MC_CAS_NOUT MD_DQ6 P6 MD_DQ7 MD_WE_N* AJ1 MD_CAS_N OUT MC_DQ6 BI 26 25 AL1 25 26 24 23 BI MC_DQ5 H5 MC_RAS_NOUT MD_DQ5 R5V6 MD_RAS_N OUT BI MC_DQ5 MC_CAS_N* OUT BI 26 25 MD_DQ6 MD_CAS_N* OUT 25 24 23 MC_DQ4 C2 E9MC_CS1_N MD_DQ426 25 P5 AH5 BI MC_RAS_N* OUT BI MD_DQ5 MD_RAS_N* MD_CS1_N OUT 24 23 MC_DQ3 MC_DQ4 E6MC_CS0_N BI MD_DQ326 25 U3 AG1 24 23 F5 MC_CS1_N* OUT MD_DQ4 MD_CS1_N* MD_CS0_N OUT MC_DQ2 E5 MC_DQ3 B3 BI MD_DQ226 25 24 23 BI E2 MC_DQ2 MC_CS0_N* BI MD_DQ3 MD_CS0_N* BI MC_DQ1 MD_DQ126 25 T5 BI 26 25 MD_DQ2 BI MC_DQ0 MC_DQ1 T7 BI 26 25 MD_DQ1 BI MC_WDQS0 D2 MC_DQ0 MD_DQ0 R7U7U5 OUT MC_WDQS0 OUT MD_DQ0 IN MC_RDQS0 G5 IN MD_WDQS0 MD_WDQS0 MC_DM0 G2 MC_RDQS0 OUT MC_DM0 OUT MD_RDQS0 MD_RDQS0 MD_DM0 MD_DM0 G1 AF1 E10 MC_VREF1 U2 V_MEM MC_VREF0 V_MEM MD_VREF1 MD_VREF0

2 X02125-001 1 X02125-001 R4R4 549 R3T2 549 V_MEM 1% V_MEM 1% CH V_MEM CH 402 MEMORY CONTROLLER D, DECOUPLING 1 402 2 2 1 MC_VREF1 MD_VREF1 R4R1 R4R6 1 1 1 1 1 1 C4T28 C4R15 C4R61 C4T38 C4R50 1 549 549 1% V_MEM 1 1% 4.7UF .22UF .22UF .22UF .22UF 1 C4T36 R4T2 10% 10% 10% 10% 10% C4R25 R4R5 CH CH 6.3V 6.3V 6.3V 6.3V 6.3V .1UF 1.27K 2 2 2 2 2 .1UF 1.27K 402 10% 1% 402 X5R X5R X5R X5R X5R 10% 1% 1 MEMORY CONTROLLER C, DECOUPLING 6.3V 2 402 402 402 402 6.3V 2 X5R CH 805 2 X5R CH MC_VREF0 402 402 402 402 2 MD_VREF0 2 1 1 C3R5 1 C4R381 C4R511 C4T141 C4R48 1 R4R2 C4R10 4.7UF .22UF .22UF .22UF .22UF 1 1.27K 10% 10% 10% 10% 10% .1UF 6.3V 6.3V 6.3V 6.3V 6.3V 1 1% 10% 2 2 2 2 2 R4R7 C4R64 6.3V X5R X5R X5R X5R X5R 1.27K 1 1 1 1 CH 2 402 402 402 402 .1UF C4T7 C4R31 C4R12 C4R19 X5R 805 1% 10% 402 402 6.3V .22UF .22UF .22UF .22UF 2 CH 2 X5R 10% 10% 10% 10% 402 6.3V 6.3V 6.3V 6.3V 402 2 X5R 2 X5R 2 X5R 2 X5R 2 402 402 402 402

1 C4R231 C4R661 C4T121 C4R32 TO CHANGE GPU VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE .22UF .22UF .22UF .22UF 10% 10% 10% 10% R4T3, R4T6, R5E1, R4T5, R4R5, R4R2, R4T2, R4R7 6.3V 6.3V 6.3V 6.3V 2 X5R 2 X5R 2 X5R 2 X5R 402 402 402 402 GPU MEM VREF RESISTOR VALUE 70% 1.27KOHM THESE ARE THE GPU VREFS NEEDED 72% 1.40KOHM FOR VARIOUS MEMORIES. CONSULT WITH MEM TEAM FOR USAGE. 73% 1.47KOHM 74% 1.54KOHM DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV PAGE_TITLE=[GPU, MEMORY CONTROLLER C + D] Tue May 08 18:24:14 2007 FALCON_RETAIL 15/82 1.0 CONFIDENTIAL CR-16 : @FALCON_LIB.FALCON(SCH_1):PAGE16

V_GPUCORE GPU, PLL POWER + FSB POWER

FB4D1

1 2 120 0.2A FB 0.5 DCR 603 1 C4D6 1 C4D5 1 C4D4 2.2UF .1UF 0.01UF 10% 10% 10% 6.3V 6.3V 16V V_GPUCORE 2 X5R 2 X5R 2 X7R 603 402 402 V_GPUPCIE

8OF12 IC U4D1 V_PVDDA GPU Y2 VERSION 1 FB4T1 VDD_FSB24 AA27 1 2 VDD_FSB23 AB28 120 PVDDA VDD_FSB22 AB32 A20 0.2A FB 1 1 A21 PVSSA VDD_FSB21 AC27 0.5 DCR 603 1 1 C5R7 C4R8 C4T48 C4T30 C4T37 .1UF .1UF VDD_FSB20 AD28 2.2UF .1UF 0.01UF 10% 10% C27 10% 10% 10% 6.3V 6.3V VDD_BSB1 VDD_FSB19 AD31 6.3V 6.3V 16V 2 X5R 2 X5R C26 VSS_BSB1 VDD_FSB18 2 2 X5R X7R 402 402 K31K28 X5R VDD_FSB17 402 402 C25 603 VDD_BSB0 VDD_FSB16 L27 C24 M28 V_PVDDA_MEM VSS_BSB0 VDD_FSB15 M32 VDD_FSB14 AG10 N27 AG9 PVDDA_MEM VDD_FSB13 P28 PVSSA_MEM VDD_FSB12 FB4R1 V_PVDDA_ED P31 VDD_FSB11 1 2 R28 A19A18 PVDDA_ED VDD_FSB10 R32 120 FB T27 0.2A 603 PVSSA_ED VDD_FSB9 1 1 U28 0.5 DCR B25 VDD_FSB8 2.2UFC4R68 C4R4 C4R6 B24 .1UF 0.01UF PVDDA_PEX VDD_FSB7 U31 10% 10% 10% PVSSA_PEX VDD_FSB6 6.3V 6.3V 16V V27 2 X5R 2 X5R X7R VDD_FSB5 V_PVDDA_FSB F34G34 V30 V_GPUPCIE 603 402 402 PVDDA_FSB VDD_FSB4 W28 PVSSA_FSB VDD_FSB3 W32 VDD_FSB2 Y28 VDD_FSB1 Y31 VDD_FSB0

X02125-001

1 C4R5 C4R7 .1UF 0.01UF 10% 10% 6.3V 16V 2 X7R 402X5R 402

FB5R1

1 2 120 FB 0.2A 603 0.5 DCR 1 C5R19 1 C5R13 C5R15 2.2UF .1UF 0.01UF 10% 10% 10% 6.3V 6.3V 16V402 2 X5R 2 X5R X7R 603 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=GPU, PLL POWER + FSB POWER] Tue May 08 18:24:14 2007 FALCON_RETAIL 16/82 1.0 CONFIDENTIAL CR-17 : @FALCON_LIB.FALCON(SCH_1):PAGE17

GPU, CORE POWER + MEM POWER

V_GPUCORE V_GPUCORE 9OF12 12 OF 12 11 OF 12 IC IC GPU Y2 VERSION 1 U4D1 GPU Y2 VERSION 1 IC VSS130 VSS65 U4D1 VDD_CORE78 AJ15 VSS129 VSS64 VDD_CORE157 U4D1GPU Y2 VERSIONVSS195 1 F21 VDD_CORE156 VDD_CORE77 V_MEM V_MEM VSS194 AJ17 VSS128 VSS63 10 OF 12 A1 VSS260 VDD_CORE155 VDD_CORE76 VSS193 AJ20 VSS127 VSS62 AA3 VSS259 E28 VDD_CORE75 U4D1 GPU Y2 VERSION 1 IC VSS192 AJ25 VSS126 VSS61 P18 VDD_CORE154VDD_CORE153 H14 AA8 F24 D27 VDD_CORE74 AL28 VSS258 AJ27 VSS125 P22 VDD_CORE152 H16 VDD_MEM111 VDD_MEM55 AA11 VSS191 F26F31 VSS60 E27 VDD_CORE73 AL30 VSS257 AJ29 P23 VDD_CORE151 H18 AA4 VDD_MEM110 VDD_MEM54 AA12 VSS190 F28G4 VSS124 VSS59 D26 VDD_CORE72 AL32 VSS256 P24 VDD_CORE150 H20 AA6 VDD_MEM109 VDD_MEM53 AA13 G7 VSS123 VSS58 R6 E26 VDD_CORE71 H22 VSS255 P27 VDD_CORE149 AB6 VDD_MEM108 VDD_MEM52 AA17 AJ31 G18 VSS122 VSS57 R11 G26 VDD_CORE70 H24 VSS254 VSS189 P32 VDD_CORE148 AC5 VDD_MEM107 VDD_MEM51 AM5 AA18 AK4 G20 VSS121 VSS56 R12 G25 VDD_CORE69 H26 VSS253 VSS188 L11 AC8 VDD_MEM106 AM7 AA22 AK18 G27 VSS120 VSS55 R13 D24 VDD_CORE147 H27 VDD_MEM50 VSS252 VSS187 VDD_CORE68 L12 AD4 VDD_MEM105 AM9 VSS185 AL3 G29 VSS119 VSS54 R17 E24 VDD_CORE146 J27 VDD_MEM49 AA23 VSS251 VSS186 VDD_CORE67 L13 AD7 VDD_MEM104 AM16 AL5 G33 VSS118 VSS53 R18 E23 VDD_CORE145 VDD_MEM48 AA24 VSS250 VDD_CORE66 L17 AE8 VDD_MEM103 AM19 AB4 AL7 H3 VSS117 VSS52 R22 G24 VDD_CORE144 VDD_MEM47 VSS249 VSS184 D23 VDD_CORE65 L18 AE28 VDD_MEM102 AM26 AB8 AL9 H6 VSS116 VSS51 R23 VDD_CORE143 VDD_MEM46 VSS248 VSS183 G23 VDD_CORE64 L22 AE31 VDD_MEM101 AM27 AB14 AL12 H8 VSS115 VSS50 R24 VDD_CORE142 VDD_MEM45 VSS247 VSS182 F22G21 VDD_CORE63 L23 AF3 VDD_MEM100 AM29 AB15 AL16 H9 VSS114 VSS49 R27 VDD_CORE141 L24 VDD_MEM44 VSS246 VSS181 H11 G22D29 VDD_CORE140 VDD_CORE62VDD_CORE61 AF6 VDD_MEM99 VDD_MEM43 AM31 AB16 AL19 VSS113 VSS48 R31 VSS245 VSS180 T4 E25 VDD_CORE139 M11 AF27 VDD_MEM98 VDD_MEM42 AN2 AB19 AL22 H13 VSS112 VSS47 AP3 VSS244 VSS179 T8 AA14 VDD_CORE138 VDD_CORE60VDD_CORE59 M12 AF30 VDD_MEM97 VDD_MEM41 AB20 AL26 H15 VSS111 VSS46 VSS243 VSS178 H17 T11 AA15 VDD_CORE137 M13 AG4 VDD_MEM96 VDD_MEM40 C3 AB21 AL27 VSS110 VSS45 M17 AG7 C5 AB27 VSS242 VSS177 H19 T12 AA16 VDD_CORE136 VDD_CORE58 VDD_MEM95 VDD_MEM39 AL29 VSS109 VSS44 VDD_CORE57 M18 AG13 C7 AB31 VSS241 VSS176 AL31 T13 AA19 VDD_MEM94 VDD_MEM38 VSS108 VSS43 VDD_CORE135 VDD_CORE56 M22 AG15 C9 AC14 VSS240 VSS175 AM4 H23 T17 AA20 VDD_MEM93 VDD_MEM37 VSS107 VSS42 AA21 VDD_CORE134 VDD_CORE55 M23 AG17 C12 AC15 VSS239 VSS174 AM6 H25 T18 VDD_MEM92 VDD_MEM36 VSS106 VSS41 AB11 VDD_CORE133 VDD_CORE54 M24 AG20 C14 AC16 VSS238 VSS173 AM8 H28 T22 VDD_MEM91 VDD_MEM35 VSS105 VSS40 AB12 VDD_CORE132 VDD_CORE53 N11 AG23 C16 AC19 VSS237 VSS172 AM11 H21 J4 T23 VDD_MEM90 VDD_MEM34 VSS104 VSS39 AB13 VDD_CORE131 VDD_CORE52 N12 AG25 C18 AC20 VSS236 VSS171 AM14 J8 T24 VDD_MEM89 VDD_MEM33 VSS103 VSS38 AB17 VDD_CORE130 VDD_CORE51 N13 AG28 D4 AC21 VSS235 VSS170 AM21 J28 U6 VDD_MEM88 VDD_MEM32 VSS102 VSS37 AB18 VDD_CORE129 VDD_CORE50 N17 AG32 D6 AC30 VSS234 VSS169 AM24 K6 VSS101 VSS36 U14 VDD_CORE128 VDD_MEM87 VDD_MEM31 D8 AB22 VDD_CORE49 N18 AH3 VDD_MEM86 AD3 VSS233 VSS168 AM28 K27 VSS100 VSS35 U15 N22 VDD_MEM30 E3 AB23 VDD_CORE127 VDD_CORE48 AH6 VDD_MEM85 AD8 VSS232 VSS167 AM30 K32 VSS99 VSS34 U16 N23 VDD_MEM29 F4 U19 AB24 VDD_CORE126 VDD_CORE47 AH8 VDD_MEM84 AD14 VSS231 VSS166 AN3 L3 VSS98 VSS33 VDD_CORE125 N24 AH9 VDD_MEM28 U20 AC11 VDD_CORE46 F7 AD15 VSS230 VSS165 AN33 L8 VSS97 VSS32 AC12 VDD_CORE124 P14 AH14 VDD_MEM83 VDD_MEM27 F9 AD16 VSS229 VSS164 B19 L14 U21 VDD_CORE45 VSS162 VSS96 VSS31 AC13 VDD_CORE44 P15 AH19 VDD_MEM82 VDD_MEM26 F11 AD19 VSS228 VSS163 B33 L15 U27 VDD_CORE123 P16 VDD_MEM81 VSS161 VSS95 VSS30 AC17 VDD_CORE43 AH24 VDD_MEM25 F13 AD20 VSS227 C4 L16 U32 VDD_CORE122 P19 VDD_MEM80 VSS94 VSS29 AC18 VDD_CORE42 AH27 VDD_MEM24 F15 AD21 VSS226 C6 L19 V5 VDD_CORE121 P20 VDD_MEM79 VSS93 VSS28 AC22 VDD_CORE41 AH29 VDD_MEM23 G3 AD27 VSS225 VSS160 C8 L20 V14 VDD_MEM78 VSS92 VSS27 AC23 VDD_CORE120 P21 AH31 VDD_MEM22 G6 AD32 C11 L21 V15 VDD_CORE40 VDD_MEM77 VSS224 VSS159 VSS91 AC24 VDD_CORE119 VDD_CORE39 AJ4 VDD_MEM21 G8 AE6 C13 L28 VSS26 V16 VDD_MEM76 VSS223 VSS158 VSS90 AD11 VDD_CORE118 AJ7 VDD_MEM20 H4 AE27 C15 M4 VSS25 V19 VDD_CORE117 VDD_CORE38 R14 VDD_MEM75 VSS222 VSS157 VSS89 AD12 VDD_CORE37 AJ11 VDD_MEM19 H7 AE32 C17 M8 VSS24 V20 VDD_CORE116 R15 VDD_MEM74 VSS221 VSS156 VSS88 AJ12 VDD_MEM18 H10 AF4 C20 M14 VSS23 V21 AD13 VDD_CORE115 VDD_CORE36 R16 VSS220 VSS155 AD17 VDD_CORE35 AJ16 VDD_MEM73 VDD_MEM17 J3 AF8 C28 M15 VSS87 VSS22 W4 VDD_CORE114 R19 VDD_MEM72 VSS219 VSS154 VSS86 AD18 VDD_CORE34 R21 AJ21 VDD_MEM16 J7 AG3 C32 M16 VSS20 W11 VDD_CORE113 R20 VSS218 VSS153 T14 AJ22 VDD_MEM71 VDD_MEM15 K8 AG6 D3 M19 VSS85 VSS21 W8 AD22 VDD_CORE112 VDD_CORE33 VSS217 VSS152 T15 AJ26 VDD_MEM70 L4 AG8 D5 M20 VSS84 VSS19 AD23 VDD_CORE32 VDD_MEM14 L6 VSS216 VSS151 VDD_CORE111 T16 VDD_MEM69 D7 VSS83 VSS18 W12 AD24 VDD_CORE31 AJ28 VDD_MEM13 AG12 VSS215 VSS150 M21 VDD_CORE110 T19 VDD_MEM68 D9 VSS82 VSS17 W13 AJ32 VDD_MEM12 M6 AG14 VSS214 VSS149 M27 B18 VDD_CORE109 VDD_CORE30 T20 AK3 N5 AG18 D19 M31 VSS81 VSS16 W17 VDD_CORE29 VDD_MEM67 VDD_MEM11 VSS213 VSS148 W18 B20 VDD_CORE108 T21 AK13 N8 AG19 D21 N14 VSS80 VSS15 VDD_CORE28 VDD_MEM66 VDD_MEM10 VSS212 VSS147 W22 C19C21 VDD_CORE107 U11 AK23 P4 AG21 D31 N15 VSS79 VSS14 W27 VDD_MEM65 VDD_MEM9 VSS211 VSS146 W23 C29 VDD_CORE106 VDD_CORE27 U12 AK31 P7U4 AG22 E4 N16 VSS78 VSS13 W24 VDD_CORE26 VDD_MEM64 VDD_MEM8 VSS210 VSS145 C31 VDD_CORE105 U13 AL4 R8 AG24 E18 N19 VSS77 VSS12 VDD_MEM63 VDD_MEM7 VSS209 VSS144 C33 VDD_CORE104 VDD_CORE25 U17 AL6 T3U8 AG26 E20 N20 VSS76 VSS11 W31 VDD_MEM62 VDD_MEM6 VSS208 VSS143 Y11 C34 VDD_CORE103 VDD_CORE24 U18 AL8 T6 AG27 E22 N21 VSS75 VSS10 Y6 D20 VDD_MEM61 VDD_MEM5 VSS207 VSS142 D17 VDD_CORE102 VDD_CORE23 U22 AL11 AG29 E30 N28 VSS74 VSS9 D22 VDD_MEM60 VDD_MEM4 VSS206 VSS141 D18 VDD_CORE101 VDD_CORE22 U23 AL14 AG31 E32 N29 VSS73 VSS8 Y12 D30 VDD_MEM59 VDD_MEM3 VDD_CORE100 VDD_CORE21 U24 AL17 W3 AH4 VSS205 VSS140 F3 N30 VSS72 Y13Y18 D32 VDD_MEM58 VDD_MEM2 VSS7 VDD_CORE99 VDD_CORE20 V11 AL21 W7 AH7 VSS204 VSS139 F6 P3 VSS71 D34 VDD_MEM57 VDD_MEM1 VSS6 Y22Y17 VDD_CORE19 V12 AL24 Y8 AH28 VSS203 VSS138 F8 P8 E17 VDD_CORE98 VDD_MEM56 VDD_MEM0 VSS70 VSS5 VDD_CORE97 VDD_CORE18 V13 VSS202 VSS137 Y23 E19 AH32 VSS135 F10 P11 VSS69 VSS4 VDD_CORE96 VDD_CORE17 V17V22 AJ3 VSS201 VSS136VSS134 F12 P12 VSS68 VSS3 X02125-001 VSS200 VDD_CORE95 VDD_CORE16 V18 AJ6 VSS133 F14 P13 VSS67 VSS2 Y24 VSS199 VDD_CORE94 VDD_CORE15 AJ8 VSS132 F16 P17 VSS66 VSS1 Y27 E21 VDD_CORE93 VDD_CORE14 V23 AJ10 VSS198 VSS131 F19 VSS0 Y32 E31 VDD_CORE92 VDD_CORE13 V24 VSS197 F17 W14 VSS196 VDD_CORE91 VDD_CORE12 W15 F18 VDD_CORE90 VDD_CORE11 X02125-001 X02125-001 F20 VDD_CORE89 VDD_CORE10 W16 F23 VDD_CORE88 VDD_CORE9 W19 F25 VDD_CORE87 VDD_CORE8 Y14W20 F27 VDD_CORE86 VDD_CORE7 W21 F29 VDD_CORE85 VDD_CORE6 F30 Y15Y16 G19 VDD_CORE84 VDD_CORE5 VDD_CORE83 VDD_CORE4 Y19 G28 Y20 G32 VDD_CORE82 VDD_CORE3 H12 VDD_CORE81 VDD_CORE2 VDD_CORE80 VDD_CORE1 Y21 VDD_CORE79 VDD_CORE0 X02125-001 DRAWING PAGE MICROSOFT PROJECT NAME REV [PAGE_TITLE=GPU, CORE POWER + MEM POWER] Tue May 08 18:24:14 2007 FALCON_RETAIL 17/82 1.0 CONFIDENTIAL XENON_FABK CR-18 : @FALCON_LIB.FALCON(SCH_1):PAGE18

V_GPUCORE V_GPUCORE V_GPUCORE GPU, DECOUPLING

N:EMPTIES C4R20 C4R11 C4R16 C4R28 C4R13 C4R54 C5D2 C6R47 C4R29 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1

.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 10% 4.7UF 10% 4.7UF 10% 10UF 20% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R .1UFEMPTY X5R X5R X5R 402 402 402 402 402 402 805 805 805

C4R37 C4R17 C4R21 C4R22 C5R16 C4T5 C6E2 C6E1 C4T17 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 2 1 6.3V .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10% 10UF 20% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R EMPTY X5R X5R X5R 402 402 402 402 402 805 805 805 X5R 402 C4R30 C4T15 C4R55 C4T26 C4T23 C5R10 C4R59 C5R5 C5D3 2 1 1 2 1 2 1 2 1 2 2 1 1 2 2 1 2 1 10UF20% .1UF 10% .1UF 10% 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10% 6.3V 6.3V 6.3V 6.3V 6.3V.1UF 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R EMPTY X5R X5R 805 402 402 X5R 402 402 402 805 805 402 C4R69 C4R14 C4R47 C4T21 C4R44 C5R12 C4T6 C5R4 C5D4 2 1 1 2 1 2 1 2 1 2 1 2 1 2 2 1 2 1 10UF 20% .1UF 10% .1UF 10% .1UF .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10% 6.3V 6.3V 6.3V 6.3V10% 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R EMPTY X5R X5R 805 402 402X5R 402 402 402 402 805 805

C4R39 C5D6 1 2 C4T20 C4R46 C4T24 C4R24 C4R57 C5R20 2 1 1 2 1 2 1 2 1 2 1 2 2 1 .1UF 10% 4.7UF 10% 6.3V .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF6.3V 10% 4.7UF 10% 6.3V X5R 6.3V 6.3V 6.3V 6.3V EMPTY 6.3V X5R 402 X5R X5R X5R X5R X5R 805 402 402 402 402 402 805

C4T25 C4R36 C4R41 C4T19 C4R40 C4R56 C5R2 C5D5 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 1 .1UF .1UF 10% .1UF 10% 10% .1UF 10% .1UF 10% .1UF 10% 4.7UF 10% 4.7UF 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R EMPTY X5R X5R 402 402 402 402 402 402 805 805

C4T11 C4R34 C4R35 C4T18 C5R8 C4T4 C5R1 1 2 1 2 1 2 1 2 1 2 1 2 2 1

.1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF .1UF 10% 10% 4.7UF 6.3V 6.3V 6.3V 6.3V402 6.3V 10% 6.3V X5R X5R X5R X5R X5R EMPTY402 6.3VX5R 402 402 402 402 805

C4T3 C4R42 C4R67 C4R62 C4R9 C4R58 C5R3 1 2 1 2 2 1 1 2 1 2 1 2 2 1 .1UF .1UF 10% .1UF 10% 10% .1UF 10% 10% .1UF 10% 4.7UF 10% 6.3V 6.3V 6.3V .1UF6.3V 6.3V 6.3V X5R X5R X5R X5R EMPTY X5R 4026.3V 402 402 402 402 402 805 EMPTY

C5R11 C4R49 C4T16 C4R63 C4R43 C5R14 C4T8 2 1 1 2 1 2 1 2 1 2 1 2 1 2 4.7UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% .1UF 10% 6.3V X5R6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R 402 X5R X5R X5R X5R EMPTY 805 402 402 402 402 402

C4R18 C4T1 C4T2 .1UFC5R17 C5R9 C5R6 .1UF1 2 1 2 1 2 1 X5R 2 1 2 2 1 10% .1UF 10% .1UF 10% 10% .1UF 10% 4.7UF 10% 6.3V402 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R 805 402 402 402 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=GPU, DECOUPLING] Tue May 08 18:24:14 2007 FALCON_RETAIL 18/82 1.0 CONFIDENTIAL CR-19 : @FALCON_LIB.FALCON(SCH_1):PAGE19

MEMORY PARTITION A, TOP CHIP SELECT = 0, MIRROR FUNCTION = 0 V_MEM

1 1 R4F3 R4F4 60.4 60.4 1% 1% V_MEM CH CH U4F1 IC 402 402 U4F1 IC 2 2 GDDR136 MA_CLK0_DP GDDR136 V1 VDDQ<21>VDDQ<20> MF=0 14 MF=0 DQ31 MA_DQ30MA_DQ31 14 20 R12 DQ30 14 20 VDDQ<19> IN T3 MA_DQ29 BI R9 VSSQ<19> T12 DQ29 MA_DQ28 14 20 R4 T9 DQ28 T2 BI VDDQ<18>VDDQ<17> VSSQ<18>VSSQ<17> R3 MA_DQ27 BI 14 20 R1 T4 DQ27 BI 20 N12 T1 R2 MA_DQ26 VDDQ<16>VDDQ<15> VSSQ<16>VSSQ<15> DQ26 M3 BI 14 20 N9 P12 DQ25 L3 MA_DQ25 BI 20 VDDQ<14> VSSQ<14> N2 MA_DQ24 BI V12 P9 DQ24 M2 20 VDDQ<13> VSSQ<13> P4 CLK_DP P2 MA_WDQS3 14 N4 CLK_DN WDQS3 IN 14 N1 VDDQ<12> VSSQ<12> P1 14 MA_CLK0_DN J10 RDQS3 P3 MA_DM3MA_RDQS3 14 VSSQ<11> N3 OUT 20 J9 L11 IN DM3 14 VDDQ<11>VDDQ<10> VSSQ<10> 14 RESET 14 J4 L2 MEM_RST J11 14 VDDQ<9> VSSQ<9> IN T10 E12 G11 DQ23 MA_DQ23 BI 14 20 MA_A<11..0> A11/A7 T11 IN E9 VDDQ<8> VSSQ<8> G2 IN 11 DQ22 MA_DQ22 14 20 L4 A10/A8 R10 E4 VDDQ<7> VSSQ<7> D12 10 V9 DQ21 MA_DQ21 14 20 K2 A9/A3 R11 E1 VDDQ<6> VSSQ<6> D9 DQ20 MA_DQ20 14 20 14 D4 A8/A10 M10 C12 VDDQ<5> VSSQ<5> 9 DQ19 N11 MA_DQ19 BI 20 VDDQ<4> VSSQ<4> 13 8 M9 A7/A11 MA_DQ18 BI C9 D1 7 K11 DQ18 L10 14 20 A6/A2 MA_DQ17 BI C4 VDDQ<3> VSSQ<3> B12 6 K10L9 DQ17 M11 14 20 A5/A1 MA_DQ16 BI C1 VDDQ<2> VSSQ<2> B9 5 H11 DQ16 P11 BI 20 MA_WDQS2 14 A12 VDDQ<1> VSSQ<1> B4 4 K9 A4/A0 WDQS2 P10 BI M4 MA_RDQS2 IN 14 A1 VDDQ<0> VSSQ<0> B1 14 3 A3/A9 RDQS2 N10 BI 20 14 K3 A2/A6 MA_DM2 BI OUT H2 DM2 14 V2 VDD<7> VSS<7> V3 1 A1/A5 G10 2 K4 F11 M12 VDD<6> VSS<6> L12 A0/A4 DQ15 MA_DQ15 IN 14 20 0 M1 VDD<5> VSS<5> L1 DQ14 F10 MA_BA<2..0> E11 14 20 V11 VDD<4> VSS<4> G12 IN 2 H10 BA2/RAS_N DQ13 MA_DQ13MA_DQ14 BI 14 20 C10 BI F12 VDD<3> VSS<3> G1 1 G9 BA1/BA0 DQ12 MA_DQ12 14 20 C11 BIBI F1 VDD<2> VSS<2> A10 0 G4 BA0/BA1 DQ11 MA_DQ11 14 20 A11 VDD<1> VSS<1> V10 DQ10 MA_DQ10 20 MA_DQ9 14 A2 VDD<0> VSS<0> A3 MA_CKE H4 CKE/WE_N DQ9 D11B10 14 20 MA_WE_N H9 B11 MA_DQ8 12 WE_N/CKE DQ8 D10 BI 20 K12 J3 14 F4 MA_WDQS1 BI 14 VDDA<1> NC<1> IN MA_CAS_N CAS_N/CS_N WDQS1 E10 IN 14 K1 J2 14 BI 20 VDDA<0> NC<0> 12 IN MA_RAS_N H3 RAS_N/BA2 RDQS1 MA_RDQS1 14 14 IN BIOUT MA_CS0_N F9 CS_N/CAS_N DM1 MA_DM1 14 14 14 IN J12 VSSA<1> 14 IN A9 G3 MA_DQ7 J1 VSSA<0> MF DQ7 F2 IN 14 20 IN MA_DQ6 14 20 MEM_SCAN_TOP_EN DQ6 F3 MA_DQ5 BI MEM_SCAN_EN V4 SCAN_EN DQ5 14 20 IN C2E2 MA_DQ4 BI X801995-011 DQ4 B3C3 BI 14 20 19 IN MEM_A_VREF1 H1 VREF1 DQ3 MA_DQ3 BI 14 20 IN H12 B2 MA_DQ2 BI 20 20 MEM_A_VREF0 VREF0 DQ2 D2 14 20 MA_CS1_N DQ1 MA_DQ1 BI 20 IN D3 BI 14 DQ0 E3 BI 20 WDQS0 MA_DQ0 14 IN 14 MX_CS1_N CONNECTED RDQS0 14 MA_WDQS0 OUT TO J3 O SUPPORT 1G DM0 14 MA_RDQS0 IN RAM CONFIGS. V_MEM MA_DM0 ZQ A4 MA_ZQ_TOP

X801995-011 R3F1 1 243 R4U4 1% 549 CH 1% 402 2 CH V_MEM 402 PARTITION A DECOUPLING 2 V_MEM MEM_A_VREF1 OUT 19 20

1 1 C3F3 C4F9 C4F11 C4F7 C3F1 C4F1 C4F6 C4F3 C4F12 .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF R4U5 C4U9 4.7UF 805 10% 10% 10% 10% 10% 10% 10% 10% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 1.27K .1UF 6.3V 10% 2 X5RMEMORYX5R A, TOP,X5R DECOUPLINGX5R X5R X5R X5R X5R 1% 6.3V TO CHANGE MEM VREF, CHANGE THESE RESISTORS TO MATCH THE TABLE X5R 402 402 402 402 402 402 402 402 CH X5R R4U5, R4F2, R5U3, R5F2, R2R2, R3D2, R2T3, R3E2 402 402 2 MEM VREF RESISTOR VALUE 70% 1.27KOHM 72% 1.40KOHM

THESE ARE THE MEM VREFS NEEDED FOR VARIOUS MEMORIES. CONSULT WITH MEM TEAM FOR USAGE. DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=DUAL ETHERNET PHY] Tue May 08 18:24:15 2007 FALCON_RETAIL 19/82 1.0 CONFIDENTIAL CR-20 : @FALCON_LIB.FALCON(SCH_1):PAGE20

CHIP SELECT = 1, MIRROR FUNCTION = 1

MEMORY PARTITION A, BOTTOM V_MEM

1 160.4 R4U2 R4U3 60.4 1% 1% CH CH 402 402 2 2 U4U1 IC MA_DQ23 V_MEM GDDR136 MA_DQ22 14 MA_CLK1_DP MF=1 DQ31 U4U1 IC DQ30 IN BI 14 19 GDDR136 DQ29 MA_DQ21 BI T3 MA_DQ20 14 19 V1 VDDQ<21> MF=1 DQ28 BI 14 19 R12 DQ27 T2 MA_DQ19 BI VDDQ<20> R3 14 19 R9 T12 MA_DQ18 BI 14 19 VDDQ<19>VDDQ<18> VSSQ<19>VSSQ<18> DQ26 R2 R4 T9 L3 BI 14 19 VDDQ<17> VSSQ<17> DQ25 M3 MA_DQ17 BI R1 T4 DQ24 M2 MA_DQ16 14 19 VDDQ<16> VSSQ<16> N2 14 19 N12 T1 J11 CLK_DP P2 VDDQ<15> VSSQ<15> WDQS3 MA_WDQS2 14 N9 P12 J10 CLK_DN P3 VDDQ<14> VSSQ<14> 14 MA_CLK1_DN RDQS3 MA_RDQS2 OUT 19 14 V12 P9 BI 14 VDDQ<13> VSSQ<13> DM3 MA_DM2 IN N4 P4 13 RESET VSSQ<12> MEM_RST N3 14 19 N1 P1 DQ23 T10 MA_DQ31 J9 VDDQ<12> VSSQ<11> MA_A<11..0> IN 14 19 L11 11 A7/A11 DQ22 T11 MA_DQ30 14 19 J4 VDDQ<11> VSSQ<10> L2 10 A8/A10 R10 MA_DQ29 BI 14 19 VDDQ<10> DQ21 E12 VSSQ<9> G11 R11 BI 14 19 9 V9L9 A3/A9 DQ20 MA_DQ28 VDDQ<9> VSSQ<8> BI 14 19 E9 G2 8 K11 A10/A8 DQ19 M10 MA_DQ27 VDDQ<8> 14 M4 BI 14 19 E4 VSSQ<7> D12 IN 7 K2 A11/A7 N11 VDDQ<7> DQ18 MA_DQ26 BI 14 19 E1 VSSQ<6> D9 L4 L10 IN 6 A2/A6 DQ17 MA_DQ25 14 C12 VDDQ<6>VDDQ<5> VSSQ<5> D4 5 K3 P11M11 19 14 A1/A5 DQ16 MA_DQ24 C9 VDDQ<4> VSSQ<4> D1 IN H2 14 K4 A0/A4 WDQS2 MA_WDQS3 BI IN C4 VDDQ<3> VSSQ<3> B12 3 P10 A9/A3 RDQS2 MA_RDQS3 BI OUT C1 VDDQ<2> VSSQ<2> B9 4 K10 N10 M9 A6/A2 DM2 MA_DM3 BI A12 VDDQ<1> VSSQ<1> B4 1 H11 14 19 2 A5/A1 A1 VDDQ<0> VSSQ<0> B1 0 K9 DQ15 G10 MA_DQ7 14 19 A4/A0 IN DQ14 F11 14 19 MA_BA<2..0> 14 19 V2 VDD<7> VSS<7> V3 IN 2 H3 F10 MA_DQ6 14 19 14 RAS_N/BA2 DQ13 BI 14 19 L12 MA_DQ5 14 19 M12 VDD<6> VSS<6> 14 1 G4 DQ12 E11 BI 14 19 14 BA0/BA1 MA_DQ4 M1 VDD<5> VSS<5> L1 14 0 G9 C10 BI 14 BA1/BA0 DQ11 V11 G12 14 C11 MA_DQ3 BI 19 14 VDD<4> VSS<4> DQ10 BI F12 VDD<3> VSS<3> G1 14 H9 B10D11 MA_DQ1MA_DQ2 WE_N/CKE DQ9 BI F1 VDD<2> VSS<2> A10 H4 DQ8 B11 MA_DQ0 BI 12 MA_CKE CKE/WE_N 14 19 A11 VDD<1> VSS<1> V10 F9 MA_WDQS0 BI 14 19 MA_WE_N CS_N/CAS_N WDQS1 A2 A3 12 IN MA_CAS_N H10 D10 MA_RDQS0 IN 14 19 VDD<0> VSS<0> IN F4 BA2/RAS_N RDQS1 E10 OUT 14 19 DM1 14 IN MA_RAS_N A9 CAS_N/CS_N IN 14 19 K12 VDDA<1> NC<1> J3 19 IN MA_CS1_N G3 MA_DM0 14 19 K1 J2 IN VDDA<0> NC<0> MF DQ7 F2 MA_DQ15 14 19 DQ6 F3 MA_DQ14 14 19 J12 IN MEM_SCAN_BOT_EN BI 14 VSSA<1> V4 DQ5 E2 SCAN_EN MA_DQ13 BI 19 14 J1 IN C2 VSSA<0> MEM_SCAN_EN DQ4 C3 MA_DQ12 BI 14 20 H1 DQ3 MA_DQ11 BI IN H12 VREF1 D2B3 MA_DQ10 IN DQ2 BI MEM_A_VREF0 VREF0 B2 MA_DQ9 BI X801995-011 MEM_A_VREF1 DQ1 DQ0 MA_DQ8 BI MA_WDQS1 BI WDQS0 IN RDQS0 D3 MA_RDQS1 OUT DM0 E3 MA_DM1 IN

V_MEM ZQ A4 MA_ZQ_BOT 19 1

X801995-011 R3U1 243 1 1% R4F1 CH 402 2 1%549 V_MEM CH 402 2 MEMORY A, BOTTOM, DECOUPLING OUT 20

MEM_A_VREF0 C3U2 C4U8 1 C4U11 C4U6 C3U1 C4U1 C4U5 C4U2 .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF R4F2 C4F2 10% 10% 10% 10% 10% 10% 10% 10% 1.27K .1UF 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 1% 10% X5R X5R X5R X5R X5R X5R X5R X5R 6.3V 402 402 402 402 402 402 402 402 CH X5R 402 402 2

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=MEMORY PARTITION A, TOP] Tue May 08 18:24:15 2007 FALCON_RETAIL 20/82 1.0 CONFIDENTIAL CR-21 : @FALCON_LIB.FALCON(SCH_1):PAGE21

MEMORY PARTITION B, TOP V_MEM CHIP SELECT = 0, MIRROR FUNCTION = 0

1 1 R5F3 R5F4 60.4 60.4 V_MEM 1% 1% CH CH 402 402 U5F1 IC 2 2 GDDR136

MB_CLK0_DP U5F1 IC VDDQ<21> MF=1 MB_DQ30 R12 VDDQ<20> GDDR136 MB_DQ31 R9 VDDQ<19> VSSQ<19> T12 14 IN MF=0 DQ31 14 22 R4 VDDQ<18> VSSQ<18> T9 DQ30 MB_DQ29 14 22 V1 R1 VDDQ<17> VSSQ<17> T4 DQ29 MB_DQ28 BI 14 22 N12 VDDQ<16> VSSQ<16> T1 DQ28 14 22 VDDQ<15> VSSQ<15> MB_DQ27 N9 P12 DQ27 T3 MB_DQ26 BI 14 22 V12 VDDQ<14> VSSQ<14> P9 DQ26 T2 22 N4 VDDQ<13> VSSQ<13> P4 R3 MB_DQ25 DQ25 MB_DQ24 BI 14 22 N1 VSSQ<12> P1 DQ24 R2 22 VDDQ<12> L11 CLK_DP BI 14 J9 VSSQ<11> J11 M3 MB_WDQS3 BI VDDQ<11> L2 WDQS3 IN 14 J4 VSSQ<10> MB_CLK0_DN J10 CLK_DN N2 MB_RDQS3 BI VDDQ<10> 14 RDQS3 L3 BI OUT 22 14 E12 VSSQ<9> G11 IN MB_DM3 VDDQ<9> RESET DM3 M2 E9 VSSQ<8> G2 MEM_RST IN VDDQ<8> IN 14 E4 VSSQ<7> D12 DQ23 T10 MB_DQ23 14 1422 E1 VDDQ<7> MB_A<11..0> A11/A7 P2 P3 BI VSSQ<6> D9 IN 11 DQ22 T11 MB_DQ22 14 22 VDDQ<6> L4 A10/A8 N3 BI C12 VDDQ<5> VSSQ<5> D4 10 V9 DQ21 R10 MB_DQ21 14 22 14 K2 A9/A3 C9 VDDQ<4> VSSQ<4> D1 DQ20 R11 MB_DQ18MB_DQ20 14 22 A8/A10 C4 VDDQ<3> VSSQ<3> B12 14 9 DQ19 M10 MB_DQ19 14 22 C1 13 8 M9 A7/A11 VDDQ<2> VSSQ<2> B9 7 K11 DQ18 N11 22 A6/A2 A12 VDDQ<1> VSSQ<1> B4 6 K10L9 DQ17 L10 MB_DQ17 22 B1 A5/A1 BI 14 A1 VDDQ<0> VSSQ<0> H11 DQ16 M11 MB_DQ16 14 22 5 A4/A0 BI 4 K9 WDQS2 P11 MB_WDQS2 BI 14 M4 A3/A9 V2 VDD<7> 3 RDQS2 P10 MB_RDQS2 BI 22 14 VSS<7> K3 BI OUT M12 VDD<6> L12 2 A2/A6 DM2 N10 MB_DM2 14 VSS<6> V3 H2 BI M1 VDD<5> L1 1 A1/A5 IN VSS<5> K4 V11 VDD<4> G12 0 A0/A4 DQ15 G10 MB_DQ15 14 22 VSS<4> IN F12 VDD<3> G1 DQ14 F11 MB_DQ14 14 22 VSS<3> MB_BA<2..0> F1 VDD<2> A10 H10 BA2/RAS_N DQ13 F10 MB_DQ13 14 22 VSS<2> 14 2 A11 VDD<1> VSS<1> V10 1 G9 BA1/BA0 DQ12 E11 MB_DQ12 14 22 A2 VDD<0> VSS<0> A3 0 G4 BA0/BA1 DQ11 C10 MB_DQ11 14 22 BI DQ10 C11 MB_DQ10 14 22 J3 IN MB_WE_N BI K12 NC<1> MB_CKE H4 CKE/WE_N DQ9 B10 MB_DQ9 14 22 VDDA<1> J2 BI K1 NC<0> 14 WE_N/CKE DQ8 B11 MB_DQ8 BI 22 VDDA<0> MB_CAS_N D11 14 14 F4 MB_WDQS1 BI CAS_N/CS_N WDQS1 IN 14 J12 IN MB_RAS_N H9 D10 BI VSSA<1> RAS_N/BA2 RDQS1 MB_RDQS1 BIOUT 22 14 J1 14 IN MB_CS0_N E10 MB_DM1 VSSA<0> 14 IN H3 CS_N/CAS_N DM1 BI 14 14 IN MEM_SCAN_TOP_ENF9 IN MF G3 MB_DQ7 14 22 DQ7 IN X801995-011 12 A9 F2 MB_DQ6 14 22 IN MEM_SCAN_EN DQ6 F3 V4 SCAN_EN DQ5 MB_DQ5 BI 14 22 12 E2 MB_DQ4 BI MB_CS1_N 14 IN DQ4 C3 14 22 MEM_B_VREF1 H1 BI 21 VREF1 DQ3 MB_DQ3 BI 14 22 IN IN MEM_B_VREF0 H12 C2 MB_DQ2 22 IN VREF0 DQ2 BI 14 22 DQ1 B3 MB_DQ1 BI 14 22 BI DQ0 B2 MB_DQ0 22 MB_WDQS0 BI 14 WDQS0 D2 IN 14 RDQS0 D3 MB_RDQS0 OUT 22 14 E3 MB_DM0 V_MEM DM0 IN 14

ZQ A4 MB_ZQ_TOP 21 1 243

1 X801995-011 R4F5 R5U4 V_MEM 549 1% 1% CH CH 402 MEMORY B, TOP, DECOUPLING 402 2 PARTITION B DECOUPLING 2 V_MEM MEM_B_VREF1 OUT 22 C4F10 C5F5 C4F8 C4F5 C4F4 C5F2 C5F3 C5F4 .22UF .22UF .22UF .22UF .22UF .22UF.22UF .22UF 10% 10% 10% 10% 10% 10% 10% 10% 1 1 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V C5F6 1 C5F8 X5R X5R X5R X5R X5R X5R X5R X5R R5U3 C5U5 4.7UF 220UF 402 402 402 402 402 402 402 402 10% 20% 1.27K .1UF 6.3V 10V 1% 10% 2 X5R ELEC 6.3V 2 RDL CH X5R 805 402 402 2

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=MEMORY PARITION A, BOTTOM] Tue May 08 18:24:15 2007 FALCON_RETAIL 21/82 1.0 CONFIDENTIAL CR-22 : @FALCON_LIB.FALCON(SCH_1):PAGE22

MEMORY PARTITION B, BOTTOM CHIP SELECT = 1, MIRROR FUNCTION = 1

V_MEM

1 1 R5U2 R5U1 60.4 60.4 1% 1% CH CH MB_CLK1_DP 402 402 U5U1 IC 2 2 V_MEM GDDR136 MB_DQ23 14 IN MF=1 DQ31 U5U1 IC DQ30 MB_DQ22 DQ29 MB_DQ21 BI GDDR136 MB_DQ20 VDDQ<21> MF=1 DQ28 R12 DQ27 MB_DQ19 VDDQ<20> T3 BI R9 T12 MB_DQ18 VDDQ<19>VDDQ<18> VSSQ<19>VSSQ<18> DQ26 T2 BI R4 T9 DQ25 R3 MB_DQ17 BIBI V1 R1 VDDQ<17> VSSQ<17> BI T4 DQ24 R2 MB_DQ16 14 21 VDDQ<16> VSSQ<16> T1 M3 BI N12 J11 CLK_DP WDQS3 MB_WDQS2 IN 14 21 VDDQ<15> VSSQ<15> CLK_DN N2 14 21 N9 P12 MB_CLK1_DN J10 RDQS3 MB_RDQS2 BI VDDQ<14> VSSQ<14> IN L3 MB_DM2 OUT 14 21 V12 P9 14 DM3 M2 14 21 VDDQ<13> VSSQ<13> P4 MEM_RST RESET N4 IN 14 21 N1 VSSQ<12> P1 VDDQ<12> DQ23 T10 P3MB_DQ31 14 21 J9 VSSQ<11> IN MB_A<11..0> P2 IN 14 21 L11 11 A7/A11 DQ22 T11 MB_DQ30 J4 VDDQ<11> VSSQ<10> 14 L2 10 A8/A10 R10N3 MB_DQ29 VDDQ<10> 14 V9 DQ21 BI 21 14 E12 VSSQ<9> G11 L9 A3/A9 DQ20 R11 MB_DQ28 BI VDDQ<9> 9 K11 14 E9 VSSQ<8> G2 13 8 M4 A10/A8 DQ19 M10 MB_DQ27 BI VDDQ<8> VSSQ<7> K2 MB_DQ26 BI E4 D12 7 A11/A7 DQ18 N11 14 21 E1 VDDQ<7> VSSQ<6> L4 BI 14 21 D9 A2/A6 DQ17 L10 MB_DQ25 BI VDDQ<6> 6 K3 14 21 C12 VDDQ<5> VSSQ<5> D4 5 M11 MB_DQ24 BI H2 A1/A5 DQ16 14 21 14 21 C9 VDDQ<4> VSSQ<4> D1 4 P11 MB_WDQS3 K4 A0/A4 WDQS2 IN 14 21 C4 VDDQ<3> VSSQ<3> B12 14 3 P10 MB_RDQS3 14 21 A9/A3 RDQS2 OUT C1 VDDQ<2> VSSQ<2> B9 K10M9 A6/A2 DM2 N10 MB_DM3 14 21 2 BI A12 VDDQ<1> VSSQ<1> B4 1 H11 A5/A1 B1 K9 14 A1 VDDQ<0> VSSQ<0> 0 A4/A0 DQ15 G10 MB_DQ7 21 14 F11 IN MB_BA<2..0> DQ14 MB_DQ6 14 V2 VDD<7> VSS<7> RAS_N/BA2 DQ13 F10 MB_DQ5 BI 2 14 21 M12 VDD<6> VSS<6> L12 1 G4 DQ12 E11 MB_DQ4 BI V3 BA0/BA1 14 21 M1 VDD<5> VSS<5> L1 0 G9 C10 MB_DQ3 BI H3 BA1/BA0 DQ11 14 21 V11 G12 C11 MB_DQ2 BI VDD<4> VSS<4> IN DQ10 BI 14 21 F12 VDD<3> VSS<3> G1 MB_CKE B10 MB_DQ1 14 21 WE_N/CKE DQ9 BI F1 A10 MB_WE_N H4 B11 MB_DQ0 14 21 VDD<2> VSS<2> CKE/WE_N DQ8 D11 A11 V10 14 H9 14 21 VDD<1> VSS<1> 14 CS_N/CAS_N WDQS1 IN 14 21 A2 A3 IN MB_CAS_N H10 D10 VDD<0> VSS<0> 14 BA2/RAS_N RDQS1 MB_WDQS0 OUT 14 IN MB_RAS_N F9 F4 E10 MB_DM0 14 IN MB_CS1_N CAS_N/CS_N DM1 MB_RDQS0 BI 21 14 K12 J3 14 IN BI 14 VDDA<1> NC<1> J2 K1 VDDA<0> NC<0> IN MF G3 MB_DQ15 12 MEM_SCAN_BOT_EN DQ7 14 21 21 A9 F2 MB_DQ14 IN IN DQ6 F3 14 21 J12 VSSA<1> 12 V4 DQ5 MB_DQ13 14 21 SCAN_EN E2 BI J1 IN MEM_SCAN_EN DQ4 MB_DQ12 14 21 VSSA<0> C3 BI 14 21 22 H1 DQ3 MB_DQ11 BI IN VREF1 14 21 IN MEM_B_VREF0 H12 DQ2 C2 MB_DQ10 BI VREF0 BI 14 21 X801995-011 MEM_B_VREF1 DQ1 B3 MB_DQ9 14 21 B2 BI DQ0 MB_DQ8 BI 14 WDQS0 D2 MB_WDQS1 BI 21 14 14 RDQS0 D3 MB_RDQS1 OUTIN V_MEM E3 MB_DM1 DM0 IN

ZQ A4 MB_ZQ_BOT

1 X801995-011 R4U1 R5F1 243 549 1% 1% CH 21 V_MEM CH 402 402 2 2 MEMORY B, BOTTOM, DECOUPLING MEM_B_VREF0 OUT 22

1 C4U10 C5U4 C4U7 C4U4 C4U3 C5U1 C5U2 C5U3 R5F2 C5F1 .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF 1.27K .1UF 10% 10% 10% 10% 10% 10% 10% 10% 1% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R X5R X5R X5R CH X5R 402 402 402 402 402 402 402 402 402 402 2

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=MEMORY PARITION B, TOP] Tue May 08 18:24:15 2007 FALCON_RETAIL 22/82 1.0 CONFIDENTIAL CR-23 : @FALCON_LIB.FALCON(SCH_1):PAGE23

CHIP SELECT = 0, MIRROR FUNCTION = 0

MEMORY PARTITION C, TOP

V_MEM

1 1 R3D5 R3D4 60.4 60.4 V_MEM 1% 1% CH CH U3D1 IC 402 U3D1 IC 2 2 GDDR136 GDDR136 VDDQ<21> MF=0 MC_CLK0_DP MC_DQ30 VDDQ<20> 15 402 MF=0 DQ31 MC_DQ31 15 24 R12 IN MC_DQ29 VDDQ<19> DQ30 15 24 R9 VSSQ<19> T12 BI R4 DQ29 MC_DQ28 15 24 VDDQ<18> VSSQ<18> T9 BI V1 R1 VDDQ<17> VSSQ<17> DQ28 15 24 T4 BI T1 DQ27 T3 MC_DQ27 BI 15 24 N12 VDDQ<16> VSSQ<16> VDDQ<15> VSSQ<15> DQ26 T2 MC_DQ26 BI 24 N9 P12 VDDQ<14> VSSQ<14> DQ25 R3 MC_DQ24MC_DQ25 BI 15 24 V12 P9 DQ24 R2 MC_WDQS3 BI 24 N4 VDDQ<13> VSSQ<13> P4 J11 CLK_DP M3 BI 15 N1 VDDQ<12> VSSQ<12> P1 WDQS3 MC_RDQS3 IN 15 MC_CLK0_DN J10 CLK_DN N2 J9 VSSQ<11> L11 15 RDQS3 L3 MC_DM3 OUT 24 15 VDDQ<11> L2 IN MEM_RST J4 VDDQ<10> VSSQ<10> RESET DM3 M2 15 13 MC_DQ23 15 E12 VDDQ<9> VSSQ<9> G11 IN 15 DQ23 T10 15 24 E9 VDDQ<8> VSSQ<8> G2 MC_A<11..0> A11/A7 P2 P3MC_DQ22 IN IN 11 DQ22 T11 15 24 E4 VDDQ<7> VSSQ<7> D12 L4 A10/A8 N3 E1 10 V9 DQ21 R10 MC_DQ21 BI 24 VDDQ<6> VSSQ<6> D9 K2 A9/A3 MC_DQ20 9 DQ20 R11 BI 15 24 C12 VDDQ<5> VSSQ<5> D4 A8/A10 MC_DQ19 BI D1 8 M9 DQ19 M10 15 24 C9 VDDQ<4> VSSQ<4> A7/A11 MC_DQ18 BI C4 7 K11 DQ18 N11 15 24 VDDQ<3> VSSQ<3> B12 A6/A2 MC_DQ17 BI C1 15 K10L9 DQ17 L10 BI 15 24 VDDQ<2> VSSQ<2> B9 6 A5/A1 MC_DQ16 H11 DQ16 M11 BI 24 A12 VDDQ<1> VSSQ<1> B4 5 MC_WDQS2 15 B1 4 K9 A4/A0 WDQS2 P11 A1 VDDQ<0> VSSQ<0> M4 MC_RDQS2 BI 15 3 A3/A9 P10 IN K3 RDQS2 MC_DM2 OUT 24 15 2 A2/A6 DM2 N10 15 V2 H2 IN VDD<7> VSS<7> 1 A1/A5 M12 L12 K4 VDD<6> VSS<6> V3 A0/A4 G10 MC_DQ15 M1 L1 DQ15 BI 15 24 VDD<5> F11 MC_DQ14 V11 VSS<5> G12 MC_BA<2..0> 0 DQ14 BI 15 24 VDD<4> VSS<4> H10 BA2/RAS_N DQ13 F10 MC_DQ13 15 24 F12 G1 2 VDD<3> VSS<3> 1 G9 BA1/BA0 DQ12 E11 MC_DQ12 15 24 F1 VDD<2> A10 G4 BI VSS<2> 0 BA0/BA1 DQ11 C10 MC_DQ11 BI 15 24 A11 VDD<1> VSS<1> V10 15 C11 MC_DQ10 A2 A3 IN DQ10 BI 15 24 VDD<0> VSS<0> MC_CKE H4 CKE/WE_N DQ9 B10 MC_DQ9 15 24 J3 MC_WE_N WE_N/CKE DQ8 B11 MC_DQ8 24 K12 D11 15 VDDA<1> NC<1> 15 MC_CAS_N F4 MC_WDQS1 BI K1 J2 15 CAS_N/CS_N WDQS1 IN 15 VDDA<0> NC<0> IN H9 D10 BI 15 MC_RAS_N RAS_N/BA2 RDQS1 MC_RDQS1 OUT 24 15 IN E10 MC_DM1 BI J12 15 IN MC_CS0_N H3 CS_N/CAS_N DM1 15 VSSA<1> 15 J1 IN F9 VSSA<0> IN MF G3 MC_DQ7 15 24 12 MEM_SCAN_TOP_EN DQ7 IN A9 F2 MC_DQ6 15 24 IN DQ6 F3 IN 12 V4 MC_DQ5 BI 15 24 X801995-011 MEM_SCAN_EN SCAN_EN DQ5 E2 MC_DQ4 BI IN DQ4 C3 BI 15 24 H1 MC_DQ3 BI 23 MEM_C_VREF1 VREF1 DQ3 15 24 IN H12 C2 MC_DQ2 BI 24 IN MEM_C_VREF0 VREF0 DQ2 BI 15 24 DQ1 B3 MC_DQ1 15 24 B2 BI MC_CS1_N DQ0 BI 24 15 D2 15 WDQS0 MC_DQ0 IN 15 RDQS0 D3 OUT 24 15 E3 MC_WDQS0 IN DM0 MC_RDQS0 15 ZQ A4 MC_ZQ_TOPMC_DM0 V_MEM 1

X801995-011 R3D1 243 1% V_MEM 1 CH R2R1 402 MEMORY C, TOP, DECOUPLING 549 2 1% PARTITION C DECOUPLING CH V_MEM 402 2 C2E1 C3E2 C3E1 C3E3 C3E5 C3E7 C3E6 C2E3 .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF OUT 23 24 10% 10% 10% 10% 10% 10% 10% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V MEM_C_VREF1 X5R X5R X5R X5R X5R X5R X5R X5R 1 C2D3 1 C3C5 1 C2E8 402 402 402 402 402 402 402 402 1 4.7UF 4.7UF 4.7UF 10% 10% 10% R2R2 C2R9 6.3V 6.3V 6.3V 1.27K .1UF 2 X5R 2 X5R 2 X5R 1% 10% 805 805 805 6.3V CH X5R 402 402 2

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=MEMORY PARTITION B, BOTTOM] Tue May 08 18:24:15 2007 FALCON_RETAIL 23/82 1.0 CONFIDENTIAL CR-24 : @FALCON_LIB.FALCON(SCH_1):PAGE24

MEMORY PARTITION C, BOTTOM CHIP SELECT = 1, MIRROR FUNCTION = 1 V_MEM

1 1 R2R4 R2R3 60.4 60.4 1% 1% CH CH V_MEM 402 402 U3R1 IC 2 2 V_MEM GDDR136 MC_CLK1_DP U3R1 IC 15 MF=1 DQ31 MC_DQ23 15 23 DQ30 MC_DQ22 15 23 GDDR136 T3 BI 1 DQ29 MC_DQ21MC_DQ20 15 23 C3T4 VDDQ<21> MF=1 T2 BI 6.3V DQ28 23 .1UF R12 R3 MC_DQ19 BI 10% VDDQ<20> DQ27 BI 15 23 R9 VDDQ<19> VSSQ<19> T12 R2 MC_DQ18 2 VDDQ<18> VSSQ<18> DQ26 BI 15 23 X5R R4 T9 M3 402 V1 VDDQ<17> VSSQ<17> DQ25 L3 MC_DQ17 BI 15 23 R1 T4 N2 BI VDDQ<16> VSSQ<16> T1 DQ24 M2 MC_DQ16 23 N12 CLK_DP BI 15 VDDQ<15> VSSQ<15> J11 WDQS3 P2 MC_WDQS2 IN N9 P12 CLK_DN MC_RDQS2 15 VDDQ<14> VSSQ<14> MC_CLK1_DN J10 RDQS3 P3 OUT 23 15 15 V12 P9 IN MC_DM2 N4 VDDQ<13> VSSQ<13> P4 15 MEM_RST DM3 15 RESET N3 N1 VSSQ<12> P1 VDDQ<12> VSSQ<11> L11 DQ23 T10 MC_DQ31 IN15 23 J9 MC_A<11..0> MC_DQ30 VDDQ<11> VSSQ<10> L2 11 A7/A11 DQ22 T11 15 23 J4 15 MC_DQ29 BI VDDQ<10> VSSQ<9> 10 V9 A8/A10 DQ21 R10 15 23 E12 G11 L9 MC_DQ28 BI VDDQ<9> VSSQ<8> 9 A3/A9 DQ20 R11 BI 15 23 E9 G2 13 K11 MC_DQ27 VDDQ<8> VSSQ<7> 8 M4 A10/A8 DQ19 M10 BI 15 23 E4 D12 IN K2 MC_DQ26 VDDQ<7> VSSQ<6> 7 A11/A7 DQ18 N11 BI 15 23 E1 D9 L4 MC_DQ25 BI VDDQ<6> VSSQ<5> D4 IN A2/A6 DQ17 L10 15 23 C12 VDDQ<5> 6 K3 BI D1 A1/A5 DQ16 M11 MC_DQ24 23 C9 VDDQ<4> VSSQ<4> IN 5 H2 P11 BI 15 4 MC_WDQS3 C4 VSSQ<3> B12 K4 A0/A4 WDQS2 IN 15 VDDQ<3> 15 3 A9/A3 RDQS2 P10 MC_RDQS3 23 15 C1 VDDQ<2> VSSQ<2> B9 M9 OUT 2 K10 A6/A2 DM2 N10 MC_DM3 15 A12 VDDQ<1> VSSQ<1> B4 B1 1 H11 A5/A1 A1 VDDQ<0> VSSQ<0> K9 A4/A0 DQ15 G10 MC_DQ7 IN15 23 DQ14 F11 MC_DQ6 15 23 V2 VSS<7> MC_BA<2..0> 0 BI VDD<7> IN H3 DQ13 F10 MC_DQ5 15 23 M12 VSS<6> L12 2 RAS_N/BA2 BI VDD<6> V3 1 G4 BA0/BA1 DQ12 E11 MC_DQ4 BI 15 23 M1 VDD<5> VSS<5> L1 0 G9 BA1/BA0 DQ11 C10 MC_DQ3 BI 15 23 V11 VDD<4> VSS<4> G12 DQ10 C11 MC_DQ2 BI 15 23 F12 VDD<3> VSS<3> G1 BI 23 MC_CKE H9 WE_N/CKE DQ9 B10 MC_DQ1 15 23 F1 VDD<2> VSS<2> A10 H4 B11D11 MC_DQ0 BI A11 V10 15 MC_WE_N CKE/WE_N DQ8 BI 23 VDD<1> VSS<1> F9 15 A2 A3 15 MC_CAS_N CS_N/CAS_N WDQS1 15 VDD<0> VSS<0> 15 IN MC_RAS_N H10 D10 15 15 IN F4 BA2/RAS_N RDQS1 MC_DM0MC_WDQS0 OUT DM1 E10 15 K12 J3 15 IN MC_CS1_N CAS_N/CS_N MC_RDQS0 IN VDDA<1> NC<1> A9 K1 J2 IN G3 MC_DQ15 VDDA<0> NC<0> 12 IN MEM_SCAN_BOT_EN MF DQ7 IN15 23 F2 MC_DQ14 J12 DQ6 15 23 VSSA<1> 12 IN V4 F3 MC_DQ13 BI J1 MEM_SCAN_EN SCAN_EN DQ5 E2 BI 15 23 VSSA<0> 24 MC_DQ12 IN DQ4 C2C3 BI 15 23 23 H1 DQ3 MC_DQ11 BI 15 23 IN MEM_C_VREF0 VREF1 H12 DQ2 B3 MC_DQ10 BI 15 23 X801995-011 IN MEM_C_VREF1 VREF0 D2 MC_DQ9 BI DQ1 B2 BI 15 23 DQ0 MC_DQ8 23 BI 15 WDQS0 MC_WDQS1 IN 15 RDQS0 D3 MC_RDQS1 OUT 23 15 DM0 E3 MC_DM1 15 V_MEM IN ZQ A4 MC_ZQ_BOT

1 X801995-011 R3R1 243 R3D3 1% 549 CH V_MEM 1% 402 CH 2 402 2 OUT 23 24 C3T2 C3T3 C3T5 C3T7 MEM_C_VREF0 C2T1 C3T1 C3T6 C2T3 .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF 1 10% 10% 10% 10% 10% 10% 10% 10% 6.3V 6.3V 6.3V 6.3V 6.3V X5R 6.3V 6.3V R3D2 C3D3 X5RMEMORYX5R C, BOTTOM,X5R DECOUPLINGX5R 402 X5R 6.3VX5R X5R 1.27K .1UF 402 402 402 402 402 402 402 10% 1% 6.3V CH X5R 402 402 2

DRAWING [PAGE_TITLE=MEMORY PARITION C, TOP] FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:15 2007 FALCON_RETAIL 24/82 1.0 CONFIDENTIAL CR-25 : @FALCON_LIB.FALCON(SCH_1):PAGE25

V_MEM MEMORY PARTITION D, TOP CHIP SELECT = 0, MIRROR FUNCTION = 0

1 1 R3E5 R3E4 MD_CLK0 60.4 60.4 V_MEM 1% 1% STITCHING CAP CH CH U3E1 IC MD_CLK0_DP 402 402 V_MEM 2 2 U3E1 IC GDDR136 V1 VDDQ<21>VDDQ<20> MF=0 GDDR136 R12 15 DQ31 MD_DQ31 15 26 VDDQ<19> MF=0 1 R9 T12 DQ30 MD_DQ30 VSSQ<19> IN 15 26 C3R3 R4 T9 DQ29 MD_DQ29 .1UF VDDQ<18>VDDQ<17> VSSQ<18>VSSQ<17> 15 26 10% R1 T4 DQ28 MD_DQ28 BI 15 26 6.3V N12 T1 MD_DQ27 2 X5R VDDQ<16>VDDQ<15> VSSQ<16>VSSQ<15> DQ27 MD_DQ26 BI 15 26 402 N9 P12 26 VDDQ<14> VSSQ<14> DQ26 T3 MD_WDQS3 BI V12 P9 MD_DQ25 15 26 VDDQ<13> VSSQ<13> DQ25 T2 BI 15 N4 P4 DQ24 MD_DQ24 26 VDDQ<12> VSSQ<12> CLK_DP R3 15 N1 P1 CLK_DN WDQS3 R2 BI IN J9 VSSQ<11> L11 15 MD_CLK0_DN J10 RDQS3 P3M3 MD_RDQS3 BI 26 15 J4 VDDQ<11>VDDQ<10> VSSQ<10> L2 N2 OUT IN J11 DM3 MD_DM3 15 VDDQ<9> VSSQ<9> RESET L3 E12 G11 MEM_RST 15 VDDQ<8> VSSQ<8> IN M2 MD_DQ23 15 E9 G2 DQ23 T10 15 26 MD_A<11..0> A11/A7 IN E4 VDDQ<7> VSSQ<7> D12 IN 11 T11 MD_DQ22 BI V9 DQ22 15 26 E1 VDDQ<6> VSSQ<6> D9 10 A10/A8 R10 MD_DQ21 BI L4 DQ21 P2 26 C12 VDDQ<5> VSSQ<5> D4 A9/A3 DQ20 R11N3 MD_DQ20 BI K2 BI 15 26 C9 VDDQ<4> VSSQ<4> D1 9 A8/A10 MD_DQ19 13 M9 DQ19 M10 BI 15 26 C4 8 A7/A11 VDDQ<3> VSSQ<3> B12 7 K11L9 DQ18 N11 MD_DQ18 BI 15 26 C1 VDDQ<2> VSSQ<2> B9 K10 A6/A2 L10 15 6 DQ17 MD_DQ17 BI 15 26 B4 M11 A12 VDDQ<1> VSSQ<1> H11 A5/A1 DQ16 MD_DQ16 BI 26 5 15 A1 VDDQ<0> VSSQ<0> B1 4 K9 A4/A0 P11 MD_WDQS2 WDQS2 IN 15 3 M4 A3/A9 P10 MD_RDQS2 RDQS2 OUT 26 15 V2 VDD<7> VSS<7> V3 2 K3 A2/A6 N10 MD_DM2 BI DM2 15 M12 VDD<6> VSS<6> L12 1 H2 A1/A5 K4 M1 VDD<5> VSS<5> L1 A0/A4 DQ15 G10 MD_DQ15 IN 15 26 0 V11 VDD<4> VSS<4> G12 DQ14 F11 MD_DQ14 MD_BA<2..0> 15 26 F12 VDD<3> VSS<3> G1 2 H10 BA2/RAS_N DQ13 F10 MD_DQ13 BI 15 26 BI F1 VDD<2> VSS<2> A10 1 G9 BA1/BA0 DQ12 E11 MD_DQ12 15 26 BI A11 VDD<1> VSS<1> V10 IN 0 G4 BA0/BA1 DQ11 C10 MD_DQ11 15 26 15 BI A2 VDD<0> VSS<0> A3 DQ10 C11 MD_DQ10 BI 15 26 MD_CKE H4 CKE/WE_N DQ9 B10 MD_DQ9 15 26 K12 VDDA<1> NC<1> J3 MD_WE_N WE_N/CKE DQ8 B11D11 MD_DQ8 26 15 15 K1 NC<0> J2 IN F4 CAS_N/CS_N WDQS1 MD_WDQS1 VDDA<0> 15 IN MD_CAS_N D10 BI IN 15 15 RAS_N/BA2 RDQS1 MD_RDQS1 BI 26 15 IN MD_RAS_NH9 E10 OUT J12 VSSA<1> 15 F9 CS_N/CAS_N DM1 MD_DM1 BI 15 IN MD_CS0_N J1 15 IN H3 VSSA<0> IN A9 MF DQ7 G3 MD_DQ7 15 26 12 IN MEM_SCAN_TOP_EN F2 IN DQ6 MD_DQ6 15 26 V4 F3 MD_DQ5 X801995-011 12 IN MEM_SCAN_EN SCAN_EN DQ5 E2 BI 15 26 DQ4 C3 MD_DQ4 BI 15 26 25 DQ3 MD_DQ3 BI 15 26 IN H1 VREF1 MEM_D_VREF1 H12 C2 MD_DQ2 BI 26 IN VREF0 DQ2 BI 15 26 MD_CS1_N MEM_D_VREF0 DQ1 B3 MD_DQ1 BI 15 26 15 DQ0 B2 MD_DQ0 26 BI 15 WDQS0 D2 MD_WDQS0 BI IN 15 RDQS0 D3 MD_RDQS0 OUT 26 15 E3 MD_DM0 DM0 IN 15

ZQ A4 MD_ZQ_TOP V_MEM 1 243 X801995-011 R3E1 402 V_MEM 1% 1 CH R2T4 MEMORY D, TOP, DECOUPLING 2 PARTITION D DECOUPLING 549 V_MEM 1% CH 402 2 C2D2 C2D1 C3D1 C3D2 C3D4 C3D6 C3D5 C2D4 .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF MEM_D_VREF1 25 26 10% 10% 10% 10% 10% 10% 10% 10% OUT 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 1 C2E2 X5R X5R X5R X5R X5R X5R X5R X5R X5R 402 402 402 402 402 402 402 402 8054.7UF 10% 1 6.3V 2 R2T3 C2T2 1.27K .1UF 1% 10% 6.3V CH X5R 402 402 2

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=MEMORY PARTITION C, BOTTOM] Tue May 08 18:24:15 2007 FALCON_RETAIL 25/82 1.0 CONFIDENTIAL CR-26 : @FALCON_LIB.FALCON(SCH_1):PAGE26

CHIP SELECT = 1, MIRROR FUNCTION = 1

MEMORY PARTITION D, BOTTOM V_MEM

1 1 R2T5 R2T6 60.4 60.4 1% 1% CH CH 402 402 2 2 U3T1 IC MD_DQ23 MD_CLK1_DP GDDR136 V_MEM 15 IN MF=1 DQ31 MD_DQ22 25 U3T1 IC DQ30 15 25 GDDR136 DQ29 MD_DQ21 15 25 BI VDDQ<21> MF=1 DQ28 MD_DQ20 25 MD_DQ19 BI R12 VDDQ<20> DQ27 T3 15 25 R9 T12 DQ26 T2 MD_DQ18 VDDQ<19> VSSQ<19> BI 15 25 R4 VDDQ<18> VSSQ<18> T9 DQ25 R3 MD_DQ17 BI 1515 25 V1 R1 VDDQ<17> VSSQ<17> T4 R2 DQ24 MD_DQ16 15 25 N12 VDDQ<16> VSSQ<16> T1 MD_CLK1_DN J11 CLK_DP M3 MD_WDQS2 WDQS3 IN 15 N9 VDDQ<15> VSSQ<15> P12 J10 CLK_DN N2 15 RDQS3 L3 MD_RDQS2 BIOUT 25 15 V12 VDDQ<14> VSSQ<14> P9 IN DM3 M2 MD_DM2 BIBI 15 VDDQ<13> VSSQ<13> P4 15 N4 13 RESET P1 IN MEM_RST 15 N1 VSSQ<12> 15 DQ23 T10 MD_DQ31 25 VDDQ<12> L11 MD_A<11..0> P2 P3 IN J9 VSSQ<11> IN A7/A11 DQ22 T11 MD_DQ30 15 25 J4 VDDQ<11> L2 11 N3 BI VSSQ<10> 10 V9 A8/A10 DQ21 R10 MD_DQ29 BI 15 25 VDDQ<10> L9 E12 VSSQ<9> G11 9 A3/A9 DQ20 R11 MD_DQ28 BI 15 25 VDDQ<9> K11M4 BI E9 VSSQ<8> G2 A10/A8 DQ19 M10 MD_DQ27 BI 15 25 E4 VDDQ<8> 8 K2 VSSQ<7> D12 7 A11/A7 DQ18 N11 MD_DQ26 BI 15 25 VDDQ<7> L4 E1 VSSQ<6> D9 6 A2/A6 DQ17 L10 MD_DQ25 BI 15 25 VDDQ<6> K3 BI C12 VDDQ<5> VSSQ<5> D4 5 A1/A5 DQ16 M11 MD_DQ24 15 25 D1 4 H2 BI C9 VDDQ<4> VSSQ<4> A0/A4 WDQS2 P11 MD_WDQS3 15 K4 IN C4 VDDQ<3> VSSQ<3> B12 3 A9/A3 RDQS2 P10 MD_RDQS3 25 15 OUT C1 VDDQ<2> VSSQ<2> B9 K10M9 A6/A2 DM2 N10 MD_DM3 15 15 2 A12 VDDQ<1> VSSQ<1> B4 1 H11 A5/A1 15 A1 VDDQ<0> VSSQ<0> B1 0 K9 A4/A0 DQ15 G10 MD_DQ7 25 IN DQ14 F11 MD_DQ6 15 25 MD_BA<2..0> V2 VDD<7> IN 2 RAS_N/BA2 DQ13 F10 MD_DQ5 BI 15 25 VSS<7> 15 M12 VDD<6> L12 1 G4 E11 MD_DQ4 BI 15 25 VSS<6> V3 15 BA0/BA1 DQ12 M1 L1 0 G9 C10 MD_DQ3 BI VDD<5> VSS<5> 15 H3 BA1/BA0 DQ11 15 25 V11 G12 C11 MD_DQ2 BI VDD<4> VSS<4> DQ10 BI 15 25 F12 G1 MD_CKE B10 MD_DQ1 BI VDD<3> VSS<3> IN WE_N/CKE DQ9 15 25 F1 A10 15 MD_WE_N H4 B11 MD_DQ0 BI VDD<2> VSS<2> IN CKE/WE_N DQ8 D11 15 25 15 12 BI A11 V10 MD_CAS_N H9 MD_WDQS0 15 VDD<1> VSS<1> CS_N/CAS_N WDQS1 IN BI A2 VSS<0> A3 IN H10 D10 MD_RDQS0 25 15 VDD<0> MD_RAS_N F9 F4 BA2/RAS_N RDQS1 MD_DM0 OUT BI IN DM1 E10 15 J3 MD_CS1_N CAS_N/CS_N K12 NC<1> IN 15 V_MEM VDDA<1> J2 K1 NC<0> MEM_SCAN_BOT_EN MF G3 15 25 IN VDDA<0> IN DQ7 F2 MD_DQ14MD_DQ15 IN15 A9 DQ6 25 J12 V4 F3 VSSA<1> 12 IN MEM_SCAN_EN SCAN_EN DQ5 E2 MD_DQ13 BI 25 J1 DQ4 C3 MD_DQ12 BI 15 25 VSSA<0> H1 MD_DQ11 BI 1 26 IN MEM_D_VREF0 VREF1 DQ3 BI 15 25 C2T7 25 H12 DQ2 C2 MD_DQ10 15 25 IN MEM_D_VREF1 VREF0 BI 4.7UF X801995-011 DQ1 B3 MD_DQ9 BI 15 25 10% B2 6.3V DQ0 MD_DQ8 15 25 2 X5R WDQS0 D2 MD_WDQS1 15 805 MD_RDQS1 IN RDQS0 D3 OUT 25 15 DM0 E3 MD_DM1 15 V_MEM ZQ A4 MD_ZQ_BOT

1 X801995-011 R3T1 243 V_MEM R3E3 1% 549 CH 1% 402 MEMORY D, BOTTOM, DECOUPLING CH 2 402 2 C3R1 OUT 25 26 V_MEM C2R7 C3R2 C3R4 C3R7 C3R6 C2R10 C2R8 .22UF .22UF .22UF .22UF .22UF .22UF .22UF.22UF MEM_D_VREF0 10% 10% 10% 10% 10% 10% 10% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 1 MEMORY D, BOTTOM, DECOUPLING X5R X5R X5R X5R X5R X5R X5R X5R 402 402 402 402 402 402 402 402 R3E2 C3E4 1.27K .1UF 1% 10% C2R13 C2T6 6.3V C3E8 C3F5 C3U4 C4F14 C4F15 C4U12 CH X5R .22UF .22UF .22UF .22UF .22UF .22UF .22UF .22UF 402 402 10% 10% 10% 10% 10% 10% 10% 10% 2 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R X5R X5R X5R X5R X5R X5R X5R 402 402 402 402 402 402 402 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=MEMORY PARTITION D, BOTTOM] Tue May 08 18:24:15 2007 FALCON_RETAIL 26/82 1.0 CONFIDENTIAL CR-27 : @FALCON_LIB.FALCON(SCH_1):PAGE27

HANA_V_12P0_DET_R

V_12P0 HANA, CLOCKS + STRAPPING R4C11 1 R4C9 2 5% 49.9 1% 402 CH 402 CH 33 CPU_CLK_DP 4 1 CPU_CLK_DN 4 1 R4B9 2 1 R4B8 2 1 R4B2 2 FTP FT4P4 1 R3B2 2 ANA_VRST_OK OUT 1% 75 1% 68.1 34 R4C12 1 R4C10 2 OUT 1M 5% CH 402 1 CH 402 CH ANA_V12P0_PWRGD 49 1% 1K C4B13 OUT 33 5% 1% 402 CH 1 SMC_RST_N 47 58 49.9 FT2P7 470PF 402 OUT CH CH FTP 5% 34 402 402 50V 1 2 OUT Y3B1 EMPTY 1 1 R4B1 2 27MHZ 402 HANA_V_12P0_DET U4C2 1OF4 IC R2P3 FT2N3 CH 1K FTP 1 2 1 1 R3C16 2 5% 10K HANA 5% FT3P4FTP R3C8 CH 402 HANA_POR_BYPASS V_12P0_DET SMC_RST_N_R SM V_RST_OK 33 5% 49.9 1% B6 CORE_RST_N* 402 402 CH 402 CH XTAL V_12P0_OK 2 34 ANA_RST_N M2 POR_BYPASS SMC_RST_N* D10 E11 2 2 IN 2 R2P1 1 13 C3B7 C3B6 1 E12 GPU_CLK_DP 22PF 22PF FT4P1 FTP 34 GPU_CLK_DN OUT 13 5% 5% 10K5% OUT 50V 50V 402CH R3C7 1 R3C15 2 1 NPO 1 NPO M3 402 402 33 5% 49.9 1% V_3P3STBY CPU_CLK_DP 402 CH 402 CH XTAL_IN CPU_CLK_DP_R HANA_XTAL_IN HANA_XTAL_OUTP2 CPU_CLK_DN R14 R2 XTAL_OUT P14 CPU_CLK_DN_R HANA_XTAL_VSS_CAPXTAL_VSS_CAP NB_CLK_DP GPU_CLK_DN_R R4C8 P3 R13 GPU_CLK_DP_R 1 R3C9 2 HANA_XTAL_BYPASS NB_CLK_DN P13 33 5% 49.9 1% 33 2 R4N5 1 M4 XTAL_BYPASS 402 CH 402 CH R10 PCIEX_CLK_DP PCIEX_CLK_DP_R 1K 5% P10 34 1 402 EMPTY PCIEX_CLK_DN PCIEX_CLK_DN_R OUT FT2P4 FTP PCIEX_CLK_DNPCIEX_CLK_DP OUT

2 1 SATA_CLK_DP SATA_CLK_DP_R 1 2 1 2 R4B17 R9 R4B27 R3B5 1 IN N3 FTP FT3P233 ANA_CLK_OE SATA_CLK_DN P9 1 ANA_CLK_OE 1K 5% ANA_CLK_OE_R SATA_CLK_DN_R 33 5% 49.9 1% FTP FT3P1 2 402 CH CH 402 CH R6 SATA_CLK_REF_R 402 2 R4P1 1 HANA_CLK_DRV_RSET2 K13 SATA_CLK_REF R3B1 CLK_DRV_RSET2 M15 10K 475 HANA_CLK_DRV_RSET1R11 CLK_DRV_RSET1 PIX_CLK_OUT_DP M14 ANA_PIX_CLK_2X_DP_R 5% 402 1% PIX_CLK_OUT_DN ANA_PIX_CLK_2X_DN_R 1 R4B26 2 1 R3B4 2 EMPTY CH 2 R4N6 1 402 ENET_CLK 33 49.9 1% 1 34 P6 475 1% ENET_CLK_R 402 CH5% 402 CH 402 CH STBY_CLK R8 SATA_CLK_DP 33 CH OUT STBY_CLK_R R4 SATA_CLK_DN 33 AUD_CLK OUT 1 R4B25 2 1 R3B6 2 58 N1 BI P1 AUD_CLK_R 1 58 34 SMB_CLK SMB_CLKSMB_DATA 33 5% 49.9 1% FTP FT1P2 IN SMB_DATA N2 1 402 402 CH FTP FT1P1 AV_CLK 1 FTP FT4N5 1 R4B6 2 SATA_CLK_REF HANA_AV_CLK 33 5% OUT HANA_TCLK G12 TCK CH 1 33 1 FTP FT2N4 HANA_TDO F11 TDO 1 402 C3B1 10PF HANA_TDI J12 TDI HANA_TMS R4N4 5% F12 TMS 10K 50V 1 2 1 2 2 HANA_TRST H12 5% R4C15 R4C13 EMPTY TRST 402 CH 33 5% 49.9 1% 402 402 CH 402 CH X802478-003 2 OUT 13 ANA_PIX_CLK_2X_DP OUT 13 ANA_PIX_CLK_2X_DN 1 R4C16 2 1 R4C14 2 1 FT4P2 5% 49.9 1% 1 39 402 CH 402 CH FTP FT4P3 J5C1 FTP 2X3HDR

1 2 33 1 R4B5 2 3 4 OUT 40 5 6 33 5% ENET_CLK 402 CH 1 C3B4 34 HDR 5%10PF 50V 2 EMPTY 402

1 R4B24 2 SMB_CLK STITCH STBY_CLK STITCH SATA_CLK STITCH OUT 33 5% ENET_CLK STITCH 402 CH STBY_CLK 1 1 V_3P3 SATA_CLK_REF STITCH C3B210PF FTP FT2R2 V_1P8STBY V_1P8STBY V_3P3 V_3P3 5%50V 36 2 EMPTY 1 402 FTP FT2P2 .1UF 1 R4B4 2 AUD_CLK 1 1 1 OUT C2P7 X5RC3N6 C1P9 402 1 1 33 5% .1UF .1UF C1B4 C2B14 1 402 CH 1 10% 10% 10% C2B17 C3B12 6.3V 6.3V 6.3V .1UF .1UF 2 V_3P3STBY 2 2 10% 10% .1UF 10PF X5R X5R 6.3V 6.3V 10% 5% 402 402 2 X5R 2 X5R 6.3V 50V 402 402 2 X5R 2 EMPTY 402 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=HANA, CLOCKS + STRAPING] Tue May 08 18:24:16 2007 FALCON_RETAIL 27/82 1.0 CONFIDENTIAL CR-28 : @FALCON_LIB.FALCON(SCH_1):PAGE28

HANA, VIDEO + FAN + JTAG ANA_VID_INT U4C2 2OF4 HANAIC GPU_PIX_CLK_1X G14 PIX_CLK_IN VID_INT L3 VID_DACD_DP 33 STBY_CLK STITCH PIX_DATA<14..0> 14 C14 PIX_DATA14 DAC_D_OUT_DP A7 1 R4B10 2 V_1P8STBY V_3P3STBY V_1P8STBY V_3P3STBY 13 C15 PIX_DATA13 DAC_D_OUT_DN B7 VID_DACD_DN 12 D14 PIX_DATA12 37.4 1% 11 D15 A8 VID_DACC_DP 402 CH PIX_DATA11 DAC_C_OUT_DP VID_DACC_DN B8 OUT 1 R4B11 2 10 E14 PIX_DATA10 DAC_C_OUT_DN 13 E15 1 PIX_DATA9 A9 OUT 37.4 1% C2R1 9 F14 VID_DACB_DP CH 1 1 1 1 13 PIX_DATA8 DAC_B_OUT_DP 402 .1UF IN B9 1 R4B13 2 C3P4 C2R2 C3N10 C2P50 7 F15 VID_DACB_DN 10% IN 8 PIX_DATA7 DAC_B_OUT_DN .1UF .1UF .1UF .1UF 6 G15 6.3V PIX_DATA6 OUT 37.4 1% 10% 10% 2 X5R 10% 10% H14 6.3V 6.3V 6.3V 6.3V 5 A10 VID_DACA_DP 44 402 CH 2 2 402 2 2 PIX_DATA5 DAC_A_OUT_DP 1 2 X5R X5R X5R X5R 4 H15 B10 VID_DACA_DN R4B14 402 402 402 402 J14 PIX_DATA4 DAC_A_OUT_DN 3 OUT 37.4 1% V_1P8STBY J15 PIX_DATA3 HDMI_EXT_SWING 44 2 B5 402 CH K14 PIX_DATA2 HSYNC_OUT VID_HSYNC_OUT_R OUT 1 A5 V_3P3STBY V_3P3STBY K15 PIX_DATA1 VSYNC_OUT VID_VSYNC_OUT_R OUTOUT 0 B1 44 PIX_DATA0 1 R4B23 2 GPU_HSYNC_OUT L14 13 IN HSYNC_IN TMDS_EXT_SWING 422 1% 13 IN GPU_VSYNC_OUT L15 402 44 CH HDMI_TXC_DP_R VSYNC_IN A2 2 R4B12 1 HANA_DAC_RSET TMDS_TXC_DP B2 HDMI_TXC_DP DAC_RSET TMDS_TXC_DN 44 C4B12 787 2 1 2 R4B22 1 C8 44 402 CH A4 H1 OUT 1 R4B18 2 I2S_SD3 HDMI_HPD TMDS_TX2_DP H2 10% 301 1% TMDS_TX2_DN 6.3V 603 CH 10K 5% F1 X5R 402 CH 402 .1UF 29 HDMI_HPD TMDS_TX1_DP F2 29 1% TMDS_TX1_DN I2S_SD2 HDMI_TXC_DN 1 R4N3 2 IN D1 TMDS_TX0_DP D2HANA_SPDIF_OUT HDMI_TX2_DP OUT 40210K CH5% TMDS_TX0_DN 29 36 SB_SPDIF_OUT M1 B4 C4B4 OUT 44 2 1 IN SPDIF_IN SPDIF_OUT HDMI_DDC_DATA 2 1 HDMI_TX2_DP_R R4B19 OUT 1 R4N2 2 B3 HDMI_DDC_CLK 44 29 29 I2S_SD1 36 I2S_BCLK K1 301 36 IN DDC_SCK A3 34 44 29 .1UF 10% 10K402 5% I2S_WS K2 I2S_SCK 6.3V 603 IN L2 DDC_SDA OUT CH I2S_WS X5R 1% K4 OUT 402 CH K3 I2S_SD3 L1 I2S_SD2 HDMI_TX2_DN 29 I2S_SD B11 36 IN I2S_SD1 HDMI_TX1_DP I2S_SD0 OUT 2 R4B15 1 HANA_OP2_DP C11 29 A11 10K 5% 28 HANA_OP2_DN FAN_OP2_DP FAN_OUT2 34 IN C4B10 OUT 402 CH 2 1 FAN1_FDBK FAN_OP2_DN 2 1 HDMI_TX1_DP_R R4B20 C12 A12 FAN1_OUT OUT 301 1% 43 B12 FAN_OP1_DP FAN_OUT1 .1UF 10% IN 6.3V 603 CH FAN_OP1_DN X5R A15 C13 402 SMC_PWM0 B15 TEMP_N TEMP3_P 43 BND_GAP_CAP A6 B13 HDMI_TX1_DN 2 R4C1 1 FAN_OP1_DP TEMP2_P IN A13 OUT 29 BND_GAP_CAP TEMP1_P 205K 1% TEMP_RSET A14 B14 HDMI_TX0_DP 402 CH 1 C4P2 TEMP0_P .22UF TEMP_RSET TEMPCAL_P OUT 29 10% C4B11 2 1 2 R4B21 1 6.3V 1 HDMI_TX0_DP_R 2 DB4P5 34 X5R X802478-003 402 301 1% SATA_CLK_REF STITCH .1UF 10% 603 CH 1 6.3V 29 X5R R4C2 402 ST4C1 11K V_3P3 HDMI_TX0_DN 1% OUT28 4 2 1 CPU_TEMP_N CH SHORT 402 2 1 R4B3HANA_OP2_DN2 IN HANA_OP2_OUT OUT ST4C2 1 C1P13 V_1P8 GPU_TEMP_N 2 1 0 5% X5R .1UF 402 CH 13 10% IN IN SHORT 6.3V 1 2 FT4N4 FTP ST4C5 402 13 EDRAM_TEMP_N 2 1 28 2 1 C4B3 DB4P1 SHORT 0.01UF 1 DB4P2 10% 16V 1 ST4C4 1 DB4P3 28 X7R Q1G3 1 BRD_TEMP_N 2 1 CUSTOMDB4P4 THERMAL IN IN 402 MMBT3906 1 2 XSTR CALIBRATION PADS FT4N1 FTP SHORT 1 LOCATION MUST REMAIN LOCKED ST4C3 CAL_TEMP_P CAL_TEMP_N 3 OUT 2 1 CPU_TEMP_P OUT 4 28 GPU_TEMP_P OUT 13 CAL_TEMP_N SHORT EDRAM_TEMP_P 13 BRD_TEMP_P OUT OUT 28 BRD_TEMP_P 28 IN

28 OUT BRD_TEMP_N DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:16 2007 FALCON_RETAIL 28/82 1.0 [PAGE_TITLE=HANA, VIDEO + FAN + JTAG] CONFIDENTIAL CR-29 : @FALCON_LIB.FALCON(SCH_1):PAGE29

R2A11

0 5% 603 CH V_AVIP NA IN SM 1 FT2M2 HDMI_TX2_DP 1 CM2A1CMCHOKEEMPTY 1 C2A9 FTP FT2M3 .1UF 1 FTP 44 10% 1 2 FT2M4 6.3V 2 1 X5R HDMI_TX2_DN FTP FT2M5 402 1 FTP FT3M1 28 4 3 ESDB-MLP7 ESDB-MLP7 1 FTP 1 1 FT3M2 402 402 1 FTP X801560-001 EG2A2 EG2A1 FT3M3 J2A1 HDR 28 1 FTP HDMI FT3M4 HDMI_TX2_DP_CM R2A12 1 TMDS_DATA2_DP DIO DIO FTP 0 5% 2 TMDS_DATA2_SHD 603 CH HDMI_TX2_DN_CM 3 TMDS_DATA2_DN 2 2 HDMI_TX1_DP_CM 4 TMDS_DATA1_DP 5 TMDS_DATA1_SHD 6 HDMI_TX1_DN_CM TMDS_DATA1_DN 87 TMDS_DATA0_DP R2A13 HDMI_TX0_DP_CM TMDS_DATA0_SHD HDMI_TX0_DN_CM 9 TMDS_DATA0_DN IN 0 5% HDMI_TXC_DP_CM 10 TMDS_CLK_DP 603 CH 11 TMDS_CLK_SHD V_5P0STBY 12 NA TMDS_CLK_DN IN SM 1 HDMI_CEC CEC DB3A1HDMI_TXC_DN_CM 14 CM2A2CMCHOKEEMPTY 1513 RESERVED HDMI_TX1_DP 16 SCL 1 2 SDA 28 17 DDC_CEC_GND HDMI_TX1_DN 18 5VCC 1 1 19 4 3 HOT_PLUG_DET ESDB-MLP7 ESDB-MLP7 28 1 1 R3M5 R3M6 23 ME4 X801560-001 402 2K 2K 22 ME3 402EG2A4 EG2A3 1% 1% 1 21 ME2 CH CH FTP FT4N2 R2A14 20 ME1 DIO DIO 402 402 2 2 0 5% X806395-002 603 CH

2 2 HDMI_DDC_CLK 34 28 IN 44 IN 28 IN HDMI_DDC_DATA 1 FTP FT2N6 HDMI_HPD_PIN 34 44 1 R3M7 2 HDMI_HPD 28 IN OUT R3A10 CR3M1 CR3M1 10K 5% 402 CH 0 5% 2 5 603 CH 6 NA 3 PGB0010603 1 1 SM 603 CM3A1 EMPTY 1 4 R3M1 EG3M1 ESDB-MLP7 28 CMCHOKE 1 ESDB-MLP7 47K 402 1 5% DIO HDMI_TX0_DP 1 2 BAV99 BAV99 402 DIO EG3M2 DIO CH EG3M3 402 28 2 EMPTY 2 HDMI_TX0_DN 4 3 EMPTY ESDB-MLP7 ESDB-MLP7 1 1

402 2 X801560-001 2 IN 402EG3A2 EG3A1 R3A11 DIO DIO IN 0 5% 603 CH 2 2

R3A12

0 5% 603 CH NA 28 SM CM3A2 EMPTY 28 CMCHOKE 1 2 IN HDMI_TXC_DP

HDMI_TXC_DN 4 3 IN 402 ESDB-MLP7 ESDB-MLP7 1 1 402 X801560-001 EG3A4 EG3A3 R3A13 DIO DIO 0 5% 603 CH 2 2

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=CONN, HDMI] Tue May 08 18:24:16 2007 FALCON_RETAIL 29/82 1.0 CONFIDENTIAL CR-30 : @FALCON_LIB.FALCON(SCH_1):PAGE30

HANA, POWER + DECOUPLING

V_3P3STBY FB4N5

1 2 V_HANA_VAA_RTS33S 120 FB 0.2A 603 1 C4N36 0.5 DCR C4N37 C4N35 4.7UF 4.7UF .1UF 10% 10% 10% 6.3V 6.3V 6.3V X5R 2 X5R X5R 805 805 402 3OF4 V_1P8STBY U4C2 IC HANA V_3P3 D12 VAA_RTS33S VAA_VID_PLL M12 D11 AVSS_RTS33S AVSS_VID_PLL FB4N8 M13 1 2 E9 VAA_DAC33M3 VAA_GP_PLL R7 V_HANA_VAA_DAC33M 60 FB D9 VAA_DAC33M2 AVSS_GP_PLL P7 0.5A 603 C9 0.1DCR 1 1 VAA_DAC33M1 C4N15 C4N24 C4N23 C4N29 D8 AVSS_DAC33M1 VAA_100M_PLL_A N15 4.7UF 4.7UF .1UF 10% 10% 10% 10% AVSS_100M_PLL_A1 P15 6.3V 6.3V 6.3V 6.3V V_3P3STBY C7 VAA_DAC33M0 AVSS_100M_PLL_A0 R15 X5R 2 X5R X5R .1UF2 X5R D7 805 805 402 402 AVSS_DAC33M0 R12 VAA_100M_PLL_D C6 P12 VAA_POR33S AVSS_100M_PLL_D C10 N7 VAA_FAN33S VDDC_STBY_PLL M7 VSSC_STBY_PLL V_3P3STBY R3 VAA_XTAL33S V_1P8STBY VDDC_25M_PLL N5 1 R4N1 2 N8 M5 P8 VDDIO33S_STBY_PLL VSSC_25M_PLL 402 100 5% V_HANA_VAA_XTAL_33S VSSIO33S_STBY_PLL N4 CH M6 VDDC_AUD_PLL P4 1 C4N16 N6 VDDIO33S_25M_PLL VSSC_AUD_PLL .1UF VSSIO33S_25M_PLL E7 D6 10% P5 VDD_DAC18S 1 1 1 6.3V R5 C3C6 C4P13 C3N3 2 X5R VDDIO33S_AUD_PLL VAA_POR18S 4.7UF 4.7UF 4.7UF 402 10% 10% 10% VSSIO33S_AUD_PLL 6.3V 6.3V 6.3V VDDIO18S_100M_PLL5 N14 2 X5R 2 X5R 2 X5R N13 805 805 805 VDDIO18S_100M_PLL4 P11 VDDIO18S_100M_PLL3 M10 VDDIO18S_100M_PLL2 N12 VSSIO18S_100M_PLL2 N9 V_3P3STBY VDDIO18S_100M_PLL1 N11 VSSIO18S_100M_PLL1 M9 VDDIO18S_100M_PLL0 N10 VSSIO18S_100M_PLL0 L13 L12 1 1 VDDIO18S_PIX_PLL C4N25 C4N8 VSSIO18S_PIX_PLL 4.7UF 4.7UF 10% 10% 6.3V 6.3V X802478-003 2 X5R 2 X5R 805 805

V_1P8STBY V_3P3STBY

.1UF 1 C4N31 1 C4N17 1 C4P5 1 C4N34 1 C4P6 1 C4N27 1 C4P11 1 C4P1 1 C4P9 1 C4N26 1 1 1 1 1 1 .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF C4N18 C4N19 C4N20 C4N28 C4P8 C4N42 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% .1UF .1UF .1UF .1UF .1UF .1UF 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R 10% 10% 10% 10% 10% 10% 2 X5R 2 X5R 2 X5R 2 X5R2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 402 402 402 402 402 402 402 402 402 402 2 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 402 402 402 402 402 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=HANA, POWER + DECOUPLING] Tue May 08 18:24:16 2007 FALCON_RETAIL 30/82 1.0 CONFIDENTIAL CR-31 : @FALCON_LIB.FALCON(SCH_1):PAGE31

HANA, POWER + DECOUPLING V_3P3STBY V_1P8STBY

U4C2 4of4 IC HANA FB4P1 V_HANA_VDD18S E13 VDD33S3 VDD18S21 1 2 J4 V_3P3STBY VDD33S2 VDD18S20 L11 120 FB J3 VDD33S1 VDD18S19 0.5A 603 C3 K11 1 1 0.2DCR 1 VDD33S0 VDD18S18 G11J10 C4P4 C4P3 C3P1 H10 4.7UF 4.7UF VDD18S17 10%.1UF 10% 10% VSSIO_33S_AVSS8 VDD18S16 J9 6.3V 6.3V 6.3V H9 2 X5R 2 X5R 2 X5R VSSIO_33S_AVSS7 VDD18S15 FB4N6 M8 805 805 V_HANA_VDDIO_33S_AVCC F4 VSSIO_33S_AVSS6 VDD18S14 402 1 2 L8 E4 VDDIO_33S_AVCC5 VDD18S13 K8 120 FB G4F3 VDDIO_33S_AVCC4 VDD18S12 G8 0.5A 603 1 1 1 1 G3 VDDIO_33S_AVCC3 VDD18S11 F8 0.2DCR G1 C4N3 C4N6 C4N9 C4N10 C4N14 C4N13 C2 VDDIO_33S_AVCC2 VDD18S10 4.7UF 4.7UF .1UF .1UF .1UF .1UF C1 L7 10% 10% 10% 10% 10% 10% VDDIO_33S_AVCC1 VDD18S9 G2 K7 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VDDIO_33S_AVCC0 VDD18S8 X5R 2 X5R X5R 2 X5R 2 X5R 2 X5R G7 805 402 402 402 402 VDD18S7 A1 F7 805 V_3P3STBY E1 VSSIO_33S_AVSS5 VDD18S6 J6 J1 VSSIO_33S_AVSS4 VDD18S5 H6 VSSIO_33S_AVSS3 VDD18S4 J5 1 1 1 1 1 1 1 E2 E5 C4N32 C4N30 C4N41 C4N33 C4N22 C4P7 C4N21 VSSIO_33S_AVSS2 VDD18S3 H5 .1UF .1UF .1UF .1UF .1UF .1UF E3 D5 .1UF VSSIO_33S_AVSS1 VDD18S2 10% 10% 10% 10% 10% 10% 10% J2 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VSSIO_33S_AVSS0 VDD18S1 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R402 402 402 402 402 H3 VDD18S0 402 402 VDDIO_33S_PVDD1 J13 D3 VSS35 H13 1 C4N5 C4N12 VDDIO_33S_PVCC0 VSS34 G13 .1UF .1UF VSS33 F13 10% 10% 6.3V 6.3V H4 VSS32 D13 2 X5R D4 VSSIO_33S_PVSS1 VSS31 K12 X5R 402 402 VSSIO_33S_PVSS0 VSS30 VSS29 V_3P3STBY VSS28 VSS27 M11L10 VSS26 J11K10 VSS25 G10H11 VSS24 F10 FB4N7 VSS22 E10 1 2 VSS23 VSS21 L9 120 FB V_HANA_VDDIO_33S_PVCC0 VSS20 K9 0.2A 603 VSS19 G9 0.5 DCR 1 C4N4 C4N7 C4N11 VSS18 F9 4.7UF 4.7UF .1UF J8 10% 10% 10% VSS17 6.3V 6.3V 6.3V VSS16 H8 2 E8 X5R X5R X5R VSS15 805 805 402 J7 VSS14 VSS13 H7 F6 VSS12 L6 E6 K6 L5 VSS10 G6 VSS11 K5 VSS9 G5 VSS8 F5 VSS7 VSS6 VSS5 VSS4 L4 VSS3 C5 VSS2 C4 VSS1 VSS0 R1

X802478-003

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=HANA, POWER + DECOUPLING] Tue May 08 18:24:16 2007 FALCON_RETAIL 31/82 1.0 CONFIDENTIAL CR-32 : @FALCON_LIB.FALCON(SCH_1):PAGE32

POWER TRACE DECOUPLING

V_12P0 V_12P0 V_5P0STBY V_3P3STBY V_5P0DUAL V_VREG_V1P8V5P0 55 IN

C7G2 C3N2 C7B1 C2F2 C1C8 C4F13 1 2 1 2 1 2 1 2 1 2 1 2

0.01UF 10% 0.01UF 10% .1UF 10% .1UF 10% 10% 0.01UF 10% 16V 16V 6.3V 6.3V 6.3V 16V X7R X5R .1UF 402 402X7R 402 X5R 402 X7R 402 X5R 402 C4N40 C1N12 C6B1 C2G1 C5G1 1 2 1 2 1 2 1 2 C8G2 1 2 1 2 10% 0.01UF 10% 0.01UF .1UF 10% .1UF 10% 0.01UF 10% 16V 16V 6.3V 6.3V .1UF 10% 16V X7R X7R X5R X5R 6.3V X7R 402 402 402 402 X5R 402 402

C9F2 C1C7 C4A1 C3G3 1 2 1 2 1 2 1 2 C1F1 1 2 0.01UF 10% 0.01UF 10% .1UF .1UF 10% 16V 16V 6.3V 6.3V .1UF10% X7R X7R X5R X5R 6.3V 402 402 402 402 X5R 402 V_5P0 10% C9E2 C1D8 C5G3 1 2 1 2 1 2 C5G5 1 2 0.01UF 10% .1UF 10% .1UF 10% .1UF 16V 6.3V 6.3V 10% X7R X5R 6.3V 402 402 X5R X5R C5V1 402 402 1 2 V_1P8 C9C7 .1UF 10% C1B2 C1C12 1 2 6.3V 1 2 1 2 X5R 402 0.01UF 10% .1UF 10% 10% 16V 6.3V 6.3V.1UF X7R X5R X5R 402 402 C3U3 402 C9N1 1 2 1 2

C1C15 .1UF 10% C1C1 C1N13 .1UF 10% 1 2 6.3V 1 2 1 2 6.3V X5R 402 X5R 0.01UF 10% 10% .1UF 10% 402 16V .1UF6.3V 6.3V 402X7R X5R X5R C2T4 402 402 1 2 C5N2 1 2 C7N1 .1UF 10% C1D10 C1G1 1 2 6.3V 1 2 1 2 .1UF 10% X5R 6.3V 402 X5R 0.01UF 10% .1UF 10% .1UF 10% 402 16V 6.3V 6.3V X7R X5R X5R 402 402 402 C3N1 1 2 C6N1 C1B3 C1F2 1 2 1 2 .1UF 1 2 .1UF 10% 6.3V X5R 0.01UF 10% .1UF402 10% 10% 16V 6.3V 6.3V 402 X7R X5R X5R 402 402 C7N2 1 2

C5N1 .1UF 10% 1 2 6.3V X5R 402 0.01UF 10% 16V 402X7R

C4N1 1 2

0.01UF 10% 16V X7R 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=POWER TRACE EMI CAPS] Tue May 08 18:24:16 2007 FALCON_RETAIL 32/82 1.0 CONFIDENTIAL CR-33 : @FALCON_LIB.FALCON(SCH_1):PAGE33

ADB:ADD CONFIG TABLE SB, PCIEX + SMM GPIO + JTAG]

U2C1 1of6 IC PEX_SB_GPU_L1_DP SATA_CLK_DPSATA_CLK_DN SATA_CLK_DP SB VERSION 106 C2C2 SATA_CLK_DN 1 2 2 R2P9 1 K1 58 J1 1K 5% IN SATA_CLK_REF .1UF 10% OUT CH 27 IN SATA_CLK_REF 6.3V V_3P3 SATA_CLK_SEL X5R 402 IN H3 402 13 27 SATA_CLK_SEL 27 H4 ECB_CLK_BYP C2C1PEX_SB_GPU_L1_DN DB1N5 ECB_CLK_BYP 1 2 ECB_CLK_SEL 58 1 ECB_CLK_SEL A6 2 R2P5 1 V_1P8 B6 .1UF 10% OUT HBEDB_CLK_SEL HBEDB_CLK_BYP 6.3V 1K 5% DB2P15 HBEDB_CLK_BYP HBEDB_CLK_SEL X5R 13 402 EMPTY 1 U20 402 2 R2P16 1 XUSB_CLK_BYP V20 TP XUSB_CLK_SEL XUSB_CLK_BYP 1K 5% DB2N8 EMPTY 1 B15 XUSB_CLK_SEL C2C4 402 1 PEX_SB_GPU_L0_DP2 2 R2P2 1 C15 13 58 TP OUT 5% PEX_CLK_DP .1UF 10% 402 27EMPTY PCIEX_CLK_DN 6.3V 27 L22 PEX_CLK_DN X5R TP IN PCIEX_CLK_DP L21 402 1K IN PEX_RX1_DP PEX_TX1_DP PEX_SB_GPU_L1_DP_C PEX_GPU_SB_L1_DP P22 PEX_RX1_DN PEX_TX1_DN N20 C2C3 13 1 PEX_SB_GPU_L0_DN2 IN PEX_GPU_SB_L1_DN N22 M20 PEX_SB_GPU_L1_DN_C OUT 13 58 13 IN .1UF PEX_RX0_DP PEX_TX0_DP 10% PEX_GPU_SB_L0_DP T21 PEX_RX0_DN PEX_TX0_DN R19 PEX_SB_GPU_L0_DP_C 6.3V 13 IN X5R 13 IN PEX_GPU_SB_L0_DN R21 P19 PEX_SB_GPU_L0_DN_C 402 PEX_RBIAS1 PEX_RBIAS1 K20 PEX_RBIAS0 K19 2 R2N8 1 PEX_RBIAS0 KER_DBG_TXD OUT 58 58 1 UART0_RXD UART0_TXD 47 5% KER_DBG_RXD D15 D14 KER_DBG_TXD_R 402 CH 1 1 IN C2P25 R2P11 .1UF 124 1 C2P18 R2P8 GPIO31 10% D10 SB_GPIO_RESERVED31 1 6.3V 10% 1% .1UF 499 GPIO30 DB2P1 2 402 CH 1% D11 SB_GPIO_RESERVED30 1 X5R 6.3V GPIO29 DB2P2 402 2 CH D12 SB_GPIO_RESERVED29 1 2 X5R GPIO28 DB2P3 402 402 D13 SB_GPIO_RESERVED28 1 2 GPIO27 DB2P4 C8 1 GPIO26 SB_GPIO_RESERVED27 DB2P5 V_3P3 D9 1 GPIO25 SB_GPIO_RESERVED26 DB2P6 C9 1 GPIO24 SB_GPIO_RESERVED25 DB2P7 B9 1 GPIO23 SB_GPIO_RESERVED24 DB2N6 A9 1 GPIO22 SB_GPIO_RESERVED23 DB2N5 C10 1 GPIO21 SB_GPIO_RESERVED22 DB2N4 B10 1 1 1 1 1 1 1 1 1 GPIO20 SB_GPIO_RESERVED21 DB2N3 A10 1 GPIO19 SB_GPIO_RESERVED20 DB2N11 R1P6 R1P2 R1P3 R1P5 R1P1 R2N6 R2N4 R2N5 1 GPIO18 SB_GPIO_RESERVED19 DB2N12 10K 10K 10K 10K 10K 10K 10K 10K C11 44 1 5% 5% 5% 5% 5% 5% 5% 5% SB_GPIO_RESERVED18 DB2N10 GPIO17 B11 1 EMPTY EMPTY CH CH EMPTY EMPTY EMPTY EMPTY GPIO16 SB_GPIO_RESERVED17 DB2N9 C12A11 1 SB_GPIO<0..15> 402 402 402 402 402 402 402 402 GPIO15 SB_GPIO_RESERVED1628 DB2N7 33 2 2 2 2 2 2 2 2 B12 15 BI GPIO14 A12 14 GPIO13 0 1 2 3 5 11 14 1533 SB_GPIO<0..15> C13 OUT BI GPIO12 B13 SCART_RGB 41 GPIO11 OUT44 A13 AUD_RST_N 44 11 1 1 1 1 1 1 1 1 GPIO10 C14 GPIO9 WSS_CNTL0ANA_VID_INT IN R1C7 R1C4 R1C5 R1C6 R1C2 R2B10 R2B8 R2B9 B14 OUT DB1P1 1K 1K 1K 1K 1K 1K 1K 1K GPIO8 A14 WSS_CNTL1 5% 5% 5% 5% 5% 5% 5% 5% OUT TP DB1P2 GPIO7 E3 1 TP CH CH EMPTY EMPTY CH CH CH CH GPIO6 F1 1 402 402 402 402 402 402 402 402 SB_GPIO_RESERVED6PCIEX_INT 2 2 2 2 2 2 2 2 GPIO5 F2 5 F3 GPIO4 OUT 39 40 GPIO3 G1 ENET_RST_N 3 GPIO2 G2 2 0 GPIO1 G3 1 GPIO0 G4

W20 1 TCK FTP FT1N1 SB_TDO V22 TDO SB_TCLKSB_TDI V21 TDI W22 TMS V_3P3 GPIO<1> = 0 ENABLE DEBUG OUTPUT W21 TRST 1 DISABLE DEBUG OUTPUT SB_TMS SATA_CLK V_3P3 STITCH J2D1 SB_TRST GPIO<0,2,3> = 111 XENON 2X3HDR 110 ZEPHYR A 1 2 2 2 101 ZEPHYR B X02047-012 C1C2 C2B16 3 100 ZEPHYR C 4 .1UF .1UF 5 6 10% 10% 011 FALCON 6.3V 6.3V 1 X5R 1 X5R 010 JASPER HDR 402 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=SB, PCIEX + SMM GPIO + JTAG] Tue May 08 18:24:16 2007 FALCON_RETAIL 33/82 1.0 CONFIDENTIAL CR-34 : @FALCON_LIB.FALCON(SCH_1):PAGE34

SB, SMC V_3P3STBY STBY_CLK V_12P0 SMC_RST_N 2

IN 27 R8N17 4.7K 27 C2P51 IN 1UF 5% 2 R2N15 1 10% CH OUT TRAY_OPEN 16V 5% 402 33 X7R 1VREG_GPU_PWRGD 402 CH 603 48 IN 2 R2N21 1 IN EXT_PWR_ON_N U2C1 2of6 IC 1.82K 1 R8N18 2 10K 402 CH SB VERSION 106 SMC_DBG_TXD OUT 1% 58 44 402 CH HDMI_DDC_DATA 53 BI 5% Y12 STBY_CLK

1 29 44FT2N528 FTP 1 C17 FT2P10 FTP SMC_RST_N* 58 SMC_CPU_CHKSTOP_DETECT SB_RST_N BI V_3P3STBY N: TIED TO V_MEMPORT IN G20 SB_RST_N* FOR BETTER ROUTING V_5P0 58 34 IN G19 MAIN_PWR_OK SB_MAIN_PWRGD 1 R7V4 2 D16 B16 1 R2N9 2 SMC_UART1_RXD SMC_UART1_TXD SMC_DBG_TXD_R 10K 5% 402 CH 34 47 5% VREG_CPU_PWRGD 58 IN C16 SMC_DBG 402 CH 1 1 SMC_DBG_EN IN 51 R2P6 R2P4 2.2K 2.2K TRAY_OPEN_R A18 PWRSW_N 49 5% 5% SMC_P4_GPIO7 SMC_P2_GPIO7 E22 OUT 48 TRAY_STATUS B18 E21 VREG_3P3_EN CH CH IN SMC_P4_GPIO6 SMC_P2_GPIO6 OUT C18 E20 ANA_V12P0_PWRGD 56 27 1 402 402 EXT_PWR_ON_R SMC_P4_GPIO5 SMC_P2_GPIO5 IN FT2P24 FTP 2 2 41 AUD_CLAMP D18 E19 1 OUT A19 SMC_P4_GPIO4 SMC_P2_GPIO4 FT2P15 FTP F22 ANA_RST_NVREG_GPU_EN_N OUT 2 R3P7 1 SMC_P4_GPIO3 SMC_P2_GPIO3 27 GPU_RST_DONE B19 F21 OUT 53 IN SMB_DATA C19 SMC_P4_GPIO2 SMC_P2_GPIO2 F20 PSU_V12P0_EN 1K 5% 58 27 BI SMC_P4_GPIO1 SMC_P2_GPIO1 OUT 402 CH 2 27 58 SMB_CLK A20 F19 ANA_CLK_OE 2749 BI SMC_P4_GPIO0 SMC_P2_GPIO0 OUT R3P6 13 AV_MODE2_R B20 10K Y21 VREG_CPU_EN 51OUT 44 SMC_P3_GPIO7 SMC_P1_GPIO7 5% 2 R2M3 1 AV_MODE1_R B21 Y22 AV_MODE2 AV_MODE0_R C20 SMC_P3_GPIO6 SMC_P1_GPIO6 AA20 55 CH 10K 5% VREG_V5P0_EN OUT 402 C22 SMC_P3_GPIO5 SMC_P1_GPIO5 AA21 47 1 IN 402 CH SMC_P3_GPIO4 SMC_P1_GPIO4 VREG_V5P0_SEL OUT 55 C21 AB20 OUT IN D22 SMC_P3_GPIO3 SMC_P1_GPIO3 Y20 VREG_V1P8_EN 44 BINDSW_N 43 IN AV_MODE1 2 R2M5 1 D21 SMC_P3_GPIO2 SMC_P1_GPIO2 AA19 D20 SMC_P3_GPIO1 SMC_P1_GPIO1 AB19 TILTSW_N IN 10K 5% EJECTSW_N IN 43 402 CH SMC_P3_GPIO0 SMC_P1_GPIO0 FTP 44 J20 1 FT2P5 2 1 AV_MODE0 R2A2 H21 34 IN SMC_P0_GPIO7 4 CPU_RST_N OUT 2 R2P15 1 10K 5% SMC_P0_GPIO6 H19 OUT 34 H20 SB_MAIN_PWRGD_R SB_MAIN_PWRGD 402 CH SMC_P0_GPIO5 1K 5% SMC_P0_GPIO4 J19 SB_RST_NGPU_RST_DONE_R OUT 402 CH SMC_P0_GPIO3 J22 2 J21 A17 GPU_RST_N SMC_P0_GPIO2 OUT 13 R2P10 5% HDMI_DDC_CLK 43 H22 B17 29 44 28 OUT SMC_P0_GPIO1 OUT 4 60 10K SMC_P0_GPIO0 CPU_PWRGD IR_DATA A16 SMC_PWM11 IN DB2B1 CH SMC_IR_IN SMC_PWM1 28 402 OUT 1 SMC_PWM0 SMC_PWM0 TP DB2P8 EN_TEST1_N1 G22 13 GPU_TCLK_R TP 1 G21 BI DB2P9 ENTEST1_N* 27 ANA_VRST_OK EN_TEST0_N ENTEST0_N* 55 VREG_V5P0_VMEM_PWRGD V_1P8STBY X02047-012 BI BI 1 FT3P3 FTP

1 34 FT2P25 FTP 1 FT1U2 FTP 1 1

1 R2P12 R2P13 DB1F1 2K 10K 10K 5% 34 BI 5% 49 V_5P0DUAL CH CH 49 V_5P0DUAL U1U1 IC 402 402 2 2 DBG_LED0 1 2 SN74LVC1G14 R2B16 R2B19 5 VCC D1F1 2K 4 1 R1U3 2 DBG_LED0 2 IN OUT DBG_LED0_LED_R DBG_LED0_LED 2 1 BI 1% 1% IN 3 1 BI GND N/C 249 1% YELLOW CH EMPTY CH ARGON_DATA V_3P3STBY 402 402 402 LED SM ARGON_CLK 2 1 X801189-001

N: DBG_LED0 PULLDOWN = SMC PRODUCTION MODE DBG_LED0 PULLUP = SMC DEVELOPMENT MODE DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=SB, SMC] Tue May 08 18:24:17 2007 FALCON_RETAIL 34/82 1.0 CONFIDENTIAL CR-35 : @FALCON_LIB.FALCON(SCH_1):PAGE35

SB, FLASH + USB + SPI

U2C1 3of6 IC SPI_SS_N SB VERSION 106 2 R1R1 1 SPI_CLK U3 SPI_CLK SPI_MISO AB5 SPI_MISO_R SPI_MISO SPI_MOSI Y5 IN SPI_MOSI 33 5% OUT IN AA5 SPI_SS_N* 402 CH 58 IN 58 58 58 FLSH_DATA<7..0> Y2 BI 7 FLSH_DATA7 FLSH_CLE W1 FLSH_CLE V_3P3STBY AA2 FLSH_DATA6 OUT 42 FLSH_WP_N 6 Y3 V3 OUT 5 FLSH_DATA5 FLSH_CE_N* FLSH_CE_N 42 4 AA3 V2 OUT FLSH_DATA4 42 3 AB3 42 FLSH_DATA3 FLSH_RE_N* FLSH_RE_NW3 2 Y4 OUT FLSH_DATA2 42 1 AA4 2 R1P7 1 FLSH_DATA1 FLSH_WE_N* FLSH_WE_N OUT 0 AB4Y1 W2 FLSH_DATA0 42 V1 2.2K 5% FLSH_ALE FLSH_ALE OUT 402 CH FLSH_WP_N* 42 IN FLSH_READY 42 FLSH_READY USBPORTA3_DP USBPORTA3_DN

1 W18 Y10 FT2P22 FTP USBPORTA2_DP MEMPORT1_DP 49 1 Y18 USBA_D3_DP USBB_D4_DP W10ARGONPORT_DP FT2P23 FTP USBPORTA2_DN USBA_D3_DN USBB_D4_DN MEMPORT1_DN 49 ARGONPORT_DN BI 1 AA17 Y8 FT2P20 FTP GAMEPORT2_DP BI 46 1 AB17 USBA_D2_DP USBB_D3_DP W8 BI 46 FT2P21 FTP GAMEPORT2_DN USBA_D2_DN USBB_D3_DN 46 W16 AB7 45 BI 46 GAMEPORT1_DP Y16 USBA_D1_DP USBB_D2_DP AA7 45 BI EXPPORT_DP BI BI GAMEPORT1_DN USBA_D1_DN USBB_D2_DN EXPPORT_DN 46 AA15 AB9 46 46 46 BI USBA_D0_DP USBB_D1_DP AA9 BI BI AB15 MEMPORT2_DP BI USBA_D0_DN USBB_D1_DN MEMPORT2_DN 60 AB11 60 W12 AA11 BI USBB_D0_DP MEMPORT3_DP BI USB_RBIAS USBB_D0_DN MEMPORT3_DN X02047-012 SB_USB_RBIAS

1 1 C2P40 R2P14 .1UF 113 10% 1% 6.3V 2 EMPTY CH 402 402 2

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:17 2007 FALCON_RETAIL 35/82 1.0 CONFIDENTIAL

[PAGE_TITLE=SB, FLASH + USB + SPI] CR-36 : @FALCON_LIB.FALCON(SCH_1):PAGE36

SB, ETHERNET + AUDIO + SATA

MII_TX_CLK MII_TX_CLK_R 40 39 IN R1B9 5% 40233 CH MII_MDC_CLK_OUT_R R1C3 MII_MDC_CLK_OUT 39 40 U2C1 4of6 IC 33 OUT 5% 40 39 MII_RX_CLK R1B10 MII_RX_CLK_R SB VERSION 106 402 CH 33 5% B3 MII_TX_CLK MII_MDC_CLK_OUT IN 402 CH C3 MII_RX_CLK E2 MII_TXD3 MII_TXD3 39 40 40 39 MII_RXD3 D1 MII_RXD3 C5 OUT MII_TXD2 MII_TXD2 39 40 40 39 IN MII_RXD2 D2 MII_RXD2 A4 OUT MII_TXD1 MII_TXD1 39 40 40 39 IN MII_RXD1 D3 MII_RXD1 B4 OUT IN C1 MII_TXD0 C4 MII_TXD0 OUT 39 40 40 39 IN MII_RXD0 MII_RXD0 C2 MII_TXEN A3 MII_TXEN OUT 39 40 40 39 MII_RXDV B2 MII_RXDV 40 39 IN MII_RXER MII_RXER IN 40 39 MII_COL B5 MII_COL IN A5 R2B11 I2S_MCLK 40 39 IN MII_CRS MII_CRS E1 OUT 40 39 BI MII_MDIO MII_MDIO 5% 41 27 R2B14 47402 CH I2S_BCLK OUT 28 41 47 5% A8 I2S_MCLK_R 402 CH R2B13 IN AUD_CLK AUD_CLK I2S_MCLK_OUT C7 I2S_SD OUT 4128 B8 I2S_BCLK_R 28 I2S_BCLK_OUT 47 A7 I2S_SD_R 5% I2S_SD R2B12 402 CH B7 I2S_WS_R I2S_WS OUT 41 I2S_WS C6 SPDIF_R SPDIF 47 5% 48 402 CH 1 R2B15 2 SB_SPDIF_OUT 28 48 48 47 5% OUT 48 402 CH 48 N4 R2 HDD_TX_DP 48 P4 SATA1_RX_DP SATA1_TX_DP P2 HDD_TX_DN OUT 48 IN HDD_RX_DP 48 IN HDD_RX_DN SATA1_RX_DN SATA1_TX_DN OUT 1 R2N12 2 L3 N1 OUT 10K 5% IN M3 SATA0_RX_DP SATA0_TX_DP M1 IN ODD_RX_DP ODD_TX_DP OUT 402 CH ODD_RX_DN SATA0_RX_DN SATA0_TX_DN ODD_TX_DN SATA_RBIAS U2 1 R2N11 2 SATA_RBIAS 10K 5% 402

1 1 R2N10CH2 1 10K C1C9 R1C8 X02047-012 10K 5% .1UF 374 402 CH 10% 1% 6.3V 2 X5R CH 1 R1B3 2 402 402 2 5% 402 CH

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=SB, ETHERNET + AUDIO + SATA] Tue May 08 18:24:17 2007 FALCON_RETAIL 36/82 1.0 CONFIDENTIAL CR-37 : @FALCON_LIB.FALCON(SCH_1):PAGE37

SB, STANDBY POWER + DECOUPLING V_1P8STBY

U2C1 SB VERSION5of6 106 IC VDD18_AUX<9> VDD18_AUX<8> V_1P8STBY J18 VDD18_AUX<7> H18 VDD18_AUX<6> G18 VDD18_AUX<5> J15 VDD18_AUX<4> H15 VDD18_AUX<3> R14 VDD18_AUX<2> H14 SB BALLS V18 AND V19 ARE IN THE VDD18_AUX<1> R12 VDD18_AUX<0> LOWER RIGHT HAND OF THE CHIP P12 THEY HAVE BEEN ISOLATED R9 VDD33_AUX<14> FOR BETTER POWER ROUTING VDD33_AUX<13> V_3P3STBY V_CMPAVDD33_USB 37 AVDD_USB VDD33_AUX<12> V19 IN FB2P4 D19 1 AVSS_USB VDD33_AUX<11> 2 V_AVDD_USB AB13 V18 VDD33_AUX<10> 120 FB V_AVSS_USB AA13 F18 0.2A 603 CMPAVDD18_USB VDD33_AUX<9> 1 1 E18 C2R5 0.5 DCR C2P47 C2P43 V_CMPAVDD18_USB Y13 CMPAVSS18_USB VDD33_AUX<8> E17 4.7UF 2.2UF .1UF VDD33_AUX<7> D17 10% 10% 10% W13 6.3V 6.3V 6.3V V_CMPAVSS18_USB VDD18_USB<9> VDD33_AUX<6> E16 X5R 2 X5R 2 X5R V13 VDD18_USB<8> VDD33_AUX<5> E15 805 603 402 ST2P3 V_VDD18_USB V12 VDD18_USB<7> VDD33_AUX<4> W5 1 2 SHORT V11 VDD18_USB<6> VDD33_AUX<3> V5 V10 VDD18_USB<5> VDD33_AUX<2> U5 W4 V9 VDD18_USB<4> VDD33_AUX<1> V4 V8 VDD18_USB<3> VDD33_AUX<0> U4 FB2P3 V7 VDD18_USB<2> Y6 1 2 VDD18_USB<1> VSS_USB<25> W6 VDD18_USB<0> VSS_USB<24> Y19 FB V6 W19 0.2A 603 VSS_USB<23> 1 1 AB18 0.5120 DCR C2P46 C2P42 CMPAVDD33_USB VSS_USB<22> 2.2UF .1UF Y14 CMPAVSS33_USB VSS_USB<21> AA18 10% 10% W14 VSS_USB<20> Y17 6.3V 6.3V W17 2 X5R 2 X5R VDD33_USB<3> VSS_USB<19> ST2P2 603 402 V17 VDD33_USB<2> VSS_USB<18> AB16 1 2 V_CMPAVSS33_USB V16 VDD33_USB<1> VSS_USB<17> AA16 SHORT V15 VDD33_USB<0> VSS_USB<16> Y15 V_1P8STBY W15 V14 VSS_USB<15> V_VDD33_USB AB14 VSS_USB<14> FB2R1 AA14 VSS_USB<13> 1 2 AB12 VSS_USB<12> AA12 120 FB VSS_USB<11> 0.5A 603 Y11 1 1 1 1 1 VSS_USB<10> C2R3 0.2DCR C2P45 C2P41 C2P2 C2P3 W11 VSS_USB<9> 1 4.7UF 10UF .1UF .1UF .1UF AB10 C2P38 C2P37 C2P23 C2P24 10% 20% 10% 10% 10% VSS_USB<8> 6.3V 6.3V 6.3V 6.3V 6.3V AA10 .1UF .1UF .1UF .1UF 37 2 2 2 2 2 VSS_USB<7> 10% 10% 10% 10% X5R X5R X5R X5R X5R Y9 6.3V 6.3V 6.3V 6.3V 805 805 402 402 402 VSS_USB<6> W9 2 X5R X5R X5R X5R 402 402 402 402 VSS_USB<5> AB8 VSS_USB<4> AA8 VSS_USB<3> Y7 VSS_USB<2> W7 VSS_USB<1> AB6 VSS_USB<0> AA6 V_3P3STBY V_3P3STBY V_CMPAVDD33_USB FB2P5 OUT X02047-012

1 2 120 FB 0.2A 603 C2R6 0.5 DCR 1 C2P48 1 C2P44 1 C2P6 C2N1 C2P5 4.7UF 2.2UF .1UF .1UF .1UF .1UF 10% 10% 10% 10% 10% 10% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V X5R 2 X5R 2 X5R 2 X5R X5R X5R 805 ST2P4 603 402 402 402 402 1 2

SHORT FB2P1

1 2 120 FB 0.2A 603 C2P8 0.5 DCR 1 C2P34 1 C2P35 4.7UF 2.2UF .1UF 10% 10% 10% 6.3V 6.3V 6.3V X5R 2 X5R 2 X5R 805 603 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=SB, STANDBY POWER + DECOUPLING] Tue May 08 18:24:17 2007 FALCON_RETAIL 37/82 1.0 CONFIDENTIAL CR-38 : @FALCON_LIB.FALCON(SCH_1):PAGE38

V_SBPCIE V_1P8 6of6 V_1P8 1 R2C1 2 U2C1 IC 0 5% SB VERSION 106 603 CH VDD18<17> U19 V_1P8 STUFF THIS WHEN NOT USING V_SBPCIE REGULATOR VDD18<16> U18 VDD18<15> R15 VDD18<14> P15 VDD18<13> M15 VDD18<12> M14 1 1 1 1 1 1 1 1 1 V_SBPCIE J12 C2P22 C2P21 C2P16 C2P28 C2P30 C2P17 C2P15 C2P33 C2P29 FB2P2 VDD18<11> .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF VDD18<10> H12 10% 10% 10% 10% 10% 10% 10% 10% 10% 1 2 V_AVDD_PEX R11 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V L19 AVDD_PEX VDD18<9> 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R J11 402 402 402 402 402 402 402 402 402 120 FB V_AVSS_PEX L20 AVSS_PEX VDD18<8> 0.2A 603 H11 1 1 1 VDD18<7> 0.5 DCR T18 M9 C3P3 C2P27 C2P26 V_VDD_PEX_FB VDD_PEX<4> VDD18<6> 4.7UF 2.2UF 0.01UF R18 H9 10% 10% 10% VDD_PEX<3> VDD18<5> 6.3V 6.3VX5R 16V P18 R8 2 X5R 2 2 X7R N18 VDD_PEX<2> VDD18<4> P8 805 ST2P1 603 402 M18 VDD_PEX<1> VDD18<3> M8 1 2 VDD_PEX<0> VDD18<2> J8 V_3P3 SHORT U22 VDD18<1> H8 T22 VSS_PEX<15> VDD18<0> V_1P8 R22 VSS_PEX<14> E14 R2P17 M22 VSS_PEX<13> VDD33<13> E13 K22 VSS_PEX<12> VDD33<12> E12 0 5% 603 CH U21 VSS_PEX<11> VDD33<11> E11 1 1 1 1 C2P10 C2P32 C2P31 P21 VSS_PEX<10> VDD33<10> E10 C2P39 C2P20 C1D2 4.7UF .1UF 0.01UF N21 VSS_PEX<9> VDD33<9> E9 1UF 1UF 4.7UF 10% 10% 10% M21 10% 10% 10% 6.3V 6.3V 16V VSS_PEX<8> VDD33<8> D8 16V 16V 6.3V 2 X5R 2 X5R 2 X7R K21 VSS_PEX<7> VDD33<7> D7 X7R X7R 2 X5R 805 402 402 603 603 805 T20 VSS_PEX<6> VDD33<6> D6 R20 VSS_PEX<5> VDD33<5> G5 P20 VSS_PEX<4> VDD33<4> D5 T19 VSS_PEX<3> VDD33<3> F4 V_1P8 N19 VSS_PEX<2> VDD33<2> E4 M19 VSS_PEX<1> VDD33<1> D4 FB1P2 VSS_PEX<0> VDD33<0> 1 2 J3 N15 120 FB J2 AVDD1_SATA VSS<41> L15 0.2A 603 AVSS1_SATA VSS<40> K15 1 1 1 1 U1 V_3P3 C1P2 C1P7 0.5 DCR C1P5 C1P6 H1 P14 T1 H2 VSS<39> 4.7UF 4.7UF 2.2UF .1UF N14 10% 10% 10% 10% V_AVDD1_SATA AVDD0_SATA VSS<38> 6.3V 6.3V 6.3V 6.3V AVSS0_SATA VSS<37> L14 2 2 2 2 V_AVSS1_SATA X5R X5R X5R X5R VSS<36> K14 805 805 ST1P2 603 402 CMPAVDD_SATA VSS<35> J14 1 1 1 1 1 1 2 C2P13 C2P12 C2P14 C2P11 C2P9 V_AVDD0_SATA CMPAVSS_SATA VSS<34>VSS<33> R13 .1UF .1UF .1UF .1UF .1UF V_AVSS0_SATA T5 P13 10% 10% 10% 10% 10% SHORT R5 N13 6.3V 6.3V 6.3V 6.3V 6.3V VDD_SATA<5> VSS<32> 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R P5 M13 402 402 402 402 402 V_CMPAVDD_SATA N5 VDD_SATA<4> VSS<31> L13 FB1P1 V_CMPAVSS_SATA M5 VDD_SATA<3> VSS<30> L5 K13 1 2 VDD_SATA<2> VSS<29> J13 VDD_SATA<1> VSS<28> 120 FB V_VDD_SATA H13 0.2A 603 VDD_SATA<0> VSS<27> 1 1 T4 N12 0.5 DCR VSS<26> C1P3 C1P4 R4 M12 2.2UF .1UF VSS_SATA<18> VSS<25> 10% 10% M4 L12 6.3V 6.3V L4 VSS_SATA<17> VSS<24> K12 2 X5R 2 X5R K4 VSS_SATA<16> VSS<23> P11 ST1P1 603 402 J4 VSS_SATA<15> VSS<22> N11 1 2 T3 V_3P3 R3 VSS_SATA<14> VSS<21> M11 P3 VSS_SATA<13> VSS<20> SHORT L11 N3 VSS_SATA<12> VSS<19> K11 K3 FB1P4 VSS_SATA<11> VSS<18> R10 T2 VSS_SATA<10> VSS<17> 1 2 N2 P10 VSS_SATA<9> VSS<16> 1 120 FB M2 N10 C2P4 C2P1 0.2A 603 L2 VSS_SATA<8> VSS<15> M10 1UF 4.7UF 1 1 10% 10% 0.5 DCR C1P10 C1P11 K2 VSS_SATA<7> VSS<14> L10 R1 16V 6.3V 2.2UF .1UF VSS_SATA<6> VSS<13> K10 X7R 2 X5R 10% 10% P1 603 805 6.3V 6.3V VSS_SATA<5> VSS<12> J10 2 X5R 2 X5R VSS_SATA<4> VSS<11> H10 402 ST1P3 603 VSS_SATA<3> VSS<10> P9 1 2 L1 VSS_SATA<2> VSS<9> N9 VSS_SATA<1> VSS<8> L9 SHORT VSS_SATA<0> VSS<7> K9 VSS<6> J9 FB1P3 VSS<5> N8 VSS<4> L8 1 2 VSS<3> K8 120 FB A15 0.5A 603 VSS<2> 0.2DCR 1 C1P8 1 C2P52 1 C1P1 VSS<1> 10UF .1UF .1UF VSS<0> 20% 10% 10% 6.3V 6.3V 6.3V 2 X5R 2 X5R 2 X5R X02047-012 805 402 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=SB, MAIN POWER + DECOUPLING] Tue May 08 18:24:17 2007 FALCON_RETAIL 38/82 1.0 CONFIDENTIAL CR-39 : @FALCON_LIB.FALCON(SCH_1):PAGE39

N: 123.8 OHM TERMINATION REQUIRED FOR ICS N: 100 OHM TERMINATION REQUIRED FOR BROADCOM

ENET_RX_DP

1 R1A4 V_ENET 39 IN 61.9 1%

1 CH 402 R1B7 2 40 45 1K 5% ENET_RX_DP_R CH 1 402 ENET_CLK 2 R1M1 27 0 IN ENET_POAC_R 45 OUT STUFF FOR BROADCOM 5% IC BI U1B2 1 1 EMPTY FOR ICS CH ICS1893BF 603 R1B6 R1B13 2 10K 332 REF_IN VDD<7> 48 5% 47 REF_OUT 1% ENET_RX_DN_R 1 ENET_REF_CLK_OUT 45 CH IN DB1N4 46 VDD<6> EMPTY VDD<5> 33 402 RESET_N* 14 2 402 1 33 ENET_RST_N MII_RX_CLK 23 VDD<4> 2 VDD<3> 7 R1A3 RXCLK 61.9 36 40 34 VDD<2> 24 OUT 2 OUT RXDV ENET_ACT_N 40 45 1% 36 40 MII_RXDV 32 VDD<1> 22 10K OUT RXER CH R1C1 36 40 MII_RXER 35 VDD<0> 18 OUT MII_RXD3 402 5% 2 28 RXD<3> TP_AP 36 40 12 CH OUT 29 RXD<2> TP_AN 402 36 OUTMII_RXD2 13 1 36 40 30 RXD<1> OUT40MII_RXD1 ENET_RX_DN 36 40 OUTMII_RXD0 31 RXD<0> TP_BP 16 TP_BN 15 OUT ENET_TX_DP 36 40 TXCLK 36 MII_TX_CLK 38 TXEN 8 40 45 37 P4RD 1 36 MII_TXEN 6 IN P3TD 4 40 45 IN MII_MDC_CLK_OUT MII_TXD3 42 TXD<3> P2LI R1A1 36 41 61.9 36 IN MII_TXD2 TXD<2> 3 BI 36 IN 36 40 P1CL 1% 2 R1B11 1 TXD<1> 1 ENET_P2LI_R 39 V_ENET IN P0AC OUT CH BI IN MII_TXD1 39 TXD<0> 1.5K 1% IN 402 36 MII_TXD0 9 1 2 402 CH 10/100 27 MDC R1B4 26 36 45 40 BI MDIO VSS<6> 10K ENET_TX_DP_R MII_MDIO 25 5% 43 VSS<5> ENET_P3TD ENET_P4RD 36 40 MII_COL COL 21 ENET_P1CL CH OUT 44 VSS<4> 17 1 36 MII_CRS CRS 1 402 OUT VSS<3> 2 10 11 R1M2 VSS<2> R1N6 0 ENET_AMDIX_EN AMDIX_EN 5 10K OUT 20 VSS<1> 2 ENET_LINK_N 40 45 5% 40 2 R1N4 1 5% 39 19 VSS<0> CH 1 CH 1 1 IN 100 5% 100TCSR 603 402 2 402 EMPTY 10TCSR R1N7 2 R1N510K R1B5 10K 1K ENET_TX_DN_R 5% 5% 5% 2 R1N1 1 V_ENET ENET_100BIAS X800188-002 CH CH CH 1 9.53K 1% ENET_10BIAS 402 402 402 R1A2 CH 2 2 2 402 EMPTY FOR BROADCOM 61.9 1 ENET_10_100_OUT 1% 2 2 DB1N3 STUFF FOR ICS CH R1N2 R1N3 AMDIX_EN HAS INTERNAL PULLUP 402 1.58K 2K AUTO MDIX IS ON BY DEFAULT 2 1% 1% CH CH 402 402 10/100 PIN IS FOR OUTPUT 1 1 INDICATION OF CONNECTION SPEED BI 40 45 ETHERNET ADDRESS="00001" ENET_TX_DN 39

V_3P3 OUT FB1B1 1 2 V_ENET 40 45 60 0.1DCR 0.5A 603 2 C1B1 C1N1 C1N4 C1N5 C1N3 C1N9 C1N11 C1N2 C1N10 1 C1A5 10UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF .1UF 100UF 20% 10% 10% 10% 10% 10% 10% 10% 10% 20% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 16V 1 X5R X5R X5R X5R X5R X5R X5R X5R X5R ELEC 402 402 402 2 RDL 805 402 402 402 402 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=SB OUT, ETHERNET] Tue May 08 18:24:17 2007 FALCON_RETAIL 39/82 1.0 CONFIDENTIAL CR-40 : @FALCON_LIB.FALCON(SCH_1):PAGE40

BDCM PHY

V_1P8

FB1N1 2 1 ENET_AVDD OUT 40 60 EMPTY 0.5A 603 0.1DCR 1 C1N7 1 C1N14 1 10UF .1UF C1N8 20% 10% 4.7UF 6.3V 6.3V 10% 2 EMPTY 2 EMPTY 6.3V 805 402 2 EMPTY 805

EMPTY U1B1 27 ENET_CLK IN BCM5241 1 XTALI2 1 ENET_REF_CLK2_OUT 2 DB1N1 XTALO2 V_ENET ENET_RST_N IN 33 RESET_N IN 10 39 MII_RX_CLK 1 20 MII_RXDV RXC OUT 19 RX_DV/TEST0 R1B12 36 39 OUT MII_RXER 21 OVDD2 22 V_ENET 4.7K 36 39 RX_ER/TEST1 IN 5% OUT36 39 OVDD1 9 39 EMPTY 36 39 MII_RXD2MII_RXD3 15 RXD3/ISOLATE 402 OUT 16 RXD2/F100 AVDD 7 ENET_AVDD 40 2 OUT MII_RXD1 17 IN OUT36 39 18 RXD1/ANEN 36 39 MII_RXD0 RXD0/PHYAD0 LINK# ENET_LINK_N 39 45 OUT 36 39 ACT# 11 ENET_ACT_N OUT39 45 36 39 23 TXC 12 OUT OUT36MII_TX_CLK 24 TX_EN TDP 3 ENET_RX_DP 39 45 MII_TXEN 4 OUT 36 IN 36 TDN ENET_RX_DN OUT 39 45 36 36 28 TXD3 IN MII_TXD3 27 TXD2 RDP 6 39 45 5 ENET_TX_DP OUT IN MII_TXD2 26 TXD1 RDN 39 45 IN MII_TXD1 ENET_TX_DN OUT 25 8 36 IN MII_TXD0 TXD0 RDAC IN 14 MDC_CLK_OUT MII_MDC_CLK_OUTMII_MDIO36 39 13 GND 33 39 36 BI MDIO 29 OUT 32 COL/ENERGYDET

MII_CRS 30 ENET_RDAC 36 39 OUT MII_COL CRS/LOWPWR0

31 1 ENET_AVDD REGVDDIN 40 IN R1N8 REGVDDOUT 1.27K 1 C1N6 1% .1UF X801554-002 LCC32 EMPTY 10% 402 6.3V 2 2 EMPTY 402

DRAWING PROJECT NAME PAGE REV FALCON_FABD MICROSOFT [PAGE_TITLE=XDK, DEBUG LEDS, BDCM PHY] FALCON_RETAIL 40/82 1.0 Tue May 08 18:24:20 2007 CONFIDENTIAL CR-41 : @FALCON_LIB.FALCON(SCH_1):PAGE41

V_12P0

AUD_CLAMP_R FB2B2 2 R2B3 1 C2B10 1 2 1 1K 0.7DCR FT2M1 AUD_AC_R 1K 5% V_3P3 1 2 402 CH 0.2A 603 10UF FTP 1 R2B1 2 16V AUD_VAA TANT 1206 1 0 5% 20% FT2N1 603 CH C2A7 2 C2B7 2 FTP 1 R2B6 2 AUD_VDD 4.7UF 0.1UF R2B5 10% 10% 10K 0 5% 16V 25V 1 5% 603 CH X5R X7R 1206 603 1 CH C2B11 C2B5 402 PGB0010603 1 2 4.7UF .1UF 1 C2B3 10% 10% 603 6.3V 6.3V 470PF 2 EG2B2 5% X5R X5R 50V 805 402 X801161-001 1 X7R U2B1 IC EMPTY 402 XDAC 2 14 DVDD

I2S_MCLK 13 AUD_R_OUT 44 AUD_DCAP MCLK AVDD 9 OUT 36 I2S_BCLK 4 36 BCLK I2S_SDIN 3 AUD_VOUTR 36 IN SD VOUTR 6 1 I2S_WS 2 10 AUD_L_OUT FT2N2 36 IN WS VOUTL OUT 44 IN 8 FTP 5 NC AVREF AUD_ACAP 33 AUD_RST_N 12 PDN IN AUD_VOUTL 11 DVREF 7 C2B1 AGND C2B4 C2B8 1 .1UF 10UF 1 PGB0010603 C2B6 1 DGND 10% 20% R2N3 2 20% 10UF .1UF 6.3V 6.3V 603 EG2B1 1K 10% X5R X5R 5% 6.3V 6.3V X02238-003 402 805 X801161-001 R2B4 X5R X5R 10K CH 805 EMPTY 5% 402 402 2 CH 2

2 C2B2 402 470PF 1 5% 50V 1 X7R 402

C2B9 AUD_AC_L 10UF 1 2 AUD_CLAMP_L FB2B1 20% 16V 2 R2B2 1 TANT1K 1 2 1206 1K 5% 1K 0.7DCR 402 CH 0.2A 603

1 5% FT2P1 FTP CR2M2 CH MBT3904 3 6 AUD_CLAMP_B2 AUD_CLAMP_B3 2 2 R2N2 1 5 2 R2N1 1 AUD_CLAMP 2 3 AUD_CLAMP_C 34 IN Q2N1 5% 4 1K MMBT3906 402 CH XSTR 402 XSTR 1 V_3P3STBY 1

1 R2N23 2 AUD_CLAMP_B1 4.7K 5% 402 CH 1 R2N22 1K 5% CH 402 2

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:17 2007 FALCON_RETAIL 41/82 1.0 [PAGE_TITLE=SB OUT, AUDIO] CONFIDENTIAL CR-42 : @FALCON_LIB.FALCON(SCH_1):PAGE42

N: RETAIL=16MB FLSH_DATA0 N: XDK=64MB 0 1

0 8MB 16MB

1 32MB 64MB FLSH_DATA1

V_3P3STBY

N: STUFFED AT CONFIG LEVEL 1 1 1

1 1 1 N: UPDATE TO RECENT PART NO# R2D7 R2D6 R1E2 C2E6 C2E5 C2R11 10K 10K 10K 4.7UF .1UF .1UF 1 5% 5% 5% 10% 10% 10% FT1R3FTP 6.3V 6.3V 6.3V 1 CH CH CH 2 X5R 2 X5R 2 X5R FT1R4FTP 1 402 402 402 402 402 U2E1 IC FT1R5FTP 2 2 2 FT2R3 1 805 FTP 1 NAND FLASH FT2R4FTP RDY 7 FLSH_READY 1 OUT FT2R5FTP 1 FT2R6FTP NC<27> 38 FLSH_NC38 2 R2D2 1 1 NC<26> 35 FT2R7FTP 37 VCC1 48 0 5% 1 12 NC<25> 47 FTP FT1T1 VCC0 402 EMPTY NC<24> 46 FLSH_DATA<7..0> IN 7 44 DATA<7> NC<23> 45 6 43 DATA<6> NC<22> 40 35 42 5 DATA<5> NC<21> 39 4 41 NC<20> 35 DATA<4> 34 3 32 NC<19> DATA<3> 33 31 NC<18> 2 DATA<2> 1 30 NC<17> 28 FLSH_CE_N DATA<1> 0 29 DATA<0>IN NC<16> 27 IN NC<15> 26 IN 35 9 CE_N* NC<14> 25 IN 24 35 8 RE_N*IN NC<13> 10K 35 FLSH_RE_N 23 1 5%1 1 1 1 1 1 1 18 WE_N*IN NC<12> 35 FLSH_WE_N 19 22 R2D8 R2D5 R2D4 R2D3 R2D1 R1D4 R1D3 R1D2 35 WP_N* NC<11> FLSH_WP_N 1716 21 10K 10K 10K 10K 10K 10K 10K 35 ALE NC<10> 5% 5% 5% 5% 5% FLSH_ALE 20 5% 5% CLE NC<9> CH FLSH_CLE 15 EMPTY EMPTY CH CH CH CH CH NC<8> 402 402 402 402 402 402 402 402 6 VSS/NC 14 2 2 2 2 2 2 2 2 NC<7> 36 VSS1 NC<6> 11 13 VSS0 NC<5> 10 5 NC<4> 4 NC<3> NC<2> 3 NC<1> 2 NC<0> 1

X802184-001 TSOP

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:17 2007 FALCON_RETAIL 42/82 1.0 [PAGE_TITLE=SB OUT, FLASH] CONFIDENTIAL CR-43 : @FALCON_LIB.FALCON(SCH_1):PAGE43

V_3P3STBY

BINDING BUTTON FAN CONTROL 1 V_12P0 BINDSW_N_R R5V3 SWITCH 10K TH 5% 2 R3M9 1 CH SW5G1 402 5.11K 1% 2 THR 402 CH BINDSW_N 2 2 R5V2 1 4 1 FAN1_Q1_C 1 Q3M1 34 MJD210 3 2 10K 5% XSTR OUT 3 402 CH V_3P3STBY 3 FAN1_OUT 1 Q3M2 X02246-002 28 IN MMBT2222 3 XSTR D3A1 2 1N4148 SOT23 ODD EJECT BUTTON 1 DIO 2 C4P14 1 2700PF 10% 50V FAN1_Q1_E J3A2 R1G4 1 X7R SWITCH 10K 402 2 1X3HDR TH 5% V_FAN1 1 CH EJECTSW_N_R R3M8 2 SW1G1 402 3 2 5% C3A9 THR 1UF CH 10% CONN 2 R1G3 1 402 16V 4 1 EJECTSW_N 34 48 1 1 5% OUT X7R 3 2 603 10K 100 R3A7 402 CH 30.1K X02246-002 1% CH FAN1_FDBK_R 402 2 2 R4P2 1 FAN1_FDBK V_3P3STBY 5.11K 1% OUT 28 402 CH 1 R3A2 11K 1% TILT SWITCH, ALPS CH 1 402 R2G2 2 10K EMPTY 5% SW2G1 CH SM 402 2

4 1 2 R2G3 1 3 2 TILTSW_N_R 34 10K 5% TILTSW_N X800550-003 402 CH OUT

IR MODULE

TILT SWITCH, SOLICO N: X800550-003 HOLDS ALL THREE TILT SWITCHES V_3P3STBY TMEC ONLY HAS 3 PINS WHICH REQUIRES A DIFFERENT SM UNIQUE PART NUMBER TO HOLD THE SYMBOL NAME 1 R2V1 2 SW2G2 N: BOM MUST CALL OUT X800550-003 WITH QTY 1 AND V_IR SM LIST ALL THREE REF DES. FACTORY CHOOSES FROM THERE 49.9 1% C2V1 402 CH 2 4 1 1 C2V2 3 2 .1UF R2N7 4.7UF 10% 10K 10% 6.3V 5% X800550-003 6.3V 2 X5R X5R 402 CH U1G1 IC 805 402 34 1 IR

VCC 3 DATA 1 IR_DATA OUT GND 2 TILT SWITCH, TMEC ME2 5 4 EMPTY ME1 SW2G3 TH X803473-002 1 3 2

X813350-001

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:18 2007 FALCON_RETAIL 43/82 1.0 [PAGE_TITLE=CONN, FAN + INFRARED + SWITCHES] CONFIDENTIAL CR-44 : @FALCON_LIB.FALCON(SCH_1):PAGE44

VID_DACA_OUT VID_DACA_DP

6 L3A3 V_5P0 1 2 IN 44 OUT DAC STANDARD ADVANCED SDTV HDTV SCART VGA

BAV99 .27UH IND OUT RT2M1

SOT363 1 2 29 1 0.45A 1210 DIO V_AVIP NA R3A4 A N/A Y(LUMA) Y Y G 1 1 1.1A THRMSTR G 75 C3A6 C3A3 0.21DCR 1206 1% 62PF 75PF 1 R 28 HANA_SPDIF_OUT C2M5 C2A1 PR CH 5% 5% 4.7UF 470PF B N/A C(CHROMA) PR R V_3P3 402 50V 50V IN 10% 5%

CR3A2 2 2 2 NPO NPO 6.3V

1 402 402 2 2 X5R 28 805 N/A 1 50V C N/A PB PB B B C2A6 X7R 22PF

3 402 5% 50V 2 D

DIO SOT23S CVBS(COMP) CVBS(COMP) CVBS N/A CVBS CVBS NPO BAV99 VID_DACB_DP 402 L3A2 VID_DACB_OUT

1 2 D2A1 OUT 1 .27UH IND 44 2 J3A1 CONN SOT363 1 1210 DIO 0.45A V_3P3 3 NA XENON AVIP CONNECTOR

BAV99 R3A3 29 28 1 1 V_AVIP 75 C3A5 C3A2 27 V_AVIP_RET 1% 62PF 75PF V_3P3 CH 5% 5% 50V 50V VID_DACA_OUT 4 VID_DACA_OUT

CR3A2 2 2 NPO NPO 44 2 2 402 402 VID_DACA_RET 5 4 402 VID_DACB_OUT V_12P0 3 VID_DACB_OUT 1 EXT_PWR_ON_N IN 44 VID_DACC_OUT VID_DACB_RET OUT EXT_PWR_ON 34 44 58 8 VID_DACC_OUT 44 6 2130 HDMI_DDC_CLK 34 29 VID_DACC_RET DDC_CLK BI 28 VID_DACC_DP 6 L3A1 VID_DACC_OUT VID_DACD_OUT 23 HDMI_DDC_DATA 28 34 29

1 DDC_DATA BI 1 2 IN 7 AV_MODE2 OUT 44 VID_DACD_OUT 1% CH 5 28 .27UH IND VID_DACD_RET AV_MODE2 34 44 OUT 0.45A 1210 OUT VID_HSYNC_OUT AV_MODE024 AV_MODE1 34 44 OUT 28 DIO 44 IN AV_MODE1 1 NA 11 20 34 44 R2A8 44 VID_HSYNC_OUT AV_MODE0 BAV99 R3A6 9 SOT363 VID_HSYNC_RET 1 1 VID_VSYNC_OUT 26

75 402 IN C3A4 C3A1 2 GND<2>

1.82K 22 1% 62PF 75PF 44 2512 5% 5% WSS_CNTL1 10 VID_VSYNC_OUT GND<1> 18 V_3P3 CH 1 R2A6 2 WSS_CNTL_B CR3A1 50V 50V IN VID_VSYNC_RET GND<0> 402 2 NPO 2 NPO 1 IN 2 2 402 402 33 5.36K 1% CR2A1 34 IN 402 CH MBT3904 SPDIF SHIELD<3> 33 3 6 IN AUD_R_OUT 32 15 SHIELD<2> 2 41 5 13 AUD_R_OUT SHIELD<1> 31 IN AUD_R_RET SHIELD<0> WSS_CNTL0 1 R2A7 2 33 IN AUD_L_OUT 16 4 41 14 4.75K 1% AUD_L_OUT MTGB<8-1> CH XSTR 402 1 AUD_L_RET MTGA<8-1> WSS_CNTL_OUT_RIN 2 R2A5 1 WSS_CNTL_OUT 17 WSS_CNTL_E 1K 5% 19 WSS_CNTL

CH SCART_RGB 2 2 IN 402 CH 1%

CH 2 C2A850V TH 75PFNPO L3A4 5%402 X806743-001 R2A9 R2A4 1 2 1 28 VID_DACD_DP VID_DACD_OUT OUT 44 10K 5% 1 402 1 402 .27UH IND IN 1 0.45A 1210 DIO 301 3 R3A9 NA

BAV99 2 75 C3A7 2 IN SOT363 1% 62PF C3A8 V_3P3STBY CH 5% 75PF V_3P3 50V 5% 402 1 NPO 50V 1 CR3A1 2 402 NPO 58 44 402 5 4 44 1 1 1 1 28 44 44 44 R2A1 R2M6 R2M4 R2N20 V_3P3 10K 10K 10K 10K 33 5% 5% 5% 5% CH CH CH CH SCART_RGB_OUT 402 402 402 402 2 2 2 2 28 44 2 EXT_PWR_ON_N 2 R2N19 1 SCART_RGB SCART_RGB_R 1 Q2N3 IN AV_MODE2 VID_VSYNC_OUT_R 1 R3M3 2 VID_VSYNC_OUT IN OUT MMBT3906 IN AV_MODE1 10K 5% XSTR IN 49.9 1% 402 CH AV_MODE0 402 CH 3 IN

3 1 1 1 1 SCART_RGB_OUT_R 1 R2M9 2 C2A3 C2M3 C2M2 C2N3 470PF 470PF 470PF 33 5%

1 5% 5% 5% 5% V_3P3STBY 1 R3M2 2 402 CH 50V 50V 50V 50V 6 VID_HSYNC_OUT 470PF VID_HSYNC_OUT_R 1 2 X7R 2 2 X7R 2 X7R IN OUT 5% CH X7R

DIO 402 402 402 49.9402 1% C2M4 402 CR3M2 CH 0.01UF

BAV99 10% 5 4

SOT363 16V R2M10 2 X7R

DIO 402 10K 402 2 LAYOUT:PLACE CLOSE TO CONNECTOR BAV99 V_3P3STBY EMI CAPS CR3M2 1 2 DRAWING PROJECT NAME PAGE REV FALCON_FABD MICROSOFT [PAGE_TITLE=[CONN, AVIP] FALCON_RETAIL 44/82 1.0 Tue May 08 18:24:18 2007 CONFIDENTIAL CR-45 : @FALCON_LIB.FALCON(SCH_1):PAGE45

V_5P0DUAL

RT1B1 2 1 V_EXPPORT OUT 45 45 IN V_EXPPORT 1.1A THRMSTR 0.21DCR 1206 2 2 4.7UF 1 D1A2 1 C2A4 C1A3 C1M2 FTP FT1N2 220UF 470PF 6.3V R1B2 2 20% 5% 10% 10V 50V ELEC 1 X7R 1 X5R 0 5% 2 3 RDL 402 805 603 CH

1 NA SM BAV99 L1B1 EMPTY SOT23S CMCHOKE DIO EXPPORT_DN_CM 35 BI EXPPORT_DN 1 2

EXPPORT_DP 4 3 EXPPORT_DP_CM X801560-001 D1A1 PGB0010603 PGB0010603 2 1 1 35 603 603 EG1A2 EG1A1 BI 3 R1B1 EMPTY 1 EMPTY

0 5%

603 CH BAV99 2 2 CONN SOT23S J1A1 DIO XENON RJ45/USB COMBO VBUS

D- IN D+ ARGON_NTX D1B1 2 GND C1A4 12 45 IN 2 470PF 5% 13 V_EXPPORT 50V IN 14 OMNI 3 1 15 X7R 39 ENET_P2LI_RIN 1 LED_LEFT_A 402 LED_LEFT_C 40 39 ENET_LINK_N 2 1 IN 16 IN ENET_POAC_R 3 LED_RIGHT_A BAV99 39 39 ENET_ACT_NIN LED_RIGHT_C SOT23S 40 DIO IN 39 40 39 ENET_TX_DP 114 XFMER2_P V_ENET 1 R1M3 2 ENET_TX_CT IN 10 XFMER2_C IN 7 0 5% 40 39 ENET_TX_DNIN XFMER2_N 402 EMPTY 40 39 ENET_RX_DP 9 XFMER1_P 1 R1A5 2 6 XFMER1_C ENET_RX_CT 5 0 5% 40 39 ENET_RX_DN XFMER1_N 402 EMPTY 8 CAP C1M1 C1A2 .1UF .1UF 20 10% 10% EMI4 6.3V 6.3V 19 EMI3 X5R X5R 18 402 402 EMI2 21 EMI1 17 ME1

X806148-001

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:18 2007 FALCON_RETAIL 45/82 1.0 [PAGE_TITLE=CONN, RJ45 + USB COMBO] CONFIDENTIAL CR-46 : @FALCON_LIB.FALCON(SCH_1):PAGE46

V_MEMPORT1 V_MPORT V_5P0DUAL V_GAMEPORT2 OUT 60

RT2G1 FB5G1 RT8G1 2 1 2 1 V_MEMPORT2 2 1 120 FB 1.1A THRMSTR 0.5A THRMSTR 0.21DCR 1206 1 2 1.1A 0.2DCR 1 C5G4 C4V6 C5G6 0.21DCR 1206 2 4.7UF 2 603 220UF C9G5 1 C9G2 C9G1 470PF 4.7UF 220UF ELEC20% 5% 10% 6.3V 470PF 10V 10% 20% 5% 50V 6.3V 2 X7R 1 X5R 10V 50V 2 RDL 1 ELEC 1 402 805 X5R 2 X7R 805 RDL 402 PGB0010603 1 603 R4G5 EG9G2 MEMPORT2_DN_CM V_5P0DUAL 0 5% CH EMPTY NA 603 SM

2 L4G1 D9G2 CMCHOKEEMPTY

2 MEMPORT2_DN 1 2 1 R9G2 2 BI

0 5% 3 603 CH 35 BI MEMPORT2_DP 4 3 MEMPORT2_DP_CM 1 NA PGB0010603 PGB0010603 SM X801560-001 1 1 BAV99 603 GAMEPORT2_DN L9G1 EMPTY 603 SOT23S PGB0010603 EG4G2 EG4G1 J4G2 CONN 1 CMCHOKE DIO 603 4 3 XENON MU EG9G1 DIO DIO BI 35 GAMEPORT2_DP EMPTY 1 GND R4G4 2 VBUS 2 2 1 2 3 BI TH 0 5% D- 603 CH D+

2 CONN D9G1 4 X801560-001 J9G1 5 GND 2 XENON GAME 6 GND 35 CONN 7 3 VBUS 1 VBUS 8 D- 1 R9G1 2 GAMEPORT2_DN_CM 2 D- 9 D+ 35 1 2 2 GAMEPORT2_DP_CM 3 1 C2G2 C3V5 C2G3 10 D+ 220UF GND 0 5% GND 470PF 4.7UF 603 CH BAV99 20% 5% 10% 4 10V 50V 6.3V EMI4 SOT23S ELEC 1 X7R 1 X5R DIO 5 VBUS 2 RDL 402 805 14 EMI3 GAMEPORT1_DN_CM 6 D- R3G4 13 EMI2 V_5P0DUAL GAMEPORT1_DP_CM 7 D+ 1211 EMI1 8 0 5% GND 603 CH 15 ME4 RT8G2 9 NA EMI1 SM 16 ME3 2 1 V_GAMEPORT1 10 EMI2 17 ME2 L2G1 EMPTY 18 ME1 1.1A THRMSTR 11 ME1 CMCHOKE MEMPORT1_DN_CM 0.21DCR 1206 2 MEMPORT1_DN 1 2 2 1 C9G3 C9G4 12 ME2 MTGA<8-1> C9G6 220UF 470PF BI 4.7UF 20% 5% MTGB<8-1> 10% 10V 50V MEMPORT1_DP 6.3V ELEC 1 MTGC<8-1> X7R 4 3 MEMPORT1_DP_CM 1 X5R 2 RDL 402 X800245-003 BI 35 805 X800059-001 TH X801560-001 35 603PGB0010603 PGB0010603 1 1 603 V_5P0DUAL EG3G1 EG2G1 DIO R2G5 D9V2 DIO

2 PGB0010603 0 5% R9V2 1 603 CH 603 2 2 0 5% 3 EG9V2 603 CH

1 EMPTY NA SM BAV99 L9V1 EMPTY SOT23S 2 V_5P0 V_MPORT CMCHOKE DIO U1F2 IC 35 GAMEPORT1_DN 4 3 BI 1 PGB0010603 NCP1117 603 3 2 1 EG9V1 IN OUT FTP FT1V1 35 1 2 1 BI GAMEPORT1_DP ADJUST/GND EMPTY 1 D9V1 1 C1F6 1 C1F4 X801560-001 C1U2 0.1UF 100UF 1.0UF X800499-001 20% 2 2 10% 10% 25V 16V 16V 2 ELEC 2 X7R 2 3 X7R 603 RDL 805

R9V1 1

0 5% 603 CH SOT23SBAV99 DIO

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:18 2007 FALCON_RETAIL 46/82 1.0 [PAGE_TITLE=CONN, MEMORY PORTS + GAME PORTS] CONFIDENTIAL CR-47 : @FALCON_LIB.FALCON(SCH_1):PAGE47

XDK BOARD MAPPING

DEBUG BOARD MAPPING

CPU_DBGSEL_XDK<0..69> 1 FT6U11 CPU_DBGSEL_DEBUG<0..69> CPU_DBG_TERM<0..69> IN 1 IN 0 OUT FTP FT6U9 0 N:CONNECT TO CPU 1 FTP FT6U10 N:CONNECT TO CPU 1 1 DEBUG OUT FTP DEBUG OUT 2 2 3 3

4 5 4 6 5 1 6 59 52 DBG_CPU_LINKTRAINED DB6E1 7 7 1 53 DBG_CPU_SECURE_SYSDBG_CPU_PLL_LOCK DB6E2 8 1 8 54 DB6E3 9 9 55 1 DBG_CPU_TST_CLK DB6E4 10 10 11 11

12 56 1 13 DBG_CPU_POST_OUT0 FTP FT6U8 12 14 57 1 FTP FT6U2 13 15 58 DBG_CPU_POST_OUT1DBG_CPU_POST_OUT2 1 14 FTP FT6U3 16 59 DBG_CPU_POST_OUT3 1 15 17 FTP FT6U4 60 DBG_CPU_POST_OUT4 1 16 18 FTP FT6U5 17 61 DBG_CPU_POST_OUT5 1 19 FTP FT6U6 18 DBG_CPU_POST_OUT6 1 62 FTP FT6U7 1920 63 DBG_CPU_POST_OUT7 1 21 FTP FT6U1 20 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 31 31 30 V_5P0STBY 32 V_5P0STBY 33 32 V_12P0 34 33 35 34 36 35 1 C1D11 37 36 1 1 220UF 37 20% 38 R1R2 R1R3 10V 39 ELEC 10K 10K 2 40 5% 5% VREG_V5P0_SEL_PGATE RDL U1R1 IC 3841 CH CH 3942 402 402 SI4501DY 40 2 2 43 3 S2 V_5P0DUAL 41 2 R1R5 1 44 4 G2 42 FTP 45 43 10K 5% VREG_V5P0_SEL_NGATE 5 D<3> 1 46 44 402 CH 8 FT1R2 VREG_V5P0_SEL_C D<2> 47 45 2 V_5P0 D<1> C1R3 7 1 1 1 46 CR1D1 D<0> 48 MBT3904 .22UF 2 6 49 47 10% R1G2 R1G1 R1V2 48 50 6.3V 1K 20 20 49 1 X5R G1 1% 1 R1D6 2 402 5% 1% 51 50 34 VREG_V5P0_SEL VREG_V5P0_SEL_B1 VREG_V5P0_SEL_B2 1 S1 CH CH CH 52 51 FTP 4.7K 5% 402 1206 1206 53 52 1 402 CH 2 2 2 2 53 FT1R1 XSTR X801132-002 54 54 R1D5 55 IN 4.7K 5% 55 56 56 57 57 CH 58 402 58 59 1 59 60 60 BLEEDER_C2 BLEEDER_C1 61 3 62 61 1 Q1G2 6268 MMBT2222 63 VREG_5P0_SEL 64 6369 XSTR 64 3 65 VREG_5P0_SEL NGATE/PGATE V_5P0DUAL 2 65 2 R1V1 1 66 66 27 SMC_RST_N BLEEDER_B 1 Q1V1 IN MMBT2222 67 67 HIGH LOW V_5P0STBY 10K 5% XSTR 68 402 CH 2 69 LOW HIGH V_5P0

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V_5P0 D1E4

2 HDD_TX_DP

3 C1E4 1 2 HDD_TX_DP_C 1 0.01UF 10% 16V SOT23SBAV99 HDD SATA AND POWER IN X7R HDD_TX_DN_C 402 DIO

HDD_TX_DN D1E3 C1E3 J1E1 CONN 1 2 2 IN XENON HDD 0.01UF 10% CONN 16V 3 1 GND 36 X7R 2 D+ 402 1 3 D- 4 GND SOT23SBAV99 5 D- 6 D+ DIO 7 GND

V_5P0 8 GND 9 GND 36 D1E2 10 GND PGB0010603 PGB0010603 PGB0010603 PGB0010603 11 V_HDD 2 1 1 1 1 603 603 603 603 12 V_HDD EG1E4 EG1E3 EG1E2 EG1E1 13 V_HDD HDD_RX_DN 3 C1E2 14 V_XPOD 1 2 36 EMPTY EMPTY EMPTY EMPTY 1 EMI1 OUT 15 0.01UF 10% 16 16V EMI2 2 2 BAV99 2 2 X7R SOT23S 402 17 ME2ME1 HDD_RX_DN_C DIO 18

MTGA<8-1> HDD_RX_DP_C V_5P0 MTGB<8-1> D1E1 RT1U1 V_HDD HDD_RX_DP C1E1 1 2 2 OUT 2 1 X800351-002 TH 10% 0.01UF 3 1.5A THRMSTR 0.11DCR 1812 1 C1E5 C1T5 C1T4 C1T3 X7R 100UF 1UF 470PF 402 1UF 1 20% 10% 10% 5% 16V 16V 16V 50V ELEC 2 X7R X7R X7R 16V RDL 603 603 402 36 BAV99 SOT23S DIO

V_5P0DUAL RT1R1 ODD SATA 2 1 V_XPOD V_3P3 ODD_TX_DP_C 1.1A THRMSTR V_3P3 C1C6 ODD POWER DECOUPLING 0.21DCR 1206 C1T1 C1T2 ODD_TX_DP 1 2 36 1UF 470PF 10% 5% 0.01UF 10% 16V 50V ODD POWER AND CONTROL IN 16V V_12P0 V_3P3 X7R X7R 603 402 36 X7R CR1D2 402 CR1D3 2 C1C5 J1C1 2 36 1 2 ODD_TX_DN_C SATA IN ODD_TX_DN 1 C1C10 C1C14 C1C13 1 C1C11 C1D6 C1R1 3 100UF 100UF 3 9 1UF 0.1UF 1UF .1UF 0.01UF 10% 20% 10% 20% 10% 10% 16V 10% 16V 16V 25V 16V 16V 6.3V 1 X7R 1 ELEC ELEC 1 2 X7R X7R 2 X7R X5R 402 2 RDL 603 603 RDL 603 402 BAV99 36 3 TRAY_STATUS 1 R1R4 2 TRAY_STATUS_R SOT23S BAV99 OUT SOT23S C1C4 4 EMPTY 1 2 ODD_RX_DN_C 34 100 5% EMPTY ODD_RX_DN 5 402 CH OUT 68 0.01UF 10% V_5P0 IN 16V 7 V_3P3 J1D1 X7R 402 V_5P0 1 43 EJECTSW_N3 TRAY_OPEN 4 IN 34 CONN V_12P0 65 C1C3 1 C1D9 C1D4 C1D1 C1D3 1 2 7 OUT 100UF 1UF 1UF .1UF 8 ODD_RX_DP ODD_RX_DP_C 20% 10% 10% 10% 10 9 1 0.01UF 10% 16V X7R16V 16V 6.3V C1R4 ELEC 12 11 16V 2 X7R X5R 75PF X7R RDL 603 603 402 5% 402 50V CONN 2 NPO 402

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V_3P3STBY V_12P0 1 DB8M1 1 1 DB8M2 FT9N1 1 DB8M3 FTP 2 1 C6G5 C6G2 100UF 470PF 1 1 1 1 5% 1 C9B1 C9A1 0.1UFC9A5 C9A6 C9A2 16V 50V 1500UF 0.1UF 0.1UF 0.1UF 20%ELEC 1 2 X7R 20% 10% 10% 10% 10% J9A1 CONN RDL 402 16V 25V 25V 25V 25V ALUM 2 X7R 2 X7R 2 X7R 2 X7R 2 RDL 603 603 603 603 XENON PWR PSU_V12P0_EN_R 1 GND 2 GND 3 GND

4 V12P0 5 V12P0 6 V12P0

1 R6G7 2 PSU_V12P0_EN 2 R8A2 1 7 IN PSU_EN 0 5% 34 1 100 5% 1 1 8 603 CH 402 CH C8A1 C8A2 VSB5P0 NA R8A1 .1UF 470PF SM 10K 10% 5% 9 EMI1 5% 6.3V 50V ARGONPORT_DN 2 X5R 2 EMPTY 10 EMI2 L6G1 EMPTY CH 402 402 402 13 EMI3 CMCHOKE 2 14 EMI4 35 4 3 BI 11 ME1 ARGON_DP_CM TH 12 ME2 J6G1 CONN ARGONPORT_DP 1 2 35 BI MTGA<8-1> XENON RF X801560-001 MTGB<8-1> 1 1 CONN 1 C6G3 C6G4 1 VCC DB8N1 470PF 470PF ARGON_DN_CM 2 D- 1 5% 5% V_5P0STBY FTP FT8N1 X811487-001 TH 50V 50V 3 D+ 2 2 EMPTY EMPTY402 GND 1 R6G8 2 402 4 SPARE 1 0 5% 5 1 C5B7 1 C8B1 C9A4 603 CH 6 C_DATA 100UF 100UF 470PF V_3P3STBY 7 C_CLK 20% 20% 5% 16V 16V 50V 8 GND ELEC ELEC 2 2 2 X7R USE LC NETWORK FOR USB 1.1 9 NTX RDL RDL 402 USE USB CHOKE FOR USB 2.0 10 EMI1 34 11 1 34 EMI2

R3N7 12 ME1 10K 13 ME2 V_5P0STBY 5% ARGON_DATA 34 BI ARGON_CLK CH PWRSW_N_R BI V_12P0 402 2 2 2 X800095-001 2 R3N6 1 C6V11 C6V10 V_12P0 PWRSW_N 470PF 470PF 1 1 10K 5% 5% 5% R8B5 R7B2 2 50V 50V 402 CH C6V15 1 X7R 1 X7R 2.2K 2.2K 470PF 402 402 5% 5% 5% CH CH IN 50V 1 402 402 X7R 2 2 3 402 2 R8N1 1 BLEEDER_V12P0_B2 1 Q8N1 1 R6G37 2 BCP51 549 1% XSTR 0 5% 402 CH 603 EMPTY 2 4 NA BLEEDER_V12P0_LOAD SM L6G2 EMPTY 1 1 1 1 MEMPORT3_DP_ARGON_CM R7N3 R7N1 R7N4 R7N2 MEMPORT3_DP_ARGON 4 CMCHOKE 3 60 BI 10 10 10 10

BLEEDER_V12P0_C1 BLEEDER_V12P0_C2 1% 1% 1% 1% 3 CH CH CH CH Q8B4 60 1 805 805 805 805 MEMPORT3_DN_ARGON 1 2 MEMPORT3_DN_ARGON_CM MMBT2222 2 2 2 2 BI XSTR 3 2 X801560-001 2 R8A4 1 BLEEDER_V12P0_B1 1 Q8B5 MMBT2222 2.2K 5% XSTR 402 CH 2 1 R6G38 2

56 5% ANA_V12P0_PWRGD 2 R8A3 1 603 EMPTY 27 IN 4022.2K 5% CH

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V_GPUCORE CPU_VREG_APS5 R7E3 CPU_VREG_APS4 5 0 5% 402 CH R7E1 4 4 IN CPU_VREG_APS3 0 5% 4 R7E5 402 CH IN 3 N: WATERNOSE=011100=1.1625V 4 CPU_VREG_APS2 0 5% 1 1 1 1 1 1 IN 402 CH R7E4 N: DD1.0 REQUIRES VID0 RC 4 2 R7T6 R7T4 R7T8 R7T7 R7T5 R7T9 N: DD2.0 NO STUFF RC IN CPU_VREG_APS1 0 5% 10K 10K 10K 10K 10K 10K 4 R7E2 402 CH 5% 5% 5% 5% 5% N: LOKI=100001=1.05V 1 CH EMPTY EMPTY EMPTY EMPTY CH 4 IN 5% CPU_VREG_APS00 5% 402 402 402 402 402 402 402 CH R7E6 2 2 2 2 2 2 IN 0 1K 5% VREG_CPU_VID<5..0> 402 CH 5 4 3 2 1 0 OUT 51

1 1 1 1 1 1 R7T13 R7T11 R7T15 R7T14 R7T12 R7T16 10K 10K 10K 10K 10K 10K 5% 5% 5% 5% 5% 5% EMPTY CH CH CH CH EMPTY 402 402 402 402 402 402 2 2 2 2 2 2

V_12P0 V_12P0 N:GPU INPUT FILTER

N:CPU INPUT FILTER L8B1 1 2 V_VREG_GPU OUT 53 54 L9B1 OUT 1.6UH IND TH 1 2 V_VREG_CPU 51 52 10A 1 1 1 1 1 1 NA 1 C6B3 1 C7B3 C8B4 C6B5 C6N2 C7B4 C7N3 C8B2 1500UF 1500UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 1.6UH IND 4.7UF 20% 20% TH 10% 10% 10% 10% 10% 1 10A 1 1 16V 16V 16V 16V 16V 16V 16V C9B2 NA C9C4 C9C1 C9E3 C9D2 C9B4 C9C3 10% 1500UF 1500UF 1500UF 1500UF 16V ALUM ALUM 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 4.7UF 4.7UF 4.7UF 2 X5R 2 RDL 2 RDL 1206 1206 1206 1206 1206 10% 20% 20% 20% 20% 10% 10% 1206 16V 16V 16V 16V 16V 16V 16V 2 X5R ALUM ALUM ALUM ALUM 2 EMPTY 2 EMPTY 1206 RDL RDL RDL RDL 1206 1206

1 DB8P1 V_GPUCORE V_CPUCORE 1 DB8P2

1 FT7T9 1 FT5R2 N:CPU OUTPUT FILTER FTP FTP N:GPU OUTPUT FILTER

1 C8C2 1 C8E3 1 C8E1 1 C8F1 1 C8E2 1 C8D1 1 C8C1 1 C8D4 1 C7C2 1 C7C1 1 C6C3 1 C7C3 1 C6C2 1 C6C1 1 C5C8 1 C5C9 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 820UF 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 2.5V 2.5V EMPTY ALUM ALUM ALUM ALUM ALUM EMPTY ALUM ALUM ALUM ALUM ALUM ALUM ALUM EMPTY EMPTY 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 RDL 2 8X8 2 8X8 1 FTP FT7U4

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3188 3190A

R8G1 STUFF EMPTY V_VREG_CPU R8V10 EMPTY STUFF V_5P0 C8U4 EMPTY STUFF IN

1 R8G1 2 1 R8U5 10 1%603 50 CH 1K 1% CH V_VREG_CPU 402 2 R8V10 1 2 IN VREG_CPU_VCC 10 1% VREG_CPU_EN 805 EMPTY VREG_CPU_RAMPADJ_R 34 IN 50 C8V15 1 C8G5 100UF 1 1UF 10% 20% 1 1 16V 16V FT2P17 FTP R8F7 1 X7R ELEC R8U3 C8U4 10K 603 2 RDL 5% 294K .1UF 1% 10% 1 CH 6.3V FT2P16FTP 402 CH 2 X5R 2 402 402 2 VREG_CPU_PWRGD 34 OUT U8U1 IC VREG_CPU_PHASE3 R8V6 IN ADP3190A 0 5% 28 VCC 52 603 EMPTY PWRGD R8V7 RAMPADJ VREG_CPU_VID<5..0> VREG_CPU_PHASE2 VID5 6 5 IN 11 1 50 52 IN 0 5% EN VID4 10 4 CH VREG_CPU_RAMPADJ 14 20 VID3 2 3 DB8U4 603 1 VREG_CPU_SW4 SW4 VID2 3 VREG_CPU_PHASE1 R8V9 TP 2 VREG_CPU_PHASE3_R 21 4 1 IN SW3 VID1 1 R8F8 2 52 VREG_CPU_PHASE2_R 5 0 5% 22 SW2 VID0 0 0 5% 603 CH VREG_CPU_PHASE1_R 23 SW1 402 CH PWM4 VREG_CPU_DELAY24 VREG_CPU_CSCOMP 25 RT8F1 CSCOMP PWM3 VREG_CPU_PWM3 52 1 2 26 VREG_CPU_PWM2 OUT 18 PWM2 OUT 52 PWM1 27 VREG_CPU_PWM1 52 17 CSSUM OUT THRMSTR FTP 1 NA FT8U1 15 100K 603 ILIMIT VREG_CPU_DRV_EN 52 TEMP SENSOR 16 CSREF OUT 8 DELAY 12 2 2 2 FB VREG_CPU_RT 2 R8V1 R8V2 R8V4 1 2 9 13 2 R8V3 RT 19 R8U4 47.5K 47.5K 47.5K COMP 1 2 1% 1% 1% 35.7K 1% C8U1 R8U1 240K C8U2 VREG_CPU_CSCOMP_R 7 GND .047UF 324K 1000PF EMPTY CH CH 603 CH FBRTN 2 5% 10% 1% 10% 603 603 603 2 16V 603 50V 1 1 1 R8U2 2 CH CH 1 1 1 X7R EMPTY R8V5 C8V1 C8U3 X806818-001 422K 603 402 1 402 76.8K 360PF 8200PF 1% 1 1% 10% 10% CH 50V 16V ST7T1 CH 2 2 402 NPO CH VREG_CPU_FBRTN 2 1 603 603 603 1 1 SHORT

2 C8U10 V_CPUCORE 1000PF N: TARGET FSW=233KHZ 10% 50V VREG_CPU_CSSUM FTP 1 X7R LAYOUT:ATTACH TO 402 CLOSEST INDUCTORVREG_CPU_CSREF FT8U2 1

ST8F1 1 R8G3 2 1 2 VREG_CPU_CSREF_R 10 1% SHORT 402 CH 2 C8G1 1000PF 10% 50V 1 X7R 402

R8U13 ST7T2 C8U7 1 2 2 1 1 VREG_V_CPUCORE_S 2 5% 0 SHORT EMPTY 402 10% 0.1UF VREG_CPU_FB C8U8 25V 2 22PF EMPTY 603 5% 50V NPO 1 402 C8U6 1 2 1 2 R8U10 1 2 VREG_CPU_COMP_R R8U11 VREG_CPU_COMP 1% 1.33K 24.3K 1% 330PF 5% CH CH 603 50V 402 X7R 402

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V_VREG_CPU

50 IN D9C1 1N4148 3 VREG_CPU3_VCC 3 VREG_CPU_BST3 C9P3 1 R9P2 2 1 2 Q9D2 Q9D1 V_VREG_CPU 1 3 50 1 1 2.2 1% NTD60N02R C9D3 C9D1 D VREG_CPU_PHASE3 805 EMPTY SOT23 0.01UF 10% DPAK NTD60N02R 4.7UF 4.7UF IN EMPTY 50V 10% 10% 1 EMPTY DPAK 16V 16V C9P4 805 1 2 2 1.0UF 1 X5R EMPTY V_CPUCORE 10% C9P2 G S EMPTY 1206 1206 1 R9P1 2 1 2 EMPTY 2 16V VREG_CPU_DRVH3 VREG_CPU_BST3_R 2 EMPTY 2 OUT 2.2 1% 805 EMPTY 0.015UF 5% 51 U9P1 805 EMPTY 16V VREG_CPU_DRV_EN EMPTY MOS DRIVER 805 L8D1 4 VCC BST 1 VREG_CPU_PWM3 2 8 2 1 IN IN DRVH 3 7 51 IN OD_N* SW 5 EMPTY 0.6UH 6 PGND DRVL 1 TH 30A NA R9C1 X801233-001 3 3 2.2 Q9C1 Q8C1 1%

NTD85N02R D EMPTY805 NTD85N02R 2 DPAK DPAK VREG_CPU_BG3 1 1 D G S 51 EMPTY EMPTY VREG_CPU_SW3_R 2 2 G S 1 C9C5 4700PF 10% D9E1 50V 2 EMPTY 1N4148 603 VREG_CPU_BST2 C9T2 1 2 1 R9T2 1 3 2 3 3

1% Q9E1 Q9D4 1 1 805 CH SOT23 0.01UF 10% C9D4 C9E1 2.2 DIO 50V 1 X7R 4.7UF 4.7UF C9T3 805 NTD60N02R NTD60N02R 10% 10% 1.0UF VREG_CPU2_VCC DPAK DPAK 16V 16V C9T1 1 1 2 EMPTY 2 X5R VREG_CPU_PHASE2 10% 1 R9T1 2 1 16V 2 1206 1206 2 X7R FET EMPTY 1% OUT 805 0.015UF 5% 2 D 2 U9T1 IC 2.2 CH 16V 805 X7R MOS DRIVER 805 VREG_CPU_PWM2 L8E1 4 VCC BST 1 VREG_CPU_BST2_R G S 2 IN DRVH VREG_CPU_DRVH28 2 1 3 7 D OD_N* SW 5 IND 0.6UH 51 6 PGND DRVL 1 TH 30A R9E1 NA S 3 G 3 2.2 X801233-001 1% 51 D Q9E3 Q9D3 EMPTY IN NTD85N02R 805 NTD85N02R 2 S DPAK DPAK VREG_CPU_BG2 G 1 1 FET FET VREG_CPU_SW2_R 2 2

1 C9E4 4700PF 10% D9F1 D D 50V 2.2 1N4148 2 EMPTY C9U2 603 1 R9U2 2 1 2 1 3 3 3 1% 0.01UF 10% G S Q9F1 Q9F4 G S 805 CH SOT23 1 1 1 DIO 50V C9F4 C9F1 C9U3 X7R D 4.7UF 1.0UF 805 NTD60N02R NTD60N02R 4.7UF10% 10% 10% C9U1 1 R9U1 2 1 2 DPAK DPAK 16V 16V 16V 1 1 2 X5R 2 EMPTY 2 X7R 1206 1206 VREG_CPU_PHASE1 805 2.2 1% 0.015UF 5% FET G S EMPTY OUT 805 CH 16V 2 2 51 U9U1 IC X7R D VREG_CPU_BST1 MOS DRIVER 805 VREG_CPU1_VCC L8F1 4 VCC BST 1 VREG_CPU_PWM1 2 8 S 2 1 51 IN IN DRVH G 3 7 OD_N* SW 5 IND 0.6UH 6 PGND DRVL 1 TH 30A VREG_CPU_DRVH1 NA VREG_CPU_BST1_R R9F1 X801233-001 3 3 2.2 Q9F2 Q8F1 1% EMPTY D D 805 NTD85N02R NTD85N02R 2 DPAK DPAK VREG_CPU_BG1 1 1 VREG_CPU_SW1_R G S FET FET G S 2 2 1 C9F3 4700PF 10% 50V 2 EMPTY 603

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V_GPUCORE GPU MEM VID VOLTAGE V_VREG_GPU V_VREG_GPU 50 IN <4.5 ANY VID 0=10000 1.150V 50 IN 4.5-6.0 SEC VID-1=10001 1.125V 1 4.5-6.0 IFX VID 0=10000 1.150V 62 YR1 VREG_GPU_VID4 R8N7 4.5-6.0 HYNIX VID 0=10000 1.150V 1 R8B1 2 ST5R2 D8B3 1 2 2.2 6.0-7.0 ANY VID-1=10001 1.125V 1% 0 5% VREG_GPU_PHASE1_C VREG_GPU_PHASE1 SHORT 1 7.0-8.0 ANY VID ?=01110 1.XXXV 62 402 EMPTY 1 1 1 FT8P2 FTP CH VREG_GPU_VID2 805 OUT D8B2 C8B3 YR2 1 R8B7 2 2 1 R8C9 1 2 B13 ANY VID 0=10000 1.150V VREG_GPU_VID3 1N4148 3 0 FT8P1 FTP SOT23 OUT YR3 0 5% 54 53 5% 3 10% 62 GUNGA ANY VID 0=10000 1.150V CH 2 0.1UF EMPTY 402 25V OUT OUT 62 BAV99 X7R 402 VREG_GPU_VID1 1 R8B8 2 VREG_GPU_NPNCDIO 603 2 SOT23S 1 1 DIO C8N3 C8B9 0 CH5% RT7C1 1.0UF 1.0UF 402 10% 10% OUT 62 2 1 2 R8P9 1 U8N1 IC VREG_GPU_VFB_R 16V 16V 1 R8B9 2 2 X7R 2 X7R 1.21K 1% NCP5331 NA THRMSTR 2 R8P4 1 805 805 1 CH 16 VCCL2 VREG_GPU_VID0 0 5% 2 10K 603 402 25 VCCL1 62 402 CH C9B30.1UF 5.11K 1% VID4 15 OUT OUT R8N2 14 62 402 CH VID3 1 2 10% 26 R8B10 5% VREG_GPU_VCCL VCCL 13 25V 53 VID2 1 X7R 2 R8P7 1 12 CH C8P2 VID1 0 5% 603 2 1 402 CH 805 VREG_GPU_5VREF 30 5VSB 11 1.1K 1% IN VID0 2 402 CH 1000PF 10% 20 50V 7 VFFB VCCH EMPTY VREG_GPU_VFFB 402 1 1 VFB ILIM 31 1 VREG_GPU_COMP_R C8N1 D8B1 C8P1 VREG_GPU_VFB VREG_GPU_VCCH 53 0.1UF 1 2 R8P3 1 MMSZ18 2 2 5VREF 8 VREG_GPU_5VREF 10% VDRP OUT 25V SOD123 4.02K 1% VREG_GPU_VDRP VREG_GPU_ILIM 2 X7R 2 DIO 6800PF 10% CH 50V 402 VREG_GPU_COMP 32 COMP CBOUT 21 X7R 603 603 VREG_GPU_SEN10 NSEN PGD 29

VREG_GPU_COMP_C 1 R8P1 2 VREG_GPU_CS2 CS2 GH2 19 6 17 7.5K 1% CS1 GL2 VREG_GPU_CS1 4 2 603 CH C8N5 5 1 R8B4 2 C9P1 2 1 GH1 22 .047UF CSREF 24 10% VREG_GPU_CSREF GL1 7.5K 1% 16V 6800PF 10% 9 603 CH 1 ROSC 2 X7R 50V LGND 3 3 603 X7R 2 V_5P0STBY Q8B3 603 2 VREG_GPU_CPGD 28 C9C2 R8C1 FET CPGD 0.1UF 6.19K 1 VREG_GPU_ROSC GND2 18 ST5R1 R8C7 27 23 10% 1% 35.7K GND1 25V 2N70022 SOT23 1 2 1 CH 1% COVC X7R 603 402 CH 1 SHORT 1 54 603 C8N4 X800631-001 1 0.01UF 1 10% 16V R5N1 VREG_GPU_PHASE2 2 X7R 10K 2 R8P5 1 IN 402 5% V_GPUCORE 7.5K 1% CH

603 CH 402 VREG_GPU_EN_N_R 1 C8P3 2 0.1UF 10% 1 R9B1 2 25V 34 VREG_GPU_EN_N FTP 54 53 2 X7R IN 603 1 10K 5% FT2P6 402 CH

CH VREG_GPU_PHASE1 2 R8P6 1 IN 7.5K 1% 34 603 V_GPUCORE FTP 54 1 VREG_GPU_PWRGD C8P4 0.1UF 1 OUT 10% FT2P3 54 25V 2 X7R 603 VREG_GPU_GH2_R 1 R8N5 2 VREG_GPU_GH2 54 0 1A OUT 805 CH 1 R8N6 2 VREG_GPU_GL2 54 OUT ST8C1 0 1A 2 R8B2 1 1 2 805 CH 2K 1% VREG_GPU_GH1_R 1 R8N3 2 VREG_GPU_GH1 SHORT 402 CH 2 OUT 0 1A 2 R8B3 VREG_GPU_GL2_R 805 CH C8B8 1 R8N4 2 VREG_GPU_GL1 0.1UF VREG_GPU_CSREF_R 750K OUT 10% C8B7 1% 0 1A 25V 1 2 1 X7R CH 805 CH 603 603 470PF 5% 1 50V X7R 402 VREG_GPU_GL1_R

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V_VREG_GPU

IN 50

3 C6B2 4.7UF Q6B1 10% 16V D X5R NTD60N02R 1206 DPAK V_GPUCORE 53 VREG_GPU_GH2 1 S VREG_GPU_PHASE2 G FET OUT 53 2 L6C1 2 1

IND 0.6UH 1 TH 30A 3 3 NA Q6B2 Q6C1 R6C2 2.2 IN 1% NTD85N02R NTD85N02R 53 CH DPAK DPAK 805 VREG_GPU_GL2 1 1 2 FET FET 2 2

IN D D VREG_GPU_PH2_R

G S G S 2 C5C6 3 C7B2 4700PF 10% Q7B1 4.7UF 50V 10% 1 53 16V X7R X5R 603 NTD60N02R 1206 VREG_GPU_GH1 1 DPAK FET 2 D IN L7C1 2 1 G S 53 IND 0.6UH 1 TH 30A OUT 3 3 NA 53 Q7B2 Q7C1 R7B6 2.2 D NTD85N02R D 1% VREG_GPU_PHASE1 NTD85N02R CH DPAK DPAK 805 1 1 IN 2 G S FET FET G S VREG_GPU_GL1 2 2 VREG_GPU_PH1_R

2 C8B6 10% 4700PF50V 1 X7R 603

V_5P0 V_1P8 U2T1 IC NCP1117 1 R2E7 2 V_V3P3TOV1P8 3 2 1 IN OUT FTP FT2R8 10 5% V_1P8 V_MEM 1210 CH 1 ADJUST/GND 1 1 C2T5 C2R4 1 C2D6 1 R2E6 2 0.1UF 0.1UF 100UF 10% X800500-001 10% 20% 1 R2T8 2 10 5% 25V DPAK 25V 16V 2 2 ELEC 0 1210 X7R 1.8V X7R 2 1A CH 603 603 RDL 805 EMPTY

1 R1E3 2 1 R2T7 2 10 5% 1210 CH 0 1A 805 EMPTY

1 R1E1 2

10 5% 1210 CH

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V_12P0

L7F1 1 2 V_VREG_V1P8V5P0 OUT 32 1.6UH NA 10A TH

1 C6F3 C6U2 D3V1 1500UF 1UF 20% 1 C7F1 C3V6 10% 1 1500UF 16V 16V 1 0.1UF 1UF ALUM C4V7 20% 10% 2 X7R 16V 16V RDL 603 3 ADI_VREG 55 OUT 10% 2 ALUM X7R 25V RDL 603 V_5P0 2 2 X7R 603 BAT54A SOT23S V_MEM 1 DIO C4V15 C4V8 3 3 470NF 1UF 1 1 C3V7 DB6G1 Q6F1 10% 10% Q3F1 10V 16V 470NF FET 2 10% 1 17 1 X7R X7R 28 10V DB3F1 FTP FT6V1 NTD60N02R 603 603 U4V1 IC 2 X7R NTD60N02R 603

PV DPAK DPAK IN 1 LDOSDVREG_V1P8_DL1 1 FT2U1 FTP 1 VREG_V5P0_BST2 29 VREG FET ST6F1 VREG_V5P0_DH2 11 BST2 BST1 23 VREG_V1P8_BST127 2 1 2 2 ADP1823 ST2F1 VREG_V5P0_SW2 DH2 DH1 22 VREG_V1P8_DH1 2 1 ST6F2 12 ST2F2 SHORT D D 1 2 13SW2 SW1 VREG_V1P8_SW1 21 1 2 VREG_V1P8_SW1_S 1 VREG_V5P0_SW2_S VREG_V5P0_CSL2 SHORT 1 R4V7 2 1 R3V1 2 14 CSL2 CSL1 20 1 R4V11 SHORT VREG_V1P8_CSL1 SHORT 0 7.5K 1% 7.5K G S S G VREG_V5P0_DL2 16DL2 DL1 18 1% R4G9 5% 402 CH 402 CH ST5V1 0 EMPTY 15PGND2 PGND1 19 5% 1 2 VREG_V1P8_CSL1_R 402 ST3G1 EMPTY 2 L6F1 7 COMP2 COMP1 32 VREG_V5P0_CSL2_R 1 2 402 1 2 2 SHORT 9 SS2 SS1 30 L3F1 4 1.7UH13.8A TH SHORT 1 2 5 UV2 1.7UH 4 6 FB2 FB1 1 13.8A TH C6U1 1 C7F3 3 831 VREG_V_MEM_S_0 1UF 820UF 3 10% Q6F2 TRK2 TRK1 16V 20% 6.3V FET 26EN2 EN1 25 Q2F3 1 C2F1 1 C2F3 1 C3F6 C3U5 ALUM D 2 820UF 820UF 820UF X7R 2 NTD60N02R 10 POK1 24 1UF 603 RDL POK2 20% 20% 20% 10% D DPAK 3 FREQ 4V 4V 4V 16V NTD60N02R EMPTY POLY POLY 1 SYNC DPAK 2 2 2 X7R VREG_V1P8_COMP1 RDL RDL RDL 603 1 S G 1

VREG_V5P0_COMP2 GND GNDSLUG G S 1 2 FET R4V9 VREG_V5P0_FB2_R LCC32 X807026-001 357 2 R4G1 4 464

1% 33 1% CH 1 402 1% VREG_V1P8_COMP1_R CH 2 CH 402 R4G6 2 1 VREG_V5P0_SS2 ADI_FREQ 1.91K C4V12 1 R4V3 2 VREG_V1P8_SS1 C4V11 1 2 ADI_VREG 1 2 1% R4V6 1 2 VREG_V5P0_COMP2_R R4V4 IN R4V1 1 2 34 1.82K 10K 5% 55 CH VREG_V1P8_FB1_C 7.5K 18.2K 1% 820PF 10% 1% 402 CH 330PF 5% 402 1 1 50V 402 CH 402 50V 2 C4G1 C4V1 CH 1 R4V2 2 2700PF VREG_V5P0_FB2_C X7R X7R 3300PF 402 10% 10% 402 C4V13 C4V10 402 2 1 2 10K 5% .1UF 1 2 50V 50V 2 2 402 EMPTY 1 X7R X7R 1 C4V9 402 402 220PF 5% C4V14 82PF50V5% VREG_V1P8_FB1 50V .1UF FREQ PIN 3: 10% 402 NPO 10% 0 300KHZ 6.3V 402NPO 402 6.3V 2 X5R VREG_V5P0_FB2 2 X5R 1 600KHZ 34 402 OUT 62 1 OUT VREG_V5P0_VMEM_PWRGD 1 R4V5 243 R4G7 75 1% VREG_V1P8_EN 1% 402 CH ADI_VREG 1 R4V10 2 34 55 IN CH 2 10K 5% 1 402 FTP FT2P19 2 402 CH IN 1 V_MEM R4G6 R4G7 R4G8 R3V3 1.9V 1.91K 75 806 VREG_V1P8_FB1_R 1K 1.95V 1.91K 43.2 806 1 5% 2.0V 1.91K 267 549 CH 1 R3V5 2 2.1V 1.91K 301 464 R4G8 VREG_V5P0_EN VREG_V5P0_EN_R 402 806 IN 2 47K 5% 1% FTP 1 FT2P18 1 402 CH CH THESE ARE THE VOLTAGES NEEDED 402 R3V4 2 1 FOR VARIOUS MEMORIES. CONSULT 1K C3V8 WITH MEM TEAM FOR USAGE. 5% .22UF CH 10% 6.3V 402 2 X5R 2 402

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EMPTY U6T2 V_3P3 V_5P0 V_5P0 LP2980 V_5P0 1 VIN VOUT 5 1 FT1U1 U1F1 IC 3 GND ENABLE 2 1 1 1 NCP5662 1 C1F5 1 C1F3 0.1UF 100UF VREG_EFUSE_EN_C2 NC 4 34 VREG_3P3_EN 2 IN TAB 6 FTP R7T10 R6T3 IN VREG_3P3_EN_R R1U1 10% 1.27K 25V 20% 16V 10K 10K X803461-001 2.9V 4 2 ELEC 5% 5% C7T100 1% X7R 2 1 3 603 RDL CH CH 1UF V_EFUSE C1U11.0UF GND OUT 10% EMPTY 402 402 16V 402 2 2 1 10% 2 X7R 16V 1 EN ADJ 5 603 2 VREG_V3P3_ADJ R1F7 X7R U6T1 IC 1K 805 1 5% NCP502D X807964-001 R1U2 CH 475 1 VIN 5 1 402 1% VOUT FT7T6 2 EMPTY FTP 3 ENABLE GND 1 R1F8 2 402 2 2 C7T98 C7T99 1K 5% VREG_EFUSE_EN_C1 NC 4 1UF 1UF 402 CH 10% 10% CR6T1 16V 16V TYPE PART # R1U1 R1U2 MBT3904 3 6 X810988-001 2.9V X7R EMPTY V_5P0STBY V_3P3STBY FIXED X807964-001 EMPTY EMPTY VREG_EFUSE_EN_R 603 603 2 SC70 U5B1 IC ADJ X807089-001 1.27K 475 5 NCP1117 4 3 IN OUT 2 1 2 R6T4 1 THIS IS ACTUALLY A 3.3V PART 4 FT5N1 VREG_EFUSE_EN XSTR IN 1 NCP612 FAMILY. NEED TO MAKE NEW SYMBOL 5% 1 ADJUST/GND 1K FTP 402 CH 1 1 1 C5B1 1 C5B2 FT7T8 C5B3 0.1UF 100UF FTP 2 V_3P3 1.0UF X800499-001 10% 20% 10% DPAK 25V 16V R6T1 16V 2 X7R ELEC 10K 1 R4P14 2 2 2 1 2 X7R 3.3V 603 RDL 5% R4C31 805 0 5% CH 0 5% 603 EMPTY V_GPUPCIE 402 603 CH 1 V_GPUCORE U5C1 IC V_5P0 V_5P0STBY NCP1117 N: TARGET IS 1.25V 1 R4P13 2 VREG_GPUPCIE_IN 3 IN OUT 1 2 FT5R1 0 5% 603 EMPTY 1 ADJUST/GND OUT/TAB 4 1 1 FTP

1 R5P2 R5C9 2 2 C4C6 D5N1 D5B1 VREG_1P8STBY_D2R5B1 = EMPTY X800501-001 1K 1 1.0UF 1% 1% DIO DIO IFR5B2 USING = 0 U5B2 OHM AS A FIXED - SET TO 1.8V 10% SOT223 SOD123 SMA 16V CH CH 2 X7R 1.2V 0402 1 MBR130L 1 S1A 402 805 VREG_1P8STBY_D1 IF USING U5B2 AS AN ADJUSTABLE - SET TO 1.816V 2 2 2 2 D5N2 R5B1 = 549 OHM VREG_PCIEX_ADJUST DIO R5B3 R5B2 = 221 OHM SOD123 1 1 5% GPU R4P13 R4C31 R4P14 U5C1 1 MBR130L CH 1 R5P1 1206 C5P1 0 .1UF 5% 1 V_1P8STBY B13L EMPTY STUFF EMPTY STUFF 10% U5B2 IC GUNGA STUFF EMPTY STUFF EMPTY 6.3V CH VREG_PCIEX_R 2 X5R 402 PLACEHOLDERS 402 NCP1117 2 1 3 IN OUT 2 1 C5C5 FT5N2 4.7UF VREG_1P8STBY_IN FTP 10% 1 ADJUST/GND 6.3V 1 1 2 C5N3 1 X5R 1 C5B4 V_3P3 1.0UF R5B1 C5B6 805 10% 0.1UF 100UF 1 R6C1 2 X800500-001 549 10% 20% 16V 16V 2 X7R DPAK 1% 25V 1 R5C6 2 0 2 X7R ELEC 1A 805 1.8V EMPTY 2 RDL 805 CH 402 603 0 1A V_CPUPLL VREG_1P8STBY_ADJ 2 805 EMPTY V_1P8 U6R1 EMPTY 1 R5B2 2 N: TARGET IS 2.20V NCP1117 FTP 1 VREG_CPUPLL_IN R5C4 2 1 0 5% 3 IN OUT V_3P3 2 FT7R3 402 CH V_SBPCIE 0 1A 805 CH 1 OUT/TAB 4 1 1 U3P1 EMPTY ADJUST/GND 1 R6R3 R6R1 FTP NCP1117 C6P1 1 1.0UF X800501-001 499 3 IN OUT 1 X7R 1% 1% 2 FT2P26 10% SOT223 16V EMPTY CH 2 1.8V 1 ADJUST/GND OUT/TAB 4 1 1 402 0402 805 2 2 1 R3C22 R3C21 VREG_CPUPLL_ADJUST C2C5 X800501-001 549 1 1.0UF 1% 1% 10% SOT223 16V EMPTY EMPTY 2 X7R 1.2V 402 0402 805 2 2 1

1 VREG_VDD_PEX_ADJ C6R1 R6R2 .1UF 374 VREG_CPUPLL_R 1 10% 1% 6.3V 2 EMPTY 1 1 R2C3 EMPTY C7P1 V_SBPCIE R3C22 C2C6 243 402 402 2 4.7UF .1UF 1% 10% 1.87V 499 10% 6.3V EMPTY 2 2 6.3V VREG_VDD_PEX_R X5R 1.80V 549 EMPTY 402 805 402 2 1 C3C1 4.7UF 10% 6.3V 2 EMPTY DRAWING 805 FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:19 2007 FALCON_RETAIL 56/82 1.0 [PAGE_TITLE=[VREGS, LINEAR VREGS] CONFIDENTIAL CR-57 : @FALCON_LIB.FALCON(SCH_1):PAGE57

VCS REGULATOR V_5P0

R7G23 0 805 1A 2 1 V_VREG_VCS CH CPU_SRVID L7G1 DB8U1 1 1 2 TP V_12P0 1.6UH EMPTY 4 IN 2 2 2 2 2 TH C8G4 C7G3 C7G4 1 C7G7 C7V2 C7G5 10A 1 VREG_VCS_VREF 1500UF C7F5 1 4.7UF 4.7UF 4.7UF 0.1UF 0.1UF NA V_CPUCORE 10% 10% 20% 10% 10% 4.7UF 16V 10%16V 16V 16V 25V 25V 10% R7T19 DB8U2 C7U9 C8F2 1 1 1 EMPTY 1 1 16V TP 1 X5R X5R X5R 2 X7R X7R 2 0 1UF 1UF 1206 1206 1206 RDL 603 603 X5R 5% 10% 10% 1206 16V 16V EMPTY 1 2 X7R X7R 402 1 603 603 2 R8U8 R8U9 0 0 R8U7 5% 5% 0 5% V_12P0 EMPTY CH EMPTY V_CPUVCS 402 402 IRF8915PBF 10 2 1 402 4 U7F1 2 U7U2 IC FET 3 2

NC0 VC R7F9 VREG_VCS_VP GATE0 1 2 VP VCC DRN0 FTP FT7U3 10K HDRV VREG_VCS_HDRV 5 L8F2 5% DB7U2 9 43 SRC0 DRN0 6 1 VREG_VCS_SS_SD_N 13 SS IR3638 VREG_VCS_VOUT_L 2 1 V_CPUCORE EMPTY TP 6 VREG_VCS_LDRV 1.7UH 11 LDRV IND 402 3 VREG_VCS_RT NC2 1 2 DB8F4 TH 13.8A Q7F1 C7U5 C7U6 1 2 GATE1 DRN1 7 1 EMPTY 4.7NF .1UF TP 12 COMP PGND 8 8 4 VREG_VCS_LTO DRN1 1 2N7002 10% 10% 1 SRC1 2 2 1 1 C7F4 16V 6.3V FB NC C7T103 C7T102 SOT23 GND NC1 2 2 1 X5R 2 SSOP 820UF 4.7UF 4.7UF X7R 402 1 R7U6 20% 603 C8U9 X811812-001 SO-8 10% 10% .1UF 0 X807111-001 6.3V 6.3V 6.3V 7 3 5 ALUM 1 X5R 1 X5R 10% 402 14 2 RDL 1 2 805 805 R7U4 Q7U1 6.3V 1 1 2 X5R EMPTY MMBT2222 402 1K 5% VREG_VCS_CPUCORE_R EMPTY 5% CR7V2 402 EMPTY 2

1 MBR0520L

VREG_VCS_NC 2 SOD123 EMPTY

1 DB7U1 R7U6 SWITCH FREQ

STUFF 400KHZ 1 DB8U3 EMPTY 200KHZ VREG_VCS_NC1 R8U14 ST7D2 1 R7U7 2 1 2 C7U8 2 1 1 R7U5 2 VREG_VCS_COMP_C 1 2 10K 1% 0 5% 15K 1% 3300PF 10% 402 CH 402 EMPTY SHORT 402 EMPTY 50V EMPTY VREG_VCS_FB VREG_VCS_FB_R VREG_VCS_COMP 402 C8U5 1 R8U6 2 1 2 C7U7 C7U11 VREG_VCS_FB_COMP 1 2 1 2 2.67K 1% 10% 402 EMPTY 2700PF50V 47PF 5% 220PF 5% EMPTY EMPTY50V 50V 402 NPO 402 402

1 1 R7U8 R8U12 4.02K 1% 33.2K GAIN=20% WITH R7U7=10K, R8U12=49.9K 1% OUTPUT = CPU_SRVID(1+GAIN) CH 402 CH 2 402 2 VREG_VCS_COMP_R

1 C7U10 0.01UF 10% 16V 2 X7R 402

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:20 2007 FALCON_RETAIL 57/82 1.0 CONFIDENTIAL CR-58 : @FALCON_LIB.FALCON(SCH_1):PAGE58

XDK, DEBUG CONNECTORS

J1D2 2X5HDR_10 V_5P0STBY SPI_SS_N 2 1 35 SPI_MOSI 35 OUT OUT KER_DBG_RXD 33 SPI_MISO 3 SPI_CLK OUT 35 IN 4 OUT 35 65 8 7 SMC_DBG_RXD_R 9 OUT 60

HDR C1D7

10% 1 R2P18 2 6.3V SMC_RST_N 27 X5R .1UF 402 100 5% CH 402 V_5P0STBY V_3P3STBYIN J9A2 1X2HDR 1 2 C2B12 C2B15 10% .1UF 1UF SM C9A3 10% HDR 6.3V 16V .1UF X5R X7R 10% 402 603 6.3V

J2B1 SMC_RST_XDK_N X5R V_3P3 2X7HDR_14 402 KER_DBG_TXD 2 1 33 IN SMC_DBG_TXD 34 4 3 34 IN SMC_DBG_EN OUT 65 8 7 34 10 9 1 R2N14 2 SMB_DATA SMB_CLK_R SMB_DATA_R BI 27 34 12 11 100 5% 1 C1R2 13 402 CH .1UF 10% HDR 1 R3B3 2 6.3V EXT_PWR_ON_DBG EXT_PWR_ON_N OUT 44 58 34 2 X5R SMB_CLK 1 R2N13 2 402 27 BI 1K 100 5% 402 CH5% 402 CH V_5P0STBY V_12P0

1 D8B4 C3B8 C3B9 GREEN .1UF 1UF SM 10% 10% 6.3V 16V 2 LED 2 402X5R X7R 603 1 CPU_CHECKSTOP_N_LED R8B6 2K 1% CH 402 2 CPU_CHECKSTOP_N_LED_B CPU_CHECKSTOP_N_LED_C

3 1 R8A5 2 Q8B6 1 MMBT2222 SM 1K 5% XSTR PCIEX DEBUG CONNECTOR 402 CH 2 V_3P3STBY N: DEBUG BOARDS ONLY 13 33 I225 13 2 33 V_1P8 R2P19 33 J3C1 EMPTY 13 V_1P8 10K 33 5% PCIEX CH MIDBUS 402 2 1 PEX_GPU_SB_L0_DP 2 2 2 2 2 1 PEX_SB_GPU_L0_DP 3 PEX_GPU_SB_L0_DN IN 4 R8C3 R8C4 R8C5 R8C6 1 SMC_CPU_CHKSTOP_DETECT IN PEX_SB_GPU_L0_DN 65 IN C8P5 R8P8 34 10K 10K 10K 10K BI IN 7 PEX_GPU_SB_L1_DP 5% 5% 5% 5% .1UF 10K 8 IN 13 10% 5% SMC_CPU_CHKSTOP_DETECT_B PEX_SB_GPU_L1_DP 10 9 PEX_GPU_SB_L1_DN IN EMPTY EMPTY EMPTY EMPTY 6.3V 3 IN 2 11 402 402 402 402 X5R EMPTY PEX_SB_GPU_L1_DN 12 1 R3N8 2 IN 1 1 1 1 402 402 1 Q2P1 14 13 1 MMBT2222 1K 5% 16 15 EMPTY 402 EMPTY 2 18 17 J8C1 20 19 2X5HDR 22 21 2 R8C2 1 1 R8C8 2 4 CPU_RST_V1P1_N CPU_RST_N_2_R 2 1 CPU_CHECKSTOP_N 24 23 IN IN 59 3 1K 5% 4 CPU_CHECKSTOP_N_R 0 5% 402 402 CH 65 CH CPU_TMS 7 CPU_TCLK 59 OUT 8 OUT 59 59 CPU_TRST_N 10 9 EXT_PWR_ON_N 44 58 34 X801071-001 OUT OUT 59 IN CPU_TDO 59 CPU_TDI HDR N: FOOTPRINT PADS 13-24 REMOVED. OUT N: REMOVED PADS FREE UP NEEDED 1 1 C7D23 BOARD SPACE FOR ROUTING. FT7R7 FTP .1UF 10% 6.3V 2 X5R 402 DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:19 2007 FALCON_RETAIL 58/82 1.0 [PAGE_TITLE=XDK. DEBUG CONN] CONFIDENTIAL CR-59 : @FALCON_LIB.FALCON(SCH_1):PAGE59

V_GPUCORE DEBUG BOARD, CPU + GPUCPU_TCLK DEBUG BREAKOUT] 3OF10

7OF12 IC U7D1 IC U4D1 GPU Y2 VERSION 1 CPU_TRST_N LOKI CPU_TDO 58 TCLK TDO OUT 58 58 IN CPU_TDI AF5TDI CHECKSTOP_B AG1 AG5 CPU_CHECKSTOP_N 58 TBCLK1 IN OUT G30 58 CPU_TMS AH6TMS TBCLK0 F32 58 IN D23 CPU_DBG_CLK_DP IN AH2TRST_B DEBUG_CLKOUT_DP OUT AH5 DEBUG_CLKOUT_DN C23 CPU_DBG_CLK_DN OUT CPU_DBGSEL_XDK<0..69> OUT 47 DEBUG_OUT0 DEBUG_OUT1 F9 1 C8E8 0 N:CPU_DBGSEL_DEBUG<0..69> DEBUG_OUT2 N:CPU_DBGSEL_XDK<0..69> DEBUG_OUT3 D7 23 DEBUG_OUT4 B8 V_GPUCORE A8 DEBUG_OUT5 4 DEBUG_OUT6 F11 56 DEBUG_OUT7 D9 7 C9 DEBUG_OUT8 8 DEBUG_OUT9 9 A9 F1310 1 1 1 1 DEBUG_OUT10 C6T35 C7T90 C6T36 C7T91 E10 11 DEBUG_OUT11 .1UF .1UF .1UF .1UF C10 10% 10% 10% 10% DEBUG_OUT12 6.3V 6.3V 6.3V 6.3V B10 12 2 X5R 2 X5R 2 X5R 2 X5R DEBUG_OUT13 E12 13 402 402 402 402 TB15 DEBUG_OUT14 D11 14 D28 DEBUG_OUT15 15 TB14 A10 H29 DEBUG_OUT16 TB13 C11 17 E29 DEBUG_OUT17 16 TB12 H30 V_GPUCORE A11 18 DEBUG_OUT18 TB11 C30 C12 A30 DEBUG_OUT19 TB10 B30 F15 19 DEBUG_OUT20 20 TB9 B12 G31 DEBUG_OUT21 21 TB8 E14 B31 DEBUG_OUT22 22 TB7 D13 23 A31 DEBUG_OUT23 TB6 C13 24 TB5 B32 DEBUG_OUT24 A12 25 TB4 A32 DEBUG_OUT25 C14 26 27 F33 1 1 1 1 DEBUG_OUT26 D15 TB3 C6T31 28 E33 C6T12 C6T34 C7T92 DEBUG_OUT27 C15 TB2 .1UF6.3V .1UF .1UF .1UF TB1 D33 10% 10% 10% 10% DEBUG_OUT28 B14 29 E34 6.3V 6.3V 6.3V TB0 2 X5R 2 X5R 2 X5R 2 X5R DEBUG_OUT29 E16 30 402 402 402 402 DEBUG_OUT30 A13 31 DEBUG_OUT31 A14 32 X02125-001 DEBUG_OUT32 C16 33 DEBUG_OUT33 B16 34 DEBUG_OUT34 A15 35 DEBUG_OUT35 A16 36 37 DEBUG_OUT36 A17 38 DEBUG_OUT37 D17 39 DEBUG_OUT38 C17 DEBUG_OUT39 F17 40 DEBUG_OUT40 A18 41 42 DEBUG_OUT41 B18 43 DEBUG_OUT42 A19 44 DEBUG_OUT43 C18C21 45 DEBUG_OUT44 C19 46 D19 47 DEBUG_OUT45 48 DEBUG_OUT46 E18 C20 49 DEBUG_OUT47 50 DEBUG_OUT48 51 DEBUG_OUT49 E20 52 F19 53 DEBUG_OUT50 A20 54 DEBUG_OUT51 B26 55 DEBUG_OUT52 B20 56 57 DEBUG_OUT53 A21 DEBUG_OUT54 58 A22 59 DEBUG_OUT55 A26 60 DEBUG_OUT56 B22 61 DEBUG_OUT57 A24 62 DEBUG_OUT58 63 A27 64 DEBUG_OUT59 A23 65 DEBUG_OUT60 A28 66 DEBUG_OUT61 A25 DEBUG_OUT62 F21 DEBUG_OUT63 D21 DEBUG_OUT64 B24 DEBUG_OUT65 C22 67 DEBUG_OUT66 E22 68 DEBUG_OUT67 F23 69 DEBUG_OUT68 DEBUG_OUT69 X806937-001

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:19 2007 FALCON_RETAIL 59/82 1.0 CONFIDENTIAL

[PAGE_TITLE=DEBUG BOARD, CPU + GPU DEBUG BREAKOUT] CR-60 : @FALCON_LIB.FALCON(SCH_1):PAGE66

XDK DEBUG, LEDS

2 R6G36 1 V_MEM MEMPORT3_DN_ARGONYETI5% 0 MEMPORT3_DN_ARGON 60 EMPTY 402 49 BI MEMPORT3_DP_ARGONYETI MEMPORT3_DP_ARGON 2 60 BI 49

2 R6G35 1 R7F6 0 5% 0 5% EMPTY 402 CH 603 J7G3 1 BI 2X6HDR 2 R6V2 1 BI 1 2 V_YETI 5% 0 3 4 N: CONNECTED TO V_MEMPORT EMPTY 402 MEMPORT3_DN_YETI 5 6 FOR BETTER ROUTING IN MEMPORT3_DP_YETI 7 8 V_MEMPORT1 9 10 2 R6V1 1 11 12 5% 0 EMPTY 402 HDR 1 C7G9 2 C7G8 .1UF 4.7UF 46 10% 10% 6.3V 6.3V 2 EMPTY 1 1 2 EMPTY CPU_PWRGD R7V8 CPU_PWRGD_R IN 402 805 5% 1K CH 402

2 R2D14 1

5% 0 MEMPORT3_DN EMPTY 35 402 V_5P0 V_1P8 BI MEMPORT3_DN_ARGONYETI 60 V_3P3 MEMPORT3_DP MEMPORT3_DP_ARGONYETI BI 35 BI BI 60

2 R2D13 1 C2T9 1 2 5% 0 EMPTY 402 .1UF 10% 1 2 J1E2 C2T10 C1T6 6.3V .1UF 4.7UF EMPTY 1X5HDR 402 2 R2R8 1 10% 10% 6.3V 6.3V 1 2 EMPTY 1 EMPTY C2T8 5% 0 2 402 805 1 2 EMPTY 402 MEMPORT3_DN_FLASH 3 .1UF 10% MEMPORT3_DP_FLASH 4 6.3V 2 R2R7 1 5 EMPTY402 5% 0 EMPTY 402 EMPTY TH

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:20 2007 FALCON_RETAIL 66/82 1.0 [PAGE_TITLE=XDK, DEBUG LEDS, BDCM PHY] CONFIDENTIAL CR-61 : @FALCON_LIB.FALCON(SCH_1):PAGE67

INTELLIGENT SERIAL NUMBER TARGET. LB7G1 LABEL 1 1375X250_TARGET X801181-001

EAST PCB MOUNTING HOLES

MIDDLE PCB MOUNTING HOLES EDGE CTR EDGE MTG1B1 MTG5G1 MTG9G1 MTG_HOLE MTG_HOLE MTG_HOLE NC9 9 NC9 9 NC9 9 EMPTY GND=1,2,3,4,5,6,7,8EMPTY EMPTY GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8 EDGE CTR EDGE MTG1G1 MTG5B1 MTG9B1 MTG_HOLE MTG_HOLE MTG_HOLE NC9 9 NC9 9 NC9 9 EMPTY EMPTY EMPTY GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8

HEAT SINK MOUNTING HOLES STD STD MTG8C1 MTG6E1 MTG_HOLE MTG_HOLE NC9 9 NC9 9 EMPTY EMPTY GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8

STD STD MTG3C1 MTG3E1 MTG_HOLE MTG_HOLE NC9 9 NC9 9 EMPTY EMPTY GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8

STD STD MTG6C1 MTG8E1 MTG_HOLE MTG_HOLE NC9 9 NC9 9 EMPTY EMPTY GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8

STD STD MTG5C1 MTG5E1 MTG_HOLE MTG_HOLE NC9 9 NC9 9 EMPTY EMPTY GND=1,2,3,4,5,6,7,8 GND=1,2,3,4,5,6,7,8

DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV Tue May 08 18:24:20 2007 FALCON_RETAIL 67/82 1.0 [PAGE_TITLE=LABELS AND MOUNTING, PCI SWIZ] CONFIDENTIAL CR-62 : @FALCON_LIB.FALCON(SCH_1):PAGE68

GPU VID BOARD 60 OHM COUPONS (TOP & BOTTOM) EMPTY TP7M2 TDRX2 TDR_SINGLE_XDK2

1 SIG 2 GND

90 OHM COUPONS (TOP) EMPTY THESE CONNECTORS ARE EMPTY BY DEFAULT TP5A1 THEY ARE ONLY STUFFED WHEN VIPER IS REQUIRED TDRX4 TDR_DIFF_XDK3_DP

1 DP TDR_DIFF_XDK3_DN2 GND EMPTY 3 DN TP7M1 4 GND TDRX2

1 SIG 2 GND EMPTY J8B1 1X8HDR TP5A2 EMPTY TDRX4 53 VREG_GPU_VID4 1 IN TP8A2 53 VREG_GPU_VID3 2 IN TDRX2 1 DP 53 IN VREG_GPU_VID2 3 TDR_SINGLE_XDK1 2 GND 53 IN VREG_GPU_VID1 4 1 3 53 IN SIG DN VREG_GPU_VID0 5 2 4 6 GND GND 53 VREG_GPU_VFFB 7 IN 8

EMPTY TH EMPTY TP8A1 TDRX2

1 SIG 2 GND THIS IS ON THE MOTHERBOARD THE REST IS ON A SEPARATE BOARD ON THE FAN CUTOUT

100 OHM COUPONS (TOP & BOTTOM) TP7A1 EMPTY TDRX4 V_MEM TDR_DIFF_XDK2_DP 55 1 DP 2 GND J4G1 1X2HDR TDR_DIIFF_XDK2_DN3 DN J4F1 1X3HDR VREG_V1P8_FB1 1 4 GND OUT 1 2 50 OHM COUPONS (TOP) 2 TP6A2 EMPTY 3 TH TDRX2 EMPTY EMPTY TDR_SINGLE_XDK3 1 SIG TP7A2 EMPTY 2 GND TDRX4

1 DP 2 GND 3 DN 4 GND THESE ARE ON THE MOTHERBOARD

TP6A1 EMPTY TDRX2 TP8M1 EMPTY TDRX4 1 SIG 2 GND TDR_DIFF_XDK1_DP1 DP 2 GND TDR_DIFF_XDK1_DN3 DN 4 GND

TP8M2 EMPTY TDRX4

1 DP 2 GND 3 DN 4 GND

MICROSOFT PROJECT NAME PAGE REV FALCON_RETAIL 68/82 1.0 CONFIDENTIAL BLEEDER_B 47A4 CPU_SPI_WP_N 4A2 ENET_P4RD 39B3 BLEEDER_C1 47A4 CPU_SRVID 4B6 57D7 ENET_POAC_R 39C3 45B4 BLEEDER_C2 47A3 Title: Basenet Report CPU_SYS_CONFIG0 4C6 ENET_RDAC 40B3 BLEEDER_V12P0_B1 49A3 Design: falcon CPU_SYS_CONFIG1 4C6 ENET_REF_CLK2_OUT 40C5 BLEEDER_V12P0_B2 49B2 Date: May 8 12:04:43 2007 CPU_TCLK 58A1 59D5 ENET_REF_CLK_OUT 39C6 BLEEDER_V12P0_C1 49A3 CPU_TDI 58A5 59D5 ENET_RST_N 33A2 39C8 40C6 BLEEDER_V12P0_C2 49A2 Base nets and synonyms for CPU_TDO 59D1 58A5 ENET_RX_CT 45B4 falcon_lib.FALCON(@falcon_lib.falcon(sch_ BLEEDER_V12P0_LOAD 49A2 CPU_TEMP_N 4B2 28A8 ENET_RX_DN 39C1 40B3 45B4 1)) Location([Zone][dir]) BND_GAP_CAP 28B6 CPU_TEMP_P 28A1 4B2 ENET_RX_DN_R 39C2 Base Signal BRD_TEMP_N 28A5 28A8 CPU_TEST_EN 4B5 ENET_RX_DP 39D1 40B3 45B4 ADI_FREQ 55B5 BRD_TEMP_P 28A1 28A5 CPU_TMS 58A5 59D5 ENET_RX_DP_R 39D2 ADI_VREG 55D4 55A7 55B4 CAL_TEMP_N 28A1 28A8 CPU_TRST_N 58A5 59D5 ENET_TX_CT 45B4 ANA_CLK_OE 34B3 27C8 CAL_TEMP_P 28A3 CPU_VDDE 6C5 ENET_TX_DN 39A1 40B3 45B4 ANA_CLK_OE_R 27C7 CPU_ANL_1 4B6 CPU_VDDS0_DN 4C3 ENET_TX_DN_R 39B2 ANA_PIX_CLK_2X_DN 27B1 13C8 CPU_ANL_2 4B6 CPU_VDDS0_DP 4C3 ENET_TX_DP 39C1 40B3 45B4 ANA_PIX_CLK_2X_DN_R 27C4 CPU_CHECKSTOP_N 59D1 58A1 CPU_VDDS1_DN 4C3 ENET_TX_DP_R 39B2 ANA_PIX_CLK_2X_DP 27B1 13C8 CPU_CHECKSTOP_N_LED 58B2 CPU_VDDS1_DP 4C3 EN_TEST0_N 34A6 ANA_PIX_CLK_2X_DP_R 27C4 CPU_CHECKSTOP_N_LED_B 58B3 CPU_VGATE 4B5 EN_TEST1_N 34A6 ANA_RST_N 34C3 27D7 CPU_CHECKSTOP_N_LED_C 58B2 CPU_VREG_APS0 4B2 50C7 EXPPORT_DN 35B3 45C8 ANA_V12P0_PWRGD 27D3 34C3 49A5 CPU_CHECKSTOP_N_R 58A3 CPU_VREG_APS1 4B2 50D7 EXPPORT_DN_CM 45C5 ANA_VID_INT 28D3 33B2 CPU_CLK_DN 27D1 4D6 CPU_VREG_APS2 4B2 50D7 EXPPORT_DP 35B3 45C8 ANA_VRST_OK 27D3 34A8 CPU_CLK_DN_C 4D5 CPU_VREG_APS3 4B2 50D7 EXPPORT_DP_CM 45C5 ARGONPORT_DN 35C3 49C8 CPU_CLK_DN_R 27C4 CPU_VREG_APS4 4B2 50D7 EXT_PWR_ON_DBGEXT_PWR_ON_R 34C658C5 ARGONPORT_DP 35C3 49C8 CPU_CLK_DP 27D1 4D6 CPU_VREG_APS5 4B2 50D7 EXT_PWR_ON_NFAN1_FDBK 44C143C2 58A128B6 58C3 34D8 ARGON_CLK 34A1 49B7 CPU_CLK_DP_C 4D5 DBG_CPU_LINKTRAINED 47C5 FAN1_FDBK_R44A3 43C4 ARGON_DATA 34A1 49B7 CPU_CLK_DP_R 27C4 DBG_CPU_PLL_LOCK 47C5 FAN1_OUT 28B3 43D5 ARGON_DN_CM 49C6 CPU_CORE_IF_BGR_PLL 4D3 DBG_CPU_POST_OUT0 47C5 FAN1_Q1_C 43D4 ARGON_DP_CM 49C6 CPU_DBGSEL_DEBUG<0..69> 47D3 DBG_CPU_POST_OUT1 47C5 FAN1_Q1_E 43C4 ARGON_NTX 45B6 CPU_DBGSEL_XDK<0..69> 59D1 47D7 DBG_CPU_POST_OUT2 47C5 FAN_OP1_DP 28B7 AUD_ACAP 41C5 CPU_DBG_CLK_DN 59D1 DBG_CPU_POST_OUT3 47C5 FLSH_ALE 35C3 42B5 AUD_AC_L 41B5 CPU_DBG_CLK_DP 59D1 DBG_CPU_POST_OUT4 47C5 FLSH_CE_N 35C3 42B5 AUD_AC_R 41D5 CPU_EXT_CLK_EN 4C6 DBG_CPU_POST_OUT5 47C5 FLSH_CLE 35C3 42B5 AUD_CLAMP 34C6 41A6 CPU_FSB_CLK_SEL 4C6 DBG_CPU_POST_OUT6 47C5 FLSH_DATA<7..0> 35C6 42C8 AUD_CLAMP_B1 41A6 CPU_FSB_HF_CLKOUT_DN 4C2 DBG_CPU_POST_OUT7 47C5 FLSH_NC38 42C2 AUD_CLAMP_B2 41A4 CPU_FSB_HF_CLKOUT_DP 4C2 DBG_CPU_SECURE_SYS 47C5 FLSH_READY 42C1 35C7 AUD_CLAMP_B3 41A2 CPU_FSB_IMPED_CAL_DN 4C2 DBG_CPU_TST_CLK 47C5 FLSH_RE_N 35C3 42B5 AUD_CLAMP_C 41A5 CPU_FSB_IMPED_CAL_DP 4C2 DBG_LED0 34A8 34A6 FLSH_WE_N 35C3 42B5 AUD_CLAMP_L 41B3 CPU_PLL_BYPASS 4C6 DBG_LED0_LED 34A4 FLSH_WP_N 35C6 42B5 AUD_CLAMP_R 41D3 CPU_POST_IN<0..4> 4C6 DBG_LED0_LED_R 34A5 FSB_BYPCLK_DN 12D7 AUD_CLK 27A1 36C7 CPU_PSRO0_OUT 4C3 ECB_CLK_BYP 33D6 FSB_BYPCLK_DP 12D7 AUD_CLK_R 27B4 CPU_PULSE_LIMIT_BYPASS 4C6 ECB_CLK_SEL 33D6 FSB_BYPCLK_SEL 12D7 AUD_DCAP 41C7 CPU_PWRGD 34B3 4D8 60C5 EDRAM_TEMP_N 13C8 28A8 FSB_CLK_DN 4C6 AUD_L_OUT 41C1 44B4 CPU_PWRGD_R 60C4 EDRAM_TEMP_P 28A1 13C8 FSB_CLK_DP 4C6 AUD_RST_N 33B2 41C8 CPU_PWRGD_V1P1_N 4D7 EJECTSW_N 43C6 34B3 48A1 FSB_CP_GP0_CLK_DN 5D3 12D8 AUD_R_OUT 41C1 44B4 CPU_RES0_DN 4C3 EJECTSW_N_R 43C7 FSB_CP_GP0_CLK_DP 5D3 12D8 AUD_VAA 41D6 CPU_RES0_DP 4C3 ENET_10BIAS 39B6 FSB_CP_GP0_DATA0_DN 5C3 12C8 AUD_VDD 41D7 CPU_RST_N 34B3 4D8 ENET_10_100_OUT 39B5 FSB_CP_GP0_DATA0_DP 5C3 12C8 AUD_VOUTL 41C6 CPU_RST_N_2_R 58A4 ENET_100BIAS 39B6 FSB_CP_GP0_DATA1_DN 5C3 12C8 AUD_VOUTR 41C6 CPU_RST_V1P1_N 4D8 58A6 ENET_ACT_N 39C3 40B3 45B4 FSB_CP_GP0_DATA1_DP 5C3 12C8 AV_MODE0 44C1 34B8 44A3 CPU_SPI_CLK 4B1 4A5 ENET_AMDIX_EN 39B6 FSB_CP_GP0_DATA2_DN 5C3 12C8 AV_MODE0_R 34B6 CPU_SPI_CLK_R 4A4 ENET_AVDD 40C4 40B3 40B6 FSB_CP_GP0_DATA2_DP 5C3 12C8 AV_MODE1 44C1 34B8 44A3 CPU_SPI_EN 4B2 4A6 ENET_CLK 27A1 39C7 40C6 FSB_CP_GP0_DATA3_DN 5C3 12C8 AV_MODE1_R 34B6 CPU_SPI_EN_R 4A4 ENET_CLK_R 27C4 FSB_CP_GP0_DATA3_DP 5C3 12C8 AV_MODE2 44C1 34B8 44A3 CPU_SPI_SI 4A1 4B6 ENET_LINK_N 39B2 40B3 45B4 FSB_CP_GP0_DATA4_DN 5C3 12C8 AV_MODE2_R 34B6 CPU_SPI_SI_R 4A2 ENET_P1CL 39B4 MICROSOFT PROJECT NAME PAGE REV BINDSW_N 43D6 34B3 FALCON_RETAIL 69/82 1.0 CPU_SPI_SO 4B2 4A5 ENET_P2LI_R 39B2 45B4 CONFIDENTIAL BINDSW_N_R 43D7 CPU_SPI_SO_R 4A4 ENET_P3TD 39B4 FSB_CP_GP0_DATA4_DP 5C3 12C8 FSB_GP_CP1_DATA3_DN 12B4 5B7 HANA_OP2_OUT 28A3 FSB_CP_GP0_DATA5_DN 5C3 12C8 FSB_GP_CP1_DATA3_DP 12B4 5B7 HANA_POR_BYPASS 27D6 FSB_CP_GP0_DATA5_DP 5C3 12C8 FSB_GP_CP1_DATA4_DN 12B4 5B7 HANA_SPDIF_OUT 28C3 44D6 FSB_CP_GP0_DATA6_DN 5C3 12C8 FSB_GP_CP1_DATA4_DP 12B4 5B7 HANA_TCLK 27B6 IR_DATA 43A1 34B6 FSB_CP_GP0_DATA6_DP 5C3 12C8 FSB_GP_CP1_DATA5_DN 12B4 5B7 HANA_TDI 27B6 KER_DBG_RXDI2S_SD3 58D4 28C7 33C6 FSB_CP_GP0_DATA7_DN 5C3 12C8 FSB_GP_CP1_DATA5_DP 12B4 5B7 HANA_TDO 27B6 KER_DBG_TXDI2S_SD_R 33C1 36C4 58C6 FSB_CP_GP0_DATA7_DP 5C3 12C8 FSB_GP_CP1_DATA6_DN 12B4 5B7 HANA_TMS 27B6 KER_DBG_TXD_RI2S_WS 33C336C1 28C6 41C7 FSB_CP_GP0_FLAG_DN 5C3 12C8 FSB_GP_CP1_DATA6_DP 12B4 5B7 HANA_TRST 27B6 LVLCNTI2S_WS_R 44B5 36C4 FSB_CP_GP0_FLAG_DP 5C3 12C8 FSB_GP_CP1_DATA7_DN 12B4 5B7 HANA_V_12P0_DET 27D6 MA_A<11..0> 19C8 20C8 14C5 FSB_CP_GP1_CLK_DN 5C3 12C8 FSB_GP_CP1_DATA7_DP 12B4 5B7 HANA_V_12P0_DET_R 27D6 MA_A<12..0> 14C5 FSB_CP_GP1_CLK_DP 5C3 12C8 FSB_GP_CP1_FLAG_DN 12B4 5B7 HANA_XTAL_BYPASS 27C6 MA_BA<2..0> 14C5 19B8 20C8 FSB_CP_GP1_DATA0_DN 5B3 12B8 FSB_GP_CP1_FLAG_DP 12C4 5B7 HANA_XTAL_IN 27C6 MA_CAS_N 14B5 19B8 20B8 FSB_CP_GP1_DATA0_DP 5B3 12B8 FSB_IMPED_CAL 12B7 HANA_XTAL_OUT 27C6 MA_CKE 14B5 19B8 20B8 FSB_CP_GP1_DATA1_DN 5B3 12B8 FSB_IMPED_NCAL 12B7 HANA_XTAL_VSS_CAP 27C6 MA_CLK0_DN 14C5 19C8 FSB_CP_GP1_DATA1_DP 5B3 12B8 GAMEPORT1_DN 35B6 46A8 HBEDB_CLK_BYP 33D6 MA_CLK0_DP 14C5 19D8 FSB_CP_GP1_DATA2_DN 5B3 12B8 GAMEPORT1_DN_CM 46B6 HBEDB_CLK_SEL 33C6 MA_CLK1_DN 14C5 20C8 FSB_CP_GP1_DATA2_DP 5B3 12B8 GAMEPORT1_DP 35B6 46A8 HDD_RX_DN 48C8 36B7 MA_CLK1_DP 14C5 20D8 FSB_CP_GP1_DATA3_DN 5B3 12B8 GAMEPORT1_DP_CM 46B6 HDD_RX_DN_C 48C6 MA_CS0_N 14B5 19B8 FSB_CP_GP1_DATA3_DP 5B3 12B8 GAMEPORT2_DN 35B6 46C8 HDD_RX_DP 48B8 36B7 MA_CS1_N 14B5 19B1 20B8 FSB_CP_GP1_DATA4_DN 5B3 12B8 GAMEPORT2_DN_CM 46B6 HDD_RX_DP_C 48B6 MA_DM0 14B8 19B4 20B5 FSB_CP_GP1_DATA4_DP 5B3 12B8 GAMEPORT2_DP 35B6 46C8 HDD_TX_DN 36B3 48D8 MA_DM1 14C8 19B4 20B5 FSB_CP_GP1_DATA5_DN 5B3 12B8 GAMEPORT2_DP_CM 46B6 HDD_TX_DN_C 48D6 MA_DM2 14C8 19C4 20C5 FSB_CP_GP1_DATA5_DP 5B3 12B8 GPU_CLK_DN 27D1 13D7 HDD_TX_DP 36B3 48D8 MA_DM3 14D8 19C4 20C5 FSB_CP_GP1_DATA6_DN 5B3 12B8 GPU_CLK_DN_R 27C4 HDD_TX_DP_C 48D6 MA_DQ0 14B8 19B4 20B5 FSB_CP_GP1_DATA6_DP 5B3 12B8 GPU_CLK_DP 27D1 13D7 HDMI_CEC 29C3 MA_DQ1 14B8 19B4 20B5 FSB_CP_GP1_DATA7_DN 5B3 12B8 GPU_CLK_DP_R 27C4 HDMI_DDC_CLK 28C3 34B8 44C1 29B5 MA_DQ2 14B8 19B4 20B5 FSB_CP_GP1_DATA7_DP 5B3 12B8 GPU_HSYNC_OUT 13C4 28C6 HDMI_DDC_DATA 28C3 34C8 44C1 29B5 MA_DQ3 14B8 19B4 20B5 FSB_CP_GP1_FLAG_DN 5B3 12B8 GPU_PIX_CLK_1X 13C3 28D6 HDMI_EXT_SWING 28C4 MA_DQ4 14B8 19B4 20B5 FSB_CP_GP1_FLAG_DP 5B3 12C8 GPU_RST_DONE 13D3 34C1 HDMI_HPD 29B1 28C6 MA_DQ5 14B8 19B4 20B5 FSB_GP_CP0_CLK_DN 12D4 5D7 GPU_RST_DONE_R 34B4 HDMI_HPD_PIN 29B2 MA_DQ6 14B8 19B4 20C5 FSB_GP_CP0_CLK_DP 12D4 5D7 GPU_RST_N 34B3 13D8 HDMI_TX0_DN 28B1 29B8 MA_DQ7 14B8 19B4 20C5 FSB_GP_CP0_DATA0_DN 12C4 5C7 GPU_SCAN_BUFF_EN_N 13A7 12A3 HDMI_TX0_DN_CM 29C3 MA_DQ8 14C8 19B4 20B5 FSB_GP_CP0_DATA0_DP 12C4 5C7 GPU_SPI_CLK 13B3 13A7 HDMI_TX0_DP 28B1 29B8 MA_DQ9 14C8 19B4 20B5 FSB_GP_CP0_DATA1_DN 12C4 5C7 GPU_SPI_CLK_R 13A5 HDMI_TX0_DP_CM 29C3 MA_DQ10 14C8 19B4 20B5 FSB_GP_CP0_DATA1_DP 12C4 5C7 GPU_SPI_CS_N 13B3 13A7 HDMI_TX0_DP_R 28B2 MA_DQ11 14C8 19B4 20B5 FSB_GP_CP0_DATA2_DN 12C4 5C7 GPU_SPI_CS_N_R 13A5 HDMI_TX1_DN 28B1 29C8 MA_DQ12 14C8 19B4 20B5 FSB_GP_CP0_DATA2_DP 12C4 5C7 GPU_SPI_SI 13A2 13B4 13C7 HDMI_TX1_DN_CM 29C3 MA_DQ13 14C8 19B4 20B5 FSB_GP_CP0_DATA3_DN 12C4 5C7 GPU_SPI_SO 13C3 13A7 HDMI_TX1_DP 28B1 29C8 MA_DQ14 14C8 19C4 20B5 FSB_GP_CP0_DATA3_DP 12C4 5C7 GPU_SPI_SO_R 13A5 HDMI_TX1_DP_CM 29C3 MA_DQ15 14C8 19C4 20B5 FSB_GP_CP0_DATA4_DN 12C4 5C7 GPU_SPI_WP_N 13B4 13A4 HDMI_TX1_DP_R 28B2 MA_DQ16 14C8 19C4 20C5 FSB_GP_CP0_DATA4_DP 12C4 5C7 GPU_SROM_EN_PSRO_OUT 13C5 HDMI_TX2_DN 28B1 29D8 MA_DQ17 14C8 19C4 20C5 FSB_GP_CP0_DATA5_DN 12C4 5C7 GPU_TCLK 13B7 HDMI_TX2_DN_CM 29C3 MA_DQ18 14C8 19C4 20C5 FSB_GP_CP0_DATA5_DP 12C4 5C7 GPU_TCLK_R 34A8 13C7 HDMI_TX2_DP 28C1 29D8 MA_DQ19 14C8 19C4 20C5 FSB_GP_CP0_DATA6_DN 12C4 5C7 GPU_TDI 13B7 HDMI_TX2_DP_CM 29C3 MA_DQ20 14C8 19C4 20C5 FSB_GP_CP0_DATA6_DP 12C4 5C7 GPU_TDO 13B7 HDMI_TX2_DP_R 28C2 MA_DQ21 14C8 19C4 20D5 FSB_GP_CP0_DATA7_DN 12C4 5C7 GPU_TEMP_N 13C8 28A8 HDMI_TXC_DN 28C1 29A8 MA_DQ22 14C8 19C4 20D5 FSB_GP_CP0_DATA7_DP 12C4 5C7 GPU_TEMP_P 28A1 13C8 HDMI_TXC_DN_CM 29C3 MA_DQ23 14C8 19C4 20D5 FSB_GP_CP0_FLAG_DN 12C4 5C7 GPU_TMS 13B7 HDMI_TXC_DP 28C1 29A8 MA_DQ24 14D8 19C4 20C5 FSB_GP_CP0_FLAG_DP 12C4 5C7 GPU_TRST 13B7 HDMI_TXC_DP_CM 29C3 MA_DQ25 14D8 19C4 20C5 FSB_GP_CP1_CLK_DN 12C4 5C7 GPU_TRST_ED 13B7 HDMI_TXC_DP_R 28C2 MA_DQ26 14D8 19C4 20C5 FSB_GP_CP1_CLK_DP 12C4 5C7 GPU_VSYNC_OUT 13C4 28C6 I2S_BCLK 36C1 28C6 41C7 MA_DQ27 14D8 19C4 20C5 FSB_GP_CP1_DATA0_DN 12B4 5B7 HANA_AV_CLK 27B4 I2S_BCLK_R 36C4 MA_DQ28 14D8 19C4 20C5 FSB_GP_CP1_DATA0_DP 12B4 5B7 HANA_CLK_DRV_RSET1 27C6 I2S_MCLK 36C1 41C7 MA_DQ29 14D8 19D4 20C5 FSB_GP_CP1_DATA1_DN 12B4 5B7 HANA_CLK_DRV_RSET2 27C6 I2S_MCLK_R 36C4 I2S_SD 36C1 28B6 41C7 MA_DQ30 14D8 19D4 20C5 FSB_GP_CP1_DATA1_DP 12B4 5B7 HANA_DAC_RSET 28C6 MA_DQ31 14D8 19D4 20C5 FSB_GP_CP1_DATA2_DN 12B4 5B7 HANA_OP2_DN 28A1 28B6 MA_RAS_N 14B5 19B8 20B8 FSB_GP_CP1_DATA2_DP 12B4 5B7 HANA_OP2_DP 28B6 MICROSOFT PROJECT NAME PAGE REV I2S_SD1 28C7 FALCON_RETAIL 70/82 1.0 I2S_SD2 28C7 CONFIDENTIAL MD_DQ21 15C4 25C4 26D5 MD_DQ22 15C4 25C4 26D5 MD_DQ23 15D4 25C4 26D5 MB_DQ29 14D4 21C5 22C5 MC_DQ25 15D8 23C4 24C4 MD_DQ24 15D4 25C4 26C5 MA_RDQS0 19B4 20B5 14B8 MB_DQ30 14D4 21C5 22C5 MC_DQ26 15D8 23C4 24C4 MD_DQ25 15D4 25C4 26C5 MA_RDQS1 19B4 20B5 14C8 MB_DQ31 14D4 21D5 22C5 MC_DQ27 15D8 23C4 24C4 MD_DQ26 15D4 25C4 26C5 MA_RDQS2 19C4 20C5 14C8 MB_RAS_N 14B1 21B8 22B8 MC_DQ28 15D8 23C4 24C4 MD_DQ27 15D4 25D4 26C5 MA_RDQS3 19C4 20C5 14D8 MB_RDQS0 21B4 22B4 14B4 MC_DQ29 15D8 23D4 24C4 MD_DQ28 15D4 25D4 26C5 MA_VREF0 14A7 MB_RDQS1 21B4 22B4 14C4 MC_DQ30 15D8 23D4 24C4 MD_DQ29 15D4 25D4 26C5 MA_VREF1 14A8 MB_RDQS2 21C4 22C4 14C4 MC_DQ31 15D8 23D4 24C4 MD_DQ30 15D4 25D4 26C5 MA_WDQS0 14B8 19B4 20B5 MB_RDQS3 21C4 22C4 14D4 MC_RAS_N 15B5 23B8 24B8 MD_DQ31 15D4 25D4 26C5 MA_WDQS1 14C8 19B4 20B5 MB_VREF0 14A4 MC_RDQS0 23B4 24B4 15B8 MD_RAS_N 15B1 25B8 26B8 MA_WDQS2 14C8 19C4 20C5 MB_VREF1 14A4 MC_RDQS1 23B4 24B4 15C8 MD_RDQS0 25B4 26B4 15B4 MA_WDQS3 14D8 19C4 20C5 MB_WDQS0 14B4 21B4 22B4 MC_RDQS2 23C4 24C4 15C8 MD_RDQS1 25B4 26B4 15C4 MA_WE_N 14B5 19B8 20B8 MB_WDQS1 14C4 21B4 22B4 MC_RDQS3 23C4 24C4 15D8 MD_RDQS2 25C4 26C4 15C4 MA_ZQ_BOT 20B5 MB_WDQS2 14C4 21C4 22C4 MC_VREF0 15A7 MD_RDQS3 25C4 26C4 15D4 MA_ZQ_TOP 19B5 MB_WDQS3 14D4 21C4 22C4 MC_VREF1 15A8 MD_VREF0 15A3 MB_A<11..0> 21C8 22C8 14C1 MB_WE_N 14B1 21B8 22B8 MC_WDQS0 15B8 23B4 24B4 MD_VREF1 15A4 MB_A<12..0> 14C1 MB_BA<2..0> 14C1 21B8 22B8 MB_ZQ_BOT 22A5 MC_WDQS1 15C8 23B4 24B4 MD_WDQS0 15B4 25B4 26B4 MB_CAS_N 14B1 21B8 22B8 MB_ZQ_TOP 21A5 MC_WDQS2 15C8 23C4 24C4 MD_WDQS1 15C4 25B4 26B4 MB_CKE 14B1 21B8 22B8 MC_A<11..0> 23C8 24C8 15C5 MC_WDQS3 15D8 23C4 24C4 MD_WDQS2 15C4 25C4 26C4 MB_CLK0_DN 14C1 21C8 MC_A<12..0> 15C5 MC_WE_N 15B5 23B8 24B8 MD_WDQS3 15D4 25C4 26C4 MB_CLK0_DP 14C1 21D8 MC_BA<2..0> 15C5 23B8 24B8 MC_ZQ_BOT 24B5 MD_WE_N 15B1 25B8 26B8 MB_CLK1_DN 14C1 22C8 MC_CAS_N 15B5 23B8 24B8 MC_ZQ_TOPMD_BA<2..0> 23B5 15C1 25C8 26B8 MD_ZQ_BOT 26B5 MB_CLK1_DP 14C1 22D8 MC_CKE 15C5 23B8 24B8 MD_A<11..0>MD_CAS_N 25C8 15B126C8 25B8 15C1 26B8 MD_ZQ_TOP 25B5 MB_CS0_N 14B1 21B8 MC_CLK0_DN 15C5 23C8 MD_A<12..0>MD_CKE 15C1 15C1 25B8 26B8 MEMPORT1_DN 35C3 46B4 MB_CS1_N 14B1 21B1 22B8 MC_CLK0_DP 15C5 23D8 MD_CLK0_DN 15C1 25C8 MEMPORT1_DN_CM 46B2 MB_DM0 14B4 21B4 22B4 MC_CLK1_DN 15C5 24C8 MD_CLK0_DP 15C1 25D8 MEMPORT1_DP 35C3 46B4 MB_DM1 14C4 21B4 22B4 MC_CLK1_DP 15D5 24D8 MD_CLK1_DN 15C1 26C8 MEMPORT1_DP_CM 46B2 MB_DM2 14C4 21C4 22C4 MC_CS0_N 15B5 23B8 MD_CLK1_DP 15D1 26D8 MEMPORT2_DN 35B3 46C4 MB_DM3 14D4 21C4 22C4 MC_CS1_N 15B5 23B1 24B8 MD_CS0_N 15B1 25B8 MEMPORT2_DN_CM 46C2 MB_DQ0 14B4 21B5 22B5 MC_DM0 15B8 23B4 24B4 MD_CS1_N 15B1 25B1 26B8 MEMPORT2_DP 35B3 46C4 MB_DQ1 14B4 21B5 22B5 MC_DM1 15C8 23B4 24B4 MD_DM0 15B4 25B4 26B4 MEMPORT2_DP_CM 46C2 MB_DQ2 14B4 21B5 22B5 MC_DM2 15C8 23C4 24C4 MD_DM1 15C4 25B4 26B4 MEMPORT3_DN 35B3 60B6 MB_DQ3 14B4 21B5 22B5 MC_DM3 15D8 23C4 24C4 MD_DM2 15C4 25C4 26C4 MEMPORT3_DN_ARGON 49A8 60D3 MB_DQ4 14B4 21B5 22B5 MC_DQ0 15B8 23B4 24B4 MD_DM3 15D4 25C4 26C4 MEMPORT3_DN_ARGONYETI 60B3 60D6 MB_DQ5 14B4 21B5 22B5 MC_DQ1 15B8 23B4 24B4 MD_DQ0 15B4 25B4 26B5 MEMPORT3_DN_ARGON_CM 49A6 MB_DQ6 14B4 21B5 22B5 MC_DQ2 15B8 23B4 24B4 MD_DQ1 15B4 25B4 26B5 MEMPORT3_DN_FLASH 60A4 MB_DQ7 14B4 21B5 22B5 MC_DQ3 15B8 23B4 24B4 MD_DQ2 15B4 25B4 26B5 MEMPORT3_DN_YETI 60C4 MB_DQ8 14C4 21B5 22B5 MC_DQ4 15B8 23B4 24B4 MD_DQ3 15B4 25B4 26B5 MEMPORT3_DP 35B3 60B6 MB_DQ9 14C4 21B5 22B5 MC_DQ5 15B8 23B4 24B4 MD_DQ4 15B4 25B4 26B5 MEMPORT3_DP_ARGON 49A8 60D3 MB_DQ10 14C4 21B5 22B5 MC_DQ6 15B8 23B4 24B4 MD_DQ5 15B4 25B4 26B5 MEMPORT3_DP_ARGONYETI 60B3 60D6 MB_DQ11 14C4 21B5 22B5 MC_DQ7 15B8 23B4 24C4 MD_DQ6 15B4 25B4 26C5 MEMPORT3_DP_ARGON_CM 49A6 MB_DQ12 14C4 21B5 22B5 MC_DQ8 15C8 23B4 24B4 MD_DQ7 15B4 25B4 26C5 MEMPORT3_DP_FLASH 60A4 MB_DQ13 14C4 21B5 22B5 MC_DQ9 15C8 23B4 24B4 MD_DQ8 15C4 25B4 26B5 MEMPORT3_DP_YETI 60C4 MB_DQ14 14C4 21B5 22B5 MC_DQ10 15C8 23B4 24B4 MD_DQ9 15C4 25B4 26B5 MEM_A_VREF0 20A6 19B8 20B8 MB_DQ15 14C4 21B5 22B5 MC_DQ11 15C8 23B4 24B4 MD_DQ10 15C4 25B4 26B5 MEM_A_VREF1 19A6 19B8 20B8 MB_DQ16 14C4 21C5 22C5 MC_DQ12 15C8 23B4 24B4 MD_DQ11 15C4 25B4 26B5 MEM_B_VREF0 22A6 21B8 22B8 MB_DQ17 14C4 21C5 22C5 MC_DQ13 15C8 23B4 24B4 MD_DQ12 15C4 25C4 26B5 MEM_B_VREF1 21A6 21B8 22B8 MB_DQ18 14C4 21C5 22C5 MC_DQ14 15C8 23C4 24B4 MD_DQ13 15C4 25C4 26B5 MEM_CALA 13B7 MB_DQ19 14C4 21C5 22C5 MC_DQ15 15C8 23C4 24B4 MD_DQ14 15C4 25C4 26B5 MEM_CALB 13B7 MB_DQ20 14C4 21C5 22C5 MC_DQ16 15C8 23C4 24C4 MD_DQ15 15C4 25C4 26B5 MEM_C_VREF0 24A6 23B8 24B7 MB_DQ21 14C4 21C5 22C5 MC_DQ17 15C8 23C4 24C4 MD_DQ16 15C4 25C4 26C5 MEM_C_VREF1 23A6 23B8 24B7 MB_DQ22 14C4 21C5 22C5 MC_DQ18 15C8 23C4 24C4 MD_DQ17 15C4 25C4 26C5 MEM_D_VREF0 26A7 25B7 26B8 MB_DQ23 14C4 21C5 22D5 MC_DQ19 15C8 23C4 24C4 MD_DQ18 15C4 25C4 26C5 MEM_D_VREF1 25A6 25B7 26B8 MB_DQ24 14D4 21C5 22C5 MC_DQ20 15C8 23C4 24C4 MD_DQ19 15C4 25C4 26C5 MEM_RST 13B3 19C8 20C8 21C8 MB_DQ25 14D4 21C5 22C5 MC_DQ21 15C8 23C4 24C4 MD_DQ20 15C4 25C4 26C5 22C8 23C8 24C8 25C8 26C8 PROJECT NAME PAGE REV MB_DQ26 14D4 21C5 22C5 MC_DQ22 15C8 23C4 24D4 MICROSOFT FALCON_RETAIL 71/82 1.0 MB_DQ27 14D4 21C5 22C5 MC_DQ23 15D8 23C4 24D4 CONFIDENTIAL MB_DQ28 14D4 21C5 22C5 MC_DQ24 15D8 23C4 24C4 PEX_SB_GPU_L0_DP 33C1 13D8 58A8 SMC_DBG_EN 58C6 34C6 VREG_1P8STBY_IN 56B8 MEM_SCAN_BOT_EN 12A1 20B8 22B8 24B8 PEX_SB_GPU_L0_DP_C 33C3 SMC_DBG_RXD 60C5 34D8 VREG_3P3_EN 34C3 56D8 26B8 MEM_SCAN_BOT_EN_BUFF 13B3 12A4 PEX_SB_GPU_L1_DN 33D1 13D8 58A8 SMC_DBG_RXD_R 58D4 60C8 VREG_3P3_EN_R 56D6 MEM_SCAN_EN 12D1 19B8 20B8 21B8 PEX_SB_GPU_L1_DN_C 33C3 SMC_DBG_TXD 34C3 58C6 VREG_CPU1_VCC 52B7 22B8 23B8 24B8 25B8 26B8 PEX_SB_GPU_L1_DP 33D1 13D8 58A8 SMC_DBG_TXD_R 34C4 VREG_CPU2_VCC 52C7 VREG_CPU_BG1 52A5 MEM_SCAN_EN_BUFF 13B3 12D4 PEX_SB_GPU_L1_DP_C 33C3 SMC_PWM0 34B3 28B8 VREG_CPU3_VCC 52D7 VREG_CPU_BG2 52B5 MEM_SCAN_TOP_EN 12B1 19B8 21B8 23B8 PIX_DATA<14..0> 13C3 28D6 SMC_PWM1 34B4 VREG_CPUPLL_ADJUST 56A2 VREG_CPU_BG3 52C5 25B8 PSU_V12P0_EN 34B3 49C5 SMC_RST_N 27D3 34D6 47A5 58D3 VREG_CPUPLL_IN 56A4 VREG_CPU_BST1 52B6 MEM_SCAN_TOP_EN_BUFF 13B3 12B4 PSU_V12P0_EN_R 49C2 SMC_RST_N_R 27D4 VREG_CPUPLL_R 56A1 VREG_CPU_BST1_R 52A5 MII_COL 39B7 40B6 36C7 PWRSW_N 34C3 49B8 SMC_RST_XDK_N 58C5 VREG_CPU_BST2 52C6 MII_CRS 39B7 40B6 36C7 PWRSW_N_R 49B7 SPDIF_R 36C4 VREG_CPU_BST2_R 52C5 MII_MDC_CLK_OUT 36D2 39C8 40B6 SATA_CLK_DN 27B1 33D6 SPI_CLK 58D6 35D6 VREG_CPU_BST3 52D6 MII_MDC_CLK_OUT_R 36D4 SATA_CLK_DN_R 27C4 SPI_MISO 35D2 58D8 VREG_CPU_BST3_R 52D5 MII_MDIO 36C7 39B8 40B6 SATA_CLK_DP 27C1 33D6 SPI_MISO_R 35D4 VREG_CPU_COMP 51A5 MII_RXD0 39C7 40B7 36C7 SATA_CLK_DP_R 27C4 SPI_MOSI 58D6 35D6 VREG_CPU_COMP_R 51A6 MII_RXD1 39C7 40B6 36C7 SATA_CLK_REF 27B1 33D6 SPI_SS_N 58D8 35D6 VREG_CPU_CSCOMP 51C5 MII_RXD2 39C7 40B6 36C7 SATA_CLK_REF_R 27C4 STBY_CLK 27A1 34D6 VREG_CPU_CSCOMP_R 51B6 MII_RXD3 39C7 40B6 36C7 SATA_CLK_SEL 33D6 STBY_CLK_R 27C4 VREG_CPU_CSREF 51A6 MII_RXDV 39C7 40B6 36C7 SATA_RBIAS 36B6 TDR_DIFF_XDK1_DN 62A7 VREG_CPU_CSREF_R 51A5 MII_RXER 39C7 40B6 36C7 SB_GPIO<0..15> 33B1 33B5 TDR_DIFF_XDK1_DP 62A7 VREG_CPU_CSSUM 51B6 MII_RX_CLK 39C7 40C6 36C8 SB_GPIO_RESERVED6 33B3 TDR_DIFF_XDK2_DP 62B7 VREG_CPU_DELAY 51B3 MII_RX_CLK_R 36C6 SB_GPIO_RESERVED16 33B3 TDR_DIFF_XDK3_DN 62C7 VREG_CPU_DRVH1 52A5 MII_TXD0 36C3 39B7 40B6 SB_GPIO_RESERVED17 33B3 TDR_DIFF_XDK3_DP 62D7 VREG_CPU_DRVH2 52B5 MII_TXD1 36C3 39B7 40B6 SB_GPIO_RESERVED18 33B3 TDR_DIIFF_XDK2_DN 62B7 VREG_CPU_DRVH3 52D5 MII_TXD2 36C3 39B7 40B6 SB_GPIO_RESERVED19 33B3 TDR_SINGLE_XDK1 62C2 VREG_CPU_DRV_EN 51B1 52D8 MII_TXD3 36C3 39C7 40B6 SB_GPIO_RESERVED20 33B3 TDR_SINGLE_XDK2 62D2 VREG_CPU_EN 34B3 51D7 MII_TXEN 36C3 39C7 40B6 SB_GPIO_RESERVED21 33B3 TDR_SINGLE_XDK3 62B2 VREG_CPU_FB 51A6 MII_TX_CLK 39C7 40B6 36D8 SB_GPIO_RESERVED22 33B3 TEMP_RSET 28B6 VREG_CPU_FBRTN 51B5 MII_TX_CLK_R 36D6 SB_GPIO_RESERVED23 33B3 TILTSW_N 43B6 34B3 VREG_CPU_PHASE1 52A1 51C8 ODD_RX_DN 48A8 36B7 SB_GPIO_RESERVED24 33B3 TILTSW_N_R 43B7 VREG_CPU_PHASE1_R 51C5 ODD_RX_DN_C 48A7 SB_GPIO_RESERVED25 33B3 TRAY_OPEN 34D8 48A1 VREG_CPU_PHASE2 52C1 51C8 ODD_RX_DP 48A8 36B7 SB_GPIO_RESERVED26 33B3 TRAY_OPEN_R 34C6 VREG_CPU_PHASE2_R 51C5 ODD_RX_DP_C 48A7 SB_GPIO_RESERVED27 33B3 TRAY_STATUS 48A4 34C6 VREG_CPU_PHASE3 52D1 51C8 ODD_TX_DN 36B3 48A8 SB_GPIO_RESERVED28 33B3 TRAY_STATUS_R 48A3 VREG_CPU_PHASE3_R 51C5 ODD_TX_DN_C 48A7 SB_GPIO_RESERVED29 33C3 USBPORTA2_DN 35C6 VREG_CPU_PWM1 51B3 52A7 ODD_TX_DP 36B3 48B8 SB_GPIO_RESERVED30 33C3 USBPORTA2_DP 35C6 VREG_CPU_PWM2 51C3 52B7 ODD_TX_DP_C 48B7 SB_GPIO_RESERVED31 33C3 USBPORTA3_DN 35C6 VREG_CPU_PWM3 51C3 52D7 PCIEX_CLK_DN 27C1 33C6 SB_MAIN_PWRGD 34B1 34C6 USBPORTA3_DP 35C6 VREG_CPU_PWRGD 51C2 34C1 PCIEX_CLK_DN_R 27C4 SB_MAIN_PWRGD_R 34B4 VID_DACA_DN 28D4 VREG_CPU_RAMPADJ 51C5 PCIEX_CLK_DP 27C1 33C6 SB_RST_N 34B3 34C6 VID_DACA_DP 28D3 44D8 VREG_CPU_RAMPADJ_R 51D5 PCIEX_CLK_DP_R 27C4 SB_SPDIF_OUT 36B1 28C6 VID_DACA_OUT 44D5 44C4 VREG_CPU_RT 51B3 PCIEX_INT 33B3 SB_TCLK 33A5 VID_DACB_DN 28D4 VREG_CPU_SW1_R 52A2 PEX_GPU_SB_L0_DN 13C1 33C7 58A5 SB_TDI 33A5 VID_DACB_DP 28D3 44C8 VREG_CPU_SW2_R 52B2 PEX_GPU_SB_L0_DN_C 13D4 SB_TDO 33A5 VID_DACB_OUT 44C6 44C4 VREG_CPU_SW3_R 52C2 PEX_GPU_SB_L0_DP 13D1 33C7 58A5 SB_TMS 33A5 VID_DACC_DN 28D4 VREG_CPU_SW4 51C5 PEX_GPU_SB_L0_DP_C 13D4 SB_TRST 33A5 VID_DACC_DP 28D3 44C8 VREG_CPU_VCC 51D6 PEX_GPU_SB_L1_DN 13D1 33C7 58A5 SB_USB_RBIAS 35B6 VID_DACC_OUT 44C6 44C4 VREG_CPU_VID<5..0> 50C2 51C2 PEX_GPU_SB_L1_DN_C 13D4 SCART_RGB 33B2 44A6 VID_DACD_DN 28D4 VREG_EFUSE_EN 4D2 56C6 PEX_GPU_SB_L1_DP 13D1 33C7 58A5 SCART_RGB_OUT 44A3 VID_DACD_DP 28D3 44B8 VREG_EFUSE_EN_C1 56C4 PEX_GPU_SB_L1_DP_C 13D4 SCART_RGB_OUT_R 44A4 VID_DACD_OUT 44B6 44C4 VREG_EFUSE_EN_C2 56D3 PEX_ICAL 13C8 SCART_RGB_R 44A5 VID_HSYNC_OUT 44A4 44C4 VREG_EFUSE_EN_R 56C4 PEX_NCAL 13D7 SMB_CLK 34B8 58C7 27B6 VID_HSYNC_OUT_R 28C3 44A7 VREG_GPUPCIE_IN 56C4 PEX_PCAL 13D8 SMB_CLK_R 58C6 VID_VSYNC_OUT 44A6 44C4 MICROSOFT PROJECT NAME PAGE REV PEX_RBIAS0 33C6 SMB_DATA 27B7 34B8 58C3 VID_VSYNC_OUT_R 28C3 44A8 FALCON_RETAIL 72/82 1.0 PEX_RBIAS1 33C6 SMB_DATA_R 58C5 VREG_1P8STBY_ADJ 56A7 CONFIDENTIAL PEX_SB_GPU_L0_DN 33C1 13D8 58A8 SMC_CPU_CHKSTOP_DETECT 34C8 58A1 VREG_1P8STBY_D1 56B8 PEX_SB_GPU_L0_DN_C 33C3 SMC_CPU_CHKSTOP_DETECT_B 58A2 VREG_1P8STBY_D2 56B7 VREG_V5P0_BST2 55C6 VREG_V5P0_COMP2 55B6 VREG_V5P0_COMP2_R 55B7 VREG_GPU_5VREF 53C3 53C6 VREG_V5P0_CSL2 55C6 V_CMPAVSS_SATA 38B6 VREG_GPU_COMP 53C6 VREG_V5P0_CSL2_R 55C6 V_CPU_CORE_HF_GNDA_PLL 6C5 VREG_GPU_COMP_C 53C8 VREG_V5P0_DH2 55C6 V_CPU_CORE_HF_VDDA_PLL 6C5 VREG_GPU_COMP_R 53C7 VREG_V5P0_DL2 55C6 V_CPU_CORE_IF_GNDA_PLL 6C5 VREG_GPU_CPGD 53B6 VREG_V5P0_EN 34B3 55A8 V_CPU_CORE_IF_VDDA_PLL 6C5 VREG_GPU_CS1 53C6 VREG_V5P0_EN_R 55A6 V_CPU_FSB_HF_GNDA_PLL 6C5 VREG_GPU_CS2 53C6 VREG_V5P0_FB2 55B8 V_CPU_FSB_HF_VDDA_PLL 6C5 VREG_GPU_CSREF 53C6 VREG_V5P0_FB2_C 55B8 V_CPU_FSB_IF_GNDA_PLL 6B5 V_CPU_FSB_IF_VDDA_PLL 6B5 VREG_GPU_CSREF_RVREG_GPU_GH1 53A853A1 54C7 VREG_V5P0_FB2_R 55B8 V_CPU_GNDA_RNG 6B5 VREG_GPU_EN_NVREG_GPU_GH1_R 53A334C3 53B3 VREG_V5P0_SEL 34B3 47B8 V_CPU_VDDA_RNG 6B5 VREG_GPU_EN_N_RVREG_GPU_GH2 53A1 53B1 54D7 VREG_V5P0_SEL_B1 47B7 V_ENETV_EXPPORT 39A345D2 45B639B8 45D739B8 39D5 VREG_GPU_GH2_R 53A3 VREG_V5P0_SEL_B2 47B6 40B3V_FAN1 40C7 45B6 43C3 VREG_GPU_GL1 53A1 54B7 VREG_V5P0_SEL_C 47B7 V_GAMEPORT1 46B7 VREG_GPU_GL1_R 53A3 VREG_V5P0_SEL_NGATE 47B6 V_GAMEPORT2 46D7 VREG_GPU_GL2 53A1 54C7 VREG_V5P0_SEL_PGATE 47B6 V_HANA_VAA_DAC33M 30C7 VREG_GPU_GL2_R 53A3 VREG_V5P0_SS2 55B5 V_HANA_VAA_RTS33S 30D6 VREG_GPU_ILIM 53C4 VREG_V5P0_SW2 55C6 V_HANA_VAA_XTAL_33S 30C7 VREG_GPU_NPNC 53C2 VREG_V5P0_SW2_S 55C7 V_HANA_VDD18S 31D3 VREG_GPU_PH1_R 54B3 VREG_V5P0_VMEM_PWRGD 34A8 55A7 V_HANA_VDDIO_33S_AVCC 31C7 VREG_GPU_PH2_R 54C3 VREG_VCS_COMP 57B6 V_HANA_VDDIO_33S_PVCC0 31B6 VREG_GPU_PHASE1 53D1 54B2 53B8 VREG_VCS_COMP_C 57B6 V_HDD 48B4 VREG_GPU_PHASE1_C 53D2 VREG_VCS_COMP_R 57A6 V_IR 43A3 VREG_GPU_PHASE2 54D2 53B8 VREG_VCS_CPUCORE_R 57B8 V_MEMPORT1 46D1 60C1 VREG_GPU_PWRGD 53A1 34D1 VREG_VCS_FB 57B5 V_MEMPORT2 46D2 VREG_GPU_ROSC 53B6 VREG_VCS_FB_COMP 57B3 V_PVDDA 16C4 VREG_GPU_SEN 53C6 VREG_VCS_FB_R 57B3 V_PVDDA_ED 16C5 VREG_GPU_VCCH 53C4 VREG_VCS_HDRV 57C4 V_PVDDA_FSB 16B5 VREG_GPU_VCCL 53C6 VREG_VCS_LDRV 57C4 V_PVDDA_MEM 16C5 VREG_GPU_VDRP 53C6 VREG_VCS_LTO 57C8 V_V3P3TOV1P8 54A6 VREG_GPU_VFB 53C6 VREG_VCS_NC 57B4 V_VDD18_USB 37C6 VREG_GPU_VFB_R 53D8 VREG_VCS_NC1 57B4 V_VDD33_USB 37B5 VREG_GPU_VFFB 53D8 62C5 VREG_VCS_RT 57C5 V_VDD_PEX_FB 38D6 VREG_GPU_VID0 53C3 62C5 VREG_VCS_SS_SD_N 57C7 V_VDD_SATA 38B6 VREG_GPU_VID1 53D3 62C5 VREG_VCS_VOUT_L 57C3 V_VREG_CPU 50B4 51D6 51D7 52D5 VREG_VCS_VP 57C5 VREG_GPU_VID2 53D4 62C5 52D8V_VREG_GPU 50B1 53D4 53D7 54D7 VREG_GPU_VID3 53D4 62C5 VREG_VCS_VREF 57C5 V_VREG_V1P8V5P0 55D4 32D4 VREG_GPU_VID4 53D4 62C5 VREG_VDD_PEX_ADJ 56A7 V_VREG_VCS 57D2 VREG_PCIEX_ADJUST 56B3 VREG_VDD_PEX_R 56A5 V_XPOD 48B3 VREG_PCIEX_RVREG_V1P8_BST1 55C4 56B1 VREG_V_CPUCORE_S 51A7 V_YETI 60C3 VREG_V1P8_COMP1 55B4 VREG_V_MEM_S_0 55B1 WSS_CNTL0 33B2 44B6 VREG_V1P8_COMP1_R 55B3 WSS_CNTL1 33B2 44B6 VREG_V1P8_CSL1 55C4 WSS_CNTL_B 44B4 VREG_V1P8_CSL1_R 55C4 WSS_CNTL_E 44B5 V_AVDD0_SATA 38B6 VREG_V1P8_DH1 55C4 WSS_CNTL_OUT 44B3 V_AVDD1_SATA 38C6 VREG_V1P8_DL1 55C4 WSS_CNTL_OUT_R 44B4 V_AVDD_PEX 38D6 VREG_V1P8_EN 34B3 55A3 XUSB_CLK_BYP 33C6 V_AVDD_USB 37C6 VREG_V1P8_FB1 55A1 62B5 XUSB_CLK_SEL 33C6 VREG_V1P8_FB1_C 55B1 V_AVIP 44D3 29D3 VREG_V1P8_FB1_R 55A1 V_AVSS0_SATA 38B6 V_AVSS1_SATA 38C6 VREG_V1P8_SS1 55B4 V_AVSS_PEX 38D6 VREG_V1P8_SW1 55C4 V_AVSS_USB 37C6 VREG_V1P8_SW1_S 55C3 V_CMPAVDD18_USB 37C6 PROJECT NAME PAGE REV V_CMPAVDD33_USB 37A7 37C2 MICROSOFT VREG_V3P3_ADJ 56D5 FALCON_RETAIL 73/82 1.0 V_CMPAVDD_SATA 38B6 CONFIDENTIAL V_CMPAVSS18_USB 37C6 V_CMPAVSS33_USB 37C6 C1N6 CAPN_402 [40A5] C2C2 CAPN_402 [33D2] C2P28 CAPN_402 [38D3] C1N7 CAPN_805 [40C4] C2C3 CAPN_402 [33C2] C2P29 CAPN_402 [38D1] C1N8 CAPN_805 [40C5] C2C4 CAPN_402 [33C2] C2P30 CAPN_402 [38D2] Title: Cref Part Report C1N9 CAPN_402 [39A5] C2C5 CAPN_805 [56A8] C2P31 CAPN_402 [38C6] Design: falcon Date: May 8 12:04:43 2007 C1N10 CAPN_402 [39A4] C2C6 CAPN_402 [56A7] C2P32 CAPN_402 [38C7] C1A2 CAPN_402 [45B3] C1N11 CAPN_402 [39A4] C2D1 CAPN_402 [25A2] C2P33 CAPN_402 [38D1] C1A3 CAPN_402 [45D4] C1N12 CAPN_402 [32C6] C2D2 CAPN_402 [25A3] C2P34 CAPN_603 [37A7] C1A4 CAPN_402 [45B5] C1N13 CAPN_402 [32B5] C2D3 CAPN_805 [23A4] C2P35 CAPN_402 [37A7] C1A5 CAP_P_RDL [39A7] C1N14 CAPN_402 [40C4] C2D4 CAPN_402 [25A1] C2P37 CAPN_402 [37B2] C1B1 CAPN_805 [39A6] C1P1 CAPN_402 [38A6] C2D5 CAPN_402 [12A3] C2P38 CAPN_402 [37B2] C1B2 CAPN_402 [32B5] C1P2 CAPN_805 [38B8] C2D6 CAP_P_RDL [54A4] C2P39 CAPN_603 [38C2] C1B3 CAPN_402 [32B5] C1P3 CAPN_603 [38B7] C2E1 CAPN_402 [23A3] C2P40 CAPN_402 [35B6] C1B4 CAPN_402 [27A5] C1P4 CAPN_402 [38B7] C2E2 CAPN_805 [25A4] C2P41 CAPN_402 [37B7] C1C1 CAPN_402 [32B5] C1P5 CAPN_603 [38B7] C2E3 CAPN_402 [23A1] C2P42 CAPN_402 [37C6] C1C2 CAPN_402 [33A3] C1P6 CAPN_402 [38B7] C2E4 CAPN_402 [12D3] C2P43 CAPN_402 [37C6] C1C3 CAPN_402 [48A7] C1P7 CAPN_805 [38B8] C2E5 CAPN_402 [42C5] C2P44 CAPN_402 [37A7] C1C4 CAPN_402 [48A7] C1P8 CAPN_805 [38A7] C2E6 CAPN_805 [42C5] C2P45 CAPN_805 [37B7] C1C5 CAPN_402 [48A7] C1P9 CAPN_402 [27A7] C2E8 CAPN_805 [23A3] C2P46 CAPN_603 [37C7] C1C6 CAPN_402 [48B7] C1P10 CAPN_603 [38A7] C2F1 CAP_P_RDL [55B2] C2P47 CAPN_603 [37C7] C1C7 CAPN_402 [32C6] C1P11 CAPN_402 [38A7] C2F2 CAPN_402 [32D5] C2P48 CAPN_603 [37A7] C1C8 CAPN_402 [32D4] C1P13 CAPN_402 [28A5] C2F3 CAP_P_RDL [55B2] C2P50 CAPN_402 [28D7] C1C9 CAPN_402 [36B6] C1R1 CAPN_402 [48A4] C2G1 CAPN_402 [32C5] C2P51 CAPN_603 [34D6] C1C10 CAP_P_RDL [48A6] C1R2 CAPN_402 [58C7] C2G2 CAP_P_RDL [46B2] C2P52 CAPN_402 [38A7] C1C11 CAP_P_RDL [48A5] C1R3 CAPN_402 [47B5] C2G3 CAPN_805 [46B2] C2R1 CAPN_402 [28D8] C1C12 CAPN_402 [32B5] C1R4 CAPN_402 [48A1] C2M2 CAPN_402 [44A1] C2R2 CAPN_402 [28D8] C1C13 CAPN_603 [48A5] C1T1 CAPN_603 [48B3] C2M3 CAPN_402 [44A2] C2R3 CAPN_805 [37B8] C1C14 CAPN_603 [48A6] C1T2 CAPN_402 [48B3] C2M4 CAPN_402 [44A3] C2R4 CAPN_603 [54A4] C1C15 CAPN_402 [32B7] C1T3 CAPN_402 [48B3] C2M5 CAPN_805 [44D4] C2R5 CAPN_805 [37C8] C1D1 CAPN_603 [48A5] C1T4 CAPN_603 [48B3] C2N1 CAPN_402 [37A1] C2R6 CAPN_805 [37A8] C1D2 CAPN_805 [38C2] C1T5 CAPN_603 [48B4] C2N3 CAPN_402 [44A1] C2R7 CAPN_402 [26A3] C1D3 CAPN_402 [48A5] C1T6 CAPN_805 [60B2] C2N4 CAPN_402 [60C6] C2R8 CAPN_402 [26A1] C1D4 CAPN_603 [48A6] C1U1 CAPN_805 [56D6] C2P1 CAPN_805 [38A2] C2R9 CAPN_402 [23A7] C1D6 CAPN_603 [48A5] C1U2 CAPN_805 [46A3] C2P2 CAPN_402 [37B6] C2R10 CAPN_402 [26A1] C1D7 CAPN_402 [58D6] C2A1 CAPN_402 [44D3] C2P3 CAPN_402 [37B6] C2R11 CAPN_402 [42C4] C1D8 CAPN_402 [32C5] C2A3 CAPN_402 [44A2] C2P4 CAPN_603 [38A2] C2R12 CAPN_402 [12C3] C1D9 CAP_P_RDL [48A6] C2A4 CAP_P_RDL [45D4] C2P5 CAPN_402 [37A1] C2R13 CAPN_402 [26A5] C1D10 CAPN_402 [32B5] C2A6 CAPN_402 [44D5] C2P6 CAPN_402 [37A6] C2T1 CAPN_402 [24A3] C1D11 CAP_P_RDL [47B5] C2A7 CAPN_1206 [41D6] C2P7 CAPN_402 [27A8] C2T2 CAPN_402 [25A7] C1E1 CAPN_402 [48B7] C2A8 CAPN_402 [44B4] C2P8 CAPN_805 [37A8] C2T3 CAPN_402 [24A1] C1E2 CAPN_402 [48C7] C2A9 CAPN_402 [29D3] C2P9 CAPN_402 [38B2] C2T4 CAPN_402 [32B6] C1E3 CAPN_402 [48D7] C2B1 CAPN_805 [41C7] C2P10 CAPN_805 [38C7] C2T5 CAPN_603 [54A5] C1E4 CAPN_402 [48D7] C2B2 CAPN_402 [41B2] C2P11 CAPN_402 [38B2] C2T6 CAPN_402 [26A4] C1E5 CAP_P_RDL [48B4] C2B3 CAPN_402 [41C2] C2P12 CAPN_402 [38B3] C2T7 CAPN_805 [26B4] C1F1 CAPN_402 [32C4] C2B4 CAPN_402 [41C5] C2P13 CAPN_402 [38B3] C2T8 CAPN_402 [60A2] C1F2 CAPN_402 [32B5] C2B5 CAPN_402 [41C7] C2P14 CAPN_402 [38B2] C2T9 CAPN_402 [60B2] C1F3 CAP_P_RDL [56D4] C2B6 CAPN_402 [41C7] C2P15 CAPN_402 [38D2] C2T10 CAPN_402 [60B3] C1F4 CAP_P_RDL [46A2] C2B7 CAPN_603 [41D6] C2P16 CAPN_402 [38D3] C2V1 CAPN_805 [43A3] C1F5 CAPN_603 [56D5] C2B8 CAPN_805 [41C5] C2P17 CAPN_402 [38D2] C2V2 CAPN_402 [43A3] C1F6 CAPN_603 [46A2] C2B9 CAP_P_1206 [41B5] C2P18 CAPN_402 [33C6] C3A1 CAPN_402 [44C6] C1G1 CAPN_402 [32B5] C2B10 CAP_P_1206 [41D5] C2P20 CAPN_603 [38C2] C3A2 CAPN_402 [44C6] C1M1 CAPN_402 [45B4] C2B11 CAPN_805 [41C7] C2P21 CAPN_402 [38D3] C3A3 CAPN_402 [44D6] C1M2 CAPN_805 [45D4] C2B12 CAPN_402 [58C4] C2P22 CAPN_402 [38D4] C3A4 CAPN_402 [44C7] C1N1 CAPN_402 [39A6] C2B14 CAPN_402 [27A5] C2P23 CAPN_402 [37B1] C3A5 CAPN_402 [44C7] C1N2 CAPN_402 [39A4] C2B15 CAPN_603 [58C4] C2P24 CAPN_402 [37B1] C3A6 CAPN_402 [44D7] C1N3 CAPN_402 [39A5] C2B16 CAPN_402 [33A3] C2P25 CAPN_402 [33C7] C3A7 CAPN_402 [44B7] C1N4 CAPN_402 [39A5] C2B17 CAPN_402 [27A4] C2P26 CAPN_402 [38D7] C3A8 CAPN_402 [44B6] C1N5 CAPN_402 [39A5] C2C1 CAPN_402 [33D2] C2P27 CAPN_603 [38D7] C3A9 CAPN_603 [43C3] MICROSOFT PROJECT NAME PAGE REV FALCON_RETAIL 74/82 1.0 CONFIDENTIAL C3B1 CAPN_402 [27B2] C3U3 CAPN_402 [32B6] C4N21 CAPN_402 [31C1] C4R28 CAPN_402 [18D5] C3B2 CAPN_402 [27A2] C3U4 CAPN_402 [26A4] C4N22 CAPN_402 [31C2] C4R29 CAPN_805 [18D1] C3B4 CAPN_402 [27A1] C3U5 CAPN_603 [55B1] C4N23 CAPN_402 [30C7] C4R30 CAPN_805 [18C1] C3B6 CAPN_402 [27D8] C3V5 CAPN_402 [46B2] C4N24 CAPN_805 [30C7] C4R31 CAPN_402 [15A2] C3B7 CAPN_402 [27D8] C3V6 CAPN_603 [55D2] C4N25 CAPN_805 [30B7] C4R32 CAPN_402 [15A5] C3B8 CAPN_402 [58B5] C3V7 CAPN_603 [55C4] C4N26 CAPN_402 [30A2] C4R33 CAPN_402 [12A6] C3B9 CAPN_603 [58B4] C3V8 CAPN_402 [55A6] C4N27 CAPN_402 [30A3] C4R34 CAPN_402 [18B7] C3B12 CAPN_402 [27A2] C4A1 CAPN_402 [32C5] C4N28 CAPN_402 [30A7] C4R35 CAPN_402 [18B6] C3C1 CAPN_805 [56A5] C4B3 CAPN_402 [28A6] C4N29 CAPN_402 [30C7] C4R36 CAPN_402 [18B7] C3C2 CAPN_805 [13A2] C4B4 CAPN_402 [28C2] C4N30 CAPN_402 [31C3] C4R37 CAPN_402 [18C8] C3C5 CAPN_805 [23A4] C4B10 CAPN_402 [28B2] C4N31 CAPN_402 [30A5] C4R38 CAPN_402 [15A6] C3C6 CAPN_805 [30C3] C4B11 CAPN_402 [28B2] C4N32 CAPN_402 [31C3] C4R39 CAPN_402 [18B8] C3D1 CAPN_402 [25A2] C4B12 CAPN_402 [28C2] C4N33 CAPN_402 [31C2] C4R40 CAPN_402 [18B5] C3D2 CAPN_402 [25A2] C4B13 CAPN_402 [27D6] C4N34 CAPN_402 [30A4] C4R41 CAPN_402 [18B6] C3D3 CAPN_402 [24A7] C4C6 CAPN_805 [56B4] C4N35 CAPN_402 [30D6] C4R42 CAPN_402 [18A7] C3D4 CAPN_402 [25A2] C4D1 CAPN_402 [13D3] C4N36 CAPN_805 [30D7] C4R43 CAPN_402 [18A5] C3D5 CAPN_402 [25A1] C4D2 CAPN_402 [13D3] C4N37 CAPN_805 [30D7] C4R44 CAPN_402 [18C5] C3D6 CAPN_402 [25A1] C4D3 CAPN_402 [13D3] C4N40 CAPN_402 [32C7] C4R45 CAPN_402 [12A6] C3E1 CAPN_402 [23A2] C4D4 CAPN_402 [16D6] C4N41 CAPN_402 [31C3] C4R46 CAPN_402 [18B6] C3E2 CAPN_402 [23A2] C4D5 CAPN_402 [16D6] C4N42 CAPN_402 [30A6] C4R47 CAPN_402 [18C7] C3E3 CAPN_402 [23A2] C4D6 CAPN_603 [16D7] C4P1 CAPN_402 [30A2] C4R48 CAPN_402 [15A5] C3E4 CAPN_402 [26A7] C4D7 CAPN_402 [13C3] C4P2 CAPN_402 [28B7] C4R49 CAPN_402 [18A8] C3E5 CAPN_402 [23A2] C4F1 CAPN_402 [19A1] C4P3 CAPN_805 [31D3] C4R50 CAPN_402 [15A1] C3E6 CAPN_402 [23A1] C4F2 CAPN_402 [20A7] C4P4 CAPN_402 [31D3] C4R51 CAPN_402 [15A5] C3E7 CAPN_402 [23A1] C4F3 CAPN_402 [19A1] C4P5 CAPN_402 [30A4] C4R54 CAPN_402 [18D4] C3E8 CAPN_402 [26A4] C4F4 CAPN_402 [21A2] C4P6 CAPN_402 [30A4] C4R55 CAPN_402 [18C7] C3F1 CAPN_402 [19A2] C4F5 CAPN_402 [21A2] C4P7 CAPN_402 [31C2] C4R56 CAPN_402 [18B4] C3F3 CAPN_402 [19A3] C4F6 CAPN_402 [19A1] C4P8 CAPN_402 [30A6] C4R57 CAPN_402 [18B4] C3F5 CAPN_402 [26A4] C4F7 CAPN_402 [19A2] C4P9 CAPN_402 [30A2] C4R58 CAPN_402 [18A4] C3F6 CAP_P_RDL [55B2] C4F8 CAPN_402 [21A2] C4P11 CAPN_402 [30A3] C4R59 CAPN_402 [18C4] C3G3 CAPN_402 [32C5] C4F9 CAPN_402 [19A2] C4P13 CAPN_805 [30C2] C4R60 CAPN_402 [12A5] C3N1 CAPN_402 [32B4] C4F10 CAPN_402 [21A3] C4P14 CAPN_402 [43C4] C4R61 CAPN_402 [15A2] C3N2 CAPN_402 [32D6] C4F11 CAPN_402 [19A2] C4R3 CAPN_805 [14A6] C4R62 CAPN_402 [18A5] C3N3 CAPN_805 [30C2] C4F12 CAPN_805 [19A4] C4R4 CAPN_402 [16C6] C4R63 CAPN_402 [18A6] C3N6 CAPN_402 [27A7] C4F13 CAPN_402 [32D3] C4R5 CAPN_402 [16B6] C4R64 CAPN_402 [15A3] C3N10 CAPN_402 [28D7] C4F14 CAPN_402 [26A3] C4R6 CAPN_402 [16C6] C4R65 CAPN_402 [12A5] C3P1 CAPN_805 [31D2] C4F15 CAPN_402 [26A3] C4R7 CAPN_402 [16B6] C4R66 CAPN_402 [15A6] C3P3 CAPN_805 [38D8] C4G1 CAPN_402 [55B1] C4R8 CAPN_402 [16C5] C4R67 CAPN_402 [18A6] C3P4 CAPN_402 [28D8] C4N1 CAPN_402 [32A7] C4R9 CAPN_402 [18A5] C4R68 CAPN_603 [16C7] C3R1 CAPN_402 [26A2] C4N3 CAPN_805 [31C8] C4R10 CAPN_402 [15A7] C4R69 CAPN_805 [18C1] C3R2 CAPN_402 [26A2] C4N4 CAPN_805 [31B7] C4R11 CAPN_402 [18D7] C4R70 CAPN_402 [12A7] C3R3 CAPN_402 [25D4] C4N5 CAPN_402 [31C7] C4R12 CAPN_402 [15A2] C4T1 CAPN_402 [18A7] C3R4 CAPN_402 [26A2] C4N6 CAPN_805 [31C7] C4R13 CAPN_402 [18D5] C4T2 CAPN_402 [18A6] C3R5 CAPN_805 [15A6] C4N7 CAPN_805 [31B6] C4R14 CAPN_402 [18C8] C4T3 CAPN_402 [18A8] C3R6 CAPN_402 [26A1] C4N8 CAPN_805 [30B7] C4R15 CAPN_402 [15A2] C4T4 CAPN_402 [18B4] C3R7 CAPN_402 [26A2] C4N9 CAPN_402 [31C7] C4R16 CAPN_402 [18D6] C4T5 CAPN_402 [18C4] C3R8 CAPN_402 [13A1] C4N10 CAPN_402 [31C6] C4R17 CAPN_402 [18C7] C4T6 CAPN_402 [18C4] C3R9 CAPN_402 [13A2] C4N11 CAPN_402 [31B6] C4R18 CAPN_402 [18A8] C4T7 CAPN_402 [15A2] C3T1 CAPN_402 [24A3] C4N12 CAPN_402 [31C6] C4R19 CAPN_402 [15A1] C4T8 CAPN_402 [18A4] C3T2 CAPN_402 [24A2] C4N13 CAPN_402 [31C6] C4R20 CAPN_402 [18D8] C4T11 CAPN_402 [18B8] C3T3 CAPN_402 [24A2] C4N14 CAPN_402 [31C6] C4R21 CAPN_402 [18C6] C4T12 CAPN_402 [15A5] C3T4 CAPN_402 [24C4] C4N15 CAPN_805 [30C8] C4R22 CAPN_402 [18C5] C4T13 CAPN_402 [12A5] C3T5 CAPN_402 [24A2] C4N16 CAPN_402 [30C7] C4R23 CAPN_402 [15A6] C4T14 CAPN_402 [15A5] C3T6 CAPN_402 [24A1] C4N17 CAPN_402 [30A4] C4R24 CAPN_402 [18B5] C4T15 CAPN_402 [18C8] C3T7 CAPN_402 [24A2] C4N18 CAPN_402 [30A8] C4R25 CAPN_402 [15A8] C4T16 CAPN_402 [18A7] C3U1 CAPN_402 [20A2] C4N19 CAPN_402 [30A7] C4R26 CAPN_402 [13A1] C4T17 CAPN_805 [18C1] C3U2 CAPN_402 [20A3] C4N20 CAPN_402 [30A7] C4R27 CAPN_402 [12A7] C4T18 CAPN_402 [18B5] MICROSOFT PROJECT NAME PAGE REV FALCON_RETAIL 75/82 1.0 CONFIDENTIAL C4T19 CAPN_402 [18B5] C5B6 CAPN_603 [56B6] C5U5 CAPN_402 [21A7] C6T2 CAPN_402 [10D3] C4T20 CAPN_402 [18B7] C5B7 CAP_P_RDL [49B3] C5V1 CAPN_402 [32C6] C6T3 CAPN_402 [11B7] C4T21 CAPN_402 [18C6] C5C3 CAPN_402 [13A3] C6B1 CAPN_402 [32C5] C6T4 CAPN_402 [11D3] C4T22 CAPN_402 [12A6] C5C5 CAPN_805 [56B1] C6B2 CAPN_1206 [54D5] C6T6 CAPN_402 [10C5] C4T23 CAPN_402 [18C5] C5C6 CAPN_603 [54C3] C6B3 CAP_P_RDL [50B3] C6T7 CAPN_402 [5A5] C4T24 CAPN_402 [18B5] C5C8 CAP_P_8X8 [50A1] C6B5 CAPN_1206 [50B2] C6T9 CAPN_402 [11B7] C4T25 CAPN_402 [18B8] C5C9 CAP_P_8X8 [50A1] C6C1 CAP_P_RDL [50A2] C6T10 CAPN_402 [10D4] C4T26 CAPN_402 [18C6] C5D2 CAPN_805 [18D3] C6C2 CAP_P_RDL [50A2] C6T11 CAPN_402 [11C3] C4T27 CAPN_402 [14A6] C5D3 CAPN_805 [18C2] C6C3 CAP_P_RDL [50A3] C6T12 CAPN_402 [59C5] C4T28 CAPN_805 [15A2] C5D4 CAPN_805 [18C2] C6D1 CAPN_402 [6C7] C6T13 CAPN_402 [11C6] C4T29 CAPN_402 [14A6] C5D5 CAPN_805 [18B2] C6D4 CAPN_603 [6C6] C6T14 CAPN_402 [11C5] C4T30 CAPN_402 [16C6] C5D6 CAPN_805 [18B2] C6E1 CAPN_805 [18C2] C6T16 CAPN_402 [11C7] C4T31 CAPN_402 [14A2] C5E1 CAPN_402 [14A4] C6E2 CAPN_805 [18C3] C6T17 CAPN_402 [11D4] C4T32 CAPN_402 [14A5] C5F1 CAPN_402 [22A7] C6F1 CAPN_402 [4A2] C6T18 CAPN_402 [11C4] C4T33 CAPN_402 [14A2] C5F2 CAPN_402 [21A1] C6F3 CAP_P_RDL [55D8] C6T19 CAPN_402 [5A5] C4T34 CAPN_402 [14A2] C5F3 CAPN_402 [21A1] C6G2 CAPN_402 [49D6] C6T21 CAPN_402 [11A6] C4T35 CAPN_402 [14A6] C5F4 CAPN_402 [21A1] C6G3 CAPN_402 [49C6] C6T22 CAPN_402 [11B5] C4T36 CAPN_402 [15A4] C5F5 CAPN_402 [21A2] C6G4 CAPN_402 [49C6] C6T24 CAPN_402 [11D6] C4T37 CAPN_402 [16C6] C5F6 CAPN_805 [21A4] C6G5 CAP_P_RDL [49D6] C6T25 CAPN_402 [10B4] C4T38 CAPN_402 [15A1] C5F8 CAP_P_RDL [21A4] C6N1 CAPN_402 [32B7] C6T26 CAPN_402 [10A5] C4T39 CAPN_402 [14A1] C5G1 CAPN_402 [32C3] C6N2 CAPN_1206 [50B2] C6T27 CAPN_402 [5A5] C4T40 CAPN_402 [14A8] C5G3 CAPN_402 [32C5] C6P1 CAPN_805 [56A4] C6T31 CAPN_402 [59C4] C4T41 CAPN_402 [14A5] C5G4 CAP_P_RDL [46D2] C6R1 CAPN_402 [56A3] C6T32 CAPN_402 [5A4] C4T42 CAPN_402 [14A5] C5G5 CAPN_402 [32C4] C6R2 CAPN_402 [6B7] C6T33 CAPN_402 [5A4] C4T43 CAPN_402 [14A5] C5G6 CAPN_805 [46D2] C6R3 CAPN_402 [6B7] C6T34 CAPN_402 [59C5] C4T44 CAPN_402 [14A5] C5N1 CAPN_402 [32A7] C6R4 CAPN_603 [6B6] C6T35 CAPN_402 [59C5] C4T45 CAPN_402 [14A7] C5N2 CAPN_402 [32B4] C6R5 CAPN_603 [6B6] C6T36 CAPN_402 [59C5] C4T46 CAPN_402 [14A3] C5N3 CAPN_805 [56B8] C6R6 CAPN_402 [5A4] C6U1 CAPN_603 [55B8] C4T47 CAPN_805 [14A2] C5P1 CAPN_402 [56B3] C6R7 CAPN_805 [9D3] C6U2 CAPN_603 [55D7] C4T48 CAPN_603 [16C7] C5R1 CAPN_805 [18B3] C6R10 CAPN_805 [9C3] C6V10 CAPN_402 [49B6] C4U1 CAPN_402 [20A1] C5R2 CAPN_805 [18B3] C6R12 CAPN_402 [11A6] C6V11 CAPN_402 [49B6] C4U2 CAPN_402 [20A1] C5R3 CAPN_805 [18A3] C6R13 CAPN_402 [11A7] C6V15 CAPN_402 [49B7] C4U3 CAPN_402 [22A2] C5R4 CAPN_805 [18C3] C6R14 CAPN_402 [5A6] C7B1 CAPN_402 [32D5] C4U4 CAPN_402 [22A2] C5R5 CAPN_805 [18C3] C6R15 CAPN_402 [5A7] C7B2 CAPN_1206 [54C5] C4U5 CAPN_402 [20A1] C5R6 CAPN_805 [18A3] C6R16 CAPN_402 [10B6] C7B3 CAP_P_RDL [50B3] C4U6 CAPN_402 [20A2] C5R7 CAPN_402 [16C5] C6R17 CAPN_402 [10C7] C7B4 CAPN_1206 [50B1] C4U7 CAPN_402 [22A2] C5R8 CAPN_402 [18B5] C6R18 CAPN_402 [5A6] C7C1 CAP_P_RDL [50A3] C4U8 CAPN_402 [20A2] C5R9 CAPN_402 [18A5] C6R19 CAPN_402 [10B6] C7C2 CAP_P_RDL [50A4] C4U9 CAPN_402 [19A7] C5R10 CAPN_402 [18C5] C6R20 CAPN_402 [10B5] C7C3 CAP_P_RDL [50A2] C4U10 CAPN_402 [22A3] C5R11 CAPN_805 [18A3] C6R21 CAPN_402 [10A5] C7D1 CAPN_603 [6A7] C4U11 CAPN_402 [20A2] C5R12 CAPN_402 [18C5] C6R23 CAPN_402 [10B5] C7D2 CAPN_603 [6A6] C4U12 CAPN_402 [26A3] C5R13 CAPN_402 [16A6] C6R24 CAPN_402 [11D5] C7D3 CAPN_805 [9C5] C4V1 CAPN_402 [55B8] C5R14 CAPN_402 [18A5] C6R25 CAPN_402 [5A6] C7D4 CAPN_805 [9C4] C4V6 CAPN_402 [46D2] C5R15 CAPN_402 [16A6] C6R26 CAPN_402 [11C7] C7D5 CAPN_805 [9B5] C4V7 CAPN_603 [55D3] C5R16 CAPN_402 [18C5] C6R28 CAPN_402 [10C7] C7D7 CAPN_805 [9B4] C4V8 CAPN_603 [55C6] C5R17 CAPN_402 [18A5] C6R29 CAPN_402 [10C7] C7D8 CAPN_805 [9C4] C4V9 CAPN_402 [55B4] C5R18 CAPN_402 [12A6] C6R30 CAPN_402 [11B3] C7D11 CAPN_805 [9B5] C4V10 CAPN_402 [55B3] C5R19 CAPN_603 [16A7] C6R32 CAPN_402 [10D5] C7D12 CAPN_805 [9C5] C4V11 CAPN_402 [55B2] C5R20 CAPN_805 [18B3] C6R35 CAPN_402 [10A6] C7D18 CAPN_805 [9C4] C4V12 CAPN_402 [55B7] C5T1 CAPN_402 [14A1] C6R36 CAPN_402 [10C5] C7D19 CAPN_805 [9C5] C4V13 CAPN_402 [55B6] C5T2 CAPN_402 [14A1] C6R37 CAPN_402 [5A5] C7D23 CAPN_402 [58A5] C4V14 CAPN_402 [55B5] C5T3 CAPN_402 [14A2] C6R39 CAPN_402 [10B7] C7E1 CAPN_805 [9C5] C4V15 CAPN_603 [55C6] C5T4 CAPN_402 [14A2] C6R41 CAPN_402 [11A7] C7E2 CAPN_805 [9C5] C5B1 CAPN_603 [56C7] C5U1 CAPN_402 [22A1] C6R42 CAPN_402 [10B7] C7E5 CAPN_805 [9B5] C5B2 CAP_P_RDL [56C6] C5U2 CAPN_402 [22A1] C6R44 CAPN_402 [10D5] C7E6 CAPN_805 [9D5] C5B3 CAPN_805 [56C8] C5U3 CAPN_402 [22A1] C6R47 CAPN_805 [18D2] C7E9 CAPN_805 [9B6] C5B4 CAP_P_RDL [56B6] C5U4 CAPN_402 [22A2] C6T1 CAPN_805 [9A5] C7E10 CAPN_805 [9B6] MICROSOFT PROJECT NAME PAGE REV FALCON_RETAIL 76/82 1.0 CONFIDENTIAL C7F1 CAP_P_RDL [55D2] C7R66 CAPN_402 [11D3] C7T29 CAPN_402 [11D2] C8E3 CAP_P_RDL [50A8] C7F3 CAP_P_RDL [55B8] C7R67 CAPN_402 [10A7] C7T30 CAPN_402 [11D2] C8F1 CAP_P_RDL [50A7] C7F4 CAP_P_RDL [57C2] C7R68 CAPN_402 [10C5] C7T31 CAPN_402 [11C2] C8F2 CAPN_603 [57C4] C7F5 CAPN_1206 [57C1] C7R69 CAPN_402 [10B5] C7T32 CAPN_805 [9B6] C8G1 CAPN_402 [51A5] C7G2 CAPN_402 [32D7] C7R74 CAPN_402 [11B3] C7T33 CAPN_805 [9C6] C8G2 CAPN_402 [32C4] C7G3 CAPN_1206 [57C2] C7R75 CAPN_402 [11B5] C7T37 CAPN_402 [10B4] C8G4 CAPN_1206 [57C3] C7G4 CAPN_1206 [57C2] C7R76 CAPN_402 [10B7] C7T38 CAPN_402 [11D5] C8G5 CAP_P_RDL [51D5] C7G5 CAPN_603 [57C1] C7R81 CAPN_402 [10C5] C7T39 CAPN_402 [11B4] C8N1 CAPN_603 [53C2] C7G7 CAP_P_RDL [57C2] C7R82 CAPN_402 [11B3] C7T40 CAPN_402 [11B5] C8N3 CAPN_805 [53D6] C7G8 CAPN_805 [60C2] C7R83 CAPN_402 [11B4] C7T41 CAPN_402 [11B5] C8N4 CAPN_402 [53B5] C7G9 CAPN_402 [60C2] C7R89 CAPN_402 [10B4] C7T46 CAPN_402 [11A5] C8N5 CAPN_603 [53C7] C7N1 CAPN_402 [32B7] C7R90 CAPN_805 [9C5] C7T47 CAPN_402 [11A5] C8P1 CAPN_603 [53C8] C7N2 CAPN_402 [32A4] C7R91 CAPN_805 [9B4] C7T48 CAPN_402 [11A4] C8P2 CAPN_402 [53C7] C7N3 CAPN_1206 [50B1] C7R95 CAPN_402 [11D4] C7T49 CAPN_402 [11B5] C8P3 CAPN_603 [53B7] C7P1 CAPN_805 [56A1] C7R99 CAPN_402 [10A4] C7T50 CAPN_402 [11C5] C8P4 CAPN_603 [53A6] C7R1 CAPN_402 [6C7] C7R100 CAPN_402 [10A4] C7T51 CAPN_402 [10C4] C8P5 CAPN_402 [58A3] C7R2 CAPN_805 [9C6] C7R101 CAPN_402 [11C4] C7T54 CAPN_402 [11D7] C8U1 CAPN_603 [51B3] C7R3 CAPN_805 [9D5] C7R102 CAPN_402 [10C5] C7T55 CAPN_402 [11B4] C8U2 CAPN_402 [51B2] C7R4 CAPN_805 [9A4] C7R106 CAPN_402 [11C5] C7T56 CAPN_402 [11C5] C8U3 CAPN_603 [51B5] C7R5 CAPN_805 [9B4] C7R110 CAPN_402 [11D5] C7T57 CAPN_402 [11C4] C8U4 CAPN_402 [51C5] C7R7 CAPN_603 [6C6] C7R111 CAPN_402 [10C3] C7T58 CAPN_402 [11D5] C8U5 CAPN_402 [57B3] C7R14 CAPN_402 [11C5] C7R112 CAPN_603 [4D6] C7T83 CAPN_805 [9B5] C8U6 CAPN_402 [51A6] C7R19 CAPN_402 [10C6] C7R113 CAPN_603 [4D6] C7T84 CAPN_805 [9B5] C8U7 CAPN_603 [51A7] C7R20 CAPN_402 [11C6] C7R114 CAPN_402 [6D5] C7T90 CAPN_402 [59C5] C8U8 CAPN_402 [51A5] C7R21 CAPN_402 [11B7] C7R115 CAPN_402 [6D5] C7T91 CAPN_402 [59C4] C8U9 CAPN_402 [57C6] C7R22 CAPN_402 [10D6] C7R116 CAPN_402 [6D5] C7T92 CAPN_402 [59C5] C8U10 CAPN_402 [51B4] C7R23 CAPN_805 [9A5] C7R119 CAPN_805 [9C5] C7T93 CAPN_805 [9C6] C8V1 CAPN_603 [51B6] C7R24 CAPN_805 [9A5] C7R120 CAPN_805 [9B5] C7T94 CAPN_805 [9D6] C8V15 CAPN_603 [51D6] C7R25 CAPN_805 [9A4] C7R121 CAPN_805 [9B5] C7T98 CAPN_603 [56C2] C9A1 CAPN_603 [49D3] C7R26 CAPN_805 [9B6] C7T1 CAPN_805 [9A6] C7T99 CAPN_603 [56C1] C9A2 CAPN_603 [49D2] C7R27 CAPN_805 [9D4] C7T2 CAPN_402 [10A5] C7T100 CAPN_603 [56D3] C9A3 CAPN_402 [58C2] C7R28 CAPN_805 [9C3] C7T3 CAPN_402 [10A7] C7T102 CAPN_805 [57C1] C9A4 CAPN_402 [49B2] C7R29 CAPN_805 [9C3] C7T4 CAPN_805 [9B3] C7T103 CAPN_805 [57C1] C9A5 CAPN_603 [49D3] C7R30 CAPN_805 [9A5] C7T5 CAPN_805 [9B4] C7U5 CAPN_603 [57C6] C9A6 CAPN_603 [49D3] C7R31 CAPN_402 [11D7] C7T6 CAPN_805 [9A6] C7U6 CAPN_402 [57C6] C9B1 CAP_P_RDL [49D4] C7R32 CAPN_402 [11A5] C7T7 CAPN_402 [11D2] C7U7 CAPN_402 [57A6] C9B2 CAPN_1206 [50B8] C7R33 CAPN_402 [11A5] C7T8 CAPN_402 [11C2] C7U8 CAPN_402 [57B6] C9B3 CAPN_603 [53C2] C7R34 CAPN_402 [10C6] C7T9 CAPN_402 [10D6] C7U9 CAPN_603 [57C4] C9B4 CAPN_1206 [50B6] C7R35 CAPN_402 [10C6] C7T10 CAPN_402 [10C3] C7U10 CAPN_402 [57A6] C9C1 CAP_P_RDL [50B7] C7R39 CAPN_402 [11B6] C7T11 CAPN_402 [11B5] C7U11 CAPN_402 [57A5] C9C2 CAPN_603 [53B3] C7R40 CAPN_402 [11B6] C7T12 CAPN_402 [11C2] C7V2 CAPN_603 [57C1] C9C3 CAPN_1206 [50B5] C7R41 CAPN_402 [11B6] C7T13 CAPN_402 [11C2] C8A1 CAPN_402 [49C3] C9C4 CAP_P_RDL [50B7] C7R42 CAPN_402 [11C6] C7T14 CAPN_402 [11D2] C8A2 CAPN_402 [49C2] C9C5 CAPN_603 [52C1] C7R43 CAPN_402 [10B6] C7T15 CAPN_402 [11C3] C8B1 CAP_P_RDL [49B3] C9C7 CAPN_402 [32B7] C7R44 CAPN_402 [10D7] C7T16 CAPN_402 [11B2] C8B2 CAPN_1206 [50B4] C9D1 CAPN_1206 [52D2] C7R48 CAPN_402 [10C4] C7T17 CAPN_402 [11B2] C8B3 CAPN_603 [53D2] C9D2 CAP_P_RDL [50B6] C7R49 CAPN_402 [10D7] C7T18 CAPN_402 [11B2] C8B4 CAPN_1206 [50B2] C9D3 CAPN_1206 [52D3] C7R50 CAPN_402 [10C5] C7T19 CAPN_402 [11A2] C8B6 CAPN_603 [54B3] C9D4 CAPN_1206 [52C3] C7R51 CAPN_402 [10D5] C7T20 CAPN_402 [11A2] C8B7 CAPN_402 [53A7] C9E1 CAPN_1206 [52C2] C7R52 CAPN_402 [10D5] C7T21 CAPN_402 [10D3] C8B8 CAPN_603 [53A7] C9E2 CAPN_402 [32C7] C7R56 CAPN_402 [11C7] C7T22 CAPN_402 [10D4] C8B9 CAPN_805 [53D5] C9E3 CAP_P_RDL [50B7] C7R57 CAPN_402 [10B5] C7T23 CAPN_402 [11A3] C8C1 CAP_P_RDL [50A5] C9E4 CAPN_603 [52B1] C7R58 CAPN_402 [10B5] C7T24 CAPN_402 [11C3] C8C2 CAP_P_RDL [50A8] C9F1 CAPN_1206 [52A2] C7R59 CAPN_402 [10B5] C7T25 CAPN_402 [11D6] C8D1 CAP_P_RDL [50A6] C9F2 CAPN_402 [32C7] C7R60 CAPN_402 [10A5] C7T26 CAPN_402 [11A4] C8D4 CAP_P_RDL [50A5] C9F3 CAPN_603 [52A1] C7R61 CAPN_402 [10A6] C7T27 CAPN_402 [10C4] C8E1 CAP_P_RDL [50A7] C9F4 CAPN_1206 [52A3] C7R65 CAPN_402 [11A3] C7T28 CAPN_402 [11C5] C8E2 CAP_P_RDL [50A6] C9G1 CAPN_402 [46D6] MICROSOFT PROJECT NAME PAGE REV FALCON_RETAIL 77/82 1.0 CONFIDENTIAL DB4P4 DBPAD_TP [28A2] FB2P1 FERRITE_603 [37A7] DB4P5 DBPAD_TP [28B5] FB2P2 FERRITE_603 [38D7] C9G2 CAP_P_RDL [46D6] DB6E1 DBPAD_TP [47C4] FB2P3 FERRITE_603 [37C7] C9G3 CAP_P_RDL [46B6] D2A1 DIOSOT23S_SOT [44D4] DB6E2 DBPAD_TP [47C4] FB2P4 FERRITE_603 [37C7] C9G4 CAPN_402 [46B6] 23S D3A1 DIODE_SOT23 [43C3] DB6E3 DBPAD_TP [47C4] FB2P5 FERRITE_603 [37A7] C9G5 CAPN_805 [46D6] D3V1 BAT54A_SOT23S [55D6] DB6E4 DBPAD_TP [47C4] FB2R1 FERRITE_603 [37B7] C9G6 CAPN_805 [46B7] D5B1 DIODE_SMA [56B7] DB6G1 DBPAD_TP [55C8] FB4D1 FERRITE_603 [16D7] C9N1 CAPN_402 [32B4] D5N1 DIODE_SOD123 [56B8] DB7R1 DBPAD_TP [4C1] FB4N5 FERRITE_603 [30D7] C9P1 CAPN_603 [53C8] D5N2 DIODE_SOD123 [56B8] DB7R2 DBPAD_TP [4C6] FB4N6 FERRITE_603 [31C7] C9P2 CAPN_805 [52D4] D8B1 ZENER_SOD123 [53C2] DB7U1 DBPAD_TP [57B4] FB4N7 FERRITE_603 [31B6] C9P3 CAPN_805 [52D5] D8B2 DIODE_SOT23 [53D3] DB7U2 DBPAD_TP [57C7] FB4N8 FERRITE_603 [30C7] C9P4 CAPN_805 [52D7] D8B3 DIOSOT23S_SOT [53D2] DB8F4 DBPAD_TP [57C5] FB4P1 FERRITE_603 [31D2] C9T1 CAPN_805 [52C4] 23S DB8M1 DBPAD_TP [49D2] FB4R1 FERRITE_603 [16C7] C9T2 CAPN_805 [52C5] D8B4 LED_SM [58B2] DB8M2 DBPAD_TP [49D2] FB4T1 FERRITE_603 [16C7] C9T3 CAPN_805 [52C7] D9C1 DIODE_SOT23 [52D6] DB8M3 DBPAD_TP [49D2] FB5G1 FERRITE_603 [46D2] C9U1 CAPN_805 [52A4] D9E1 DIODE_SOT23 [52C6] DB8N1 DBPAD_TP [49C3] FB5R1 FERRITE_603 [16B7] C9U2 CAPN_805 [52B5] D9F1 DIODE_SOT23 [52B6] DB8P1 DBPAD_TP [50B5] FB6D1 FERRITE_603 [6C7] C9U3 CAPN_805 [52A7] D9G1 DIOSOT23S_SOT [46C6] DB8P2 DBPAD_TP [50B5] FB6R1 FERRITE_603 [6B7] CM2A1 CMCHOKE_SM [29D6] 23S DB8U1 DBPAD_TP [57D6] FB6R2 FERRITE_603 [6B7] CM2A2 CMCHOKE_SM [29C6] D9G2 DIOSOT23S_SOT [46C6] DB8U2 DBPAD_TP [57C6] FB7D1 FERRITE_603 [6A7] CM3A1 CMCHOKE_SM [29B6] 23S DB8U3 DBPAD_TP [57B4] FB7R1 FERRITE_603 [6D7] CM3A2 CMCHOKE_SM [29A6] D9V1 DIOSOT23S_SOT [46A6] DB8U4 DBPAD_TP [51C5] FT1N1 FTPAD_TP [33A2] CR1D1 MBT3904DUAL_S [47B6] 23S EG1A1 ESDGUARD_603 [45C4] FT1N2 FTPAD_TP [45D3] OT D9V2 DIOSOT23S_SOT [46A6] DB1F1 DBPAD_TP [34A7] EG1A2 ESDGUARD_603 [45C5] FT1P1 FTPAD_TP [27B1] CR1D2 DIOSOT23S_SOT [48A2] 23S DB1N1 DBPAD_TP [40C5] EG1E1 ESDGUARD_603 [48C3] FT1P2 FTPAD_TP [27B1] 23S DB1N3 DBPAD_TP [39B5] EG1E2 ESDGUARD_603 [48C4] FT1R1 FTPAD_TP [47A8] CR1D3 DIOSOT23S_SOT [48A1] DB1N4 DBPAD_TP [39C7] EG1E3 ESDGUARD_603 [48C4] FT1R2 FTPAD_TP [47B3] 23S CR2A1 MBT3904DUAL_S [44B5] DB1N5 DBPAD_TP [33D6] EG1E4 ESDGUARD_603 [48C5] FT1R3 FTPAD_TP [42C7] OT DB1P1 DBPAD_TP [33B2] EG2A1 ESDGUARD_402 [29D6] FT1R4 FTPAD_TP [42C7] CR2M2 MBT3904DUAL_S [41A3] DB1P2 DBPAD_TP [33B2] EG2A2 ESDGUARD_402 [29D6] FT1R5 FTPAD_TP [42C7] OT DB2B1 DBPAD_TP [34B3] EG2A3 ESDGUARD_402 [29C6] FT1T1 FTPAD_TP [42C4] CR3A1 BAV99DUAL_SOT [44B8 44C8] DB2N3 DBPAD_TP [33B2] EG2A4 ESDGUARD_402 [29C6] FT1U1 FTPAD_TP [56D4] 363 DB2N4 DBPAD_TP [33B2] EG2B1 ESDGUARD_603 [41B5] FT1U2 FTPAD_TP [34A7] CR3A2 BAV99DUAL_SOT [44D8 44C8] DB2N5 DBPAD_TP [33B2] EG2B2 ESDGUARD_603 [41C5] FT1V1 FTPAD_TP [46A1] 363 DB2N6 DBPAD_TP [33B2] EG2G1 ESDGUARD_603 [46B1] FT2M1 FTPAD_TP [41D6] CR3M1 BAV99DUAL_SOT [29B4 29B3] DB2N7 DBPAD_TP [33B2] EG3A1 ESDGUARD_402 [29B5] FT2M2 FTPAD_TP [29D4] 363 DB2N8 DBPAD_TP [33C6] EG3A2 ESDGUARD_402 [29B6] FT2M3 FTPAD_TP [29D4] CR3M2 BAV99DUAL_SOT [44A7 44A6] DB2N9 DBPAD_TP [33B2] EG3A3 ESDGUARD_402 [29A5] FT2M4 FTPAD_TP [29D4] 363 DB2N10 DBPAD_TP [33B2] EG3A4 ESDGUARD_402 [29A6] FT2M5 FTPAD_TP [29D4] CR6T1 MBT3904DUAL_S [56C4] DB2N11 DBPAD_TP [33B2] EG3G1 ESDGUARD_603 [46B2] FT2N1 FTPAD_TP [41D7] OT DB2N12 DBPAD_TP [33B2] EG3M1 ESDGUARD_603 [29B2] FT2N2 FTPAD_TP [41C8] CR7V2 MBR0520L_SOD1 [57B4] DB2P1 DBPAD_TP [33C2] EG3M2 ESDGUARD_402 [29B4] FT2N3 FTPAD_TP [27D3] 23 DB2P2 DBPAD_TP [33C2] EG3M3 ESDGUARD_402 [29B3] FT2N4 FTPAD_TP [27B1] D1A1 DIOSOT23S_SOT [45C6] DB2P3 DBPAD_TP [33C2] EG4G1 ESDGUARD_603 [46C2] FT2N5 FTPAD_TP [34C8] 23S DB2P4 DBPAD_TP [33B2] EG4G2 ESDGUARD_603 [46C2] FT2N6 FTPAD_TP [29B3] D1A2 DIOSOT23S_SOT [45D6] DB2P5 DBPAD_TP [33B2] EG9G1 ESDGUARD_603 [46C5] FT2P1 FTPAD_TP [41B6] 23S DB2P6 DBPAD_TP [33B2] EG9G2 ESDGUARD_603 [46D5] FT2P2 FTPAD_TP [27A1] D1B1 DIOSOT23S_SOT [45B6] DB2P7 DBPAD_TP [33B2] EG9V1 ESDGUARD_603 [46A5] FT2P3 FTPAD_TP [53A2] 23S DB2P8 DBPAD_TP [34A6] EG9V2 ESDGUARD_603 [46A5] FT2P4 FTPAD_TP [27C8] D1E1 DIOSOT23S_SOT [48B6] 23S DB2P9 DBPAD_TP [34A6] FB1B1 FERRITE_603 [39A6] FT2P5 FTPAD_TP [34B1] D1E2 DIOSOT23S_SOT [48C6] DB2P15 DBPAD_TP [33D6] FB1N1 FERRITE_603 [40C5] FT2P6 FTPAD_TP [53B2] 23S DB3A1 DBPAD_TP [29C3] FB1P1 FERRITE_603 [38B7] FT2P7 FTPAD_TP [27D7] D1E3 DIOSOT23S_SOT [48C5] DB3F1 DBPAD_TP [55C1] FB1P2 FERRITE_603 [38C7] FT2P10 FTPAD_TP [34C6] 23S DB4D1 DBPAD_TP [13C3] FB1P3 FERRITE_603 [38A7] FT2P11 FTPAD_TP [4D8] D1E4 DIOSOT23S_SOT [48D5] DB4P1 DBPAD_TP [28A2] FB1P4 FERRITE_603 [38B7] FT2P12 FTPAD_TP [4D8] 23S DB4P2 DBPAD_TP [28A2] FB2B1 FERRITE_603 [41B3] FT2P13 FTPAD_TP [13D4] DB4P3 DBPAD_TP [28A2] FB2B2 FERRITE_603 [41D3] FT2P14 FTPAD_TP [13D8] MICROSOFT PROJECT NAME PAGE REV FALCON_RETAIL 78/82 1.0 D1F1 LED_SM [34A3] CONFIDENTIAL Q7B2 FET_VREG_DPAK [54B5] Q7C1 FET_VREG_DPAK [54B4] FT2P15 FTPAD_TP [34C8] FT7R6 FTPAD_TP [4A7] L6G2 CMCHOKE_SM [49A6] Q7F1 FET_SOT23 [57C7] FT2P16 FTPAD_TP [51C2] FT7R7 FTPAD_TP [58A5] L7C1 INDUCTOR_TH [54B2] Q7U1 NPN_SOT23 [57B7] FT2P17 FTPAD_TP [51C7] FT7T1 FTPAD_TP [4B3] L7F1 INDUCTOR_TH [55D5] Q8B3 FET_SOT23 [53B1] FT2P18 FTPAD_TP [55A7] FT7T2 FTPAD_TP [4B3] L7G1 INDUCTOR_TH [57D1] Q8B4 NPN_SOT23 [49A2] FT2P19 FTPAD_TP [55A3] FT7T3 FTPAD_TP [4B2] L8B1 INDUCTOR_TH [50B4] Q8B5 NPN_SOT23 [49A3] FT2P20 FTPAD_TP [35C6] FT7T4 FTPAD_TP [4B2] L8D1 INDUCTOR_TH [52D1] Q8B6 NPN_SOT23 [58B2] FT2P21 FTPAD_TP [35C6] FT7T5 FTPAD_TP [4B2] L8E1 INDUCTOR_TH [52B1] Q8C1 FET_VREG_DPAK [52C3] FT2P22 FTPAD_TP [35C6] FT7T6 FTPAD_TP [56D1] L8F1 INDUCTOR_TH [52A1] Q8F1 FET_VREG_DPAK [52A3] FT2P23 FTPAD_TP [35C6] FT7T7 FTPAD_TP [4B3] L8F2 INDUCTOR_TH [57C2] Q8N1 PNP_2C_SOT223 [49B1] FT2P24 FTPAD_TP [34C8] FT7T8 FTPAD_TP [56C6] L9B1 INDUCTOR_TH [50B8] Q9C1 FET_VREG_DPAK [52C4] FT2P25 FTPAD_TP [34A7] FT7T9 FTPAD_TP [50A5] L9G1 CMCHOKE_SM [46C7] Q9D1 FET_VREG_DPAK [52D3] FT2P26 FTPAD_TP [56A5] FT7U3 FTPAD_TP [57C1] L9V1 CMCHOKE_SM [46A7] Q9D2 FET_VREG_DPAK [52D4] FT2R2 FTPAD_TP [27A1] FT7U4 FTPAD_TP [50A4] LB7G1 LABEL_SM [61D5] Q9D3 FET_VREG_DPAK [52B3] FT2R3 FTPAD_TP [42C7] FT8N1 FTPAD_TP [49C3] MTG1B1 STD_MTG_HOLE_ [61C6] Q9D4 FET_VREG_DPAK [52C3] FT2R4 FTPAD_TP [42C7] FT8P1 FTPAD_TP [53D7] TH Q9E1 FET_VREG_DPAK [52C4] FT2R5 FTPAD_TP [42C7] FT8P2 FTPAD_TP [53D7] MTG1G1 STD_MTG_HOLE_ [61C6] Q9E3 FET_VREG_DPAK [52B4] FT2R6 FTPAD_TP [42C7] FT8U1 FTPAD_TP [51B5] TH Q9F1 FET_VREG_DPAK [52A4] FT2R7 FTPAD_TP [42C7] FT8U2 FTPAD_TP [51B5] MTG3C1 STD_MTG_HOLE_ [61B6] Q9F2 FET_VREG_DPAK [52A4] FT2R8 FTPAD_TP [54A4] FT9N1 FTPAD_TP [49D3] TH Q9F4 FET_VREG_DPAK [52A3] FT2U1 FTPAD_TP [55C1] J1A1 XENONRJ45USB_ [45B2] MTG3E1 STD_MTG_HOLE_ [61B4] R1A1 RESN_402 [39B2] FT3M1 FTPAD_TP [29D4] TH TH J1C1 1X7SATA_TH [48A7] R1A2 RESN_402 [39B2] FT3M2 FTPAD_TP [29D4] MTG5B1 STD_MTG_HOLE_ [61C5] J1D1 2X6HDR2_TH [48A2] R1A3 RESN_402 [39C2] FT3M3 FTPAD_TP [29D4] TH J1D2 2X5HDR10_TH [58D7] R1A4 RESN_402 [39D2] FT3M4 FTPAD_TP [29D4] MTG5C1 STD_MTG_HOLE_ [61A6] J1E1 XENONHDD_TH [48C2] R1A5 RESN_402 [45B5] FT3P1 FTPAD_TP [27C1] TH J1E2 1X5HDR_TH [60A3] R1B1 RESN_603 [45C7] FT3P2 FTPAD_TP [27C1] MTG5E1 STD_MTG_HOLE_ [61A4] J2A1 HDMI_1X19HDR [29C1] R1B2 RESN_603 [45D7] FT3P3 FTPAD_TP [34A7] TH J2B1 2X7HDR14_TH [58C5] MTG5G1 STD_MTG_HOLE_ [61C5] R1B3 RESN_402 [36B3] FT3P4 FTPAD_TP [27D3] J2D1 2X3HDR_TH [33A6] TH R1B4 RESN_402 [39B3] FT4N1 FTPAD_TP [28A6] J2D2 2X4HDR_TH [13A8] MTG6C1 STD_MTG_HOLE_ [61A6] R1B5 RESN_402 [39B3] FT4N2 FTPAD_TP [29C3] J3A1 XENONAVIP_TH [44C2] TH R1B6 RESN_402 [39C4] FT4N4 FTPAD_TP [28A6] J3A2 1X3HDR_TH [43C2] MTG6E1 STD_MTG_HOLE_ [61B4] R1B7 RESN_402 [39D4] FT4N5 FTPAD_TP [27B4] J3C1 PCIEXMIDBUS_S [58A7] TH R1B9 RESN_402 [36D7] FT4P1 FTPAD_TP [27D7] M MTG8C1 STD_MTG_HOLE_ [61B6] R1B10 RESN_402 [36C7] FT4P2 FTPAD_TP [27B1] TH R1B11 RESN_402 [39B7] FT4P3 FTPAD_TP [27B1] J4F1 1X3HDR_TH [62B5] MTG8E1 STD_MTG_HOLE_ [61A4] R1B12 RESN_402 [40B6] FT4P4 FTPAD_TP [27D3] J4G1 1X2HDR_TH [62B4] TH R1B13 RESN_402 [39C3] FT5N1 FTPAD_TP [56C6] J4G2 XENONMU_TH [46C1] MTG9B1 STD_MTG_HOLE_ [61C3] R1C1 RESN_402 [39C7] FT5N2 FTPAD_TP [56B5] J5C1 2X3HDR_TH [27A6] TH R1C2 RESN_402 [33B7] FT5R1 FTPAD_TP [56C1] J5C2 2X3HDR_TH [13A5] MTG9G1 STD_MTG_HOLE_ [61C3] R1C3 RESN_402 [36D3] FT5R2 FTPAD_TP [50A2] J6G1 XENONRF_TH [49B5] Q1G2TH NPN_SOT23 [47A3] R1C4 RESN_402 [33B8] FT6U1 FTPAD_TP [47C4] J7G3 2X6HDR_TH [60C3] Q1G3 PNP_SOT23 [28A4] R1C5 RESN_402 [33B8] FT6U2 FTPAD_TP [47C4] J8B1 1X8HDR_TH [62C4] Q1V1 NPN_SOT23 [47A4] R1C6 RESN_402 [33B7] FT6U3 FTPAD_TP [47C4] J8C1 2X5HDR_TH [58A3] Q2F3 FET_VREG_DPAK [55B3] R1C7 RESN_402 [33B8] FT6U4 FTPAD_TP [47C4] J9A1 XENONPWR_TH [49C1] Q2N1 PNP_SOT23 [41A5] R1C8 RESN_402 [36B6] FT6U5 FTPAD_TP [47C4] J9A2 1X2HDR_SM [58C2] Q2N3 PNP_SOT23 [44A4] R1D2 RESN_402 [42B5] FT6U6 FTPAD_TP [47C4] J9G1 XENONGAME_TH [46B5] Q2P1 NPN_SOT23 [58A1] R1D3 RESN_402 [42B5] FT6U7 FTPAD_TP [47C4] L1B1 CMCHOKE_SM [45C6] Q3F1 FET_VREG_DPAK [55C3] R1D4 RESN_402 [42B5] FT6U8 FTPAD_TP [47C4] L2G1 CMCHOKE_SM [46B2] Q3M1 PNP_DPAK [43D3] R1D5 RESN_402 [47A6] FT6U9 FTPAD_TP [47D5] L3A1 INDUCTOR_1210 [44C7] Q3M2 NPN_SOT23 [43D4] R1D6 RESN_402 [47B7] FT6U10 FTPAD_TP [47D5] L3A2 INDUCTOR_1210 [44C7] Q6B1 FET_VREG_DPAK [54D5] R1E1 RESN_1210 [54A7] FT6U11 FTPAD_TP [47D5] L3A3 INDUCTOR_1210 [44D7] Q6B2 FET_VREG_DPAK [54C5] R1E2 RESN_402 [42C5] FT6V1 FTPAD_TP [55C8] L3A4 INDUCTOR_1210 [44B7] Q6C1 FET_VREG_DPAK [54C4] R1E3 RESN_1210 [54A7] FT7R1 FTPAD_TP [4A7] L3F1 INDUCTOR_TH [55C2] Q6F1 FET_VREG_DPAK [55C7] R1F7 RESN_402 [56D7] FT7R2 FTPAD_TP [4A7] L4G1 CMCHOKE_SM [46C3] Q6F2 FET_VREG_DPAK [55B7] R1F8 RESN_402 [56D7] FT7R3 FTPAD_TP [56A1] L6C1 INDUCTOR_TH [54D2] Q7B1 FET_VREG_DPAK [54C5] R1G1 RESN_1206 [47B3] FT7R4 FTPAD_TP [4A7] L6F1 INDUCTOR_TH [55C7] MICROSOFT PROJECT NAME PAGE REV FT7R5 FTPAD_TP [4A7] FALCON_RETAIL 79/82 1.0 L6G1 CMCHOKE_SM [49C6] CONFIDENTIAL R1G2 RESN_402 [47B4] R2B19 RESN_402 [34A7] R2P4 RESN_402 [34C7] R3D2 RESN_402 [24A7] R1G3 RESN_402 [43C6] R2C1 RESN_603 [38D7] R2P5 RESN_402 [33D7] R3D3 RESN_402 [24A7] R1G4 RESN_402 [43C7] R2C3 RESN_402 [56A6] R2P6 RESN_402 [34C7] R3D4 RESN_402 [23D7] R1M1 RESN_603 [39C2] R2D1 RESN_402 [42B6] R2P8 RESN_402 [33C6] R3D5 RESN_402 [23D7] R1M2 RESN_603 [39B2] R2D2 RESN_402 [42C2] R2P9 RESN_402 [33D6] R3E1 RESN_402 [25A5] R1M3 RESN_402 [45B5] R2D3 RESN_402 [42B6] R2P10 RESN_402 [34B2] R3E2 RESN_402 [26A8] R1N1 RESN_402 [39B7] R2D4 RESN_402 [42B6] R2P11 RESN_402 [33C7] R3E3 RESN_402 [26A7] R1N2 RESN_402 [39B7] R2D5 RESN_402 [42B6] R2P12 RESN_402 [34A2] R3E4 RESN_402 [25D7] R1N3 RESN_402 [39B6] R2D6 RESN_402 [42C5] R2P13 RESN_402 [34A2] R3E5 RESN_402 [25D7] R1N4 RESN_402 [39B6] R2D7 RESN_402 [42C6] R2P14 RESN_402 [35B6] R3F1 RESN_402 [19A5] R1N5 RESN_402 [39B3] R2D8 RESN_402 [42B7] R2P15 RESN_402 [34B2] R3G4 RESN_603 [46B3] R1N6 RESN_402 [39B4] R2D9 RESN_402 [13A7] R2P16 RESN_402 [33C7] R3M1 RESN_402 [29B2] R1N7 RESN_402 [39B4] R2D10 RESN_402 [13A8] R2P17 RESN_603 [38C7] R3M2 RESN_402 [44A6] R1N8 RESN_402 [40A3] R2D11 RESN_402 [12C1] R2P18 RESN_402 [58D4] R3M3 RESN_402 [44A7] R1P1 RESN_402 [33B7] R2D12 RESN_402 [12C2] R2P19 RESN_402 [58A1] R3M5 RESN_402 [29C4] R1P2 RESN_402 [33B8] R2D13 RESN_402 [60B4] R2R1 RESN_402 [23A7] R3M6 RESN_402 [29C4] R1P3 RESN_402 [33B8] R2D14 RESN_402 [60B4] R2R2 RESN_402 [23A7] R3M7 RESN_402 [29B2] R1P5 RESN_402 [33B7] R2E1 RESN_402 [13B4] R2R3 RESN_402 [24D7] R3M8 RESN_402 [43C4] R1P6 RESN_402 [33B8] R2E2 RESN_402 [13B8] R2R4 RESN_402 [24D7] R3M9 RESN_402 [43D4] R1P7 RESN_402 [35C6] R2E3 RESN_402 [13A7] R2R5 RESN_402 [12D2] R3N6 RESN_402 [49B8] R1R1 RESN_402 [35D3] R2E4 RESN_402 [13B7] R2R6 RESN_402 [12A2] R3N7 RESN_402 [49B7] R1R2 RESN_402 [47B7] R2E5 RESN_402 [12D2] R2R7 RESN_402 [60A4] R3N8 RESN_402 [58A2] R1R3 RESN_402 [47B6] R2E6 RESN_1210 [54A7] R2R8 RESN_402 [60A4] R3P6 RESN_402 [34B1] R1R4 RESN_402 [48A3] R2E7 RESN_1210 [54A7] R2T1 RESN_402 [12A1] R3P7 RESN_402 [34C2] R1R5 RESN_402 [47B6] R2G2 RESN_402 [43B7] R2T2 RESN_402 [12B1] R3R1 RESN_402 [24A5] R1U1 RESN_402 [56D5] R2G3 RESN_402 [43B6] R2T3 RESN_402 [25A7] R3T1 RESN_402 [26A5] R1U2 RESN_402 [56D5] R2G5 RESN_603 [46A3] R2T4 RESN_402 [25A7] R3T2 RESN_402 [15B4] R1U3 RESN_402 [34A4] R2M3 RESN_402 [34B7] R2T5 RESN_402 [26D7] R3U1 RESN_402 [20A5] R1V1 RESN_402 [47A4] R2M4 RESN_402 [44A1] R2T6 RESN_402 [26D7] R3V1 RESN_402 [55C3] R1V2 RESN_1206 [47B3] R2M5 RESN_402 [34B7] R2T7 RESN_805 [54A2] R3V3 RESN_402 [55A4] R2A1 RESN_402 [44A2] R2M6 RESN_402 [44A2] R2T8 RESN_805 [54A2] R3V4 RESN_402 [55A7] R2A2 RESN_402 [34B7] R2M9 RESN_402 [44A3] R2V1 RESN_402 [43A2] R3V5 RESN_402 [55A7] R2A4 RESN_402 [44B5] R2M10 RESN_402 [44A4] R3A2 RESN_402 [43B3] R4B1 RESN_402 [27D7] R2A5 RESN_402 [44B4] R2N1 RESN_402 [41A2] R3A3 RESN_402 [44C7] R4B2 RESN_402 [27D5] R2A6 RESN_402 [44B5] R2N2 RESN_402 [41A4] R3A4 RESN_402 [44D7] R4B3 RESN_402 [28A2] R2A7 RESN_402 [44B5] R2N3 RESN_402 [41B7] R3A6 RESN_402 [44C7] R4B4 RESN_402 [27A3] R2A8 RESN_402 [44C5] R2N4 RESN_402 [33B6] R3A7 RESN_402 [43C3] R4B5 RESN_402 [27A2] R2A9 RESN_402 [44B5] R2N5 RESN_402 [33B6] R3A9 RESN_402 [44B7] R4B6 RESN_402 [27B2] R2A11 RESN_603 [29D7] R2N6 RESN_402 [33B7] R3A10 RESN_603 [29B7] R4B8 RESN_402 [27D6] R2A12 RESN_603 [29C7] R2N7 RESN_402 [43A2] R3A11 RESN_603 [29B7] R4B9 RESN_402 [27D7] R2A13 RESN_603 [29C7] R2N8 RESN_402 [33C2] R3A12 RESN_603 [29A7] R4B10 RESN_402 [28D2] R2A14 RESN_603 [29B7] R2N9 RESN_402 [34C3] R3A13 RESN_603 [29A7] R4B11 RESN_402 [28D1] R2B1 RESN_603 [41D6] R2N10 RESN_402 [36B3] R3B1 RESN_402 [27C7] R4B12 RESN_402 [28C6] R2B2 RESN_402 [41B4] R2N11 RESN_402 [36B3] R3B2 RESN_402 [27D8] R4B13 RESN_402 [28D2] R2B3 RESN_402 [41D4] R2N12 RESN_402 [36B3] R3B3 RESN_402 [58C4] R4B14 RESN_402 [28D1] R2B4 RESN_402 [41B4] R2N13 RESN_402 [58C6] R3B4 RESN_402 [27C2] R4B15 RESN_402 [28B7] R2B5 RESN_402 [41C4] R2N14 RESN_402 [58C4] R3B5 RESN_402 [27C2] R4B17 RESN_402 [27C7] R2B6 RESN_603 [41D8] R2N15 RESN_402 [34D7] R3B6 RESN_402 [27B2] R4B18 RESN_402 [28C7] R2B8 RESN_402 [33B6] R2N16 RESN_402 [60C7] R3C7 RESN_402 [27C2] R4B19 RESN_603 [28C1] R2B9 RESN_402 [33B6] R2N19 RESN_402 [44A5] R3C8 RESN_402 [27D2] R4B20 RESN_603 [28B1] R2B10 RESN_402 [33B7] R2N20 RESN_402 [44A1] R3C9 RESN_402 [27C2] R4B21 RESN_603 [28B1] R2B11 RESN_402 [36C2] R2N21 RESN_402 [34D7] R3C15 RESN_402 [27C2] R4B22 RESN_603 [28C1] R2B12 RESN_402 [36C3] R2N22 RESN_402 [41A5] R3C16 RESN_402 [27D2] R4B23 RESN_402 [28C2] R2B13 RESN_402 [36C2] R2N23 RESN_402 [41A6] R3C21 RESN_0402 [56A5] R4B24 RESN_402 [27A3] R2B14 RESN_402 [36C3] R2P1 RESN_402 [27D4] R3C22 RESN_402 [56A6] R4B25 RESN_402 [27B2] R2B15 RESN_402 [36B2] R2P2 RESN_402 [33C7] R3C28 RESN_402 [13C8] R4B26 RESN_402 [27C2] R2B16 RESN_402 [34A7] R2P3 RESN_402 [27D4] R3D1 RESN_402 [23A5] R4B27 RESN_402 [27C2] MICROSOFT PROJECT NAME PAGE REV FALCON_RETAIL 80/82 1.0 CONFIDENTIAL R4C1 RESN_402 [28B7] R4T5 RESN_402 [14A3] R6E2 RESN_402 [4A5] R7R15 RESN_402 [4B7] R4C2 RESN_402 [28B6] R4T6 RESN_402 [14A7] R6G7 RESN_603 [49C7] R7R16 RESN_402 [4D7] R4C3 RESN_402 [13A6] R4T7 RESN_402 [14A7] R6G8 RESN_603 [49C7] R7R17 RESN_402 [4C8] R4C4 RESN_402 [13A5] R4T8 RESN_402 [14A3] R6G35 RESN_402 [60D4] R7R18 RESN_402 [4A7] R4C5 RESN_402 [13A5] R4U1 RESN_402 [22A5] R6G36 RESN_402 [60D4] R7R19 RESN_402 [4A7] R4C6 RESN_402 [13A3] R4U2 RESN_402 [20D7] R6G37 RESN_603 [49B6] R7R20 RESN_402 [4A8] R4C7 RESN_402 [13A6] R4U3 RESN_402 [20D7] R6G38 RESN_603 [49A6] R7R21 RESN_402 [4A8] R4C8 RESN_402 [27C2] R4U4 RESN_402 [19A7] R6R1 RESN_0402 [56A1] R7R22 RESN_402 [4A7] R4C9 RESN_402 [27D2] R4U5 RESN_402 [19A7] R6R2 RESN_402 [56A2] R7R23 RESN_402 [4A7] R4C10 RESN_402 [27D2] R4U6 RESN_402 [12A1] R6R3 RESN_402 [56A2] R7T2 RESN_402 [6C5] R4C11 RESN_402 [27D2] R4V1 RESN_402 [55B3] R6R4 RESN_402 [4D7] R7T4 RESN_402 [50D5] R4C12 RESN_402 [27D2] R4V2 RESN_402 [55B5] R6R5 RESN_402 [4C7] R7T5 RESN_402 [50D4] R4C13 RESN_402 [27B2] R4V3 RESN_402 [55B5] R6R6 RESN_402 [4C8] R7T6 RESN_402 [50D5] R4C14 RESN_402 [27B2] R4V4 RESN_402 [55B6] R6R7 RESN_402 [4C8] R7T7 RESN_402 [50D4] R4C15 RESN_402 [27B3] R4V5 RESN_402 [55A8] R6R8 RESN_402 [4C8] R7T8 RESN_402 [50D5] R4C16 RESN_402 [27B3] R4V6 RESN_402 [55B8] R6R9 RESN_402 [4C8] R7T9 RESN_402 [50D4] R4C31 RESN_603 [56C4] R4V7 RESN_402 [55C6] R6T1 RESN_402 [56C5] R7T10 RESN_402 [56D4] R4D1 RESN_402 [13C4] R4V9 RESN_402 [55B8] R6T3 RESN_402 [56D4] R7T11 RESN_402 [50C5] R4D2 RESN_402 [13C4] R4V10 RESN_402 [55A6] R6T4 RESN_402 [56C5] R7T12 RESN_402 [50C4] R4F1 RESN_402 [20A7] R4V11 RESN_402 [55C8] R6V1 RESN_402 [60C4] R7T13 RESN_402 [50C5] R4F2 RESN_402 [20A8] R5B1 RESN_402 [56B6] R6V2 RESN_402 [60C4] R7T14 RESN_402 [50C4] R4F3 RESN_402 [19D7] R5B2 RESN_402 [56A6] R7B2 RESN_402 [49B2] R7T15 RESN_402 [50C5] R4F4 RESN_402 [19D7] R5B3 RESN_1206 [56B7] R7B6 RESN_805 [54B3] R7T16 RESN_402 [50C4] R4F5 RESN_402 [21A5] R5C4 RESN_805 [56A4] R7D1 RESN_402 [4C7] R7T18 RESN_402 [4B6] R4F6 RESN_402 [13B3] R5C5 RESN_402 [13A6] R7D2 RESN_402 [4C7] R7T19 RESN_402 [57C7] R4F7 RESN_402 [12B1] R5C6 RESN_805 [56B4] R7E1 RESN_402 [50D6] R7U3 RESN_402 [4A5] R4F8 RESN_402 [12C1] R5C8 RESN_402 [13A6] R7E2 RESN_402 [50D6] R7U4 RESN_402 [57B8] R4G1 RESN_402 [55B1] R5C9 RESN_0402 [56B1] R7E3 RESN_402 [50D6] R7U5 RESN_402 [57B7] R4G4 RESN_603 [46C3] R5C10 RESN_402 [13A6] R7E4 RESN_402 [50D6] R7U6 RESN_402 [57B5] R4G5 RESN_603 [46D3] R5C11 RESN_402 [12D8] R7E5 RESN_402 [50D6] R7U7 RESN_402 [57B3] R4G6 RESN_402 [55B1] R5C12 RESN_402 [12D8] R7E6 RESN_402 [50C6] R7U8 RESN_402 [57A6] R4G7 RESN_402 [55A1] R5D1 RESN_402 [13D8] R7E7 RESN_402 [4A5] R7V4 RESN_402 [34C2] R4G8 RESN_402 [55A1] R5D2 RESN_402 [13D7] R7E8 RESN_402 [4A4] R7V8 RESN_402 [60C4] R4G9 RESN_402 [55C1] R5E1 RESN_402 [14A4] R7F1 RESN_402 [4A4] R8A1 RESN_402 [49C4] R4N1 RESN_402 [30C7] R5E2 RESN_402 [14B4] R7F2 RESN_402 [4A5] R8A2 RESN_402 [49C3] R4N2 RESN_402 [28C7] R5F1 RESN_402 [22A7] R7F3 RESN_402 [4A2] R8A3 RESN_402 [49A3] R4N3 RESN_402 [28C7] R5F2 RESN_402 [22A7] R7F4 RESN_402 [4A2] R8A4 RESN_402 [49A3] R4N4 RESN_402 [27B4] R5F3 RESN_402 [21D7] R7F6 RESN_603 [60D2] R8A5 RESN_402 [58B3] R4N5 RESN_402 [27C7] R5F4 RESN_402 [21D7] R7F7 RESN_402 [4A2] R8B1 RESN_402 [53D3] R4N6 RESN_402 [27C7] R5N1 RESN_402 [53B2] R7F9 RESN_402 [57C8] R8B2 RESN_402 [53A7] R4P1 RESN_402 [27C7] R5P1 RESN_402 [56B2] R7G23 RESN_805 [57D1] R8B3 RESN_603 [53A6] R4P2 RESN_402 [43C4] R5P2 RESN_402 [56B2] R7N1 RESN_805 [49A1] R8B4 RESN_603 [53C3] R4P13 RESN_603 [56C4] R5P3 RESN_402 [13A6] R7N2 RESN_805 [49A1] R8B5 RESN_402 [49B3] R4P14 RESN_603 [56C3] R5R1 RESN_402 [12D8] R7N3 RESN_805 [49A2] R8B6 RESN_402 [58B2] R4R1 RESN_402 [15A7] R5R2 RESN_402 [12C8] R7N4 RESN_805 [49A1] R8B7 RESN_402 [53D3] R4R2 RESN_402 [15A7] R5R3 RESN_402 [12A8] R7R1 RESN_402 [4B6] R8B8 RESN_402 [53D3] R4R3 RESN_402 [13C8] R5U1 RESN_402 [22D7] R7R2 RESN_402 [4B6] R8B9 RESN_402 [53C3] R4R4 RESN_402 [15B8] R5U2 RESN_402 [22D7] R7R3 RESN_402 [4A7] R8B10 RESN_402 [53C3] R4R5 RESN_402 [15A8] R5U3 RESN_402 [21A7] R7R4 RESN_402 [4D7] R8C1 RESN_402 [53B2] R4R6 RESN_402 [15A3] R5U4 RESN_402 [21A7] R7R5 RESN_402 [4A8] R8C2 RESN_402 [58A5] R4R7 RESN_402 [15A3] R5V2 RESN_402 [43D6] R7R8 RESN_402 [4B7] R8C3 RESN_402 [58A4] R4R8 RESN_402 [13B7] R5V3 RESN_402 [43D7] R7R9 RESN_402 [4B1] R8C4 RESN_402 [58A4] R4R9 RESN_402 [12B8] R6C1 RESN_805 [56B3] R7R10 RESN_402 [4D7] R8C5 RESN_402 [58A4] R4T1 RESN_402 [13B8] R6C2 RESN_805 [54D3] R7R11 RESN_402 [4D7] R8C6 RESN_402 [58A4] R4T2 RESN_402 [15A4] R6D4 RESN_402 [4D5] R7R12 RESN_402 [4A8] R8C7 RESN_603 [53B6] R4T3 RESN_402 [14A8] R6D5 RESN_402 [4D5] R7R13 RESN_402 [4A7] R8C8 RESN_402 [58A2] R4T4 RESN_402 [14B8] R6E1 RESN_402 [4B2] R7R14 RESN_402 [4B5] R8C9 RESN_402 [53D7] MICROSOFT PROJECT NAME PAGE REV FALCON_RETAIL 81/82 1.0 CONFIDENTIAL TP7M2 TDRX2_TH [62D1] R8F7 RESN_402 [51C7] R9V2 RESN_603 [46A7] 6 TP7R1 PROBE_SMT [4D2] R8F8 RESN_402 [51C2] RT1B1 THERMISTOR_12 [45D5] U4U1 GDDR136_BGA13 [20C2 20C6] TP7R2 PROBE_SMT [4C2] R8G1 RESN_603 [51D6] 06 6 TP7R3 PROBE_SMT [4C2] R8G3 RESN_402 [51A6] RT1R1 THERMISTOR_12 [48B3] U4V1 ADP1823_LCC32 [55C5] TP7R4 PROBE_SMT [4C2] R8N1 RESN_402 [49B2] 06 U5B1 NCP1117_DPAK [56C7] TP8A1 TDRX2_TH [62B1] R8N2 RESN_805 [53C2] RT1U1 THERMISTOR_18 [48B4] U5B2 NCP1117_DPAK [56B7] TP8A2 TDRX2_TH [62C1] R8N3 RESN_805 [53A3] 12 U5C1 NCP1117_SOT22 [56C3] TP8M1 TDRX4_TH [62A7] R8N4 RESN_805 [53A2] RT2G1 THERMISTOR_12 [46D3] 3 TP8M2 TDRX4_TH [62A7] R8N5 RESN_805 [53A3] 06 U5F1 GDDR136_BGA13 [21C2 21B6] RT2M1 THERMISTOR_12 [44D4] U1B1 BCM5241_LCC32 [40B4] 6 R8N6 RESN_805 [53A2] 06 U1B2 ICS1893BF_SSO [39C5] U5U1 GDDR136_BGA13 [22B6 22C2] R8N7 RESN_805 [53D6] RT7C1 THERMISTOR_60 [53D8] P 6 R8N17 RESN_402 [34D2] 3 U1F1 NCP5662_DPAK [56D6] U6R1 NCP1117_SOT22 [56A3] R8N18 RESN_402 [34C2] RT8F1 THERMISTOR_60 [51C6] U1F2 NCP1117_DPAK [46A3] 3 R8P1 RESN_603 [53C7] 3 U1G1 IR_WHOLDER_TH [43A4] U6T1 NCP502D_SC70 [56D2] R8P3 RESN_402 [53C7] RT8G1 THERMISTOR_12 [46D7] U1R1 SI4501DY_SO8 [47B4] U6T2 LP2980_SOT23_ [56D2] R8P4 RESN_402 [53C7] 06 U1U1 SN74LVC1G14_S [34A5] 5 R8P5 RESN_603 [53B7] RT8G2 THERMISTOR_12 [46B7] C70 U7D1 LOKI_BGA [4C4] U2B1 XDAC_SOIC14 [41C6] R8P6 RESN_603 [53B7] 06 U7D1 LOKI_BGA [5C5] R8P7 RESN_402 [53C8] U2C1 SB_BGA [33C4] U7D1 LOKI_BGA [6C3] ST1P1 SHORT_SM [38B7] R8P8 RESN_402 [58A2] U2C1 SB_BGA [34C4] U7D1 LOKI_BGA [7C7 7C2 7C5] ST1P2 SHORT_SM [38B7] R8P9 RESN_402 [53D7] U2C1 SB_BGA [35C5] U7D1 LOKI_BGA [8B7 8B4 8B2] ST1P3 SHORT_SM [38A7] R8U1 RESN_603 [51B2] U2C1 SB_BGA [36C5] U7D1 LOKI_BGA [59B3] ST2F1 SHORT_SM [55C1] R8U2 RESN_402 [51B3] U2C1 SB_BGA [37C4] U7E1 AT25020A_SOI8 [4A3] ST2F2 SHORT_SM [55C3] R8U3 RESN_402 [51C5] U2C1 SB_BGA [38B5] U7F1 FET_VREG_DUAL [57C3] ST2P1 SHORT_SM [38C7] R8U4 RESN_402 [51B2] U2D1 SN74LVC1G125_ [12B2] _1_SO-8 ST2P2 SHORT_SM [37B7] R8U5 RESN_402 [51D5] SC70 U7U2 IR3638_SSOP [57C4] ST2P3 SHORT_SM [37C7] R8U6 RESN_402 [57B4] U2E1 NAND_TSOP [42B3] U8N1 NCP5331_LQFP3 [53C5] ST2P4 SHORT_SM [37A7] R8U7 RESN_402 [57C5] U2E2 SN74LVC1G125_ [12D2] 2 ST3G1 SHORT_SM [55C3] R8U8 RESN_402 [57C6] SC70 U8U1 ADP3190A_TSSO [51C4] ST4C1 SHORT_SM [28A7] R8U9 RESN_402 [57C6] U2R1 SN74LVC1G125_ [12A2] P28 ST4C2 SHORT_SM [28A7] R8U10 RESN_603 [51A7] SC70 U9P1 MOSDRIVER_SOI [52D6] ST4C3 SHORT_SM [28A7] U2T1 NCP1117_DPAK [54A5] 8 R8U11 RESN_402 [51A5] ST4C4 SHORT_SM [28A7] U3D1 GDDR136_BGA13 [23C6 23C2] U9T1 MOSDRIVER_SOI [52B6] R8U12 RESN_402 [57A5] ST4C5 SHORT_SM [28A7] 6 8 R8U13 RESN_402 [51A7] ST5R1 SHORT_SM [53B7] U3E1 GDDR136_BGA13 [25C2 25C6] U9U1 MOSDRIVER_SOI [52A6] R8U14 RESN_402 [57B2] ST5R2 SHORT_SM [53D7] 6 8 R8V1 RESN_603 [51B7] ST5V1 SHORT_SM [55C7] U3P1 NCP1117_SOT22 [56A7] Y3B1 CRYSTAL_SM [27D8] R8V2 RESN_603 [51B7] ST6D1 SHORT_SM [6C7] 3 R8V3 RESN_603 [51B6] ST6F1 SHORT_SM [55C8] U3R1 GDDR136_BGA13 [24C2 24C6] R8V4 RESN_603 [51B7] ST6F2 SHORT_SM [55C7] 6 R8V5 RESN_603 [51B6] U3T1 GDDR136_BGA13 [26C6 26C2] ST6R1 SHORT_SM [6B7] R8V6 RESN_603 [51C6] 6 ST6R2 SHORT_SM [6A7] R8V7 RESN_603 [51C6] U4C1 AT25020A_SOI8 [13A4] ST7D1 SHORT_SM [6A7] R8V9 RESN_603 [51C6] U4C2 HANA_BGA225 [27C5] ST7D2 SHORT_SM [57B2] R8V10 RESN_805 [51D6] U4C2 HANA_BGA225 [28C4] ST7R1 SHORT_SM [6C7] R9B1 RESN_402 [53B2] U4C2 HANA_BGA225 [30C5] ST7T1 SHORT_SM [51B4] R9C1 RESN_805 [52C2] U4C2 HANA_BGA225 [31B5] ST7T2 SHORT_SM [51A8] R9E1 RESN_805 [52B2] U4D1 NBY2_BGA [12C6] ST8C1 SHORT_SM [53A8] R9F1 RESN_805 [52A2] U4D1 NBY2_BGA [13C5] ST8F1 SHORT_SM [51A7] R9G1 RESN_603 [46B7] U4D1 NBY2_BGA [14C7 14C3] TP5A1 TDRX4_TH [62C7] R9G2 RESN_603 [46C7] U4D1 NBY2_BGA [15C7 15C3] TP5A2 TDRX4_TH [62C7] R9P1 RESN_805 [52D5] U4D1 NBY2_BGA [16C3] TP6A1 TDRX2_TH [62A1] R9P2 RESN_805 [52D7] U4D1 NBY2_BGA [17B7 17B2 TP6A2 TDRX2_TH [62B1] R9T1 RESN_805 [52C5] 17B5 17B3] TP6D1 PROBE_SMT [4C7] U4D1 NBY2_BGA [59C8] R9T2 RESN_805 [52C7] TP7A1 TDRX4_TH [62B7] U4F1 GDDR136_BGA13 [19C2 19C6] R9U1 RESN_805 [52A5] TP7A2 TDRX4_TH [62A7] MICROSOFT PROJECT NAME PAGE REV R9U2 RESN_805 [52B7] FALCON_RETAIL 82/82 1.0 TP7M1 TDRX2_TH [62C1] R9V1 RESN_603 [46A7] CONFIDENTIAL