CR-1 : @FALCON_LIB.FALCON(SCH_1):PAGE1 SCHEMATIC REV PCBA NUMBER REV BOM RELEASE DATE 1.0 X8XXXXX-001 D XX/XX/06 PAGE CONTENTS PAGE CONTENTS [1] COVER PAGE [33] SB, PCIEX + SMM GPIO + JTAG [2] CLOCK DIAGRAM [34] SB, SMC [3] RESET/ENABLE DIAGRAM [35] SB, FLASH + USB + SPI [4] CPU, CLOCKS + EEPROM + STRAPPING [36] SB, ETHERNET + AUDIO + SATA [5] CPU, FSB [37] SB, STANDBY POWER + DECOUPLE [6] CPU, FSB POWER + PLL POWER [38] SB, MAIN POWER + DECOUPLE [7] CPU, CORE POWER [39] SB OUT, ETHERNET [8] CPU, POWER [40] SB OUT, AUDIO [9] CPU, DECOUPLING [41] SB OUT, FLASH FALCON [10] CPU, DECOUPLING [42] SB OUT, FAN + INFRARED + BUTTONS [11] CPU, DECOUPLING [43] CONN, AVIP [12] GPU, FSB [44] CONN, RJ45 + USB COMBO RETAIL [13] GPU, VIDEO + PCIEX + EEPROM [45] CONN, GAME PORTS + MEMORY PORTS [14] GPU, MEMORY CONTROLLER A + B [46] MISC, V_5P0 DUAL, DEBUG MAPPING REV 1.0 [15] GPU, MEMORY CONTROLLER C + D [47] CONN, ODD AND HDD [16] GPU, PLL POWER + FSB POWER [48] CONN, ARGON + POWER FAB D [17] GPU, CORE POWER + MEM POWER [49] VREGS, INPUT + OUTPUT FILTERS [18] GPU, DECOUPLING [50] VREGS, CPU CONTROLLER [19] MEMORY, A (TOP) [51] VREGS, GPU OUTPUT PHASE 1,2,3 [20] MEMORY, A MIRRORED (BOTTOM) [52] VREGS, GPU CONTROLLER [21] MEMORY, B (TOP) [53] VREGS, GPU OUTPUT PHASE 1,2 [22] MEMORY, B MIRRORED (BOTTOM) [54] VREGS, SWITCHED 1.8, 5.0V [23] MEMORY, C (TOP) [55] VREGS, LINEAR REGULATORS [24] MEMORY, C MIRRORED (BOTTOM) [56] XDK, DEBUG CONN [25] MEMORY, D (TOP) [57] DEBUG BOARD, CPU + GPU BREAKOUT [26] MEMORY, D MIRRORED (BOTTOM) [58] DEBUG BOARD, CPU CONN [27] HANA, CLOCKS + STRAPPING [59] DEBUG BOARD, CPU CONN + TERM [28] HANA, VIDEO + FAN + JTAG [60] DEBUG BOARD, CPU TERM [29] CONN, HDMI [61] DEBUG BOARD, TITAN + YETI CONN [30] HANA, POWER + DECOUPLING [62] DEBUG BOARD, GPU CONN + TERM [31] HANA, POWER + DECOUPLING [63] XDK, LEDS, BDCM PHY [32] POWER TRACE EMI CAPS [64] LABELS AND MOUNTING, PCI SWIZ [65-6] MEM QUAL BOARDS RULES: (APPLIED WHEN POSSIBLE) 1.) MSB TO LSB IS TOP TO BOTTOM FALCON 2.) WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT 3.) ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING 4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS PLEASE REFER TO THE XENON DESIGN SPEC 5.) LANED SIGNALS ARE GROUPED ON SYMBOLS 6.) TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS 7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES 8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS BOM RELEASE DATE XX/XX/06 PB NUMBER X80XXXX-00X 9.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE 10.) SUFFIX _N FOR ACTIVE LOW OR N JUNCTION SIGNATURE DATE 12.) SUFFIX _P FOR P JUNCTION DRN BY MICROSOFT XBOX 13.) SUFFIX _EN FOR ENABLE 14.) 'CLK' FOR CLOCKS, 'RST' FOR RESETS CHK BY TITLE 15.) PWRGD FOR POWER GOOD ENGR SCH, PBA, FALCON DRAWING APVD PROJECT NAME PAGE REV FALCON_FABD APVD MICROSOFT Tue May 08 18:21:43 2007 FALCON_RETAIL 1/82 1.0 [PAGE_TITLE=COVER PAGE] APVD CONFIDENTIAL CR-2 : @FALCON_LIB.FALCON(SCH_1):PAGE2 RJ45/USB AVIP CONN CONN POWER FAN * THIS IS OUT OF DATE * CONN CONN ENET_CLK(25MHZ) CLOCK DIAGRAM ENET PHY I2S_MCLK(12.288MHZ) AUDIO ANA_XTAL_IN(27MHZ) I2S_BCLK(3.072MHZ) DAC GPU VR DEBUG CONN ANA ANA BCKUP GPU VR STBY_CLK(48MHZ) CNTL SATA_CLK_REF(25MHZ) SB SATA_CLK_DP/DN(100MHZ) DVD PCIEX_CLK_DP/DN(100MHZ) SATA AUD_CLK(24.576MHZ) CONN CPU_CLK_DP/DN(100MHZ) RISCWATCH PIX_CLK_OUT_DP/DN(100MHZ) CONN GPU_CLK_DP/DN (100MHZ) DVD PWR CONN MC_CLK1_DP/DN(800MHZ) ANA MC_CLK0_DP/DN(800MHZ) BCKUP MEM MD_CLK1_DP/DN(800MHZ) GPU CPU CPU CLAM C+D MD_CLK0_DP/DN(800MHZ) VR 1P8 VR FLSH HDD CONN TITAN JTAG MA_CLK1_DP/DN(800MHZ) MA_CLK0_DP/DN(800MHZ) MB_CLK1_DP/DN(800MHZ) MB_CLK0_DP/DN(800MHZ) 3P3 VR CONN VMEM VR MEM EFUSE VR CLAM A+B CPU VR CNTL MPORT VR 5P0 VR GAME CONN EJECT MEM MEM BIND ARGON IR SW CONN CONN SW CONN DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV <PAGE_TITLE=CLOCK DIAGRAM> Tue May 08 11:47:32 2007 FALCON_RETAIL 2/82 1.0 CONFIDENTIAL CR-3 : @FALCON_LIB.FALCON(SCH_1):PAGE3 RJ45/USB AVIP CONN CONN POWER FAN CONN CONN RESET/ENABLE DIAGRAM ENET PHY ENET_RST_N AUD_CLAMP AUDIO AUD_RST_N DAC PSU_V12P0_EN GPU VR EXT_PWR_ON_N HANA_CLK_OE HANA_RST_N HANA VREG_GPU_EN_N GPU VR CNTL SMC_RST_N DVD SB VREG_GPU_PWRGD SATA EXT_PWR_ON_N CONN CPU_CHECKSTOP_N SB_RST_N CPU_RST_N CPU_PWRGD GPU_RST_N RISCWATCH DVD GPU_RST_DONE CONN PWR CONN CPU MEM_RST VR MEM_SCAN_EN MEM MEM_SCAN_TOP_EN SMC_DBG_EN CLAM C+D MEM_SCAN_BOT_EN GPU CPU VREG_3P3_EN VREG_CPU_PWRGD HDD 3P3 CONN VR MEM_RST MEM_SCAN_EN CPU_PWRGD MEM_SCAN_TOP_EN MEM_SCAN_BOT_EN TITAN JTAG MEM CONN DEBUG CLAM A+B CONN VREG_1P8_EN_N VMEM VR EFUSE VR VREG_5P0_EN_N CPU VR 5P0 VR CNTL VREG_EFUSE_EN VREG_CPU_EN GAME CONN EJECT MEM MEM BIND ARGON IR SW CONN CONN SW CONN DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=RESET/ENABLE DIAGRAM] Tue May 08 11:47:32 2007 FALCON_RETAIL 3/82 1.0 CONFIDENTIAL CR-4 : @FALCON_LIB.FALCON(SCH_1):PAGE4 CPU_RST_V1P1_N 58 OUT CPU, CLOCKS + EEPROM + STRAPPING CPU_RST_N 1 R7R4 2 34 IN 3.92K 1% 1 R6D4 2 402 CH 1 27 CPU_CLK_DP 1 R7R16 2 C7R112 IN FT2P11 FTP 1 360PF 0 5% CPU_CLK_DP_C 10% 402 CH 6.19K 1% 50V FT2P12 FTP 1 402 CH 2 EMPTY 603 1 R7R10 2 34 CPU_PWRGD CPU_PWRGD_V1P1_N 1 R6D5 2 IN 27 CPU_CLK_DN 3.92K 1% IN 402 CH 0 5% 1 402 CH V_GPUCORE 1 R7R11 2 C7R113 360PF 6.19K 1% 10% U7D1 1OF10 IC V_GPUCORE 402 CH 50V CPU_CLK_DN_C LOKI TP7R1 2 EMPTY PROBE 2 R6R4 1 603 AG23 CORE_CLK_DP CORE_IF_BGR_PLL AH15 CPU_CORE_IF_BGR_PLL 1 1K 5% TP6D1 AF23 CORE_CLK_DN 2 1 402 CH PROBE 1 1 R6R6 AF1 C7 VREG_EFUSE_EN SMT R6R9 R6R5 2 HARD_RESET_B EFU_POWERON OUT 56 10K 2 1 AD14 POWER_GOOD 10K 5% 5% 1K 5% SMT EMPTY FSB_CLK_DP AH21 AF20 CPU_FSB_HF_CLKOUT_DP CH 402 402 CH FSB_CLK_DP FSB_HF_CLKOUT_DP OUT 402 2 FSB_CLK_DN AH20 FSB_CLK_DN FSB_HF_CLKOUT_DN AG20 CPU_FSB_HF_CLKOUT_DN 2 OUT CPU_FSB_CLK_SEL AE16 FSB_CLK_SEL FSB_IMPED_CAL_DP AH23 CPU_FSB_IMPED_CAL_DP OUT FSB_IMPED_CAL_DN AH22 CPU_FSB_IMPED_CAL_DN OUT CPU_EXT_CLK_EN AD16 EXT_CLK_EN 1 TP7R3 PROBE R6R8 CPU_PLL_BYPASS AF14 PLL_BYPASS 10K 1 RESISTOR0_DP AH12 CPU_RES0_DP 1 5% 1 RESISTOR0_DN AH13 CPU_RES0_DN 2 R6R7 CPU_PULSE_LIMIT_BYPASS AG14 PULSE_LIMIT_BYPASS EMPTY 10K TP7R4 R7R17 SMT 402 5% 10K 1 PROBE 2 1 1 CH 5% R7D1 DB7R2 VDDS0_DP AF11 CPU_VDDS0_DP 1 402 CH 10K R7D2 VDDS0_DN AH10 CPU_VDDS0_DN 2 TP7R2 2 402 5% 10K V_GPUCORE PROBE 2 5% SMT CH CPU_SYS_CONFIG0 AH3 SYS_CONFIG0 VDDS1_DP AG2 CPU_VDDS1_DP 1 EMPTY 402 CPU_SYS_CONFIG1 AE2 SYS_CONFIG1 VDDS1_DN AH1 CPU_VDDS1_DN 2 2 402 2 CPU_POST_IN<0..4> SMT DB7R1 0 AF8 POST_IN0 TP V_GPUCORE 1 1 AG8 POST_IN1 1 PSRO0_OUT AE14 CPU_PSRO0_OUT 1 2 AH7 POST_IN2 R7R15 V_CPUCORE 100 R7R8 3 AH8 POST_IN3 100 1 5% 4 AH9 POST_IN4 5% EMPTY R7R9 402 EMPTY 10K 2 402 1 5% 2 4 CPU_SPI_SI C4 SPI_SI SPI_CLK B4 CPU_SPI_CLK 4 IN OUT CH R7T18 SPI_EN A3 CPU_SPI_EN 4 LAYOUT: MUST BE ACCESSIBLE 10K OUT 402 SPI_SO A4 CPU_SPI_SO 4 2 5% OUT 2 R6E1 CH AH18 CPU_TEMP_P 402 TEMP_DP IN 28 10K 2 OUT CPU_ANL_1 AE22 ANL_1 TEMP_DN AH19 CPU_TEMP_N OUT 28 5% OUT CPU_ANL_2 AD22 ANL_2 CH VID0 C5 CPU_VREG_APS0 50 402 OUT 1 57 OUT CPU_SRVID A2 SRVID VID1 B6 CPU_VREG_APS1 OUT 50 CPU_VGATE AH14 VGATE VID2 A5 CPU_VREG_APS2 OUT 50 B5 CPU_VREG_APS3 VID3 OUT 50 CPU_TEST_EN AF2 TE VID4 A6 CPU_VREG_APS4 50 V_GPUCORE V_1P8 OUT VID5 C6 CPU_VREG_APS5 OUT 50 1 R7R1 2 1 1 1 FTP FT7T5 X806937-001 FTP FT7T2 1 1.40K 1% R7R14 1 FTP FT7T4 10K FTP FT7T1 1 402 CH 1 FTP FT7T3 5% FTP FT7T7 1 1 1 1 1 CH CPU R7R1 R7R2 1 R7R2 2 402 R7R21 R7R12 R7R13 R7R22 R7R23 2 LOKI 1.40K 1K V_MEM V_MEM 10K 10K 10K 10K 10K 1K 1% ASPEN EMPTY 10K 5% 5% 5% 5% 5% 402 CH CH CH CH CH CH 402 402 402 402 402 2 2 2 2 2 1 1 V_MEM C6F1 .1UF R7F3 0 1 2 3 4 10% U7E1 EMPTY 6.3V 10K 2 X5R 5% AT25020A 402 EMPTY 1 1 1 1 1 R6E2 4 CPU_SPI_CLK CPU_SPI_CLK_R 6 SCK VCC 8 402 IN 2 R7R20 R7R5 R7R3 R7R19 R7R18 1K 5% CPU_SPI_SO_R 5 SDI 10K 10K 10K 10K 10K 2 R7F7 1 402 CH SDO 2 CPU_SPI_SI_R CPU_SPI_SI 4 5% 5% 5% 5% 5% OUT 7 HOLD_N* EMPTY EMPTY EMPTY EMPTY EMPTY R7E7 1K 5% 4 CPU_SPI_SO CPU_SPI_EN_R 1 CS_N* 402 CH 402 402 402 402 402 IN 1 2 2 2 2 2 1K 5% 3 WP_N* GND 4 V_MEM R7F4 FT7R4 FTP 1 4 402 CH V_MEM 1 100 FT7R6 FTP 3 X800552-001 5% 1 2 FT7R2 FTP 2 R7E8 1 CH FT7R1 FTP 1 1 1 402 FT7R5 FTP 1 0 R7U3 10K 5% 2 10K 402 CH 5% CH 2 R7F1 1 402 2 CPU_SPI_EN R7F2 10K 5% CPU_SPI_WP_N 4 IN 402 EMPTY IN 1K 5% 402 CH DRAWING FALCON_FABD MICROSOFT PROJECT NAME PAGE REV [PAGE_TITLE=CPU, CLOCKS + EEPROM + STRAPPING] Tue May 08 18:24:08 2007 FALCON_RETAIL 4/82 1.0 CONFIDENTIAL CR-5 : @FALCON_LIB.FALCON(SCH_1):PAGE5 CPU, FSB U7D1 2OF10 IC LOKI FSB_GP_CP0_CLK_DP V28 AE27 FSB_CP_GP0_CLK_DP 12 IN GP_CP0_CLK_DP CP_GP0_CLK_DP OUT 12 FSB_GP_CP0_CLK_DN V27 AE28 FSB_CP_GP0_CLK_DN 12 IN GP_CP0_CLK_DN CP_GP0_CLK_DN OUT 12 FSB_GP_CP0_FLAG_DP AB27 AH25 FSB_CP_GP0_FLAG_DP 12 IN GP_CP0_FLAG_DP CP_GP0_FLAG_DP OUT 12 FSB_GP_CP0_FLAG_DN AB28 AH26 FSB_CP_GP0_FLAG_DN 12 IN GP_CP0_FLAG_DN CP_GP0_FLAG_DN OUT 12 FSB_GP_CP0_DATA0_DP T26 AB26 FSB_CP_GP0_DATA0_DP 12 IN GP_CP0_DATA0_DP CP_GP0_DATA0_DP OUT 12 FSB_GP_CP0_DATA0_DN T25 AB25 FSB_CP_GP0_DATA0_DN 12 IN GP_CP0_DATA0_DN CP_GP0_DATA0_DN OUT 12 FSB_GP_CP0_DATA1_DP T28 AC27 FSB_CP_GP0_DATA1_DP 12 IN GP_CP0_DATA1_DP CP_GP0_DATA1_DP OUT 12 FSB_GP_CP0_DATA1_DN T27 AC28 FSB_CP_GP0_DATA1_DN 12 IN GP_CP0_DATA1_DN CP_GP0_DATA1_DN OUT 12 FSB_GP_CP0_DATA2_DP U27 AD28 FSB_CP_GP0_DATA2_DP 12 IN GP_CP0_DATA2_DP CP_GP0_DATA2_DP OUT 12 FSB_GP_CP0_DATA2_DN U28 AD27 FSB_CP_GP0_DATA2_DN 12 IN GP_CP0_DATA2_DN CP_GP0_DATA2_DN OUT 12 FSB_GP_CP0_DATA3_DP V26 AD25 FSB_CP_GP0_DATA3_DP 12 IN GP_CP0_DATA3_DP CP_GP0_DATA3_DP OUT 12 FSB_GP_CP0_DATA3_DN V25 AD26 FSB_CP_GP0_DATA3_DN 12 IN GP_CP0_DATA3_DN CP_GP0_DATA3_DN OUT 12 FSB_GP_CP0_DATA4_DP W27 AF28 FSB_CP_GP0_DATA4_DP 12 IN GP_CP0_DATA4_DP