2015

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 19, Number 4 WINTER

14th ANNUAL MEPTEC MEMS TECHNOLOGY SYMPOSIUM

Advancing MEMS and Sensors for Today’s Exploding Demands Wednesday, May 11, 2016 San Jose, California + page 22 The Great Miniaturization Symposium Follow-Up page 15 MEPTEC MEMBER COMPANY PROFILE Now in its 43rd year, SHENMAO TECHNOLOGY INC., the leading solder material provider globally, started by manu- facturing resin flux cored solder wire and solder bar in 1973 at its Headquarters, continuously expanding since 1998 to 10 worldwide locations. page 18

-Corp. INSIDE THIS ISSUE

Semico Research SiP module packaging The technology of IC The large number Corp. looks at provides an alternative packaging has over- of mergers and the growing and and complementary taken chip fabrication acquisitions this last changing SoC solution to System- as the focal point of year has been truly market. on-Chip. innovation. staggering. 13 23 26 SPRING 342011 MEPTEC Report 3 Wear Sense Move it. it. it.

Innovative IC, System-in-Package, and MEMS packaging portfolio for today’s miniaturization, mobility, and IoT needs.

Wire Flip 2.5D WLP Fanout SiP Bond Chip & 3D

Package it. Visit: aseglobal.com 2015 The MEPTEC Report is a Publication of the Microelectronics Packaging & Test Engineering Council 315 Savannah River Dr., Summerville, SC 29485 Tel: (650) 714-1570 Email: [email protected]

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 19, Number 4 WINTER Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown Sales Manager Gina Edwards 2015 ON THE COVER A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 19, Number 4 WINTER

14th ANNUAL MEPTEC MEPTEC Advisory Board MEMS TECHNOLOGY MEPTEC presents its 14th Annual MEMS Technology Symposium titled SYMPOSIUM

Advancing MEMS for Today’s Exploding Demands “Advancing MEMS and Sensors for Today’s Exploding Demands” on Wed- Wednesday, May 11, 2016 Board Members San Jose, California page 22 + nesday, May 11 2016 at the Holiday Inn - San Jose Airport in San Jose, The Great Miniaturization Xilinx, Inc. Symposium Follow-Up Ivor Barber page 15 California. Invited speakers will focus on the fundamental MEMS technolo- MEPTEC MEMBER COMPANY PROFILE Now in its 43rd year, SHENMAO TECHNOLOGY INC., the leading solder material provider globally, started by manu- facturing resin flux cored solder wire and solder bar in 1973 Delphon Industries at its Taiwan Headquarters, continuously expanding since gies and manufacturing techniques to address this explosive growth short to Jeanne Beacham 1998 to 10 worldwide locations. page 18

-Corp. INSIDE THIS ISSUE medium term, but also take a peek at what’s coming longer term that we all Semiops Semico Research SiP module packaging The technology of IC The large number Joel Camarda Corp. looks at provides an alternative packaging has over- of mergers and the growing and and complementary taken chip fabrication acquisitions this last changing SoC solution to System- as the focal point of year has been truly market. on-Chip. innovation. staggering. 13 23 26 SPRING 342011 MEPTEC Report 3 need to be aware of today. Jeff Demmin Booz Allen Hamilton Douglass Dixon Henkel Corporation

ANALYSIS Exar Corporation think and are treated like engineers and Nikhil Kelkar that management assigns them clearly CAN YOUR EPOXY ANALYSIS – The SoC market has been growing and defined projects that don’t easily change scope. (This implies a healthy relation- ADHESIVE GO LOW? ship between marketing and engineering, An Inside Look at the System-on-a-Chip which of its own, is a worthy discussion.) Epoxy System EP42HT-2LTE Let’s focus on the corporate culture and Features an ultra low coefficient (SoC) Market not on job titles to improve the quality of software. of thermal expansion Adrienne Downey, Director of Technology For more of my thoughts, please see X -6 in in CTE 9-12 10 / /°C Semico Research Corp. my blog http://hightechbizdev.com. TechDirect Consulting evolving for the last 15 - 20 years and is a very complex As always, I look forward to hearing LOW SHRINKAGE UPON CURE Nick Leonardi your comments directly. Please contact me to discuss your thoughts or if I can be Linear <0.01% ◆ 13 of any assistance. Volumetric <0.1% THE SOC MARKET HAS BEEN EVOLUTION OF THE ASIC MARKET growing and evolving for the last 15 - 20 Programmable years and is a very complex combination SoC Advanced IRA FELDMAN (ira@feldmanengineer- Elongation <5% of semiconductor solutions that fills every Performance Multicore SoC ing.com) is the Principal Consultant possible niche in the electronics market Standard System on System(s) today. Semico Research Corp. looks at Cell a Chip on a Chip combination of semiconductor solutions that fills every pos- of Feldman Engineering Corp. which Value this market on a regular basis and pub- Multi-core guides high technology products and HIGH DIMENSIONAL STABILITY lishes research on its makeup, direction Application SoC Basic SoC PPM Associates Custom Specific Standard Platform Phil Marcoux services from concept to high volume and evolution. ASIC Products (ASSP) SoC Customer From -60 to +300°F Platform To get a better understanding of the Owned Tooling manufacturing. He engages on a wide ASIC range of projects including technical SoC market, it is important to understand Gate Array Structured where it came from and what its roots are. ASIC marketing, product-generation process- Simple / Field Programmable Hackensack, NJ 07601, USA As Figure 1 shows, the origin of Programmable Complex Computing es, supply-chain management, and busi- Logic Device (PLD) +1.201.343.8983 ∙ mainmasterbond.com the ASIC market was the rise of what PLD System on a Array were called full custom designs in the Programmable ness development. Chip sible niche in the electronics market today. Semico Research www.masterbond.com Field mid-1970s. These devices were usually FPGA Programmable FPGA / SoC produced by large IDMs only for specific Analog Array with customers. In most cases, the customer Programmable Dow Chemical Corp. Fabric supplied the design to the IDM. The Bhavesh Muni 1974 1980 1986 1988 1997 1999 2000 2001 2002 2006 2009 2010 2012 Register now! customer consumed all the output of the March 6—9,2016 • Mesa,a rizona IDM and used the parts internally. As the Figure 1. History of the ASIC Market. (Source: Semico Research Corp.) semiconductor market grew, new types of devices arose to help meet the needs of Corp. looks at this market on a regular basis and publishes customers and markets alike. designers to be used in the creation of SoC in the market today. (see Figure 2) Around 1980, the ASIC market these designs. To track this market accu- The reason for the market evolution fragmented into three basic types: Gate rately, Semico has created a paper defini- to create a separate SoC segment was to Arrays, Standard Cells and Programmable tion that details the three main classes of provide designers with more flexibility to Logic. Later, as the demand grew for

Maxim Integrated s olutions © 2015 BiT Workshop certain types of systems, the Application Kumar Nagarajan Specific Standard Product category arose. Revised Revised The World’s Premier Event for Definitions Metrics featuring This class of device filled a gap between What’s Now & Next in Test and the three standard types of ASIC. Advanced 2+ IP Subsystems Performance 3+ Complex Interconnects research on its makeup, direction and evolution. MeMs test In the mid-1990s, the ASIC market Traditional Traditional >150 Discrete IP Blocks Burn-in of Packaged IC’s Definitions Multicore SoCs & wLcsp test again reached a point where the standard Metrics Celebrating seventeen years of exCellenCe, approaches for creating an ASIC were Value Performance 1+ IP Subsystems no longer satisfying customer or market 10M+ Gates Multicore 2+ Complex Interconnects the annual bits Workshop brings together experts SoCs needs, and another wave of innovation >16Mb Memory SoCs 75 - 150 Discrete IP Blocks and exhibitors in the field of test and burn-in from and fragmentation started with the advent around the world. Join your colleagues in arizona of the SoC. From a single type of SoC, Value Basic 1+ Bus Structure STATS ChipPAC 4 - 10M Gates or 1 Complex Interconnect for three days of speakers, technical programs, we now have moved to a market environ- 2 - 8Mb Memory SoCs SoCs ≥ 50 - 75 Discrete IP Blocks anium; Teradyne; Test Tooling Tooling Test i nc.; n anium; Teradyne; os: BBCFC/i s tock; miths Connectors; Cohu, Raj Pendse T ment where it is possible for different networking opportunities, exPo 2016, and more! Pho types of SoC to co-exist to fill necessary Simple Bus Structure 1 - 4M Gates Commodity Microcontrollers ≥ 10 - 20 Discrete IP Blocks market niches. 1 - 2Mb Memory Controllers PRemieR sPonsoR Very Low Cost

inDusTRy PaRTneR Reitzle Design: T. A major component of the SoC mar- ket is the use of 3rd Party Semiconductor Moore’s Law Continues www.bitsworkshop.org Intellectual Property (SIP) and SIP that RICH WAWRZYNIAK was created for reuse internally by the Figure 2. SoC Definition by Complexity. (Source: Semico Research Corp.) ASE (US) Inc. 12 MEPTEC REPORT WINTER 2015 meptec.org meptec.org WINTER 2015 MEPTEC REPORT 13 Rich Rice SEMICO RESEARCH CORP. Jim Walker Gartner Altera Corporation John Xie PROFILE

SHENMAO HEALTH, SAFETY AND PROFILE – SHENMAO Technology Inc. produces and SHENMAOSHENMAO HISTORY HISTORY ENVIRONMENT CONCEPTS SHENMAO Technology has achieved 1973 Established SHENMAO incorpora- 2006 Set up “SHENMAO Technology (Thai- and is maintaining the ISO 9001, ISO tion to manufacture Resin Flux Solder Wire land) Co., Ltd.”, plant and office in Thailand 14001, TS 16949, OHSAS 18001 and QC and Solder Bar. and “SHENMAO Europe GmbH” in Munich, 080000 Standards. In the future, SHEN- Germany. MAO Technology Inc. and their subsidiar- 1978 Expanded Plant and changed com- SHENMAO TECHNOLOGY INC. Now in its 43rd year, SHENMAO Technology Inc., founded by Mr. San Lian pany Name to SHENMAO Industry Co. Ltd. 2007 Signed a contract with SMIC for ies will continue to follow existing regu- offers total solutions of Solder Materials Lee, Chairman and CEO of the globally leading solder material provider, licensing the patent of Sn-Ag-Cu Lead-Free lations, and seek different international to customers by meeting and exceed- SHENMAO received CNS Certificate Solder. Awarded OHSAS 18001 Certification. standard to pursue the best quality and markets SMT Solder Paste, Solder Spheres, Wafer started by manufacturing resin flux cored solder wire and solder bar in 1982 Special Advisors Awarded ISO/TS 16949 Quality Certification. fulfill the commitment to environmen- ing their quality and reliability require- 1973 at its Taiwan Headquarters, first for Taiwan and then for the Asian Honor No. 3423 & 3424 for best quality Resin ments with products and service satis- Flux Cored Solder Wire and Solder Bar. Established Dongguan Shen Yang Micro tal protection. SHENMAO Technology faction accumulated over four decades market, continuously expanding since 1998 to 10 worldwide locations. Material Co., Ltd. in China. has continually researched and developed 18 of research and development experience. 1986 Invited solder expert Mr. Akiyama green products which are more able to be 2008 Lead-Free Solder Paste approved by from Japan to take charge as Advisor. recycled in order to meet ROHS environ- In the meantime, SHENMAO works Continental AG. Obtained “Taiwan Industrial closely with customers to develop new SHENMAO MICRO MATERIAL INSTITUTE ment protection regulations. The respon- 1987 Obtained Japan Industry Standard Sustainable Excellence Award 2008”, Signed sibilities of SHENMAO are to reduce the application products on nanotechnology In order to research and develop the generation of Solder Material products, SHENMAO (JIS) Certification TW # 8716 & 8717. up Distributor “White Solder Ltda.” in Brazil for the electronics and other industries. established the SHENMAO MICRO MATERIAL INSTITUTE (SMMI) in 2003. The main purpose of and “Persang Alloy Industries Pvt. Ltd.” in impact on the environment, protect the the institute is to study and focus on the development and improvement of Micro Lead Free Bumping Solder Paste, Dipping Flux, Wave Solder Bar, Solder From production to shipment, strictly 1989 Pooled capital with “JSKL” to set up India. Listed SHENMAO Technology Inc. on safety of its employees and customers, and N-Able Group International controlling each step, SHENMAO insists Materials with the highest Quality and Performance. The 1,500 square meter (16,146 Sq. Ft.) an office in Hong Kong and expanded by set- the Taiwan Stock Exchange. support the communities where SHEN- Ron Jones on using high quality raw materials to SMMI is staffed with 36 engineers (3 PhDs, 8 Masters) continuously developing Innovative ting up a plant in Guangdong, China. MAO does business. New Lead Free Solder Alloys, New Lead Free Solder Paste and Fluxes. SMMI’s mission is to produce high quality products. Through 2009 Introduced Wafer Bumping Solder improve on the ability of Product Development for a total solution through technological Paste for . Estab- continuous improvement, cost reduction, 1990 Set up an office and plant of “Shen SHENMAO PRODUCTS innovation. SMMI has been working closely with electronic manufacturers, universities, and lished SHENMAO America, Inc. subsidiary swift sales and service, SHENMAO keeps Mao (M) Sdn. Bdh” in Penang, Malaysia. research organizations in the field for innovated material, technology, and failure analysis. in San Jose, CA, USA to manufacture solder Semiconductor Packaging Material making efforts to help customers to be 1997 SHENMAO obtained ISO 9002 Cer- paste locally for the North American market. competitive, creating a Win-Win situa- tification. Signed up “NEVO GmbH” as European Dis- tion. tributor in Germany and the Czech Republic. Wire, Flux and Solder Preforms distributed from 10 world- SHENMAO Technology Inc., as the 1999 Expanded operations with a second Founded SHENMAO subsidiary SOLARJOIN

third largest Solder Materials provider plant in Suzhou China for mass production TECHNOLOGY, Inc. in Taiwan to provide the Gary Smith EDA founded in 1973, produces and markets for the ever growing demand of high qual- best PV Ribbon, Flux, for the Solar Industry. SMT Solder Paste, Semiconductor Pack- ity Solder Materials to serve the expanding Mary Olsson 2011 Obtained HP re-approval of Halogen electronic manufacturing service companies. aging Solder Spheres, Wafer Bumping Free Lead Free Solder Paste and Halogen In cooperation with ITRI, developed the pro- Solder Paste, Dipping Flux, Wave Sol- Free Liquid Flux. Invested and set up Shen- cess to manufacture solder spheres. der Bar, Solder Wire, Flux and Solder mao Electronics Technology (Chongqing) Preforms distributed from 10 worldwide Limited in Chong Quing City, China P.R.C. 2001 SHENMAO set up a factory to pro- locations as the strategic manufacturing wide locations as the strategic manufacturing partner of duce Solder Powder and with the coop- 2012 HP re-approved existing Low Silver partner of leading OSAT’s, the top EMS eration of JOINT, Japan, to manufacture BGA Content Solder Materials. and OEM’s. and Micro BGA Solder Spheres up to a capac- SHENMAO Technology Inc. strives to ity of 60 Billion per month. Obtained ISO 2013 Introduced Solder Paste and Flux offer the best quality without compromis- 14000 Environment Accreditation. for PoP (Package on Package) applications. ing cost and time-to-market while pro- Founded the SHENMAO Technology Inc. BGA and Micro BGA Solder Spheres viding maximum value to all customers, 2002 SHENMAO launched the latest Lead Branch Office in Japan. always by superior customer service and Free solder products featuring environmen- SHENMAO BGA Solder Spheres for technical support. Customer satisfaction tal concerns, obtained a sub-license from 2014 Started production of Solder Preform PBGA, CBGA, TBGA, CSP and Flip Iowa State University Research Foundation’s made available in Tape and Reel. Chip Assemblies are made by UMT (Ultra leading OSAT’s, the top EMS and OEM’s. and sustainable high quality are always Pb-free Patent No.5527628. SHENMAO’s priority. ) from highly pure met- Honorary Advisors 2015 Put into production Micro BGA Sol- als produced to various exact Alloy com- 2003 Established SHENMAO MICRO MA- der Spheres sizes 55µ and 50µ available in six positions using Piezoelectric Droplet Jet TERIAL INSTITUTE for up-to-date soldering different Alloys. Released Novel Laser Solder- Technology in high volumes to accurate technology research. Obtained ISO 9001 ing Solder Paste and developed machine diameter uniformity, bright shiny surface Quality Certification. Obtained FUJI ELECTRIC to Dispense and Laser Soldering. Released CO., LTD., JAPAN 5 Elements alloy solder (Sn- Novel Laser Soldering Solder Wire. finishes and high quality sphericity.- Vari Ag-Cu-Ni-Ge) Japanese Patent No.3296289; ous diameters (from 0.76 mm to as small U.S. Patent No.6179935B1. 2016 SHENMAO Technology Inc. HQ and as 0.05 mm) are available at affordable plant in Taoyuan, Taiwan will expand add- low cost from 10 worldwide SHENMAO 2004 HP and Dell approved SHENMAO ing a near-by new plant currently under locations. SHENMAO High Drop-Resis- Sunsil Lead-Free Solder Paste. Moved SHENMAO construction with the ability to smelt large tance Alloy PF902-S (SAC0307X) greatly Seth Alavi Headquarters to Taoyuan and expanded the quantity Tin Ore, providing SHENMAO with increases reliability and performance of manufacturing plant. its own Tin supply. portable electronic devices drop test. SHENMAO TECHNOLOGY INC.

18 MEPTEC REPORT WINTER 2015 meptec.org meptec.org WINTER 2015 MEPTEC REPORT 19 Gary Catlin MEMBER COMPANY PROFILE Rob Cole Skip Fehr PACKAGING – The sophistication of consumer prod- SYMPOSIUM PACKAGING 14th ANNUAL MEPTEC System-in-Package (SiP) – Shifting the Market

William Chen, Senior Technical Advisor MEMS TECHNOLOGY ASE Group Elle Technology ucts emerging today demands more diverse functional- AS WE MOVE TOWARDS A MARKET Anna Gualtieri that’s becoming dominated by personal SYMPOSIUM devices, we are seeing extensive creation 23 and proliferation of connected devices and systems. How will this impact both industry and society in order to meet Advancing MEMS for Today’s Exploding Demands related requirements? One reinterpretation of the promise of integration is moving ity – logic, memory, MEMS, sensors, mixed signal, RF, power, towards heterogeneous integration through System-in-Package (SiP). ICINTEK Wednesday, May 11, 2016 SiP module packaging provides an Marc Papageorge alternative and complementary solution Crossing Boundaries – SiP to Modules San Jose, California to System-on-Chip (SoC) for system integration and miniaturization, while adoption within mainstream semiconduc- why SiP is currently stimulating height- reducing development time, design cost, tor manufacturing. Chief among these ened interest and discussion across the time to market, and total cost of owner- are the rapid development and imple- expanding electronics ecosystem. Many ship. The sophistication of consumer mentation of new and innovative IoT and ecosystem players are coming to realize and passives, all heterogeneous components – integrated into f you are involved in the MEMS and Sensors Industry today, or are thinking about entering it, you are in the right place at the right time. products emerging today demands more mobile products requiring heterogeneous the numerous benefits, including inte- Double digit growth fueled by inertial and other sensors in , wearables, and a plethora of IOT applications have garnered the diverse functionality – logic, memory, components and affordable development grated/embedded passives, heterogeneous I attention of many who not only see the financial rewards but also the possibilities of new and exciting markets. MEMS, sensors, mixed signal, RF, power, costs, as well as the creation of differenti- components, smaller and simplified sys- and passives, all heterogeneous compo- ated platform solutions through system tem boards, reduced power consumption, With this renewed growth comes a desire to reduce costs, decrease throughput times, scale to much larger volumes faster and continually in- nents – integrated into a single package integration and optimization. and decreased component size and thick- novate with existing MEMS and sensors while preparing for the untapped broader markets. Linear technical innovations in design, processes, with a smaller and lighter form factor. Some leading players within the ness. Further simplification is achieved materials, packaging and test are enabling widespread commercialization of breakthrough MEMS products. While this is absolutely necessary Besides the traditional SoC solutions, SiP Outsourced Assembly and Test (OSAT) through module level test and qualifica- to meet today’s demands, will it be sufficient for the future five to ten years from now? If we believe the analysts and commercial companies is now increasingly being explored and community are moving beyond their tion, reduced system BOM and complex- predicating tens of billions of connected nodes and sensor arrays by 2020, can our industry keep up by sticking to the path we are on? implemented by design houses and system established core competencies and are ity, as well as the significant fact that SiP In Memoriam a single package with a smaller and lighter form factor. MEMS sensing applications will track growth in CE, mobile, wearable’s, medical, food and agriculture, environmental, energy and the catch all companies to meet new requirements for positioning themselves to serve the technology is flexible, re-usable, and re- IOT/IOE markets. The 14th Annual MEPTEC MEMS Technology Symposium will focus on the fundamental MEMS technologies and manufactur- their product development. industry’s SiP needs through leveraging configurable. SiP technology flexibility is ing techniques to address this explosive growth short to medium term but also take a peek at what’s coming longer term that we all need to According to the ASE Group, SiP can advanced IC packaging technologies to particularly important to design in product be aware of today. If you are involved in MEMS and Sensors design, processes, packaging, test and system integration you will not want to miss be defined as “a package or module that enable new generations of miniaturized functionality and differentiation, and per- this one-day action packed and informative event. contains a functional electronic system or electronic systems. Recent developments haps generating innovation in contributing subsystem that is integrated and miniatur- in advanced packaging technologies – to solutions that address concerns relating Topics to include: ized through IC assembly technologies.” wafer level packaging, fanout chip-first to privacy and security. MEMS Design – reusability and enabling faster time to market Test – design for MEMS testing and future trends Essentially, the subsystems are made up and chip-last, embedding packaging, TSV In summary, the industry is driving Process Technologies – from prototypes to production better, faster cheaper Emerging Technologies – flexible, hybrid and printed of individual dies that are manufactured 2.5D, wirebond and flip chip re-inventions towards functional diversification, hetero- Packaging – current and advanced techniques to scale more devices MEMS and sensors separately, each using its own most cost- – have great potential for addressing geneous integration and miniaturization, and functional in one package effective node. For example, the ASIC (a a broad spectrum of SiP applications. with SiP establishing itself across the Bance Hom SoC) could be in one technology node, Through established expertise in core industry, supply chain, and ecosystem. additional memories in different nodes, competencies, IC packaging technology The drive for heterogeneous device inte- peripherals in still another node, together enables highly integrated and miniatur- gration, decreased size, lower cost, and WILLIAM CHEN with discrete and integrated passives, ized modular products. In addition, it is reduced time to market and revenue is MEMS, and different sensors. These com- crucial to understand the different market leading many established and emerging REGISTER ONLINE TODAY AT WWW.MEPTEC.ORG ponents can be successfully assembled segments and to provide SiP co-design players to explore the value proposition inside the package through a variety of and co-development initiatives to support of SiP. As an industry, we are at an early established techniques – perhaps together OEM product roadmap execution in these stage of a collaborative work-in-process. Platinum Sponsor Media Sponsors with additional features such as antennas segments. With this understanding, it is There is much work that needs to be done and shielding – in existing high-volume possible to deliver rapidly scalable, high- in the ecosystem to innovate new ideas manufacturing infrastructures. SiP is still quality, high-precision, and cost-effective and to implement new solutions to bring ASE GROUP in its early stages. There are many com- SiP manufacturing capacity. SiP fully into the mainstream. ◆ Your Microelectronic Package Assembly pelling industry dynamics driving SiP There are many compelling reasons Solution for MEMS Sensors meptec.org WINTER 2015 MEPTEC REPORT 23 Contributors

SemiOps Joel Camarda TECHNOLOGY TECHNOLOGY – It is now rather widely recognized sizes which may be encountered, e.g. Packaging and Assembly Technology 01005 capacitors and transformers, would 100 Polymer make it very difficult to move the popu- Polymer with sensitizer for the Internet of Things Era lated board through any integrated wiring process. Many products do not have this Irradiated polymer and sensitizer large range, but a conventional assembly 80 company must be prepared to handle all Jayna Sheats, CEO possibilities. ASE Group Terecircuits Corporation Second, the historically rooted supply that the technology of IC packaging has overtaken William Chen 60 chain and infrastructure of the industry does not readily embrace or facilitate change. PCBs predate modern IC archi- (%) Weight 26 tectures; they were already used with 40 IT IS NOW RATHER WIDELY RECOG- because it is appreciably more expensive. aspect ratio, so the problem remains.) vacuum tubes, and 4-layer PCBs were in nized that the technology of integrated The current palate of “advanced These prominent issues for on-chip sig- production at about the same time Jack circuit (IC) packaging has overtaken chip packaging” including fan-in and fan-out nals pertain also to interchip connections Kilby came to . Thus fabrication as the focal point of innova- WLP, interposers, and monolithic as well along with other issues (e.g. wirebond the technology for fabricating them in a 20 tion in electronic fabrication. Technical as through-silicon via (TSV)-based 3D inductance). process (and typically location) separate chip fabrication as the focal point of innovation in electronic trade journals are replete with articles integration, offers routes to increasing The clarity and simplicity of Moore’s from where components would be added about the latest advances in 2.5D, 3D and a product’s performance (e.g. clock fre- Law notwithstanding, what matters for was already well entrenched. At the same 0 even 3.5D packaging, and various forms quency or power), but not lower cost per the consumer is computing “power” (an time, the sensitive and easily damaged ICs 100 200 300 400 500 600 Feldman Engineering Corp. of chip scale and wafer level packag- basic computing element (logic gate). The unfortunately subjective metric) per dol- were packaged for protection and con- Ira Feldman ing (WLP). System-in-package (SiP) success of Moore’s Law fundamentally lar, not transistors per se. Predicting how venient insertion (in most cases) into the Temperature (˚C) modules, such as Freescale’s SCM-i.MX stems from the magic of planar process- to achieve increases in this metric is much through-holes of those boards. Figure 1. Thermogravimetric analysis of the materials used in the photopolymer component 6Dual, Samsung’s Artik series, or the ing and the genius of lithographers: as more complicated. It is clear, however, The modern incarnation of this legacy transfer process; heating rate 10C/min. Faster heating eliminates the residue in the exposed proprietary but strategically important tools were developed to process smaller that shortening interconnects is vital, pro- will not go away anytime soon, but there material which in the TGA requires >100C to decompose. fabrication. Technical trade journals are replete with articles (iWatch) occupy center stage for features, the cost of those tools rose more vided cost efficacy is maintained. are numerous products, including typical designers. A recent (November 2015) Yole slowly than dimensions fell. In combina- The shortest possible connections wireless sensor modules, embedded con- mer-coated plate which is then aligned High-resolution interconnects are report projects FOWLP as supplying the tion with larger wafers, the result has been between two chips are obviously obtained trollers, and many of the components of in close proximity to the target (in a tool best made on a planar surface. This is majority of the industry’s growth during (until recently) close to a constant cost by stacking (ideally face to face; TSVs mobile phones which contain only surface similar to a contact aligner); irradiation obtained by placing the components face the next several years. per unit area of silicon processed, and being a close second). Doing this cost- mount devices (ICs, sensors and passives). of the polymer (through the plate) behind down on a release layer and embedding The impetus for this shift is with little hence steady (exponential) reduction in effectively has proved to be a formi- These products, which comprise the foun- selected components with a dose typical them in a reflowable polymer which then doubt a consequence of the inexorable cost per transistor. Short of some futuristic dable undertaking, having only recently dation of the IoT, give us an opportunity for microlithography and attendant mild becomes the substrate and matrix. Such approach of the end of Moore’s Law, an scenario with holographic processing of achieved significant commercial success to depart from conventional practices. heating causes its vaporization and release partial molding processes are certainly not N-Able Group International event that astute observers have known volume elements, there is simply no way after 15 – 20 years of intensive industrial At Terecircuits we have developed the of the components. new, and have been the subject of several about the latest advances in 2.5D, 3D and even 3.5D packag- Ron Jones had to arrive at some point (for reasons to do this in the third dimension. Stacking development (taking ALLVIA to be the technologies for an IC-like approach: This critical step allows the otherwise publications by Matti Mäntysalo and col- of atomic scale if no other). There are chips in 3D today means stacking chips pioneer of this stage). While progress will place unpackaged or minimally packaged delicate bare dice to be handled at high leagues at Tampere University in Finland, very few apparently viable options for whose cost arose from the manufacturing continue, it is worth asking if any other components onto a single substrate, inter- throughput with near-zero risk of dam- among others. Compared to conventional introducing major inventions into IC structure of planar processing, and can approach can be effective. connect them, and encapsulate the entire age. Ultrathin (25 microns or less) and molding, embedding allows consideration fabrication, and even those currently in only give a product whose transistors cost For example, what might happen if the circuit at once. This simple architecture extremely small (effectively limited only of a wider selection of polymers, optimiz- development are horrendously expensive more, not less. distinction between packaging of chips has the potential to cut the number of by the optical system) components are ing for example the coefficient of thermal and complex. Packaging, on the other There are many reasons to pursue and assembly of circuit boards were elimi- process steps for such a product by 80% readily accommodated. Because of the expansion. hand, affords many attractive options at non-planar packaging despite the added nated? Conceptually, the architecture of a or more, with concomitant reduction in array processing, throughput can be many Releasing this “front end” laminate more customary costs. cost. For example, these same transis- printed circuit board (PCB) corresponds materials use. Most importantly, it enables times greater than present pick and place from the temporary substrate and turning ing, and various forms of chip scale and wafer level packaging. It is important to remember, however, tors may be able to work faster, or con- to that of a chip: functional elements us to achieve a great deal of what 3D inte- tools with comparable capital and labor it over affords a substrate as flat as the that “More than Moore” does not offer the sume less power. As die size increases are connected by wiring. In the case of gration is designed for, but with a process costs. chips themselves on which interconnects same advantages as Moore’s Law did. The in conventional scaling, global RC delay ICs, one first forms the active elements, that is poised to actually reduce costs. Figure 1 shows the process window with resolution of a few microns can then latter, while originally expressed in terms increases as the 4th power of the scaling and then the interconnects. Arguably, at between unirradiated and irradiated poly- be built up as desired. In essence the wir- Henkel Electronic Materials, LLC of transistor count per chip, was most factor. RC-related signal delay for global the time when interconnects were made Process Details mer; it makes process control substantially ing of the “PCB” is simply a continuation Scott King fundamentally an economic phenomenon: interconnects increases even at constant with discrete wires, this is how PCBs The process can be divided into three easier than for stamp transfer printing of that in the chips. Without a package the marketplace supported the cost of die size because dielectric and conductor were constructed: finished components parts: placement, embedding (which is (which relies on relatively small differ- surrounding the chips, their edges can be the fantastic advances in equipment and thicknesses decrease, while local intercon- were placed on the board and then wired roughly equivalent to the molding in ences in adhesion between components, placed nearly contiguous (within a few processes because they facilitated making nect delays remain constant. Since the together. conventional packaging), and interconnec- stamp and substrate) or laser ablation microns), resulting in a product rather like transistors cheaper, not because they made longest lines are getting longer, resistive tion. The placement step in Terecircuits’ (where a narrow threshold margin sepa- one big chip (which of course could never them run faster. Higher speed transistors power consumption also increases. (In The Challenge process replaces the mechanical pick and rates ablated and unablated material). be made monolithically for a host of rea- fabricated from III-V materials have been practice, line and dielectric thickness have There are both historical and practi- place tool with a novel photopolymer That control is critical for achieving preci- sons). We might call it a “composite chip”. available for decades, but that is not the not decreased with the chip scaling factor, cal reasons why this is not done today. transfer operation: an entire array of com- sion, close-spaced placement in a parallel prevailing techology for most products but there is only so far one can go with In practice, the wide range of component ponents is adhered to a transparent poly- (array) process with small components. continued on page 32  JAYNA SHEATS Tom Salmon SEMI 26 MEPTEC REPORT WINTER 2015 meptec.org meptec.org WINTER 2015 MEPTEC REPORT 27 TERECIRCUITS CORPORATION Jayna Sheats Terecircuits Corporation

Rich Wawrzyniak Semico Research Corp. DEPARTMENTS 4 Member News 15 Event Follow-up 30 PacTech News 9 Industry Insights 24 SMART Microsystems News 34 Opinion SEMI Bettina Weiss 11 Coupling & Crosstalk 28 Henkel News

MEPTEC Report Vol. 19, No. 4. Published quarterly by MEPCOM LLC, 315 Savannah River Dr., Summerville, SC 29485. Copyright 2015 by MEPCOM LLC. All rights reserved. Materials may not be reproduced in whole or in part without written permission. MEPTEC Report is sent without charge to members of MEPTEC. For non-members, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere. For advertising rates and information contact Gina Edwards at 408-858-5493, Fax Toll Free 1-866-424-0130.  MEMBER NEWS SMART  HENKEL APPOINTS SHENMAO Introduces PF606-P133 HANS VAN BYLEN TO Solder Paste for Laser Soldering Microsystems SUCCEED KASPER Now ISO 9001 RORSTED AS CEO Certified

SMART MICROSYSTEMS, located in Northern Ohio, creates turn-key solutions for microelectronic pack- age assembly challenges to move MEMS sensor tech- nology from development to production. As a newly certified ISO 9001 manufac- turer, SMART Microsystems Hans Van Bylen SHENMAO PF606-P133 seconds of heating after dis- incorporates design-for- Solder Paste is designed for pensing, solder joint is well- manufacturing into the initial Henkel has announced selective laser soldering on formed with minimal flux stages of development. By that CEO Kasper Rorsted, tiny solder joints (1.5mm residue and without splash working concurrently with who has decided not to or smaller), especially on or solder ball. Process time their customer’s design team renew his current con- expensive, temperature- can be greatly reduced with and suppliers they are able to tract beyond 2017, will sensitive components and extremely high yield rate. implement process specifica- leave the company at his assemblies. In the past, PF606-P133 is approved tions, design-to-cost goals, own request as of April such a small solder joint by world leading electronic and on-time delivery objec- 30, 2016. He served on is not suitable for standard component manufacturers. tives efficiently, reducing the Henkel Management reflow processes and has to For more information, overall time and cost. Board for 11 years, thereof be soldered manually. With contact SHENMAO Amer- More information about 8 years as CEO. Effective PF606-P133 Solder Paste, ica at 408-943-1755, e-mail SMART Microsystems capa- May 1, 2016, Hans Van automatic laser soldering can [email protected], or visit bilities and services is avail- Bylen has been appointed easily be accomplished. www.shenmao.com. ◆ able at www.smartmicrosys- as his successor. His suc- Within only several tems.com. ◆ cessful career at Henkel started in 1984 and he has served as member of NAMICS Corporation Develops Improved the Management Board since 2005. The appoint- Dam-and-Fill Encapsulants ment to CEO this spring NAMICS CORPORATION HAS DEVELOPED will enable him to lead the an epoxy dam material (CHIPCOAT G8345D) development of the new and an accompanying epoxy fill material (CHIP- strategy which Henkel will COAT G8345-6) for the semiconductor market. announce at the end of Dam-and-Fill materials encapsulate your wire this year and drive its bonded device as an electrically insulating mate- successful execution. rial. Dispensing a high-viscosity dam followed www.henkel.com by a low-viscosity fill, will create a completed encapsulated package for your CSP and BGA. ALTERA’S NEW  CHIPCOAT G8345D and G8345-6 are fast cur- QUARTUS PRIME ing, low CTE (low stress), offer high package DESIGN SOFTWARE reliability and reduced warpage. EXTENDS LEADER- CHIPCOAT G8345D and G8345-6 are in SHIP IN DESIGN full production and are available for sampling. PERFORMANCE AND Standard packaging is frozen syringes with 50 PRODUCTIVITY grams in a 30cc syringe; larger cartridges are Signaling a new era in available. G8354D (Dam) G8345D & G8345-6 design productivity for a (Dam & Fill) NAMICS CORPORATION is a leading new generation of pro- source for underfills, encapsulants, adhesives, NAMICS serves its worldwide customers with grammable logic devices, and insulating and conductive materials used enabling products for leading edge applications. Altera Corporation has by producers of semiconductor devices, passive To find out more about these NAMICS released the Quartus® components and solar cells. Headquartered in Dam-and-Fill materials, please visit www.nam-  Niigata, Japan with subsidiaries in the USA, ics.co.jp/e/product/chipcoat04.html or contact Europe, Singapore, Korea, Taiwan and China, your local NAMICS sales representative. ◆

4 MEPTEC REPORT WINTER 2015 meptec.org InvenSense Announces Sensor- Based SaaS Tracking Platform For Mobile and Wearable Application Developers ACCREDITED Coursa Sports Employs Sensor Enhanced Positioning and CERT # 3558* GNSS Duty-Cycling to Provide More Accurate Speed, Dis- tance and Route Tracking at Reduced Power Consumption

INVENSENSE, INC., A tomer experience by increas- leading provider of MEMS ing the continuity and accu- sensor platform solutions, racy of the fitness data when announced Coursa Sports, GNSS signals are weak or a cloud-based Software as a unavailable. Service (SaaS) fitness track- Coursa Sports improves ing platform for mobile device battery life by and smartwatch health and up to 50% during workouts fitness applications. The plat- by frequently turning GNSS form is designed to provide off (duty-cycling). During more accurate and always duty-cycling, the lower power available speed, distance, and sensors are used to track fit- route tracking and at least ness data at the same accu- a 3X improvement in rela- racy as GNSS. This feature Surface mounted device with delamination (red) along the entire tive elevation reporting for extends battery life during length of several leads. This part walking, hiking and running fitness tracking, and enables would fail per J-STD-020 criteria. at up to 50% reduced power developers to migrate their consumption. Coursa Sports smartphone apps to smart- is comprised of an SDK for watch devices, where smaller integration into a mobile batteries and the high power ® application and a cloud . consumption of GNSS previ- SonoLab is Your Lab Mobile and wearable applica- ously prohibited fitness track- tion developers can download ing use cases. the Coursa Sports SDK today “InvenSense has made sig- An ISO/IEC 17025:2005 Certifi ed Testing Lab* from www.coursasports.com. nificant investments in human SonoLab, a division of Sonoscan®, is the world’s largest As use of mobile fitness context and location tracking inspection service specializing in Acoustic Micro Imaging applications increases, so algorithm development to (AMI). Through SonoLab, you’ll have access to the superior does the expectation of bat- serve our OEM customers,” image quality and reliable data accuracy of Sonoscan C-SAM® acoustic microscopes, plus the capabilities and tery efficiency and accuracy said Eitan Medina vice presi- careful analysis of the world’s leading AMI experts. enabling users to get full dent marketing and product credit for their exercise ses- management, InvenSense. With worldwide locations, SonoLab® Services sions. Most fitness apps use “Now, for the first time, we unmatched capabilities, • Component Qualifi cation GNSS (such as GPS) to track are enabling application extensive experience to Industry Standards the speed, distance and route developers to take advantage and the best equipment • Materials Characterization available, SonoLab gives and Evaluation of activity. However, on for- of these technology advances you the ability, fl exibility • High-Capacity Screening est running trails or in deep in their apps. Coursa Sports is and capacity you need and Lot Reclamation urban canyon environments, the first commercially avail- to meet all your AMI • Failure Analysis and GNSS can be inaccurate or able SDK and SaaS platform requirements. Constructional Analysis unavailable, resulting in lost designed to help fitness and • Inspection and Audit Services or inaccurate fitness data. health application developers • Custom Training The Coursa Sports SDK provide more accurate and uses advanced algorithms reliable fitness metrics to their To learn more visit sonoscan.com/sonolab that take sensor data from customers through the use of *For U.S. Locations Only the mobile device , MEMS inertial sensor data.” , and barometric The Coursa Sports SDK pressure sensor to generate supports iOS, Android and an inertial tracking data flow Android Wear platforms. that is combined with GNSS More information is available 847-437-6400 • sonoscan.com data. The addition of the iner- at www.coursasports.com or tial tracking system, together contact InvenSense Sales at Elk Grove Village, IL • Silicon Valley, CA • Phoenix, AZ • England Philippines • Singapore • Shanghai • Taiwan with GNSS, improves cus- [email protected]. ◆ meptec.org WINTER 2015 MEPTEC REPORT 5  MEMBER NEWS

™ Prime design software. Infineon OPTIGA TPM Chips Protect Latest Microsoft Altera’s new software envi- ronment builds upon the Surface Devices company’s proven, user- friendly Quartus II software MICROSOFT puts emphasis and incorporates the on hardware based security new productivity-centric to protect sensitive user data Spectra-Q™ engine. The stored on connected devices. new Quartus Prime design The company integrates ™ software is optimized to OPTIGA TPMs (Trusted enhance the FPGA and Platform Modules) from Infi- SoC FPGA design process neon Technologies AG into by reducing design itera- its latest personal computing tions, delivering the indus- devices. Among these are the try’s fastest compile times, new Surface Pro 4 tablet and and accelerating silicon the Surface Book, the first performance. Microsoft branded . www.altera.com TPMs are dedicated secu- stored inside the TPM. Group (TCG), an interna- rity chips to store sensitive Infineon is recognized tional standardization group  ASE RECEIVES data such as keys, certificates as the world’s leading sup- with members such as 2015 BSI GRC AWARD and passwords separated plier of security solutions and Google. TPM 2.0 speci- ASE announced that it has from the main processor. for Trusted Computing. fications are based on most received the BSI (British This increases protection Microsoft’s personal com- advanced cryptography and Standards Institute) ‘Inclu- of the computing device puting devices rely on the security mechanisms. In ™ sive Green Growth Award’ from unauthorized access, OPTIGA TPM SLB 9665, addition, they particularly and the ‘GRC (gover- manipulation and data theft. the industry’s first certified address mobile computing nance, risk management For example, the key and security controller based on such as notebooks and tab- and compliance) Award’. password of the Microsoft the latest TPM 2.0 standard. lets as well as IoT devices This is the fourth year in a BitLocker Drive Encryp- This standard was defined with special security require- row since 2012 that ASE tion application are securely by the Trusted Computing ments. ◆ has received recognition from the BSI Group Tai- FINEPLACER® wan. The BSI Group, also Coreplus BGA MARATHON PRODUCTS known as the British Stan- dards Institution, is a busi- Rework Station ness standards company AnAn EnterpriseEnterprise SoftwareSoftware SolutionSolution forfor ManagingManaging TheThe ColdCold ChainChain that develops standards and provides its services Any location. to companies to improve NO Any time. performance, reduce risk LIMITS Any users. and achieve sustainability. www.aseglobal.com The FINEPLACER® coreplus Temperature Data Loggers  DCG SOLVES is a dedicated rework system Operating ranges: -80°C to 72°C. LOCALIZATION OF that offers a level of profes- Our devices are programmed in English, sionalism that exceeds its Japanese, French, German, Spanish, ELECTRICAL SHORTS Mandarin, and Portuguese to WITH EBIRCH™ attractive price. The system support globalization. Make TECHNOLOGY offers Finetech’s long proven c\temp your last Q.C. gate In conjunction with the rework technology for a wide of product validation prior to accept- ance of critically- 41st International Sym- spectrum of SMD compo- sensitive materials for posium for Testing and nents, ranging in size from manufacturing. Failure Analysis (ISTFA), 01005 to 90 mm x 90 mm. ® DCG Systems announced The FINEPLACER core- Marathon Products, Inc. headquartered in San Leandro, CA is a global supplier of investigative temperature recording devices used the release of EBIRCH™, a plus meets the needs of single to validate shipments of epoxies, laminates and other critical new, unique technology for system, high mix rework, or materials used in the manufacture of integrated circuits. localizing shorts and other multiple system production low-resistance faults that environments where process may reside in the inter- portability and reproducibility is crucial. 800-858-6872 www.marathon products.com  Visit www.finetechusa.com Don’t ship without us® for more information. ◆

6 MEPTEC REPORT WINTER 2015 meptec.org  MEMBER NEWS

Promex Industries, Inc. Hires Rosie Medina connect structures or the polysilicon base layer of as Director of Sales and Marketing integrated circuits. Named Former Med Tech Business Development Director Joins Silicon Valley EMS to for Electron Beam Induced Promote Contract Manufacturing Services for Medical and Bioscience Products Resistance Change, EBIRCH offers fault analysis (FA) engineers PROMEX INDUSTRIES from prototype to volume and yield experts the abil- Inc., an electronic manufac- production,” said Promex ity to detect and isolate turing services (EMS) provid- President and CEO Richard low-resistance electrical er that integrates conventional Otte. “She understands the faults without resorting to SMT with semiconductor importance of quality and brute-force binary search microelectronic packaging repeatable processes in PCB approaches that rely on and assembly, has hired Rosie assembly – especially for successive Focused Ion Medina as its new director of Class III implantable devices Beam cuts. Its unparal- sales and marketing. and other complex multi- leled ability to quickly Formerly the director of technology medical devices. isolate low-resistance medical technology business Her skills in business devel- faults enables EBIRCH to development at CORWIL opment, sales and marketing boost the success rate of Technology (Milpitas, CA), in the contract manufacturing physical failure analysis Ms. Medina has close to 30 sector position her well to (PFA) imaging techniques years of experience in the lead the Promex sales team.” manufacturing initiatives. to well above 90%, accel- semiconductor industry. She In her new position, Founded in 1975, Promex erating time-to-results and has worked with a variety of Ms. Medina will be respon- Industries Inc. provides a establishing the FA lab as companies around the world, sible for supporting the rapid broad range of assembly ser- a critical partner organiza- ranging from new startups growth of Promex by enhanc- vices to the medical, biosci- tion in solving yield and to major corporations in the ing sales, marketing and cus- ence, commercial semicon- reliability problems. commercial, medical, and tomer support, among other ductor and military markets. www.dcgsystems.com mil-aero markets. responsibilities. Ms. Medina More information is avail- “Rosie knows what it will also work closely with able at the Promex website UTAC AND takes to fast track new medi- executive management on www.promex-ind.com or by  MCUBE ANNOUNCE cal and bioscience products new strategic engineering and calling +1-408-496-0222. ◆ PRODUCTION RAMP OF MEMS 3-AXIS Amkor Technology Announces Acquisition of UTAC Holdings Ltd. a Singapore-based semi- Remaining Shares of J-Devices conductor assembly and test services provider and AMKOR TECHNOLOGY INC., A LEADER our customers in Japan, and we see exciting mCube, Inc., provider of in semiconductor packaging, assembly and opportunities to expand our business worldwide the world’s smallest micro- test services, has announced that on December by capitalizing on our leadership position in electromechanical systems 30, 2015, it increased its ownership interest in automotive ICs.” (MEMS) sensors J-Devices Corporation from 65.7% to 100% J-Devices is the largest OSAT in Japan and have jointly announced the through the exercise of previously disclosed the sixth largest in the world. For the 12 months successful qualification options. ended September 30, 2015, J-Devices generated and production ramp of “Amkor will consolidate the financial results revenues of $832 million, EBITDA of $113 mil- mCube’s new MEMS of J-Devices beginning in 2016, initially adding lion and net income of $26 million. 3-axis accelerometers in about $800 million of annual revenue to our Amkor Technology Inc. is one of the world’s small packages ranging top line,” said Steve Kelley, Amkor’s president largest providers of semiconductor packaging, from 2x2 mm to 3x3 mm and chief executive officer. “This transaction assembly and test services. Founded in 1968, at UTAC’s Thailand factory. cements Amkor’s position as the world’s sec- Amkor pioneered the outsourcing of IC assem- These accelerometers fea- ond largest OSAT, well ahead of the next two bly and test and is now a strategic manufactur- ture mCube’s monolithic players. We also become the largest OSAT for ing partner for more than 250 of the world’s single-chip motion sensor the automotive market, with roughly $750 mil- leading semiconductor companies, foundries and technology which enables lion in combined automotive-based revenues in electronics OEMs. Amkor’s operational base small die size, ultra-low 2015.” encompasses more than 7 million square feet of power consumption, and “Fully combining J-Devices and Amkor is floor space with production facilities, product high-performance inertial the logical next step in our joint venture rela- development centers and sales & support offices sensors. These sensors tionship that was begun more than six years located in key electronics manufacturing regions ago,” said Yoshifumi Nakaya, J-Devices’ chief in Asia, Europe and the USA. For more infor-  executive officer. “We are fully committed to mation visit www.amkor.com. ◆ meptec.org WINTER 2015 MEPTEC REPORT 7  MEMBER NEWS are optimized in a portfolio 11th Annual Global Technology Awards of products that are spe- cifically targeted for mobile phones, wearables, and IoT devices. www.mcubemems.com www.utacgroup.com

 STATS CHIPPAC RANKED IN TOP 10 SEMICONDUCTOR EQUIPMENT MANU- FACTURERS BY IEEE FOR PATENT INNOVATIONS STATS ChipPAC Ltd. has announced that it has been ranked among the world’s top 10 semi- conductor equipment manufacturing companies in the 2015 Patent Power Scorecards published by the Institute of Electrical GLOBAL SMT & PACKAGING SUCCESS- The Global Technology Awards are held and Electronics Engineers fully held the 11th Annual Global Technology annually and rotate every second year between (IEEE). This is the sixth Awards at Productronica 2015 in Munich. Productronica, Germany and SMTAi, USA. consecutive year that The star-studded event featured the very latest Next year, the awards contest will accept STATS ChipPAC has been innovative products produced by suppliers of entries from March 1st, 2016. recognized in the annual EMS manufacturing equipment and materials The awards ceremony will be held at scorecards. over the last 12 months. Videos describing the SMTAi in Chicago, USA on Tuesday, Septem- STATS ChipPAC was winning products and why their product stood ber 27th, 2016. For further information, please ranked seventh in the out compared to the other entries was played visit http://globalsmt.net/global-technology- ◆ Semiconductor Equipment during the presentation ceremony. awards/ Manufacturing category. Category Winning Company Winning Product This is the highest ranking Adhesives/Coatings/Encapsulants YINCAE Advanced Materials LLC SMT 256 ever received by an Out- Assembly Tools Factory Automation Multi-recognition camera sourced Semiconductor Best Manufacturers Rep/Distributor Horizon Sales David Trail Assembly and Test (OSAT) Best Product – Asia MIRTEC MV-6 OMNI 3D provider. Best Product - Europe GEN 3 Systems GM Series of Contaminometers In August 2015, Best Product - Americas Indium Corporation InFORMS® Jiangsu Changjiang Elec- Bonding Equipment Nordson DAGE 4800 Bondtester tronics Technology Co. Cleaning Materials Kyzen Corporation AQUANOX® A4708 Ltd. (“JCET”) acquired Contract Services $25 - $50 Million Computrol Contractor Dispensing Equipment Nordson ASYMTEK Spectrum II with tilt & rotate the entire shareholding of Environmentally-friendly Products CAMTEK Gryphon SL STATS ChipPAC. With over Inspection - AOI Cyberoptics SQ3000™ 3D AOI System 1,500 patents issued by Inspection - SPI Test Research Inc TR7007Q 3D Solder Paste Inspection System the USPTO as of the end Inspection - x-ray ViTrox V810 S2EXi In-line 3D Advanced X-Ray of 2015 and 784 patents Inspection system granted by the State Intel- Placement - high Volume ASM Assembly Systems SIPLACE TX lectual Property Office of Placement-low to medium volume Mycronic AB Agilis Smart Bin System China, the JCET Group Printing Equipment ITW Speedline MPM Edison Programming Data I/O LumenX has a combined IP port- Rework and Repair METCAL Scarab Site Cleaning System folio that is unmatched in Software - Process Control JUKI and Cogiscan JUKI Line Solution Software the OSAT industry with a Software - Production MIRTEC and YXLON Smart Loop deep knowledge base that Solder Paste Henkel GC10 provides a powerful com- Soldering Equipment kurtz ersa SMARTFLOW 2020 petitive advantage for cus- Stencils, Nano coatings FCT Companies Nanoslic tomers in the marketplace. Storage Systems Totech Super Dry Dry Tower www.statschippac.com Test Equipment VJ Electronix XQuick www.cj-elec.com ◆ Test Services Datest Datest Reverse Engineering Service Editor’s Choice Award JUKI and ESSEGI JUKI and Essegi Storage Soltions

8 MEPTEC REPORT WINTER 2015 meptec.org COLUMN

INDUSTRY Acquirer Acquiree Amount Date INSIGHTS Avago Emulex $606 M 05/2015 By Ron Jones Avago Broadcom $37,000 M 05/2015 Cypress Spansion $4,000 M 03/2015 Who’s Next on Dialog Atmel $4,600 M 09/2015 the Dance Floor Hua Capital OmniVision Technologies $1,900 M 6/2015 Intel Altera $16,700 M 10/2015  IF IT SEEMS LIKE YOU’RE HEARING a lot of talk these days about mergers and Lattice Silicon Image $600 M 03/2015 acquisitions in the semiconductor industry, NXP Freescale $11,800 M 03/2015 it’s not your imagination. There has been an explosion in level of activity and there ON Fairchild $2,500 M 11/2015 is no sign of things slowing down as we approach the end of 2015. Ikanos $47 M 08/2015 According to IC Insights, the average Qualcomm CSR $2,400 M 08/2015 M&A for the years 2010-2014 was $12.3 B. In the first half of 2015, they report we Uphill Capital ISSI $640 M 11/2015 have already reached $72.6 B, roughly 6x SanDisk $19,000 M 11/2015 the previous annual average. Reuters has reported more than $80B through Septem- Total $101,793 M ber and there are estimates that the year may hit $100-120 B when the final buzzer Table 2. sounds. Potential Targets Potential Suitors

Year Semi M&A PMC-Sierra Skyworks and Microsemi are in play now 2010 $ 7.7 B Maxim TI, ADI, . . . 2011 $ 17.0 B Lattice Xilinx, Qualcomm, Marvell, Microsemi, . . . 2012 $ 8.5 B Cavium Intel, Qualcomm, Avago, Marvell . . . 2013 $ 11.5 B Xilinx 2014 $ 16.9 B M/A-Com Technology 2015 (1st half) $72.6 B Skyworks

Table 1. (Source: IC Insights) Table 3.

Deals range in size from small (i.e. like a rocket this year. To some degree, it semiconductor companies have an eye 10’s of millions) to very large ($37 B for is driven by trends that have been going on broadening their portfolio of products, Broadcom). Avago alone has made four on for years, such as the increasing cost technology and IP to position them for a acquisitions (LSI, PLX, Emulex, and of mask sets. It is not unusual for leading market that is expected to experience rapid Broadcom) over the past couple of years edge designs to run in excess of $100 mil- growth over the next five years. Having that total $45 B. lion, and that is just for the masks. Many been in the industry for several decades Table 2 lists some acquisitions/mergers designs continue to go up in complexity, and watching the fabless model create that have either closed or are well along in taking them beyond the technical reach of hundreds and hundreds of new companies 2015. Some dates are closings, others are smaller fabless companies. over the past 25 years, it will be interest- announcements and everything in between. The Internet of Things (IoT) and other ing to watch as consolidation reverses (Please realize that I am submitting smart technologies are finally beginning the trend to some degree with a growing this article in early December and you will to creep out of the shadows and toward number of mega fabless/IDM companies. be reading it in mid-February, 2016... a 75 the center of the radar screen for a lot of Seems that our most consistent trend is day delay.) companies. It is not a matter of whether change. ◆ There are other semiconductor compa- IoT will happen, but rather in what myriad nies that are surely on the radar screen for configurations it will reveal itself and how RON JONES is CEO of N-Able Group merger or acquisition. See Table 3. quickly it will grow over the next several International. Visit www.n-ablegroup. A reasonable question would be why years. com or email ron.jones@n-ablegroup. M&A activity in the industry has taken off Though IoT is currently small, many com for more information. meptec.org WINTER 2015 MEPTEC REPORT 9 Open Cavity QFN 1-800-776-9888

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10 MEPTEC REPORT WINTER 2015 meptec.org COLUMN

including transforming implicit assump- ware bug? Simply the development and COUPLING & tions into documented requirements. test teams’ time to fix the error and retest At the same time, quality is often the software release. And today’s digital CROSSTALK stated as an expectation versus a mea- delivery requires no physical media. (This By Ira Feldman surable goal. For example, Ford’s now ignores the often-significant business discontinued slogan of “Quality is Job 1” costs of the software error, i.e. customer is meaningless without specific, measur- support costs, lost revenue due to time to Electronic coupling is the transfer of ener- able, achievable, realistic, and time based market delay, etc.) Clearly the “stakes” gy from one circuit or medium to another. (“SMART”) goals to implement it. Hav- are often much lower due to the low cost Sometimes it is intentional and sometimes ing meaningful goals allowed Ford to to repair software. Additionally, many not (crosstalk). I hope that this column, by focus on the required transformations that web-based companies release new ver- mixing technology and general observa- positioned them well compared to their sions of their software daily eliminating tions, is thought-provoking and “couples” competitors. the issue of infrequent or delayed update with your thinking. Most of the time I will Clearly there is a difference between cycles. stick to technology but occasional cross- a software developer who attacks a Lastly, where hardware technology talk diversions may deliver a message problem in a structured manner versus aims for very low – typically single digit closer to home. one who cobbles together something part per million (ppm) - defect rates, “quick and dirty” that “works”. Using a these rates may be too “high” for Internet Engineering: structured process to ensure that all the scale software. Facebook currently has requirements are addressed is the best over 1.4 billion monthly users so a 1 ppm The Solution to engineering approach. Even though a defect could easily be seen by 1,400 users “code sprint”, often used by Agile meth- in a month. Internet scale applications Software Quality! odology practitioners, allows for focused like Facebook need extremely low defect effort to make forward progress in code rates on the order of 10 to 100’s parts per  WHO IS AN ENGINEER? IN A RECENT development, it is essential to know the billion (ppb) for critical functionality due Atlantic article, “Programmers: Stop Call- destination and the requirements. There is to the multiplier of the number of users ing Yourselves Engineers”, Ian Bogost no sense in “running” around and either and transactions. Regardless of the actual argues strongly that software developers missing the destination or solving the defect rate, software defects are quickly should not be called engineers based wrong problem, right? exposed. upon several factors including quality, Beyond a requirements issue, software But are the software failures, espe- professional licensure, and liability. Mr. has three unique aspects that are not pres- cially those for “infrastructure” that Mr. Bogost includes examples of where soft- ent in tangible products that contribute to Bogost finds the most alarming, a product ware has failed even as it has become quality issues: feature creep, perception of feature creep, simple fixes, or scale critical infrastructure. Having struck a of “simple” fixes, and scale. challenges? Clearly the defects are more nerve, there are several notable rebuttal Off-the-shelf software is often select- visible when the scale of usage is very articles and thousands of comments on ed on the basis of what it promises to do large. However, there is more to the the original article. and not on reliability. So, product market- situation than just feature creep and But instead of arguing over who ers continually identify new features to “patch it later” mentality on the part should be called an Engineer or which attract new users while the average user of the software team responsible for honorific should be used for Mr. Bogost may use only a very small percentage of these failures. It is corporate culture. based on his doctorate in Comparative existing features. Even if you do know Facebook’s previous motto of “Move Literature, we should be asking the big- most of the features of a common pro- Fast And Break Things” was appropri- ger question: How can engineering solve gram such as Microsoft Excel or Word, it ate for the race to scale as quickly as software quality problems? is highly unlikely you regularly use more possible to attract additional users and Engineering is now practiced in far than a small fraction of these features. advertisers. This set the tone for their more areas than the classical dictionary These extra features therefore “bloat” corporate hacker culture. To shift the list of endeavors that could be charac- the software and may contribute to lower culture to focus on how to do things more terized as the engines of the Industrial overall reliability due to the added com- reliably at scale, especially in their core Revolution. Wikipedia does a better job plexity. And, of course, increased product platform and services, Facebook changed of describing what is built in terms of complexity makes it more difficult to their motto last year to “Move Fast With function than specific devices. As such comprehensively test each new release of Stable Infra[structure]”. it incorporates the essence of our current the software. To do their job correctly – finding information technology revolution by Unlike hardware, the “penalty” for practical solutions that meet the busi- including tools and processes. fixing a bug in software at the first order ness needs – software developers need What is common to both definitions level is minimal. A mistake in a semicon- to fully comprehend the requirements of engineering is practicality, i.e. making ductor photolithography mask set could and test the solution thoroughly against something useful. The key to achieving easily cost tens of millions of dollars to these requirements. And there must practicality is to make sure that the true generate a corrected mask set. This cost be a corporate culture that supports requirements are fully understood and the is incurred before the actual production to innovation and quality. Arguing about end result is tested against these require- replace the defective parts and before the whether programmers are true engineers ments. A good engineer takes the time costs to repair or replace the parts in end will not solve the issues of quality. to understand the true requirements products. The actual cost of fixing a soft- What is important is that the developers meptec.org WINTER 2015 MEPTEC REPORT 11 think and are treated like engineers and that management assigns them clearly CAN YOUR EPOXY defined projects that don’t easily change scope. (This implies a healthy relation- ADHESIVE GO LOW? ship between marketing and engineering, which of its own, is a worthy discussion.) Epoxy System EP42HT-2LTE Let’s focus on the corporate culture and Features an ultra low coefficient not on job titles to improve the quality of software. of thermal expansion For more of my thoughts, please see CTE 9-12 X 10-6 in/in/°C my blog http://hightechbizdev.com. As always, I look forward to hearing LOW SHRINKAGE UPON CURE your comments directly. Please contact me to discuss your thoughts or if I can be Linear <0.01% of any assistance. ◆ Volumetric <0.1%

IRA FELDMAN (ira@feldmanengineer- Elongation <5% ing.com) is the Principal Consultant of Feldman Engineering Corp. which guides high technology products and HIGH DIMENSIONAL STABILITY services from concept to high volume From -60 to +300°F manufacturing. He engages on a wide range of projects including technical marketing, product-generation process- Hackensack, NJ 07601, USA es, supply-chain management, and busi- +1.201.343.8983 ∙ mainmasterbond.com ness development. www.masterbond.com

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12 MEPTEC REPORT WINTER 2015 meptec.org ANALYSIS

An Inside Look at the System-on-a-Chip (SoC) Market

Rich Wawrzyniak Semico Research Corp.

THE SOC MARKET HAS BEEN EVOLUTION OF THE ASIC MARKET growing and evolving for the last 15 - 20 Programmable years and is a very complex combination SoC Advanced of semiconductor solutions that fills every Performance Multicore SoC possible niche in the electronics market Standard System on System(s) today. Semico Research Corp. looks at Cell a Chip on a Chip Value this market on a regular basis and pub- Multi-core lishes research on its makeup, direction Application SoC Basic SoC Custom Specific Standard Platform and evolution. ASIC Products (ASSP) SoC Customer Platform To get a better understanding of the Owned Tooling ASIC SoC market, it is important to understand Gate Array Structured where it came from and what its roots are. ASIC Simple / Field Programmable As Figure 1 shows, the origin of Programmable Complex Computing Logic Device (PLD) the ASIC market was the rise of what PLD System on a Array were called full custom designs in the Programmable Chip mid-1970s. These devices were usually FPGA Field Programmable FPGA / SoC produced by large IDMs only for specific Analog Array with Programmable customers. In most cases, the customer Fabric supplied the design to the IDM. The customer consumed all the output of the 1974 1980 1986 1988 1997 1999 2000 2001 2002 2006 2009 2010 2012 IDM and used the parts internally. As the Figure 1. History of the ASIC Market. (Source: Semico Research Corp.) semiconductor market grew, new types of devices arose to help meet the needs of customers and markets alike. designers to be used in the creation of SoC in the market today. (see Figure 2) Around 1980, the ASIC market these designs. To track this market accu- The reason for the market evolution fragmented into three basic types: Gate rately, Semico has created a paper defini- to create a separate SoC segment was to Arrays, Standard Cells and Programmable tion that details the three main classes of provide designers with more flexibility to Logic. Later, as the demand grew for certain types of systems, the Application Specific Standard Product category arose. Revised Revised Definitions Metrics This class of device filled a gap between the three standard types of ASIC. Advanced 2+ IP Subsystems Performance 3+ Complex Interconnects In the mid-1990s, the ASIC market Traditional Traditional Multicore SoCs >150 Discrete IP Blocks again reached a point where the standard Metrics Definitions approaches for creating an ASIC were Value Performance 1+ IP Subsystems no longer satisfying customer or market 10M+ Gates Multicore 2+ Complex Interconnects SoCs needs, and another wave of innovation >16Mb Memory SoCs 75 - 150 Discrete IP Blocks and fragmentation started with the advent of the SoC. From a single type of SoC, Value Basic 1+ Bus Structure 4 - 10M Gates or 1 Complex Interconnect we now have moved to a market environ- 2 - 8Mb Memory SoCs SoCs ≥ 50 - 75 Discrete IP Blocks ment where it is possible for different types of SoC to co-exist to fill necessary Simple Bus Structure 1 - 4M Gates Commodity Microcontrollers ≥ 10 - 20 Discrete IP Blocks market niches. 1 - 2Mb Memory Controllers A major component of the SoC mar- Very Low Cost ket is the use of 3rd Party Semiconductor Moore’s Law Continues Intellectual Property (SIP) and SIP that was created for reuse internally by the Figure 2. SoC Definition by Complexity. (Source: Semico Research Corp.) meptec.org WINTER 2015 MEPTEC REPORT 13 aid in the creation of their silicon solu- 3. The drive to add connectivity to all SoC in second place and the Basic SoC in tions. New market segments like mobile mobile devices has pushed silicon third position. The Basic SoC category is computing and communications, the designers to use the SoC approach to going to be where most of the IoT solu- Internet, wireless connectivity and now incorporate the necessary functionality tions are going to reside and will exhibit the emerging Internet of Things (IoT) all through the use of 3rd Party SIP the fastest growth rate over the forecast put new demands on designers to provide blocks. period. While the unit volumes projected more functionality and richer feature sets for IoT are going to be very high, the 4. The new capability and functionality to users of the devices. The 3rd Party SIP ASPs of these devices will be fairly low found on mobile devices has caused industry grew up to support these efforts, compared to the other SoC types. This the users of those devices to consume and that is why Semico created the defini- will act to hold down the overall revenues ever-greater amounts of bandwidth. tions you see in Figure 2 – to provide a for the Basic SoC category compared to greater granularity in understanding the 5. This has caused service providers of the other SoC categories. composition of the market and a way both wired and wireless solutions to The story of the SoC market is one of of easily separating one SoC type from increase the bandwidth available in innovation and design expertise coming another. their networks, and to choose the SoC together to create new market segments Revenue for this market will grow methodology to meet the changing and industries. The pace of market evolu- from $103.4 billion in 2015 to $192.0 bil- market requirements. tion is accelerating as new process geom- lion by 2019, a CAGR (compound annual etries enter the market providing silicon growth rate) of 13.2%. Over the next five The net impact of these trends is to architects with new tools and capabilities years, higher revenues will continue to be push both the revenues of SoC devices to fulfill ever more stringent end market driven by the following factors: and the unit shipments of these devices requirements. While one can argue that to increased levels. Over time, the SoC the pace of evolution may slow down at 1. Many silicon solutions that previously design methodology will be responsible some point, the profound impact of the used older design methodologies have for the majority of the revenue in the inte- various SoC product types on the semi- switched over to using an SoC grated circuit portion of the semiconduc- conductor and electronics industries is approach. tor market. indisputable and has been very positive. 2. Many of the off-the-shelf ‘catalog’ Figure 3 looks at the revenue forecast This is a trend that will continue for the parts found in the product portfolios for the three main types of SoC along foreseeable future. ◆ of large IDMs (Independent Device with some of the more minor variants. Manufacturers) are using the SoC The SoC type responsible for the largest design methodology when they are revenue is the Advanced Performance refreshed by the manufacturers. Multicore SoC with the Value Multicore

$70,000

$60,000

$50,000

$40,000

M Dollars $30,000

$20,000

$10,000

$0 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015* 2016* 2017* 2018* 2019*

Advanced Performance Multicore SoC Value Multicore SoC Basic SoC Programmable SoC Platform SoC Slice SoC SoPC

Figure 3. Worldwide SoC Forecast by Device Type. (Source: Semico Research Corp.)

14 MEPTEC REPORT WINTER 2015 meptec.org FOLLOW-UP

THE GREAT MINIATURIZATION: SYSTEMS AND PACKAGING Technology Enabling Systems in your Pocket and Beyond

Joel Camarda, SemiOps

I RECENTLY HAD THE PRIVILEGE tively: analog vs. digital; MEMS sensors have been extensively used in automo- of co-chairing the MEPTEC-SEMI sym- vs. signal processing; power drivers vs. biles. In more recent published papers, I posium, November 10-11, along with anything. More on this topic later in Ivor have read that, for low lead counts, QFN- Rich Rice of ASE. Our thanks to all our Barber’s paper. type packaging can be cost and profile distinguished individual session leaders. competitive with WLCSP, especially if Cu They really did a terrific job recruiting all DAY 1 wire is used. The automotive IC market of our speakers and shaping the message SESSION 1: The Genius of Cars – and is forecasted to reach $28 B in 2017, up of each session. Of course, a great thanks Why Semiconductors Matter from $19 B in 2012. Professor Rao Tum- to our speakers, all recognized experts in Prasad Dhond, of Amkor Technology mala, of Georgia Tech, presented Systems their fields. For all involved, this means introduced us to some of the more strin- Scaling A New Fundamental Electronics putting some time aside from their already gent quality controls of package manufac- Frontier Technology. From 1970 to 2010, busy schedules. In some cases, there is turing for the automotive market. To my silicon node scaling progress has outpaced the added time and expense of travel. surprise, most of the Amkor automotive system line spacing by 200 to 1. Mobile Herein is the most gratifying aspect of package manufacturing is wire bonded, electronics systems are driving SiP type MEPTEC: recognized, accomplished and copper is well accepted. In my per- solutions including fine pitch and TSV professionals sharing their experience and sonal history with K&S Flip Chip Tech- expertise with colleagues, and, hopefully, nology (now Flip Chip International), the next generation of colleagues. originally a joint venture with GM Delco/ Our symposium this year, was sub- Delphi Electronics, flip chip and WLCSP titled “Systems in your Pocket” obvi- ously borrowing from some popular acro- nyms, SOC, SIP, POP. We have embarked on a new level of electronics system LRR Radar personal mobility: a smart phone in your (77 GHz) pocket; a smart watch on your wrist; a biomedical monitoring device inside your body; an infotainment system inside your automobile glove box; sensors and trans- mission devices in your automobile tires and under the hood; a driverless automo- bile (!); sensors in your clothing. The advancement of IC device inte- gration, Moore’s law in silicon, is a sig- nificant factor. Fewer, smaller chips, have more functionality. However, as device geometries approach single atom thick- nesses, Moore’s law is losing some steam, and encountering more expensive bar- riers to entry of the next node. The next (or current) venue for Moore’s law may SRR Radar well be packaging: multi-chip SiP, 2.5 D, (24/79 GHz) 3D, TSV, etc. Frankly, some silicon level technologies do not always integrate well onto a single chip, at least not cost effec- Sensor Technologies for Driver Assistance Systems. (Source: Freescale) meptec.org WINTER 2015 MEPTEC REPORT 15 interposers. Georgia Tech, working with Shinko and Unimicron, has developed new glass interposer technology

In SESSION 2: High Speed Compo- nents and Packaging, our speakers were Dr. Larry Zhu of Sarcina Technology; Ou Li, of ASE Group; and Dr. Hong Shi of Xilinx. Dr. Zhu discussed the cost and time to market advantages of mulit-chip and multi-package ASIC systems, and the particular interconnection challenges for 25 Gbps+ SerDes, where even BGA ball heights create significant differential impedance variations. Ou Li discussed chip-packaging-system co-design and the “tool box” to create virtual SOC. Dr. Shi took us one step further to 1TB data paths requiring 56 Gps transceivers. Our Tuesday keynote speaker was Dr. Joan Vrtis, CTO of Multek, a division of Flextronics, presenting Enabling a Connected World in the Age of Intelli- gence. Multek and Flex are spearheading battery technology, ICs, system design (also session leader), and Vincent Liao, wearable electronics, and were recently integration, and packaging of all have of ASE. Trevor Yancey discussed Cost featured in an article in BusinessWeek. enabled new generations of miniature, less Effective Multi Die Integration Solu- By 2025 connectivity is forecasted to be invasive, implantable devices/systems. tions for IOT, including extensive OSAT reach $2 T value, including consumer, MIMDs (Miniaturized Implantable Medi- SIP offerings in leadframes, substrates, agriculture, transportation, energy, and cal Devices) have reduced module sizes FOWLCSPs, etc. For automotive, there healthcare applications. This work starts from 15-50 cc’s, historically, to < 4 cc’s. are 3 levels of driver assist in automa- with a vision of creating new opportuni- Smaller devices can also be implanted tion: (1) Assist, include driver action; (2) ties in otherwise legacy markets. Pack- closer to the point of therapy. Partially automated, i.e. driver copilot; (3) aging and circuit technologies are key Fully automated, i.e. driverless. Interest- enablers. A small example: Multek has SESSION 4: Power Management ingly, 200 mm foundries are providing developed a shoe sole with sensors that and Energy Harvesting, Opposite the majority of IOT devices, specifically can determine foot pronation. A challenge Sides of the Same Coin Battery? MEMS sensors and RF. Ivor Barbor gave for wearable electronics: does it have to Professor Debbie Senesky, of Stanford us a lesson on single device integration be washable? There is also an interactive University, presented Gallium Nitride: A cost vs. multi-device SIP. Packaging cost dance floor which generates electricity. New Multifunctional Sensing Platform. is higher for multi-chip, especially with Dr. Vrtis quoted Daan Roosegarde’s “3 The unique structure of GaN may enable TSV interposers. However, given the phases of innovation”: (1) Cannot be a multitude of device and sensors applica- physics of defect density and yield per done; (2) Is not allowed, and (3) Why tions, and offers temperature range and wafer for very large, advanced geometry didn’t you think of this before? I might rad-hard advantages vs. silicon. Tim Dry node ICs, the die cost can be less for also add, Costs too much. (representing Dr. Jamie Schaefer), of smaller, better yielding chips. So two (or Global Foundries, presented 22DFDX more) chips, with interposer, vs. single SESSION 3: Medical and Wearables Technology Enables Energy Harvesting SOC, can be the more cost effective solu- for Human Health: Connecting the Solutions. 22FDX = 22 nm fully depleted tion. Xilinx is a leader in SSIT (stacked Dots from Silicon to Packaging. Wow, SOI, promising FinFET performance for silicon interposer technology) with TSV. this session really got to the heart (and the cost equivalent of 28 nm silicon pro- Advanced geometry nodes down to 65 nm the ear) of system in your whatever. Kurt cessing. Dr. Douglas Tham, of Silicium are available in interposers. Wafer bump- Koester, of Advanced Bionics, presented Technologies presented Energy Harvest- ing and micro-bumping (Cu post) is also Miniaturization of Cochlear implants. ing Technology Based on Next-Generation advancing to finer and finer pitches. Vin- Andrew Kelly, of Cactus Semiconduc- Thermoelectric Devices. Body heat may cent Liao introduced us to package level tor, discussed I.C. Design for Miniature provide the electrical power for the next conformal EMS and antenna on package Implantable Medical Devices. I personally generation of wearable devices. via metal sputter over mold compound. know some one with a cochlear implant, who was previously deaf. It is life chang- Day 2 SESSION 6: On the Road to SIP and ing gift, and packaging, a combination Our second day started off with SESSION Modules. Mike DeLaus, of Analog of implanted, and body worn compo- 5: Multi Die Integration, including pre- Devices, discussed how ADI, tradition- nents, makes it possible. Andrew Kelly sentations by Trevor Yancey of Tech- ally known as a single chip analog, mixed explained how MEMS devices, solid state search International, Ivor Barber of Xilinx signal and DSP devices supplier, has a

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roadmap for SiP and multi-device Hetero- per year is down 90% from year 2000. separations. An impressive example is geneous Integration. One potential exam- Silicon Catalyst is an incubator for new the Stratex 10 SiP, which includes 5 M ple: MEMS accelerometer, gyroscope, startups, offering an array of strategic logic elements, 10 B transistors, 1640 and ASIC in single package. Dr. Harrison supplier partnering and professional IO’s, FPGA, 64 bit ARM and transceiver Chang, of ASE, presented Co-Design mentoring, a virtual ecosystem of silicon on Si interposer. Tom Whipple, from the for High Density SiP. The high density experts encompassing design tools, test- CAD tool perspective, expounded further integration of heterogeneous SIP module ing, tape-out, fab & packaging production, on this integration of manufacturing dis- for IoT, wearables, and 5G, is driving the and financing. This minimizes the need ciplines and design tools, including the IC houses and OSATs to collaborate on to raise large seed cap and makes cash Pathways design environment, facilitating design for function, manufacturability, investment more impactful. Silicon Cata- more optimum layouts and package pin and testing methodology. This drives the lyst has been awarded the EDN/EE Times assignment with more flexible personnel OSAT to new expertise levels on EE/ ACE (A Champion in Education) 2015 skill levels. Tomoyuki Yamada introduced RF design, substrate layout, simulation, Startup Company of the Year Award. Si us to new low CTE organic laminate 2.5 and system validation. Dr. Ilyas Moham- Catalyst has selected 5 startups (from 50 D interposer in development, fine pitch mad, of Jawbone discussed SiP from a applicants) in 2015 to work with, includ- flip chip and line-space (6µ) capable, with Systems Perspective. The current state of ing Silicium in Session 4. build up to 5-2-5 levels. wearables includes on person computing (watches, glasses); on person health; and SESSION 7: IC-Package Co-Devel- SESSION 8: Wrap Up Panel Discus- in person health. Are we progressing to a opment in the New SIP Era. Pre- sion: The Great Consolidation. Paul sensor in your baby’s diaper, to tell you senters were Hui Liu, Altera, Product Werbaneth of Intevac led this panel, in- it’s time to change? Co-Development in the New SIP Era; cluding speakers and session leaders from On our second day, Wednesday, the Tom Whipple, Cadence Design, Chip- both days. We are seeing M&A from both key note speaker, Dr. Tarun Verma, a Package-Board Pathway Design Optimi- the IC manufacturer side (Intel-Altera, Partner at Silicon Catalyst, discussed zation; and Tomoyuki Yamada, Kyocera, Dialog-Atmel, TI-NS, Microchip-Micrel) Enabling the Next Generation of Semi- Advanced Organic Package Technologies, and the OSAT-Foundry side (JCET-STATS- conductor Startups. Dr. Verma has been Interposer and Embedded. Hui Liu dis- ChipPaC, ASE-?, Global-Charter). Who is a long time contributor to MEPTEC in cussed Product Co-Development in the going to be left? This trend is not unique his former role as Sr. Director of Pack- SiP Era. Front end and back end product to the semiconductor world. Since 1996, aging at Altera. The number of Seed/ co-development, including engineering 37 different financial institutions, globally, Series A deals for semiconductor startups and marketing, is supplanting traditional have been merged into 4. ◆ meptec.org WINTER 2015 MEPTEC REPORT 17 PROFILE

SHENMAO TECHNOLOGY INC. Now in its 43rd year, SHENMAO Technology Inc., founded by Mr. San Lian offers total solutions of Solder Materials Lee, Chairman and CEO of the globally leading solder material provider, to customers by meeting and exceed- started by manufacturing resin flux cored solder wire and solder bar in ing their quality and reliability require- 1973 at its Taiwan Headquarters, first for Taiwan and then for the Asian ments with products and service satis- faction accumulated over four decades market, continuously expanding since 1998 to 10 worldwide locations. of research and development experience. In the meantime, SHENMAO works closely with customers to develop new SHENMAO MICRO MATERIAL INSTITUTE application products on nanotechnology In order to research and develop the next generation of Solder Material products, SHENMAO for the electronics and other industries. established the SHENMAO MICRO MATERIAL INSTITUTE (SMMI) in 2003. The main purpose of From production to shipment, strictly the institute is to study and focus on the development and improvement of Micro Lead Free controlling each step, SHENMAO insists Materials with the highest Quality and Performance. The 1,500 square meter (16,146 Sq. Ft.) on using high quality raw materials to SMMI is staffed with 36 engineers (3 PhDs, 8 Masters) continuously developing Innovative New Lead Free Solder Alloys, New Lead Free Solder Paste and Fluxes. SMMI’s mission is to produce high quality products. Through improve on the ability of Product Development for a total solution through technological continuous improvement, cost reduction, innovation. SMMI has been working closely with electronic manufacturers, universities, and swift sales and service, SHENMAO keeps research organizations in the field for innovated material, technology, and failure analysis. making efforts to help customers to be competitive, creating a Win-Win situa- tion. SHENMAO Technology Inc., as the third largest Solder Materials provider founded in 1973, produces and markets SMT Solder Paste, Semiconductor Pack- aging Solder Spheres, Wafer Bumping Solder Paste, Dipping Flux, Wave Sol- der Bar, Solder Wire, Flux and Solder Preforms distributed from 10 worldwide locations as the strategic manufacturing partner of leading OSAT’s, the top EMS and OEM’s. SHENMAO Technology Inc. strives to offer the best quality without compromis- ing cost and time-to-market while pro- viding maximum value to all customers, always by superior customer service and technical support. Customer satisfaction and sustainable high quality are always SHENMAO’s priority.

18 MEPTEC REPORT WINTER 2015 meptec.org SHENMAO HEALTH, SAFETY AND SHENMAOSHENMAO HISTORY HISTORY ENVIRONMENT CONCEPTS SHENMAO Technology has achieved 1973 Established SHENMAO incorpora- 2006 Set up “SHENMAO Technology (Thai- and is maintaining the ISO 9001, ISO tion to manufacture Resin Flux Solder Wire land) Co., Ltd.”, plant and office in Thailand 14001, TS 16949, OHSAS 18001 and QC and Solder Bar. and “SHENMAO Europe GmbH” in Munich, 080000 Standards. In the future, SHEN- Germany. MAO Technology Inc. and their subsidiar- 1978 Expanded Plant and changed com- pany Name to SHENMAO Industry Co. Ltd. 2007 Signed a contract with SMIC for ies will continue to follow existing regu- licensing the patent of Sn-Ag-Cu Lead-Free lations, and seek different international 1982 SHENMAO received CNS Certificate Solder. Awarded OHSAS 18001 Certification. standard to pursue the best quality and Honor No. 3423 & 3424 for best quality Resin Awarded ISO/TS 16949 Quality Certification. fulfill the commitment to environmen- Flux Cored Solder Wire and Solder Bar. Established Dongguan Shen Yang Micro tal protection. SHENMAO Technology Material Co., Ltd. in China. has continually researched and developed 1986 Invited solder expert Mr. Akiyama green products which are more able to be 2008 Lead-Free Solder Paste approved by from Japan to take charge as Advisor. recycled in order to meet ROHS environ- Continental AG. Obtained “Taiwan Industrial ment protection regulations. The respon- 1987 Obtained Japan Industry Standard Sustainable Excellence Award 2008”, Signed sibilities of SHENMAO are to reduce the (JIS) Certification TW # 8716 & 8717. up Distributor “White Solder Ltda.” in Brazil and “Persang Alloy Industries Pvt. Ltd.” in impact on the environment, protect the 1989 Pooled capital with “JSKL” to set up India. Listed SHENMAO Technology Inc. on safety of its employees and customers, and an office in Hong Kong and expanded by set- the Taiwan Stock Exchange. support the communities where SHEN- ting up a plant in Guangdong, China. MAO does business. 2009 Introduced Wafer Bumping Solder 1990 Set up an office and plant of “Shen Paste for Semiconductor Industry. Estab- SHENMAO PRODUCTS Mao (M) Sdn. Bdh” in Penang, Malaysia. lished SHENMAO America, Inc. subsidiary in San Jose, CA, USA to manufacture solder Semiconductor Packaging Material 1997 SHENMAO obtained ISO 9002 Cer- paste locally for the North American market. tification. Signed up “NEVO GmbH” as European Dis- tributor in Germany and the Czech Republic. 1999 Expanded operations with a second Founded SHENMAO subsidiary SOLARJOIN

plant in Suzhou China for mass production TECHNOLOGY, Inc. in Taiwan to provide the for the ever growing demand of high qual- best PV Ribbon, Flux, for the Solar Industry. ity Solder Materials to serve the expanding Obtained HP re-approval of Halogen electronic manufacturing service companies. 2011 Free Lead Free Solder Paste and Halogen In cooperation with ITRI, developed the pro- Free Liquid Flux. Invested and set up Shen- cess to manufacture solder spheres. mao Electronics Technology (Chongqing) Limited in Chong Quing City, China P.R.C. 2001 SHENMAO set up a factory to pro- duce Solder Powder and with the coop- 2012 HP re-approved existing Low Silver eration of JOINT, Japan, to manufacture BGA Content Solder Materials. and Micro BGA Solder Spheres up to a capac- ity of 60 Billion per month. Obtained ISO 2013 Introduced Solder Paste and Flux 14000 Environment Accreditation. for PoP (Package on Package) applications. Founded the SHENMAO Technology Inc. BGA and Micro BGA Solder Spheres 2002 SHENMAO launched the latest Lead Branch Office in Japan. Free solder products featuring environmen- SHENMAO BGA Solder Spheres for tal concerns, obtained a sub-license from 2014 Started production of Solder Preform PBGA, CBGA, TBGA, CSP and Flip Iowa State University Research Foundation’s made available in Tape and Reel. Chip Assemblies are made by UMT (Ultra Pb-free Patent No.5527628. Micron Technology) from highly pure met- 2015 Put into production Micro BGA Sol- als produced to various exact Alloy com- 2003 Established SHENMAO MICRO MA- der Spheres sizes 55µ and 50µ available in six positions using Piezoelectric Droplet Jet TERIAL INSTITUTE for up-to-date soldering different Alloys. Released Novel Laser Solder- Technology in high volumes to accurate technology research. Obtained ISO 9001 ing Solder Paste and developed machine diameter uniformity, bright shiny surface Quality Certification. Obtained FUJI ELECTRIC to Dispense and Laser Soldering. Released CO., LTD., JAPAN 5 Elements alloy solder (Sn- Novel Laser Soldering Solder Wire. finishes and high quality sphericity. Vari- Ag-Cu-Ni-Ge) Japanese Patent No.3296289; ous diameters (from 0.76 mm to as small U.S. Patent No.6179935B1. 2016 SHENMAO Technology Inc. HQ and as 0.05 mm) are available at affordable plant in Taoyuan, Taiwan will expand add- low cost from 10 worldwide SHENMAO 2004 HP and Dell approved SHENMAO ing a near-by new plant currently under locations. SHENMAO High Drop-Resis- Lead-Free Solder Paste. Moved SHENMAO construction with the ability to smelt large tance Alloy PF902-S (SAC0307X) greatly Headquarters to Taoyuan and expanded the quantity Tin Ore, providing SHENMAO with increases reliability and performance of manufacturing plant. its own Tin supply. portable electronic devices drop test.

meptec.org WINTER 2015 MEPTEC REPORT 19 PROFILE

worldwide locations. It is said their low Lead Free Solder Paste viscosity (easy to apply), high tackiness SHENMAO provides Halide-containing (slump resistant), consistent printability for and Halide-free Solder Paste Fluxes togeth- BGA and Micro BGA Ball Assemblies and er with Lead Free Solder Powder sizes excellent wash ability after high tempera- from 2, 3, 4, 4.5, 5, 6, 7 and 8 to offer full ture reflow (255ºC and 60 seconds over selection of solder paste. 220ºC) create highly reliable solder joints with optimum maximized quality. A large Water Soluble Solder Paste chipset producer consistently uses SHEN- SHENMAO Technology offers a full line MAO SMF-WB02 / SMF-WB51 Water of Water Soluble Fluxes and Water Soluble Soluble Flux to achieve ultimately reliable Solder Paste for SMT and IC packaging and residue clean ball attach connections. applications. Halide-containing and Halide- free Fluxes for Tin/Lead as well as Lead- Free Solder Alloys. Our formulations, with wide process window, have been proven to be excellent in shell life, stencil life, wet- ting and clean-ability. Bumping Solder Paste SHENMAO Bumping Solder Paste Halogen Free Solder Paste PF608-PI-21 (Sn/Ag4.0/Cu0.5/x) and SHENMAO PF606-P26 No-Clean / Zero PF606-P-BS1 (Sn/Ag3.0/Cu0.5/x) aim to Halogen Solder Paste is made locally in the decrease voids in wafer bumping process USA and with the same quality in 8 other to yield excellent bump height unifor- worldwide locations. It is said to prevent mity. SHENMAO Micro Material Institute BGA Non-Wet Opens and Head on Pil- applications engineers focused on devel- low defects if there is oxidation on BGA oping the Bumping Solder Paste Formula Balls or PCB Pads. In case BGA compo- with excellent stencil printing transfer rate nents are warped, PF606-P26 thru excel- and the lowest Void to optimize manufac- lent printability, wetting and solder ability turing process performance. The world’s can create highly reliable solder joints that largest IC Packaging and Test Service Package on Package Solder Paste greatly reduce their failure rate. A Major OSAT’s utilize SHENMAO Bumping Sol- SHENMAO Package on Package Solder Chipset Producer is recommending the use der Paste in production. Paste provides excellent tacky property, of SHENMAO PF606-P26 Solder Paste great dipping, soldering and voiding per- to achieve ultimately reliable connections formance. to the PCB.

SMT Assembly Materials

SHENMAO Offers a Variety of Solder Paste Solutions

Tin Lead Solder Paste Tin Lead Solder Pastes are made from high purity metal ingot (Tin, Lead) with guar- anteed high quality. SHENMAO produces Laser Soldering Solder Paste solder powder and flux in house. Strict SHENMAO developed Novel Solder Paste Wafer Bumping Flux production and quality control, strong for Laser Soldering with good dispensing SHENMAO SMF-WB02 / SMF-WB51 technical and development team result in performance, low flux residue, low spatter- Water Soluble Flux are made locally in the reasonable price to meet each customer’s ing and no solder ball. USA and with the same quality in 8 other specific needs.

20 MEPTEC REPORT WINTER 2015 meptec.org SHENMAO LOCATIONS

TAIWAN HEADQUARTERS SHENMAO Technology Inc.



Paste Flux and Liquid Flux Solder Preform Full line of Water Soluble Fluxes and No- SHENMAO Solder Preforms offers accu- Clean Flux for SMT, IC packaging and NORTH AMERICA rate solder deposition for various solder- PCB Wave solder applications including SHENMAO America Inc., San Jose, CA ing processes. Reel packaging provides Halide-containing and Halide-free Fluxes opportunity of automation for efficient for Lead-Free Solder Alloys. Shenmao application. Custom Material may be for- Lead Free Liquid Flux has been approved mulated to unique material and dimen- by HP and Dell Computer. sional requirements. Solar Application Materials Wave Solder Assembly Materials

Solder Bar CHINA P.R.C. SHENMAO Solder Material (Suzhou) SHENMAO Solder Bar is made solely Co., Ltd. from high purity metal, produces a low proportion of dross and is suitable for dip Dong Guan SHEN MAO Soldering Tin Co., Ltd. and wave soldering. The quality meets J-STD-006 and JIS-Z-3282 standards. Dong Guan SHENYANG Solder Material Solder Bar is available specification in Solder Ribbon Co., Ltd. A grade, S grade, Anti-oxide Bar, Silver High quality Solder Ribbon manufactured SHENMAO Electronics Technology added Bar, Pure Tin Bar and other Lead by SHENMAO is available in many stan- (Chongqing) Ltd. Sales Office Free Solder Bars. dard alloys and sizes. It has the lowest flow Chong Qing City temperature, best wetting and best flow EUROPE characteristics. Formulated to unique alloy NeVo GmbH, Brno, Czech Republic and dimensional requirements. INDIA Persang Alloy Industries PVT Ltd. Waghodia, India

JAPAN SHENMAO Tokyo Sales Office MALAYSIA SHENMAO Solder (Malaysia) Sdn. Bhd SOUTH AMERICA Core Solder Wire White Solder, Ltda. SHENMAO Cored Solder Wire is specially Mariana, Ribeirao Preto – SP. Brazil designed with low residue, high solder abil- TAIWAN ity for Hand/Automatic soldering applica- Solder PV Ribbon and Plated Copper Wire SolarJoin Technology Inc. tions. Solder Wire is available in both Lead SHENMAO subsidiary company Solarjoin THAILAND Free and Tin Lead alloy compositions. No Technology, Inc. produces quality PV Rib- SHENMAO Technology (Thailand) Co., Ltd. Clean, Water Soluble, Halogen Free, RMA bon, Copper Wire and Flux to meet high- (Rosin Mild Activated), High Activity (for est reliability requirements. Special ribbon soldering on stainless steel, nickel, and sizes and alloys are available depending on For more information about SHENMAO aluminum surfaces) types are available for customer requests. Technology and their products please visit a variety of soldering processes. their website at www.shenmao.com. ◆

meptec.org WINTER 2015 MEPTEC REPORT 21 SYMPOSIUM

14th ANNUAL MEPTEC MEMS TECHNOLOGY SYMPOSIUM

Advancing MEMS and Sensors for Today’s Exploding Demands Wednesday, May 11, 2016 San Jose, California

f you are involved in the MEMS and Sensors Industry today, or are thinking about entering it, you are in the right place at the right time. Double digit growth fueled by inertial and other sensors in smartphones, wearables, and a plethora of IOT applications have garnered the I attention of many who not only see the financial rewards but also the possibilities of new and exciting markets. With this renewed growth comes a desire to reduce costs, decrease throughput times, scale to much larger volumes faster and continually in- novate with existing MEMS and sensors while preparing for the untapped broader markets. Linear technical innovations in design, processes, materials, packaging and test are enabling widespread commercialization of breakthrough MEMS products. While this is absolutely necessary to meet today’s demands, will it be sufficient for the future five to ten years from now? If we believe the analysts and commercial companies predicating tens of billions of connected nodes and sensor arrays by 2020, can our industry keep up by sticking to the path we are on? MEMS sensing applications will track growth in CE, mobile, wearable’s, medical, food and agriculture, environmental, energy and the catch all IOT/IOE markets. The 14th Annual MEPTEC MEMS Technology Symposium will focus on the fundamental MEMS technologies and manufactur- ing techniques to address this explosive growth short to medium term but also take a peek at what’s coming longer term that we all need to be aware of today. If you are involved in MEMS and Sensors design, processes, packaging, test and system integration you will not want to miss this one-day action packed and informative event.

Topics to include: MEMS Design – reusability and enabling faster time to market Test – design for MEMS testing and future trends Process Technologies – from prototypes to production better, faster cheaper Emerging Technologies – flexible, hybrid and printed Packaging – current and advanced techniques to scale more devices MEMS and sensors and functional in one package

REGISTER ONLINE TODAY AT WWW.MEPTEC.ORG

Platinum Sponsor Media Sponsors

Your Microelectronic Package Assembly Solution for MEMS Sensors PACKAGING

System-in-Package (SiP) – Shifting the Market

William Chen, Senior Technical Advisor ASE Group

AS WE MOVE TOWARDS A MARKET that’s becoming dominated by personal devices, we are seeing extensive creation and proliferation of connected devices and systems. How will this impact both industry and society in order to meet related requirements? One reinterpretation of the promise of integration is moving towards heterogeneous integration through System-in-Package (SiP). SiP module packaging provides an alternative and complementary solution Crossing Boundaries – SiP to Modules to System-on-Chip (SoC) for system integration and miniaturization, while adoption within mainstream semiconduc- why SiP is currently stimulating height- reducing development time, design cost, tor manufacturing. Chief among these ened interest and discussion across the time to market, and total cost of owner- are the rapid development and imple- expanding electronics ecosystem. Many ship. The sophistication of consumer mentation of new and innovative IoT and ecosystem players are coming to realize products emerging today demands more mobile products requiring heterogeneous the numerous benefits, including inte- diverse functionality – logic, memory, components and affordable development grated/embedded passives, heterogeneous MEMS, sensors, mixed signal, RF, power, costs, as well as the creation of differenti- components, smaller and simplified sys- and passives, all heterogeneous compo- ated platform solutions through system tem boards, reduced power consumption, nents – integrated into a single package integration and optimization. and decreased component size and thick- with a smaller and lighter form factor. Some leading players within the ness. Further simplification is achieved Besides the traditional SoC solutions, SiP Outsourced Assembly and Test (OSAT) through module level test and qualifica- is now increasingly being explored and community are moving beyond their tion, reduced system BOM and complex- implemented by design houses and system established core competencies and are ity, as well as the significant fact that SiP companies to meet new requirements for positioning themselves to serve the technology is flexible, re-usable, and re- their product development. industry’s SiP needs through leveraging configurable. SiP technology flexibility is According to the ASE Group, SiP can advanced IC packaging technologies to particularly important to design in product be defined as “a package or module that enable new generations of miniaturized functionality and differentiation, and per- contains a functional electronic system or electronic systems. Recent developments haps generating innovation in contributing subsystem that is integrated and miniatur- in advanced packaging technologies – to solutions that address concerns relating ized through IC assembly technologies.” wafer level packaging, fanout chip-first to privacy and security. Essentially, the subsystems are made up and chip-last, embedding packaging, TSV In summary, the industry is driving of individual dies that are manufactured 2.5D, wirebond and flip chip re-inventions towards functional diversification, hetero- separately, each using its own most cost- – have great potential for addressing geneous integration and miniaturization, effective node. For example, the ASIC (a a broad spectrum of SiP applications. with SiP establishing itself across the SoC) could be in one technology node, Through established expertise in core industry, supply chain, and ecosystem. additional memories in different nodes, competencies, IC packaging technology The drive for heterogeneous device inte- peripherals in still another node, together enables highly integrated and miniatur- gration, decreased size, lower cost, and with discrete and integrated passives, ized modular products. In addition, it is reduced time to market and revenue is MEMS, and different sensors. These com- crucial to understand the different market leading many established and emerging ponents can be successfully assembled segments and to provide SiP co-design players to explore the value proposition inside the package through a variety of and co-development initiatives to support of SiP. As an industry, we are at an early established techniques – perhaps together OEM product roadmap execution in these stage of a collaborative work-in-process. with additional features such as antennas segments. With this understanding, it is There is much work that needs to be done and shielding – in existing high-volume possible to deliver rapidly scalable, high- in the ecosystem to innovate new ideas manufacturing infrastructures. SiP is still quality, high-precision, and cost-effective and to implement new solutions to bring in its early stages. There are many com- SiP manufacturing capacity. SiP fully into the mainstream. ◆ pelling industry dynamics driving SiP There are many compelling reasons meptec.org WINTER 2015 MEPTEC REPORT 23 Your Microelectronic Package Assembly Solution for MEMS Sensors

Industrial Controls Closing the MEMS Sensor Product Life Cycle Gap from Development to Production

MICROELECTRONIC PACKAGE Located in Northern Ohio, SMART fied ISO-9001 manufacturer, SMART assembly is a key part of the $16.5B Microsystems opened a new facility with Microsystems incorporates design-for- commercial MEMS sensor market rep- over 15,000 square feet of ISO 6 (class manufacturing into the initial stages of resenting 22% of the market. In terms of 1000) and ISO 5 (class 100) cleanrooms. development—this decreases process unit growth, the MEMS microelectronic This state of the art facility, furnished iterations and reduces time needed as package assembly market is growing with flexible equipment capabilities for the product moves into volume produc- twice as fast as the IC package assembly assembling a high mix of materials and tion. By working concurrently with the market, but the needs of the entire life products, creates a turn-key solution for customer’s design team and suppliers, cycle of a MEMS product are not met. microelectronic package assembly of SMART Microsystems is able to imple- From development of initial manufactur- MEMS sensors. From prototyping all ment process specifications, design-to- ing processes and materials selection, to cost goals, and on-time delivery objec- prototype development, to environmental tives efficiently, reducing overall time life test qualification, to volume produc- and cost. SMART Microsystems applies tion, SMART Microsystems provides the this approach to aerospace, industrial, lowest overall development time and cost medical, and other markets and supports to satisfy the full life cycle requirements the package format—QFN, DIP, TO-can, of MEMS sensor products. chip-on-board, flip chip, or custom hous- Relatively common MEMS devices— ings—that is needed for the application. such as pressure, chemical, and optical In all situations, incorporating manufac- sensors—require custom package devel- turing objectives early reduces the devel- opment when being integrated into a opment time and cost, enabling SMART sub-assembly for niche applications. And Microsystems to scale-up quickly, sup- while many service providers (who focus MEMS Product Life Cycle Captured at port volume production, and meet quality on microelectronic package assembly of SMART Microsystems. assurance requirements. ICs) often underestimate MEMS sensor SMART Microsystems is located near development projects, SMART Micro- the way through market entry, SMART Cleveland, in a Midwest manufacturing systems focuses on microelectronic Microsystems is a single supplier, reduc- hub. Nearby access to an international package assembly of MEMS sensor ing the total cost of product develop- allows for fast and easy transpor- products to appropriately scope proj- ment. Prototype development and manu- tation to support medical, aerospace and ects. This reduces delays and increases facturing capabilities include dicing, die other markets that require the high-value, the ability to solve complicated process attach/flip chip, vacuum solder reflow, low-volume applications for MEMS sen- issues. SMART Microsystems provides wire bonding (ball and fine/heavy gauge sors. With a focus on MEMS package companies throughout the United States wedge with both wire and ribbon) and assembly and a certified ISO-9001 status, and Canada with MEMS sensor pro- encapsulation (adhesive dispense, lid seal SMART Microsystems creates the turn- totypes and has successfully brought and parylene coating). Environmental life key solution for customers. Accomplish- several new development programs to testing capabilities at SMART Micro- ing the full life cycle requirements of production readiness. Customers include systems include HAST, thermal shock, MEMS sensor products, SMART Micro- producers, manufacturers, and suppliers thermal/humidity cycling, high tempera- systems takes a design from prototype, who require microelectronic sub-assem- ture storage and accelerated UV durabil- through qualification, to volume produc- blies for sensor products. With expertise ity. Advanced inspection equipment is tion at the lowest overall development and a focus on MEMS sensor products, comprised of an acoustic microscope, time and cost. the SMART Microsystems engineering 3D X-ray, interferometer and a scanning More information about SMART team has solved many MEMS process electron microscope (SEM). Microsystems services can be found at challenges and understands the nuances Equipment capabilities at SMART www.smartmicrosystems.com. ◆ of MEMS sensor product development Microsystems deliver manufacturable needs. and sustainable solutions. As a certi-

24 MEPTEC REPORT WINTER 2015 meptec.org Industrial Controls Medical Applications Aerospace Systems

The SMART Advantage. Lowest Overall Development Time and Cost

SMART PROTOTYPE DEVELOPMENT As a turn-key solution, SMART Microsystems builds early proof-of-con- cept samples as well as feasibility studies to help you avoid challenges that appear early in process development. SMART Microsystems engi- neering team’s expertise in MEMS sensor products has solved many of these challenges.

SMART ENVIRONMENTAL LIFE TEST SMART Microsystems’ environmental life testing identifies reliability issues early in your MEMS sensor product development. As part of a turn-key solution, reliability study, or on an as-needed basis for overflow/band- width, SMART Microsystems can solve your issues before they become a problem in the field.

SMART MANUFACTURING SERVICES With the SMART Microsystems investment in state-of-the-art facilities and an experienced team, we are able to scale-up manufacturing quick- ly, support low-volume production, and meet your quality assurance re- quirements.

SMART Microsystems creates turn-key solutions for microelectronic package assembly challenges to move your MEMS sensor technology from development to production. With an engineering team experienced in manufacturing and state-of-the-art facilities, SMART Microsystems accelerates the transition of your new MEMS sensor product to the market.

Call us today at 440-366-4203 or visit our website at www.smartmicrosystems.com for more information about SMART Microsystems capabilities and services.

Your Microelectronic Package Assembly Solution for MEMS Sensors 141 Innovation Drive, Elyria, Ohio 44035 • [email protected] www.smartmicrosystems.com TECHNOLOGY

Packaging and Assembly Technology for the Internet of Things Era

Jayna Sheats, CEO Terecircuits Corporation

IT IS NOW RATHER WIDELY RECOG- because it is appreciably more expensive. aspect ratio, so the problem remains.) nized that the technology of integrated The current palate of “advanced These prominent issues for on-chip sig- circuit (IC) packaging has overtaken chip packaging” including fan-in and fan-out nals pertain also to interchip connections fabrication as the focal point of innova- WLP, interposers, and monolithic as well along with other issues (e.g. wirebond tion in electronic fabrication. Technical as through-silicon via (TSV)-based 3D inductance). trade journals are replete with articles integration, offers routes to increasing The clarity and simplicity of Moore’s about the latest advances in 2.5D, 3D and a product’s performance (e.g. clock fre- Law notwithstanding, what matters for even 3.5D packaging, and various forms quency or power), but not lower cost per the consumer is computing “power” (an of chip scale and wafer level packag- basic computing element (logic gate). The unfortunately subjective metric) per dol- ing (WLP). System-in-package (SiP) success of Moore’s Law fundamentally lar, not transistors per se. Predicting how modules, such as Freescale’s SCM-i.MX stems from the magic of planar process- to achieve increases in this metric is much 6Dual, Samsung’s Artik series, or the ing and the genius of lithographers: as more complicated. It is clear, however, proprietary but strategically important tools were developed to process smaller that shortening interconnects is vital, pro- Apple S1 (iWatch) occupy center stage for features, the cost of those tools rose more vided cost efficacy is maintained. designers. A recent (November 2015) Yole slowly than dimensions fell. In combina- The shortest possible connections report projects FOWLP as supplying the tion with larger wafers, the result has been between two chips are obviously obtained majority of the industry’s growth during (until recently) close to a constant cost by stacking (ideally face to face; TSVs the next several years. per unit area of silicon processed, and being a close second). Doing this cost- The impetus for this shift is with little hence steady (exponential) reduction in effectively has proved to be a formi- doubt a consequence of the inexorable cost per transistor. Short of some futuristic dable undertaking, having only recently approach of the end of Moore’s Law, an scenario with holographic processing of achieved significant commercial success event that astute observers have known volume elements, there is simply no way after 15 – 20 years of intensive industrial had to arrive at some point (for reasons to do this in the third dimension. Stacking development (taking ALLVIA to be the of atomic scale if no other). There are chips in 3D today means stacking chips pioneer of this stage). While progress will very few apparently viable options for whose cost arose from the manufacturing continue, it is worth asking if any other introducing major inventions into IC structure of planar processing, and can approach can be effective. fabrication, and even those currently in only give a product whose transistors cost For example, what might happen if the development are horrendously expensive more, not less. distinction between packaging of chips and complex. Packaging, on the other There are many reasons to pursue and assembly of circuit boards were elimi- hand, affords many attractive options at non-planar packaging despite the added nated? Conceptually, the architecture of a more customary costs. cost. For example, these same transis- printed circuit board (PCB) corresponds It is important to remember, however, tors may be able to work faster, or con- to that of a chip: functional elements that “More than Moore” does not offer the sume less power. As die size increases are connected by wiring. In the case of same advantages as Moore’s Law did. The in conventional scaling, global RC delay ICs, one first forms the active elements, latter, while originally expressed in terms increases as the 4th power of the scaling and then the interconnects. Arguably, at of transistor count per chip, was most factor. RC-related signal delay for global the time when interconnects were made fundamentally an economic phenomenon: interconnects increases even at constant with discrete wires, this is how PCBs the marketplace supported the cost of die size because dielectric and conductor were constructed: finished components the fantastic advances in equipment and thicknesses decrease, while local intercon- were placed on the board and then wired processes because they facilitated making nect delays remain constant. Since the together. transistors cheaper, not because they made longest lines are getting longer, resistive them run faster. Higher speed transistors power consumption also increases. (In The Challenge fabricated from III-V materials have been practice, line and dielectric thickness have There are both historical and practi- available for decades, but that is not the not decreased with the chip scaling factor, cal reasons why this is not done today. prevailing techology for most products but there is only so far one can go with In practice, the wide range of component

26 MEPTEC REPORT WINTER 2015 meptec.org sizes which may be encountered, e.g. 01005 capacitors and transformers, would 100 Polymer make it very difficult to move the popu- Polymer with sensitizer lated board through any integrated wiring process. Many products do not have this Irradiated polymer and sensitizer large range, but a conventional assembly 80 company must be prepared to handle all possibilities. Second, the historically rooted supply 60 chain and infrastructure of the industry does not readily embrace or facilitate change. PCBs predate modern IC archi- (%) Weight tectures; they were already used with 40 vacuum tubes, and 4-layer PCBs were in production at about the same time Jack Kilby came to Texas Instruments. Thus the technology for fabricating them in a 20 process (and typically location) separate from where components would be added was already well entrenched. At the same 0 time, the sensitive and easily damaged ICs 100 200 300 400 500 600 were packaged for protection and con- venient insertion (in most cases) into the Temperature (˚C) through-holes of those boards. Figure 1. Thermogravimetric analysis of the materials used in the photopolymer component The modern incarnation of this legacy transfer process; heating rate 10C/min. Faster heating eliminates the residue in the exposed will not go away anytime soon, but there material which in the TGA requires >100C to decompose. are numerous products, including typical wireless sensor modules, embedded con- mer-coated plate which is then aligned High-resolution interconnects are trollers, and many of the components of in close proximity to the target (in a tool best made on a planar surface. This is mobile phones which contain only surface similar to a contact aligner); irradiation obtained by placing the components face mount devices (ICs, sensors and passives). of the polymer (through the plate) behind down on a release layer and embedding These products, which comprise the foun- selected components with a dose typical them in a reflowable polymer which then dation of the IoT, give us an opportunity for microlithography and attendant mild becomes the substrate and matrix. Such to depart from conventional practices. heating causes its vaporization and release partial molding processes are certainly not At Terecircuits we have developed the of the components. new, and have been the subject of several technologies for an IC-like approach: This critical step allows the otherwise publications by Matti Mäntysalo and col- place unpackaged or minimally packaged delicate bare dice to be handled at high leagues at Tampere University in Finland, components onto a single substrate, inter- throughput with near-zero risk of dam- among others. Compared to conventional connect them, and encapsulate the entire age. Ultrathin (25 microns or less) and molding, embedding allows consideration circuit at once. This simple architecture extremely small (effectively limited only of a wider selection of polymers, optimiz- has the potential to cut the number of by the optical system) components are ing for example the coefficient of thermal process steps for such a product by 80% readily accommodated. Because of the expansion. or more, with concomitant reduction in array processing, throughput can be many Releasing this “front end” laminate materials use. Most importantly, it enables times greater than present pick and place from the temporary substrate and turning us to achieve a great deal of what 3D inte- tools with comparable capital and labor it over affords a substrate as flat as the gration is designed for, but with a process costs. chips themselves on which interconnects that is poised to actually reduce costs. Figure 1 shows the process window with resolution of a few microns can then between unirradiated and irradiated poly- be built up as desired. In essence the wir- Process Details mer; it makes process control substantially ing of the “PCB” is simply a continuation The process can be divided into three easier than for stamp transfer printing of that in the chips. Without a package parts: placement, embedding (which is (which relies on relatively small differ- surrounding the chips, their edges can be roughly equivalent to the molding in ences in adhesion between components, placed nearly contiguous (within a few conventional packaging), and interconnec- stamp and substrate) or laser ablation microns), resulting in a product rather like tion. The placement step in Terecircuits’ (where a narrow threshold margin sepa- one big chip (which of course could never process replaces the mechanical pick and rates ablated and unablated material). be made monolithically for a host of rea- place tool with a novel photopolymer That control is critical for achieving preci- sons). We might call it a “composite chip”. transfer operation: an entire array of com- sion, close-spaced placement in a parallel ponents is adhered to a transparent poly- (array) process with small components. continued on page 32  meptec.org WINTER 2015 MEPTEC REPORT 27 Uniting Thermal Control and EMI Absorption

Scott King Henkel Electronic Materials, LLC

THE SHRINKING DIMENSIONS AND These requirements were the driv- EMI absorption capabilities of 0.28 dB/ increasing functional capability of mod- ing factors behind the development of a mm at 2.4 GHz and 0.55 dB/mm @ 5 ern electronic devices place continual groundbreaking product that satisfies the GHz have been exhibited with GAP PAD demands on effective control of heat and need for both thermal control and EMI EMI 1.0. (Note: As material thickness, electromagnetic interference (EMI). Not management. Henkel’s GAP PAD® ther- part size and shape and other factors can only are new component and printed cir- mal interface materials portfolio, long largely influence EMI performance it cuit board (PCB) designs adhering to the is always recommended that GAP PAD miniaturization trend, but higher density EMI 1.0 be tested in the application for assemblies that place parts with differ- the best result.) ent operating frequencies closer to each In addition to its impressive thermal other are also becoming prolific. All of dissipation and EMI absorption perfor- these factors combine to place additional mance, GAP PAD EMI 1.0 is the softest stress on conventional EMI and thermal and most compliant thermal interface management protocols. material on the market. Its ability to Like heat management, EMI has been easily conform to various topographies analyzed by electronics specialists for and provide a high degree of flexibility decades and is well-understood. If not ensures very low stress on solder joints. controlled, EMI – which is a disturbance As compared to traditional EMI materials to an electrical circuit due to electromag- with high modulus, GAP PAD EMI 1.0 netic coupling from external sources – helps improve reliability by reducing in- can compromise or inhibit the function of field failures caused by solder joint stress a circuit, degrading signal integrity and recognized as the market’s most effective and fractures. impacting system performance and effi- gap filling thermal management product While its potential applications are ciency. In order to protect against EMI, line, has been extended with the addi- broad, GAP PAD EMI 1.0 is particularly the most common approach is the use of tion of a dual-function material. GAP well-suited for products in the consumer EMI shielding caps – metal lids attached PAD EMI 1.0 is the market’s first-ever electronics, telecommunications, and PC to grounding pads – to prevent outside extremely low stress thermal interface sectors. ASICs and DSPs can also benefit interference, minimize interference material that unites thermal conductiv- from use of GAP PAD EMI 1.0. The The smaller the device - the more solutions between components within a design ity and EMI absorption capabilities in a material is available in sheet and die-cut and to prevent crosstalk of components single product. formats, various thicknesses, custom part on printed circuit boards (PCBs). This With thermal conductivity of 1.0 sizes, and can be applied manually or No matter where you are or what your process requires, you can count on Henkel‘s expertise. solution has traditionally been highly W/m-K and EMI absorption for frequen- by automated placement. For electronics Our unmatched portfolio of advanced materials for the semiconductor and assembly markets all effective. However, as PCB component cies above 1GHz, GAP PAD EMI 1.0 specialists who are working with PCBs density becomes more challenging, the provides robust thermal management that challenge conventional approaches backed by the innovation, knowledge and support of Henkel‘s world-class global team ensures success of shielding caps – also known control and an added level of EMI pro- to heat management and effective EMI as Faraday cages – to control EMI may tection. Because of its improved wet-out control, GAP PAD EMI 1.0 is the ideal your success and guarantees a low-risk partnership proposition. require supplemental EMI absorption at the interface, GAP PAD EMI 1.0 solution. to make conductive shielding for elec- results in thermal performance that is For more information, visit www. tromagnetic compatibility (EMC) even superior to other competitive materials bergquistcompany.com. ◆ more robust. In fact, widely recognized with a similar rating. Thermal conductiv- industry standards defined to control ity is also enhanced by the material’s applications that use multiple frequencies natural tack on one side, which elimi- dictate effective EMI and heat transfer nates the requirement for any thermally- control for end product acceptance and impeding adhesive layers and also makes reliability. component rework simple. Uniquely,

28 MEPTEC REPORT WINTER 2015 meptec.org TThehe smaller smaller the the device device - -the the more more solutions solutions

NoNo matter matter where where you you are are or orwhat what your your process process requires, requires, you you can can count count on on Henkel‘s Henkel‘s expertise. expertise. OurOur unmatched unmatched portfolio portfolio of ofadvanced advanced materials materials for for the the semiconductor semiconductor and and assembly assembly markets markets all all backedbacked by by the the innovation, innovation, knowledge knowledge and and support support of ofHenkel‘s Henkel‘s world-class world-class global global team team ensures ensures youryour success success and and guarantees guarantees a low-riska low-risk partnership partnership proposition. proposition. PacTech - Packaging Technologies is a worldwide leader in both Wafer Level Bumping & Packaging Services and in Advanced Packaging Equipment Manufacturing. Packaging Technologies

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ALMOST 40 KILOMETERS NORTH- processes for the advanced packaging The electro-less plating line addresses west of Germany’s capital, Berlin, is industry. PacTech designs, manufactures applications in power MOSFET devices the city of Nauen where PacTech has its and supports solder jetting equipment, for clip attach, contactless RFID devices, headquarters. Founded as a spin-off of wafer-level solder ball transfer systems, high reliability power devices, and for the federal scientific Fraunhofer IZM in wafer-level solder rework equipment, Wire Bonding applications using Ni/Au, 1995, the company consists of two busi- laser assisted flip-chip bonders and Ni/Pd respectively, including Ni/Pd/Au ness units: automatic plating tools for high volume for Over Pad Metallization, and many electro-less Ni/Au and Ni/Pd/Au Under other applications. Ni/Pd Metallization 1. Manufacturer of advanced wafer level Bump Metallurgy (UBM) and Over Pad is qualified for volume production of packaging and wafer bumping production Metallurgy (OPM) through its global low cost Cu Wire Bonding over active equipment. sales network. pad. The new Ultra SB² tool is address- In its worldwide sales and applica- ing all wafer and substrate-related solder 2. Provider of high-quality, subcontract tion centers PacTech offers demonstra- ball applications for high volume mass manufacturing services. tion capabilities, including assembly production. PacTech has leading edge of samples and prototyping under ISO technology for Solder Ball Transfer, With subsidiaries in California and certified production conditions. More- Minimum Solder Ball diameter is 30 µm. Malaysia, the corporation supplies its over, PacTech has a unique dual business For the electro-less Plating Tool, PacTech outstanding solutions in these relevant model in which it offers its customers is the worldwide leader with more than business regions. with new chip designs or initial low vol- 20 Automatic Tools installed worldwide. PacTech has continually grown, and ume requirements the option to use in the Since its inception, PacTech has the company is to date the biggest high- initial phase PacTech’s demo centers for received more than 110 patents for prod- tech employer in the region with a staff services. After qualification of the prod- ucts developed in areas relating to wafer of some 350 people. uct the customer has the option of further bumping, flip-chip and chip-scale pack- In Europe, the U.S. and Malaysia, cost reduction by utilizing PacTech’s full aging, and laser-bonding technology. the full enterprise portfolio of differ- turnkey solution: Equipment, Process Also PacTech is providing all chemi- ent manufacturing services is available, and Technology. This reduces the cost cals for wet Chemical Pad Protection and as well as all of the backend solutions. of customers new product introductions Pad Metallization as part of a turnkey The advanced equipment manufacturing and at the same time gives the customer solution for electro-less Wafer Bumping. operations is located at the German HQ. the option to qualify and intensively Additional analytical services and sup- All machinery, sold originates from the study the technology, and understand port to customers is available. headquarters and carries the well-known the cost of ownership. Together with its It is PacTech’s mission to provide the brand: “Made in Germany”! partner and main shareholder NAGASE, highest level of innovative technology The company’s main target area is PacTech is also developing embedding solutions with an unparalleled degree of now the Asian markets, which consume technologies for wafer and substrate customer service orientation, corporate the lion’s share of products and services. level CSP technologies. The solder ball integrity and attention to its clients’ indi- With more than 20 years of experi- jetting equipment addresses markets like vidual technology demands. ence, PacTech is a prime manufacturer of Hard Disk Drive, Camera Module, Sen- More information is available at the leading-edge technology equipment and sors and Stacked TSV chip packages. PacTech website at www.pactech.de. ◆

30 MEPTEC REPORT WINTER 2015 meptec.org Your Partner for Advanced Packaging

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Wafer Bumping Wafer Backside Metallization - UBM & OPM Plating, e.g. - Wafer Thinning eless NiAu & NiPdAu, - Single Wafer Etch e-plate Cu & Au - TiNiAg & TiNiAu Evaporation - NiFe Plating for MEMS - Solder Ball Attach / Backend & Die Sort Solder Jetting - Laser Marking, Sawing, - Wafer Level RDL (Low Electrical Test Volume) - Tape & Reel - CSP & BGA Ball Rework - FC-Assembly

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 continued from page 27 ent curve) and the less testing is required. Photoprinting component transfer can Device infant mortality which is the main also be used to stack devices; the subse- The “composite chip” reason for burn-in can be brought below quent interconnect processes and prob- Such a composite chip in practice 0.5% by proper refinement of the process. lems are the same as for any 3D system. requires bare dice, however; even the Finally, wafer-level testing (including Both in-plane and vertical placements best CSPs will give component separa- non-contact approaches) is an actively may be advantageous for a given product. tions one to two orders of magnitude developing field; the same issues apply in larger. But bare dice are problematic to general to all 3D stacking architectures. Conclusion handle with pick and place tooling and The “composite chip” may sound a The innovations emerging in pack- are hard to connect due to irregular pad lot like what has been called a Multichip aging today could have been useful at locations (these points were emphasized Module (MCM), and indeed it is one vari- almost any stage in the last few decades, by Joseph Fjelstad, of Verdant Electron- ety (at Terecircuits, we refer to them as but they were far less compelling when ics, in a recent article in The PCB Design “integrated multichip circuits”, or IMCs). price per functionality could be decreased Magazine). The Terecircuits photoprint- MCMs were discussed with thoroughness at the same time that product perfor- ing component transfer process uniquely and great clarity nearly 20 years ago in mance increased. Now both of these enables such structures. With it, close, “Roadmaps of Packaging Technology” by trends are slowing or reversing. Stacking precise positioning of components such Bogatin, Potter and Peters (Integrated Cir- (either monolithically or by some form that lithographic connections can be made cuit Engineering Corp., 1997), who noted of bonding and wafer-to-wafer intercon- is not only possible, but actually cheaper that “MCMs did not become the vehicle nect) addresses the latter issue directly. than conventional packaging (cost mod- that made single chip packages obsolete. However, it will be quite some time, if eling predicts a reduction of more than They did not take over all of electron- ever, before the cost per gate of a finished 10x). ics. However, they represent over a $1B product (what is on the PCB) is decreased There is one more problem with market today.” The main impediment was by these techniques. The technology pre- bare dice (also emphasized in Fjelstad’s identified as the KGD issue. By using sented here, while perhaps not attaining article), which is testing and burn-in, or high-quality interconnects (especially the highest performance levels, still offers the availability of KGD (known good eliminating wirebonding), smaller dice, the potential for meaningful cost reduc- die). Fortunately, the smaller the die, the and mature processes for die fabrication, tions along with substantial performance greater the yield (based on exogenous this issue can be managed (as it must be improvements. ◆ defects; process variation follows a differ- also for any sort of 3D packaging).

OPINION

 continued from page 34 nologies. novel materials, wafer thinning and bond/ Another trend over the last few years de-bond, TSV characterization, automa- Europe and the SEMICON Taiwan SiP has been the shift in end-use markets for tion for back-end facilities, and more. Global Summit. However, in the last few semiconductors. Already, more semicon- In combination, the transformative years, we have seen a noticeable expan- ductors are sold into consumer products changes the industry is encountering – sion in participation from companies than into IT infrastructure. The industry from M&As, ecosystems shifts, strategic across the electronics supply chain. From is faced with a new set of time-to-market partnerships, IoT-fueled opportunity and system integrators, with Cisco, Micro- demands along with new pressures on growth, and international standards efforts soft, Huawei, Xaomi and other, through cost, performance and form-factor and – all of these efforts will help enable fabless, IDM, foundry, OSAT, EDA, companies involved in the packaging seg- advanced packaging to deliver on the equipment and materials suppliers – all ment are on the front line in addressing promise of system-scaling and drive inno- segments of the supply chain are now these needs. Co-design has become the vation well into the 2020s. represented in SEMI Advanced Packaging new norm and companies are collabo- As SEMI, our members and partners Committees around the world. rating – not just with the supply chain get ready to tackle another year of navi- To add to this intensity in the packag- segments on either side of them – but gating a rapidly changing ecosystem, we ing industry, it has become clear that very with their customers’ customer and sub- look forward to doing more together with few packages are single die any more. suppliers as well. industry stakeholders and associations The growth drivers in packaging – 2.5D, To enable efficiencies across this com- alike. There is great power in collabora- 3D, Fan-out Wafer Level Packaging plex network of technologies and constitu- tion and community-building. We have (FOWLP), SiP – are pushing towards a ents, the advanced packaging community seen it in our Standards task forces, our higher level of integration, and ultimately, is already working towards convergence Special Interest Groups and our events, system-scaling. To add to the complex- on a Standards platform. SEMI is adapt- and it’s the most effective and sustainable ity, the push from end-use customers in ing its International Standards efforts in way of keeping our promise – to advance various verticals keeps the industry on its packaging – focusing on multi-die integra- the growth and prosperity of our mem- innovating edge, creating a wide assort- tion and developing new standards in such bers. To you and yours, Happy Holidays ment of new options within these tech- areas as materials characterization for and a prosperous 2016! ◆

32 MEPTEC REPORT WINTER 2015 meptec.org FOR TOMORROW’S TECHNOLOGY

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Driving Innovation Through Transformative Change

Bettina Weiss and Tom Salmon SEMI

THE NUMBER OF MERGERS AND first such partnership with the FlexTech gaining momentum, and self-driving cars acquisitions (M&As) last year has been Alliance (www.semi.org/en/node/58856). are no longer science fiction. All this – the truly staggering. M&As and the subse- FlexTech will continue to pursue its mis- Internet of Everything – needs semicon- quent shifts in the semiconductor ecosys- sion of fostering the growth of the emerg- ductor devices. tem have had a profound impact on all ing flexible, hybrid and printed electronics Based on the exploding number of parts of the supply chain. Suppliers feel (FHE) industry – now, as part of SEMI, internet-enabled mobile devices and the the pinch of a smaller but more demand- while SEMI broadens its community emergence of the IoT, demand for sen- ing customer base, and must broaden their in this sector. FHE is high priority for sors, MEMS, analog, power and related product portfolios to remain competitive, SEMI members, especially in the context semiconductor devices is rapidly growing. while the entire semiconductor industry of the Industry of Things (IoT), because While these devices are critical to enable is forecast to grow by only single digits it combines elements of traditional IC the new era of computing, the applica- for the next few years. Customers may tions do not require leading-edge manu- now be system integrators or consumer facturing capability, and this demand is electronics manufacturers who have an For SEMI, the changes “breathing new life” into 200mm fabs. entirely different culture and way of doing According to SEMI’s recently pub- business. in the semiconductor lished “Global 200mm Fab Outlook to As 2015 came to a close, at SEMI, we industry make it 2018,” worldwide 200mm semiconductor reflected on an exceptional year. SEMI, wafer fab capacity is forecast at 5.2 million serving the electronics supply chain, has critically important wafer starts per month (wspm) in 2015 and seen its industry supply chains undergo a to partner to expanding to 5.4 million wspm in 2018 – transformative change – and trade asso- largely a reflection of IoT activity. ciations are changing as a direct result of increase value for these new dynamics. our members. Shift from Chip Scaling to System Scaling Strategic Partnerships a Key to So while consolidation is reducing the Expansion manufacturing with high-growth markets number of companies in the leading-edge What does this mean for regional in the areas of wearables, medtech, smart digital space, opportunities and growth and global associations? For SEMI, the manufacturing and “smart manufactur- still abound in emerging markets, fueled changes in the semiconductor industry ing.” Both organizations recognized that by IoT and new technology needs of make it critically important to partner to its activities were complementary and by vertical markets such as automotive, bio- increase value for our members. Value leveraging each other’s strengths, their medical and industrial automation. One means broadening engagement platforms, collective membership would benefit strong trend we see emerging, and some- deepening technical expertise, and offer- through access to more resources, global thing that was discussed in depth at the ing focused Standards and education platforms and new industry communities recent MEPTEC/SEMI symposium (see initiatives and events that bring stakehold- for collaboration, R&D initiatives, new page 15), is the shift from chip-scaling ers together, both to network and solve supplier-customer interactions and deeper to system-scaling. The focal point of this problems. We also realized that nobody engagement in Standards development. trend is solidly in the advanced packaging can go it alone because “organic growth” space. for companies and associations alike often IoT to the Rescue? SEMI has provided a platform for takes too long and lags behind innova- Internet of Things (IoT) is a tremen- programs in semiconductor packaging tion. To this end, SEMI has developed the dous opportunity for many companies for a number of years – from work on Strategic Association Partnership concept, in the ecosystem. This is good news for packaging Standards and collaboration a model that allows for a more formalized many companies: MEMS and sensors with JEDEC, IEEE and others in the early partnership with other associations and on flexible substrates for IoT and novel 1990’s to recent standards work on 3D-IC organizations, especially in adjacent mar- consumer products open the door to new and events like the SEMI 3D Summit in kets. markets and customers. Highly automated On October 7, SEMI announced its and IT-driven, “smart” manufacturing is continued on page 32 

34 MEPTEC REPORT WINTER 2015 meptec.org Connecting People and Technology

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