Netx 90 Technical Data Reference Guide

Technical data reference guide netX 90

Mass production

Table of contents

1 Introduction ...... 5 1.1 About this document ...... 5 1.2 List of revisions...... 5 1.3 References to documents ...... 6 2 General description and features ...... 7 2.1 Block diagram...... 9 2.2 Technical data netX 90 ...... 10 2.3 netX 90 signal description ...... 12 3 Core ...... 17 3.1 CPU ...... 17 3.1.1 Cortex®-M4 CPU ...... 17 3.1.2 xPIC CPU ...... 17 3.2 DMAC ...... 18 3.2.1 Overview ...... 18 3.2.2 Features ...... 19 3.2.3 Typical applications ...... 19 3.2.4 Functional description...... 20 3.2.5 Data transfer ...... 21 3.2.6 DMA channel priority ...... 22 3.2.7 DMA flow control ...... 22 3.3 Crypto core ...... 22 3.4 Memory map ...... 23 3.5 Brown-Out Detector (BOD) ...... 24 3.6 Reset ...... 25 3.7 Power-on reset and DC/DC ...... 26 3.8 System clock (oscillator) ...... 27 3.9 Temperature sensor ...... 27 3.10 Interrupt vectors ...... 30 3.11 Timer ...... 32 3.11.1 CPU timer ...... 32 3.11.2 IEEE 1588 system time ...... 33 3.12 Watchdog ...... 34 3.12.1 Function ...... 34 3.12.2 WDG_ACT signal ...... 34 3.13 Internal memory ...... 35 3.13.1 Internal Flash ...... 35 3.13.2 Internal RAM ...... 35 3.14 External memory ...... 36 3.14.1 Overview ...... 36 3.14.2 Features ...... 37 3.14.3 SDRAM interface ...... 38 3.14.4 SRAM/Flash interface to memory interface controller ...... 50 4 Booting and SYS LED ...... 61 4.1 Boot sequence and boot mode ...... 61 4.1.1 Overview ...... 62 4.1.2 Standard boot mode ...... 62 4.1.3 Console mode ...... 63 4.1.4 Alternative boot mode...... 63 4.2 System LED ...... 64 5 Interfaces ...... 65 5.1 MMIO - Multiplex Matrix ...... 65 5.2 Host interface ...... 67 5.2.1 Overview ...... 67 5.2.2 Block diagram ...... 67 5.2.3 Features ...... 68 5.2.4 Dual-port memory interface structure ...... 69 5.2.5 Parallel dual-port memory interface ...... 70 5.2.6 Serial dual-port memory interface ...... 83 5.2.7 Handshake registers...... 90 5.2.8 Parallel dual-port memory timing ...... 93 netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Introduction 3/275 5.2.9 Serial dual-port memory timing ...... 123 5.3 SQI/SPI ...... 132 5.3.1 Overview ...... 132 5.3.2 SQI ...... 134 5.3.3 SPI0…2_APP and SPI_XPIC_APP ...... 151 5.3.4 SQI0…1 ...... 156 5.4 I2C ...... 157 5.4.1 Overview ...... 157 5.4.2 Block diagram ...... 158 5.4.3 Features ...... 159 5.4.4 Typical applications ...... 159 5.4.5 Functional description...... 159 5.4.6 I2C devices ...... 159 5.4.7 I2C signals ...... 159 5.4.8 I2C signal conditions ...... 160 5.4.9 I2C transfers ...... 160 5.4.10 I2C acknowledge handling ...... 161 5.4.11 I2C 10-bit addressing ...... 161 5.4.12 I2C general call ...... 162 5.4.13 I2C cycle stretching ...... 162 5.4.14 I/O timing ...... 163 5.5 Multi LED ...... 164 5.5.1 Overview ...... 164 5.5.2 Features ...... 164 5.5.3 Typical applications ...... 165 5.5.4 Functional description...... 165 5.5.5 Time-multiplexed PWM mode ...... 166 5.5.6 Pass-through mode ...... 167 5.5.7 Features for both modes ...... 167 5.6 GPIO ...... 168 5.6.1 Overview ...... 168 5.6.2 Features ...... 170 5.6.3 Typical applications ...... 171 5.6.4 Functional description...... 171 5.6.5 Simple read/write modes ...... 171 5.6.6 Counter as system timer ...... 172 5.6.7 Event time capture...... 172 5.6.8 Event counting ...... 174 5.6.9 Active time measurement ...... 175 5.6.10 Watchdog mode ...... 175 5.6.11 Standard PWM ...... 176 5.6.12 PWM with shadow registers ...... 176 5.6.13 DC-DC PWM ...... 178 5.6.14 Sequencer ...... 179 5.6.15 Sharing between different CPUs ...... 180 5.6.16 Interrupt handling ...... 180 5.6.17 I/O timing ...... 181 5.7 PIO (application) ...... 182 5.8 BiSS/SSi ...... 183 5.8.1 Overview ...... 183 5.8.2 Functional description...... 183 5.8.3 Trigger sources ...... 184 5.8.4 Interrupt logic ...... 184 5.9 EnDat ...... 185 5.9.1 Overview ...... 185 5.9.2 Functional description...... 185 5.9.3 Trigger sources ...... 186 5.9.4 Edge detector and pulse former ...... 186 5.10 CAN controller ...... 187 5.10.1 Features ...... 187 5.11 UART ...... 188 5.12 IO-Link controller ...... 191 5.12.1 Introduction ...... 191 5.12.2 Typical application ...... 192 5.13 ADC ...... 193 5.14 Motion / motor control ...... 194 5.14.1 Target applications ...... 194 5.14.2 Features ...... 195 netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Introduction 4/275 5.14.3 Motion Pulse-Width Modulation (Motion PWM) ...... 196 5.14.4 Motion Encoder Interface / Quadrature Decoder ...... 206 5.15 Ethernet interface ...... 215 5.16 Fieldbus interface ...... 217 6 Debugging ...... 218 7 Electrical specification ...... 219 7.1 I/O ports ...... 219 7.2 Current consumption ...... 220 7.3 Oscillator ...... 222 7.4 Power-on reset and DC/DC ...... 223 7.5 BOD ...... 224 7.6 ADC ...... 225 7.7 Flash memory...... 226 7.8 Ethernet PHY ...... 226 7.9 MMIOs ...... 228 7.10 External SDRAM ...... 229 7.11 External SRAM / FLASH ...... 229 7.12 Parallel dual-port memory ...... 229 7.13 Serial dual-port memory ...... 229 7.14 QSPI ...... 230 7.15 SPI ...... 234 7.16 I2C ...... 237 7.17 UART ...... 238 8 netX 90 package and signal information ...... 239 8.1 Pin table sorted by signals ...... 239 8.2 Pin table sorted by pin number ...... 245 8.3 Pin overview netX 90 ...... 251 8.4 PAD type ...... 253 8.4.1 PAD type explanation ...... 253 8.4.2 Schematic view of netX 90 PAD types ...... 254 8.5 netX 90 package ...... 255 8.6 Thermal resistance ...... 257 8.7 Handling standards ...... 258 8.7.1 Moisture sensitivity level ...... 258 8.7.2 Storage, floor life and bake time ...... 259 8.7.3 Reflow sensitivity classification ...... 261 9 Appendix ...... 263 9.1 Terms, abbreviations, and definitions ...... 263 9.2 Legal notes ...... 266 9.3 Registered trademarks ...... 269 9.4 List of tables ...... 270 9.5 List of figures ...... 271 9.6 Contacts ...... 275

1.2 List of revisions

Rev Date Name Chapter Revision 3 2019-05-08 HNE, 3.6 Section Reset added. HHE 4.1.1 Section Overview added. 4.1.3 Section Console mode: Table 15 updated. 5.14.3 Section Motion Pulse-Width Modulation (Motion PWM) added. 5.14.4 Section Motion Encoder Interface / Quadrature Decoder added. 8.4.2 Section Schematic view of netX 90 PAD types corrected. 8.7 Section Handling standards added. 4 2019-10-11 NMÄ, 2.2 Section Technical data netX 90 updated. HHE 3.9 Section Temperature sensor expanded. 5.13 Section ADC updated. 7.1 Section I/O ports added. 7.2 Section Current consumption added. 7.3 Section Oscillator expanded. 7.6 Section ADC updated. 7.7 Section Flash memory added. 7.8 Section Ethernet PHY added. 7.9 Section MMIOs added. 7.10 Section External SDRAM added. 7.11 Section External SRAM / FLASH added. 7.12 Section Parallel dual-port memory added. 7.13 Section Serial dual-port memory added. 7.14 Section QSPI added. 7.15 Section SPI added. 7.16 Section I2C added. 7.17 Section UART added.

5 2019-10-16 NMÄ, 7.1 Section I/O ports updated: Value for Max. RPD is 144.

HHE 7.3 Section Oscillator: Values for VITH updated. 7.4 Section Power-on reset and DC/DC expanded: Information added for use case “integrated DC/DC converter is not used”. 7.5 Section BOD: Values BOD_T and BOD_H updated. 7.6 Section ADC: Values for ADC_INL updated. Table 1: List of revisions

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Introduction 6/275 1.3 References to documents This document refers to the following documents: [1] Hilscher Gesellschaft für Systemautomation mbH: regdef_netx90_arm_app.html, Englisch, 2019. [2] Hilscher Gesellschaft für Systemautomation mbH: Design-In Guide, netX 90, DOC180501DG05EN, Revision 5, English, 2019-07. [3] Hilscher Gesellschaft für Systemautomation mbH: Getting started, netX Studio CDT, netX 90 development, DOC170504GS08EN, Revision 8, English, 2019-05. [4] Hilscher Gesellschaft für Systemautomation mbH: Programming Reference Guide, xPIC Instruction Set, netX 6/10/51/52, DOC141201PRG01EN, Revision 1, English, 2015-02. [5] ARM: ARMv7-M Architecture Reference Manual, ARM DDI0403E.B, English, 2014. Download: http://infocenter.arm.com/help/index.jsp [6] Philips Semiconductors: The I2C-Bus Specification, version 2.1, 01.2000, English. [7] iC-Haus GmbH: http://www.biss-interface.com/ [8] ams Sensors Germany GmbH: http://www.mazet.de/en/products/industrial-metrology/data- sheets/item/445-endat-2-2-master-basic.html [9] IPC/JEDEC J-STD-020E (December 2014): Moisture/Reflow Sensitivity Classification for Nonhermetic Surface Mount Devices [10] IPC/JEDEC J-STD-033D (April 2018): Handling, Packing, Shipping and Use of Moisture Reflow, and Process Sensitive Devices Table 2: References to documents

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 General description and features 7/275 2 General description and features The netX 90 is a highly integrated Industrial Ethernet node in a 10x10 mm2, 144-pin BGA footprint with two ARM® Cortex®-M4 cores, on-chip Flash memory, Fast Ethernet PHYs, DC/DC converter, POR circuit, and a feature-rich set of on-chip peripherals. The industrial communication SoC fulfils the highest demand on flexibility, determinism and performance in terms of multiprotocol capability and low latency for short cycle times. As a result, the netX 90 provides a superior solution with an unmatched protocol flexibility for a variety of industrial slave or device applications in the process and factory automation.

Enhanced multiprotocol capability The SoC features two flexible communication (xC) IPs (Intellectual Property), which support all popular Industrial Ethernet standards, i.e. hard real-time. Most importantly, the xC architecture flexibly adapts by software to emerging standards and future network requirements such as TSN.

Two separate system paradigms One highlight of the chip’s internal architecture is the logical separation of the communication tasks and the application tasks, both from software quality and security aspects. The partitioning restricts the software access to on-chip peripherals on either side.

Built-in security and diagnostics Built-in security features enable developers to apply a secure by design concept by building layers of security as outlined in the IEC 62443, coupled with built-in diagnostics to monitor operating conditions for IIoT-enabled cloud services, e.g. predictive maintenance.

Prebuilt communication firmware Software protocol stacks for communication tasks come as prebuilt firmware, i.e. tested and pre- certified by Hilscher. The data exchange with the protocol stack interface using the dual-ported memory (DPM) enables application developers to quickly set up a network prototype.

Two primary design-in uses cases Suitable for modular embedded designs as a companion chip with host interface that easily pairs with any custom-specific host application processors. The host interface ensures a high degree of interoperability for maximum data throughput as either parallel or serial interfaces. Suitable for standalone chip application designs that make use of the second Cortex®-M4 at 100 MHz with DSP and FPU support, enhanced by a feature-rich set of standard and industry-related peripheral units with connectivity for highly compact product application designs.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 General description and features 8/275 netX 90 at a glance  Best-in class real-time Supports PROFINET IO Device V2.3 with Fast startup (FSU), Dynamic Frame Packing (DFP), and Fast-Forwarding (FFWD)  Scalable SoC platform Standalone chip application or companion chip with host interface  Multiprotocol capability Supports all known Industrial Ethernet and Fieldbus standards  Embedded application Feature-rich set of standard and industry-related peripheral units  Industrial IoT ready Built-in security and diagnostic features for IIoT enabled services  Energy-efficient SoC Suitable for product application designs with smallest form factors

Application examples  Multiprotocol chip interface for motion control  Black channel communication for functional safety  Variety of sensors and actuators for industrial control  Gateway interface or adapter module for universal encoders  Remote I/O with multichannel IO-Link or as analog/digital I/O blocks Suitable for any type of slave or device applications that require Industrial Ethernet or Fieldbus connectivity such as instrumentations, pneumatics, gateways, and many more.

LVDS-MII tunnels 2ch Ethernet PHY

2xMII+MDIO or 2xFieldbus SWD/JTAG GPIO xPIC App port System Master Start (reset release) from Boundary Scan System Slaves/Dataswitch 2x PHY-Ctrl Com-Side (global 8x IO-Link NETX Ctrl) 1x I2C Memory (SRAM, read-only, ext.) xC01 SWD trace 1x UART Subsystem CoreSight, ETM 1x SPI Peripherals (int, ext) Trig/Sample CPU-Ping CPU-Ping FMMUSM Cortex M4 Cortex M4 Analog Macros Systime LT Systime LT Pointer FIFO Timer Subsystem Subsystem Timer ARM Com ARM App xC BufMan WDG WDG xC Systime VIC NVIC Crypt System NVIC VIC xMAC xMAC xC Bridge MPU MPU AHB Master Channels xPIC Com Debug Slave SHA1 (160) xPIC App FPU Subsystem Subsystem tPEC tPEC rPEC AHB Slave Channels rPEC SHA2(256,284,512) AES(128,192,256)

2x 8kB dRAM 8kB dRAM Debug Master 8kB dRAM Cfg Channels (APB) MD5 4x 8kB pRAM 8kB pRAM DMAC RSA / ECC (MTGY) DMAC 8kB pRAM (4 ch) (4 ch) xPIC Com System xC Config D S cfg D I cfg D I S D I S cfg cfg D I xPIC App System INTRAM, INTFLASH: BIST, ECC(2bit detect, 1bit cor.)

INTRAM0 128kB Com ARM INTRAM1 128kB Communication Side Dataswitch Shared Dataswitch Application Side Dataswitch No access from application side except via IDPM. Access from communication side possible for debug INTRAM, INTFLASH: INTRAM2 128kB Master: Access to both sides Access to App side possible for debug and secure boot. and secure boot. BIST, ECC(2bit detect, 1bit cor.) xC01 INTRAM3 64kB For accessibility view netxtiny_master_slaves interconnection Excel sheet Access to Com-side only via IDPM. Framebuffer INTRAM4 64kB For accessibility view netxtiny_master_slaves INTRAM6 32kB App ARM interconnection Excel sheet. Com xPIC INTRAM5 32kB INTRAM7 32kB App xPIC Dual Handshake Cells Slaves/Memories: Access from both DPM Tripple boot Win sides, Com has higher priority INTFLASH2 512kB Buffer INTRAMHS 32kB App ARM boot Com ARM BootROM 128kB Win

INTFLASH0 512kB Slave INTFLASH1 512kB IDPM

GPIO ARM App port

) M Win Win ) Peripherals: 4x GPIO ) M-ADC Peripherals: Motion: 8x GPIO prog / 2x I2C 1x Timer prog 1x I2C 2x BISS/SSI 3x Timer / DPM0/ SPM1 prog CTRL / MB MB

cfg RDY/RUN PWM 1x UART 2x EnDAT PWM ( Clock 32 64 cfg IDPM cfg acyclic SDRAM / (

SPM0 NVRAM 1 BOD Stat / Ping Ping 1

Reset Ctrl Multimaster Watchdog Reset-Out Capture 3x SPI M-PWM Capture / Supervisor - - 2 4x ADC Systime x Systime CS x 0 1CS x CS x ETH

general or , 2 3 1

CRC Event 2x SQI M-Encoder Event XiP cfg 12bit SAR, nFIFO

, 256MB ( ) UART ) fast cyclic MAC gBufMan DPM Flash CPU CPU Watchdog

/ Stream 2x CAN Stream Systime LT Systime LT ECC status ECC status 1MS/s n 0 Memory BIST

MHz EA data LVDS CTRL MHz Timer _ Intlogic App 5

Blink SQI 29x PIO Blink Intlogic Com . SQI eXecute in Place / Timer 2 active ( 400 Intlogic Shared - ( 4x SH INTFLASH BOD DPM INTFLASH SPI

RstIn ExtBus8/16 PwrOnRst PLL OSC Wdg HIF Ain MUX MII2 )

DPM HostCPU16 8 + .

or 8 + Global NETX Ctrl VDD 2 x Ain

SPM0 + 2

VDD3.3 4x Multi-LED Ctrl ( 8x Multi-LED Ctrl or 20 MLED0..3 SPM0 SPM1 MLED4..11 DC/DC external or MMIO cfg Temp LX VDD3.3 crystal 8x Com-LEDs MEM8 cfg of external memories -> (25MHz) or 16x App-LEDs VDDcore MEM16 IO-cfg (MUX, physical) VDDcore or 18 MMIO

Category Features Communication Application Core ARM® Processor Cortex®-M4 at 100 MHz with MPU Cortex®-M4 at 100 MHz with MPU and FPU Hilscher 32-bit RISC xPIC at 100 MHz with 2x 8 KB TCM xPIC at 100 MHz with 2x 8 KB TCM Memory SRAM (ECC) 576 KB 64 KB Flash (ECC) 1024 KB 512 KB Mask ROM 128 KB - System DMA controller 4 channels 4 channels WDC (ARM / xPIC) 1 / 1 1 / 1 Timer (ARM / xPIC) 3x 32-bit / 3x 32-bit 3x 32-bit / 3x 32-bit Built-in bootloader Host Interface (DPM/SPM), Ethernet (xC0 DHCP/TFTP), Serial (UART, e.g. FTDI USB to UART bridge) Network xC Subsystem 2 channels - IEEE 1588 SysTime 2 1 Fast Ethernet PHY Dual-port, FX support - 100 Mbps LVDSPHY Dual-port - Ethernet MAC Ethernet MAC 10 / 100 Mbps, MII Peripheral UART (up to 6.25 Mbaud) 1 (shared) 3 SPI (up to 50 MHz) - 4 SQI (up to 50 MHz) 2 (Master only, with SPI mode) I2C (up to 3.4 MHz) 2 2 CAN 2.0B (up to 1 Mbps) - 2 IO-Link V1.1 controller - 8 channels MLED (PWM tuned) 4 8 HIF PIO / PIO / GPIO / MMIO - / - / 4 / - up to 41 / 29 / 8 / 18 Mixed signal Timer (PWM, IC/OC) 4x 32-bit (min. 10 ns) 8x 32-bit (min. 10 ns) Motion PWM unit - 1 ADC SAR (12-bit, 2 Msps) 2x 2 channels and 2x 8 channels Quadrature decoder - 2 EnDat 2.2 (Master E6) - 2 (with RTM) BiSS / SSI (Master BiSS C) - 2 / 2 Host interface Parallel (DPM) 8/16-bit (Read access min. 55 ns) Internal 32-bit Serial (SPM) 2x SPI (up to 125 MHz) / - 2x SQI (up to 33 MHz) MAC (PHY mode) MII (10/100 Mbps) - External SRAM / NOR / NAND / ✓ / ✓ / - / ✓ (8/16-bit) memory SDRAM SD/MMC / SDIO SPI mode / - SQI (XiP) ✓ Security Crypto core SSL/TLS accelerator, up to RSA-4096, ECC-512, AES-256, and SHA-512 Secure boot Mask ROM code, RSASSA-PSS/ECDSA Built-in support Security levels, AHB Firewall Debug Debug / Trace JTAG/SWD, 4-bit TPIU Boundary scan JTAG

Category Features Communication Application Analog DC/DC / POR / BOD ✓ / ✓ / ✓ Thermal diode ✓ Clock supervisor Xtal (RC-Osc) Electrical Power supply Single 3.3V

Temperature range Tj -40°C ... +125°C Power consumption ≤ 1 W Package dimension 144-pin BGA, 10x10 mm2, 0.8 mm Ball Pitch Table 3: Technical data

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 General description and features 12/275 2.3 netX 90 signal description This list groups the signals of the pin assignment table with the multiplexed signals (“shared with” operating modes), see chapter netX 90 package and signal information on page 239.

General RST_IN_N Reset input RDY_N Ready (RDY-LED/console mode) RUN_N Run (RUN-LED/Alternative boot mode) MLED0…3 Multi-LED/Status LEDs COM0/1 COM_IO0…3 Communication input output/peripherals RST_OUT_N Reset output Power VDDC Power supply voltage, core VDDIO Power supply voltage, input output VSS (GND) Ground PHY_VDDC Internal PHY, power supply, core PHY_VDDIO Internal PHY, power supply, input output VDD_PLL Power supply voltage, core - phase lock loop Misc Analog OSC_XTI (XTALIN) 25 MHz Crystal input OSC_XTO (XTALOUT) 25 MHz Crystal output DCDC_LX_OUT DCDC output inductor VSS_REF Ground, reference voltage VREF_ADC Reference voltage, analog-to-digital converter BOD Brown-out detection MII – Media-Independent Interface (External Ethernet PHY) MII_MDC Ethernet MAC management data clock MII_MDIO Ethernet MAC management data input output MII0+1_RXCLK Ethernet MAC receive clock MII0+1_RXD0…3 Ethernet MAC receive data 0...3 MII0+1_RXDV Ethernet MAC receive data valid MII0+1_RXER Ethernet MAC receive error MII0+1_TXCLK Ethernet MAC transmit clock MII0+1_TXD0…3 Ethernet MAC transmit data 0...3 MII0+1_TXEN Ethernet MAC transmit enable MII0+1_TXER Ethernet MAC transmit error MII0+1_COL Ethernet MAC collision MII0+1_CRS Ethernet MAC carrier sense PHY0+1_LED_LINK_IN Ethernet PHY Link LED input CLK25OUT Clock 25 output LVDS (Integrated dual LVDSPHY) LVDS0+1_RXN LVDSPHY, receive input negative LVDS0+1_RXP LVDSPHY, receive input positive LVDS0+1_TXN LVDSPHY, transmit output negative LVDS0+1_TXP LVDSPHY, transmit output positive

PHY (Integrated dual Ethernet PHY) PHY_EXTRES Ethernet PHY, reference resistor PHY0+1_RXN Ethernet PHY, receive input negative PHY0+1_RXP Ethernet PHY, receive input positive PHY0+1_TXN Ethernet PHY, transmit output negative PHY0+1_TXP Ethernet PHY, transmit output positive FO (Fiber optic) FO0+1_RX Ethernet PHY, fiber optic receive data FO0+1_SD Ethernet PHY, fiber optic signal detect FO0+1_TX Ethernet PHY, fiber optic transmit data FO0+1_EN_TX Ethernet PHY, fiber optic enable control MMIO MMIO0…17 Multiplex matrix I/O 0...17

PIO_APP PIO_APP0…28 Programmable Input/Output, Application side

MENC MENC_MP0+1 Motion encoder MP MENC0+1_A Motion encoder, input A MENC0+1_B Motion encoder, input B MENC0+1_N Motion encoder, input index

MPWM MPWM_BRAKE Motion Pulse Width Modulation, Brake MPWM_FAIL Motion Pulse Width Modulation, Fail MPWM0…5 Motion Pulse Width Modulation 0…5 HIF (8-bit or 16-bit DPM interface) HIF_A0...17 Host interface address lines 0…17 HIF_BHEN Host interface, byte high enable HIF_CSN Host interface, chip select HIF_D0...15 Host interface data lines 0…15 HIF_DIRQ Host interface, data interrupt request HIF_RDN Host interface, read HIF_RDY Host interface, ready HIF_SDCLK Host interface, serial data clock HIF_SIRQ Host interface, synchron interrupt request HIF_WRN Host interface, write DEBUG JT_TCK JTAG test clock JT_TMS JTAG test mode select JT_TDI JTAG test data input JT_TDO JTAG test data output JT_TRST JTAG test reset SWDCLK Serial Wire Debug clock SWDIO Serial Wire Debug data input output TRACE_DATA0…3 Trace port data TRACECLK Trace port clock TRACECTL Trace port control

EXT (Extension bus/memory interface) EXT_A0…17 Extension bus address lines 0…17 EXT_BHEN Extension bus byte high enable EXT_CS0…2N Extension bus chip select 0…2 EXT_D0…15 Extension bus data lines 0…15 EXT_RDN Extension bus read enable EXT_RDY Extension bus ready EXT_WRN Extension bus write enable IO_LINK (Controller interface) IO_LINK0…7_IN IO-Link 0…7 input IO_LINK0…7_OE IO-Link 0…7 output enable IO_LINK0…7_OUT IO-Link 0…7 output IO_LINK0…7_WAKEUP IO-Link 0…7 wake up SDRAM (Synchronous Dynamic Random Access Memory interface) SD_A0…12 SDRAM address lines 0…12 SD_BA0 SDRAM bank address 0 SD_BA1 SDRAM bank address 1 SD_CASN SDRAM column address strobe SD_CKE SDRAM clock enable SD_CLK SDRAM clock SD_CSN SDRAM chip select SD_D0…15 SDRAM data lines 0…15 SD_DQM0+1 SDRAM data qualifier mask 0+1 SD_RASN SDRAM row address strobe SD_WEN SDRAM write enable XM (Fieldbus interface) FB0+1CLK Fieldbus clock XM0+1_ECLK XMAC fieldbus, external clock XM0+1_IO0…5 XMAC fieldbus, input output 0…5 XM0+1_RX XMAC fieldbus, receive XM0+1_TX XMAC fieldbus, transmit XM0+1_TXOE XMAC fieldbus, transmit output enable XM0+1_TX_ECLK XMAC fieldbus, transmit external clock XM0+1_TXOE_ECLK XMAC fieldbus, transmit output enable, external clock GPIO GPIO0…7 and 8…11 General purpose input/output 0…7 application and 8…11 communication SPM (Serial DPM interface) DPM0+1_SPI_CLK Serial DPM (SPI, SQI), clock DPM0+1_SPI_CSN Serial DPM (SPI, SQI), chip select DPM0+1_SPI_DIRQ Serial DPM (SPI, SQI), data interrupt request DPM0+1_SPI_MISO Serial DPM (SPI), master in / slave out; Serial DPM (SQI), serial input/output data 1 DPM0+1_SPI_MOSI Serial DPM (SPI), master out / slave in; Serial DPM (SQI), serial input/output data 0 DPM0+1_SPI_SIRQ Serial DPM (SPI, SQI), synchron interrupt request DPM0+1_SQI_SIO2+3 Serial DPM (SQI), serial input/output data 2+3

UART (Universal Asynchronous Receiver/Transmitter) UART_APP_CTSN UART, application, clear to send UART_APP_RTSN UART, application, request to send UART_APP_RXD UART, application, receive data UART_APP_TXD UART, application, transmit data UART_CTSN UART, clear to send UART_RTSN UART, request to send UART_RXD UART, receive data UART_TXD UART, transmit data UART_XPIC_APP_CTSN UART, xPIC application, clear to send UART_XPIC_APP_RTSN UART, xPIC application, request to send UART_XPIC_APP_RXD UART, xPIC application, receive data UART_XPIC_APP_TXD UART, xPIC application, transmit data SQI (Serial Quad I/O) / XiP (Serial flash memory interface) SQI_CLK SQI, clock signal SQI_CS0..2N SQI, chip select signal, negated SQI_MOSI SQI, master in / slave out (serial input/output data 0) SQI_MISO SQI, master out / slave in (serial input/output data 1) SQI_SIO2+3 SQI, serial input/output data 2+3 SPI (Serial Peripheral Interface) SPI0_APP_CS0+1N SPI, application, chip select signal, negated SPI0…2_APP_CLK SPI, application, clock signal SPI0…2_APP_MISO SPI, application, master in / slave out SPI0…2_APP_MOSI SPI, application, master out / slave in SPI1+2_APP_CS0…2N SPI, application, chip select, negated SPI_XPIC_APP_CLK SPI, xPIC application, clock signal SPI_XPIC_APP_CS0…2 SPI, xPIC application, chip select SPI_XPIC_APP_MISO SPI, xPIC application, master in / slave out SPI_XPIC_APP_MOSI SPI, xPIC application, master out / slave in SQI (Serial Quad I/O) SQI0_APP_CS1…2N SQI, application, chip select signal, negated SQI0+1_APP_CLK (_B) SQI, application, clock signal (B = alternative) SQI0+1_APP_CS0N (_B) SQI, application, chip select signal, negated, (B = alternative) SQI0+1_APP_MISO (_B) SQI, application, master in / slave out (serial input/output data 1) (B = alternative) SQI0+1_APP_MOSI (_B) SQI, application, master out / slave in (serial input/output data 0) (B = alternative) SQI0+1_APP_SIO2+3 (_B) SQI, application, serial input/output data 2+3 (B = alternative) MLED MLED0…11 Multi Light Emitting Diode 0…3 communication; 4...11 application ENDAT (Master 2.2) ENDAT0+1_CLK Encoder Data clock output ENDAT0+1_IN Encoder Data data input ENDAT0+1_OE Encoder Data output enable ENDAT0+1_OUT Encoder Data data output

I2C I2C_APP_SCL I2C, application, clock signal I2C_APP_SDA I2C, application, data signal I2C_XPIC_APP_SCL I2C, xPIC application, clock signal I2C_XPIC_APP_SDA I2C, xPIC application, data signal I2C0+1_COM_SCL I2C, communication, clock signal I2C0+1_COM_SDA I2C, communication, data signal BISS (Master BiSS C) BISS0+1_MA Bidirectional/Serial/Synchronous clock output BISS0+1_MO Bidirectional/Serial/Synchronous data output BISS0+1_SL Bidirectional/Serial/Synchronous data input ADC ADC0+1_IN0+1 Analog-to-digital converter input 0+1 ADC2+3_IN0…7 Analog-to-digital converter input 0…7 CAN CAN0+1_APP_RX CAN, application, receive data CAN0+1_APP_TX CAN, application, transmit data XC XC_TRIGGER0…1 RTE synchronization signals Table 4: netX 90 signal description

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 17/275 3 Core 3.1 CPU 3.1.1 Cortex®-M4 CPU The application part of the chip features a high-performance ARM® Cortex®-M4 processor core:  ARMv7ME Architecture  Thumb-2 Technology  125 DMIPS  3-stage pipeline  Integrated NVIC and MPU  Integrated DSP and SIMD instructions  Single cycle MAC  Single precision FPU Documentation about Cortex®-M4, see reference [5].

3.1.2 xPIC CPU The xPIC (fleXible Peripheral Interface Controller) is a 32-bit RISC CPU from Hilscher optimized for fast and deterministic data processing. For instruction set, see reference [4]. The xPIC is used as peripheral controller for interfaces such as IO-Link, Ethernet MAC, etc. for which Hilscher provides low-level software drivers as HAL (Hardware Abstraction Layer) for the Cortex®-M4. The real-time capability of the xPIC enables Hilscher to program code-optimized, custom-specific features that are not supported by standard peripheral units. Therefore, the xPIC has a dedicated internal peripheral bus to ensure a deterministic response for very time critical IO tasks. If the xPIC is not used for the application, all on-chip peripherals connected at xPIC App System (see Figure 1) can be used by the Cortex®-M4 CPU.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 18/275 3.2 DMAC 3.2.1 Overview The DMA controller manages data transfers between DMA slaves and memory slaves without using the ARM CPU. This allows fast data transfers that do not affect the CPU load. A slave is a device selected by a controlling master as the source or target of a transfer. A slave can also begin a service request using an interrupt. The DMA controller  is functionally compatible with the ARM master DMA controller (PL081)  is designed to use only one master channel in the system  can support up to three DMA channels Each DMA channel can be programmed for various features, e.g.:  Transfer size  Interrupt generation  Memory and I/O address space  Transfer direction The netX 90 includes two completely independent DMA controllers: One on the com-side and one on the app-side. Therefore, both DMACs are connected to different peripherals. Some peripherals are connected to both DMACs because they can be operated from either side (not at the same time, of course).

Com-side shared App-side

DMAC DMAC ...... MUX _ 6 ...... flow control flow control DMAC cfg cfg

Dataswitch Dataswitch Dataswitch 1 1 0 + +

...... INTRAM INTRAM Peripheral x Peripheral y Peripheral z Peripheral Peripheral x Peripheral y

Figure 2: Simplified block diagram of the DMA controllers

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 19/275 3.2.2 Features  Compatible with ARM DMAC (PL081) software and register  1 AHBL master port used for DMA transfer and linked list operations  1 AHBL slave port as configuration interface  3 DMA channels with separated linked lists and configuration registers  4 FIFO elements (32-bit) per channel  Incrementing or non-incrementing addressing for source and destination  Programmable burst size.  32, 16, and 8-bit support for source and destination in all combinations  Fixed DMA channel priority:  Channel 0 has the highest priority  Channel 2 has the lowest priority  Memory-to-memory, memory-to-peripheral, peripheral-to-memory DMA transfers  DMAC or peripheral flow control  Programmable interrupt capabilities, e.g.:  error and finish interrupt generation  interrupt masking and clearing

The netX system and bus matrix implementation do not support the following DMAC features:  No AHB-protected transfers (user mode, buffer ability, cacheable)  No AHB-locked transfers  No big-endian support  No peripheral-to-peripheral DMA transfers

3.2.3 Typical applications  Optimized memory copy function  Optimized peripheral data block transfer function  Periodical data transfer to slave/master

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 20/275 3.2.4 Functional description The following section provides a detailed description of the DMA controller and its features. The 3-channel DMA controller supports the following transactions in the netX system:  Peripheral-to-memory transfer  Memory-to-peripheral transfer  Memory-to-memory transfer The netX system and its peripherals do not support peripheral-to-peripheral transfers, but they are configurable via the register interface. Interrupt

DMA Controller

Error Interrupt Terminal Count Interrupt Interrupts

Channel 0 Channel 1 Channel 2 AHBL src addr src addr src addr Flow control (slave) dest addr dest addr dest addr interface linked list linked list linked list control control control

FIFO FIFO FIFO

Mux / priority

AHBL (master)

Figure 3: Simplified internal structure of the DMA controller

Each channel supports a unidirectional DMA transfer, up to 32 bit, for a single source and destination address. A bidirectional transfer therefore requires one channel for transmit and one for receive. The source and destination address can be a memory region or a DMA-capable peripheral device of the netX. A system master programs the DMA controller via the AHBL slave interface.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 21/275 3.2.5 Data transfer The bus width for the AHB master is 32 bit. The width of source and destination transfers may differ. It can be identical to or narrower than that of the physical bus width. The DMA controller packs or unpacks data according to the programming parameters. The DMA controller supports little-endian addressing only. Internally, the DMAC treats all data as a stream of bytes instead of 16-bit or 32-bit quantities.

Note: To avoid byte swapping of the data, always address peripheral interfaces in 32-bit mode, if possible.

Source width Destination width Source transfer Source data Destination transfer Destination data 8 8 1/[7:0] 21 1/[7:0] 21212121 2/[15:8] 43 2/[15:8] 43434343 3/[23:16] 65 3/[23:16] 65656565 4/[31:24] 87 4/[31:24] 87878787 8 16 1/[7:0] 21 1/[15:0] 43214321 2/[15:8] 43 2/[31:16] 87658765 3/[23:16] 65 4/[31:24] 87 8 32 1/[7:0] 21 1/[31:0] 87654321 2/[15:8] 43 3/[23:16] 65 4/[31:24] 87 16 8 1/[7:0] 21 1/[7:0] 21212121 1/[15:8] 43 2/[15:8] 43434343 2/[23:16] 65 3/[23:16] 65656565 2/[31:24] 87 4/[31:24] 87878787 16 16 1/[7:0] 21 1/[15:0] 43214321 1/[15:8] 43 2/[31:16] 87658765 2/[23:16] 65 2/[31:24] 87 16 32 1/[7:0] 21 1/[31:0] 87654321 1/[15:8] 43 2/[23:16] 65 2/[31:24] 87 32 8 1/[7:0] 21 1/[7:0] 21212121 1/[15:8] 43 2/[15:8] 43434343 1/[23:16] 65 3/[23:16] 65656565 1/[31:24] 87 4/[31:24] 87878787 32 16 1/[7:0] 21 1/[15:0] 43214321 1/[15:8] 43 2/[31:16] 87658765 1/[23:16] 65 1/[31:24] 87 32 32 1/[7:0] 21 1/[31:0] 87654321 1/[15:8] 43 1/[23:16] 65 1/[31:24] 87 Table 5: DMA controllers data packing or unpacking depending on the programmed mode

To reduce latency and to improve the DMA transfer performance, observe the following recommendations:  If feasible, use separate memory areas for data storage and linked list information.  All memory and peripheral transactions should be 32-bit wide to improve bus efficiency.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 22/275 3.2.6 DMA channel priority The DMA channel priority is fixed. DMA channel 0 has the highest, channel 2 the lowest priority. If two DMA requests simultaneously occur on different channels, the lower channel number will be served first. If the DMA controller is transferring data for the lower priority channel and afterwards the higher priority channel becomes active: The DMA controller completes the number of transfers (delegated to the master interface by the lower priority channel) before it switches over to transfer data for the higher priority channel.

3.2.7 DMA flow control The DMA controller supports two flow control schemes:  DMAC-controlled mode  peripheral-controlled mode In the DMA-controlled mode, the transfer size is determined by programming the DMA channel. The DMA controller performs all flow control, i.e. it executes all transfers immediately without waiting for source or destination. This is typically used for memory-to-memory transfers or already filled FIFOs of peripherals the transfer size of which is known. In the peripheral-controlled mode, the source or destination peripheral performs the flow control. The flow control interface of the DMA controller provides a handshaking mechanism between the transfer logic of the DMA controller and a source or destination peripheral. You can use this mode if the transfer size is not determined prior to a transfer, but defined by the peripheral (e.g. FIFO data becoming available over time). The DMA controller supports up to 16 of these flow control channels. The com-side DMA controller has enough channels for a direct connection of all DMA-capable peripherals, but the app-side has more peripherals than flow control channels. For that reason, a DMAC_MUX module has been introduced in front of the DMAC flow control interface. The DMAC_MUX is a multiplexer between 6 DMAC flow control channels (app-side only) and the DMA-capable peripherals the app-side can use. Each peripheral flow control channel can be multiplexed to any of the 6 DMAC flow control channels. The flow control interface has a built-in clock-domain synchronization which is to be compatible with the ARM DMAC. However, the peripherals in the netX system are fully synchronized with the DMA controller, i.e. synchronization is not required. To improve the transfer performance, disabling the synchronizers in register dmac_sync is highly recommended.

3.3 Crypto core The netX 90 has an integrated crypto core for SSL/TLS acceleration with up to RSA-4096, ECC- 512, AES-256, and SHA-512. The crypto core is used to support secure boot and secure update.

Memory Size (in Kbyte) Start address intflash2 (mirror) 512 0x00000000 intram6 32 0x000b0000 intram7 (xpic) 32 0x000b8000 intflash2 512 0x00200000 hif_sdram 262144 0x10000000 intram6 (mirror) 32 0x200b0000 intram7 (xpic) (mirror) 32 0x200b8000 intram6 (mirror) 32 0x400b0000 intram7 (xpic) (mirror) 32 0x400b8000 sqirom 65536 0x64000000 cs0_base: hif_flash (ext_sram) 32768 0x68000000 cs1_base: hif_flash (ext_sram) 32768 0x6a000000 cs2_base: hif_flash (ext_sram) 32768 0x6c000000 idpm 32 0x70000000 sqirom (mirror) 65536 0xa4000000 hif_flash (mirror) 131072 0xa8000000 idpm (mirror) 32 0xb0000000 cm4 private 1024 0xe0000000 intlogic_shd 512 0xff400000 eth_system 64 0xff480000 intlogic_app 512 0xff800000 xpic_app_config 512 0xff880000 xpic_app_system 512 0xff900000 debug_slave 32 0xffff8000 Table 6: Memory map of application side

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 24/275 3.5 Brown-Out Detector (BOD) The BOD (Brown-Out Detection) serves to monitor the supply voltage. An interrupt can be used to indicate that the supply voltage has dropped under a certain value. The BOD is an analog input to which you can connect an external resistor divider in order to monitor a voltage that is higher than 3.3 V, e.g. 10 V or 24 V. For adjusting the threshold, choose the respective division factor of the resistors.

+24V VDDIO

R1a D1 opt

netX 90 R1b BOD glitch filter + vref_pw_bod -

R2 C1 opt

GND BS-NX90BOD-USED-V2

Figure 4: netX 90 BOD structure

The BOD pin  has a special ESD structure

 can be driven while VDDIO is not supplied  is not tolerant towards higher voltages Depending on the division factor and the max. value of the monitored voltage, additional clamping may be required. The example above uses an external diode to VDDIO for this purpose.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 25/275 3.6 Reset The netX offers several reset sources, which can generate a system reset.  RST_IN_N is the external reset input pin.  All others are generated by different internal function blocks.  RST_OUT_N is the output signal to reset external connected peripherals.

Reset Description RST_IN_N External reset input pin (Schmitt trigger). This is a reset input signal (active low) from an external reset source e.g. from the host system. It is a synchronous reset and an optional signal. If not used, this signal may be left unconnected, since the pin is equipped with an internal pull-up resistor (nom. 50 kΩ). However, it is recommended to tie it to VDDIO (+3.3V), since this can improve EMC behavior. POR Integrated power-on reset (POR) circuit. The integrated power watch with POR generation ensures a soft ramp up and down of the +3.3V supply (VDDIO). The POR circuit ensures that the chip operates above the specified threshold voltage (see section Power-on reset and DC/DC on page 26). It is an asynchronous reset, which initializes all internal registers and signals to their POR state. RES_WDOG If the internal watchdog counter expires, specifically WDG_COM, this reset is generated. It is also possible to generate an interrupt before the watchdog resets the chip. For more details, see section Watchdog on page 34. RES_HOST The host system interface initiates this reset by writing a special sequence into a host interface register. The reset will occur 1 ms after starting the write cycle enabling the host to finish the access and to prepare for the netX chip reset. RES_FIRMWARE This reset can be activated by a software command. RES_ARM This reset is generated by a system reset request of either one of the two Cortex-M4 cores. RES_CLKSUP This reset is generated by the clock supervisor, which is accessible by the COM system only. RST_OUT_N This is an output signal to reset connected peripheral devices. It is a tri-stateable signal that can be enabled and set to high or low level by a software command. Any reset will disable the output driver of the signal allowing you to set the desired reset default level to low or high by using an external pull-down or pull-up resistor. Table 7: Reset

A POR, hence a power-cycle, is the only reset condition that will clear the value of register RESET_CTRL. All other reset requests are stored in register RESET_CTRL. The firmware can use this information to determine which reset source has activated the last reset signal and act accordingly. Moreover, register RESET_CTRL provides 4 status bits that can be used to save information, unaffected by any reset, except for the power-on reset.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 26/275 3.7 Power-on reset and DC/DC The netX 90 features an integrated DC/DC converter that generates the core voltage of the device and an integrated power watch that ensures the soft ramp-up/down with power-on-reset (POR) generation. The DC/DC step-down converter or buck converter uses an external coil for the current mode regulation which is automatically turned on after power-up. For further information, see the Design- In Guide. The POR circuit ensures the operation above the specified threshold level. Otherwise, the netX 90 remains in a reset state without the need of an externally connected reset circuit.

Power supply scheme

Figure 5: Power supply scheme DC-DC

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 27/275 3.8 System clock (oscillator) The system oscillator circuit along with the internal PLL generates all internal clocks of the netX 90. For clock generation, either a quartz crystal with the internal oscillator circuit may be used or a quartz oscillator connected to the clock input pin.

1.2 V

VDD_PLL netX 90

C1 GND OSC_XTI

GND 25 MHz X-OSC PLL

OSC_XTO C Rd GND 2

VSS GND

Figure 6: netX 90 oscillator

3.9 Temperature sensor The on-chip die temperature sensor consists of a thermal diode internally connected to analog input channel 2 of ADC controller 0 (ADC0_IN2). The measured, digitized voltage is proportional to the junction temperature (Tj) calculated using the formula extracted from Figure 7: V(T) = – 0.003569 × T + 1.558576

Figure 7: Thermal diode netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 28/275 Temperature error The unadjusted temperature error (UTE) takes into account the total unadjusted error (TUE) of ADC controller 0 and the error caused by process variations of the on-chip thermal diode, which is thus more precisely in sensing temperature changes than absolute temperatures.

PVT variations The characteristic parameters shown in Figure 7 are verified by design. Under worst case variations of PVT conditions, the worst case error of the thermal diode is ± 15 mV.

TUE calculation The TUE is calculated using the formula in Figure 8. The corresponding ADC parameters (see Electrical Specification) are expressed in units of least signification bits (LSB).

Figure 8: Temperature error

The reference voltage VREF_ADC for the ADC can be supplied internally by a reference buffer or externally by a reference voltage. It is mandatory to put a capacitor of 100 nF between VREF_ADC and VSS_REF. In case of an external reference voltage, parameters such as temperature drift, voltage noise and stability must be considered for ADC accuracy.

UTE adjustments

Assuming VREF_ADC is supplied internally by the reference buffer ADC_VREF with 2.6 V ± 50 mV (see section ADC on page 225), the worst case UTE is ± 59 LSB, which corresponds to ± 10 °C. As shown by the equation in Figure 8, the error caused by deviations propagates due to the combination of variables with uncertainties, which increases towards the full-scale input range of the ADC. According to the formula in Figure 8, the UTE can be adjusted by either TUE or Δ F or both. In general, offset and gain errors could be calibrated out. In this case, the actual error (see TUE respectively UTE in Figure 8) would be dominated by INL and DNL errors. Offset and gain adjustments would require reference measurements, for instance by measuring the case-top temperature Tc (see section Thermal behavior in reference [2]). The reference buffer ADC_VREF is a temperature compensated voltage that is trimmed and tested against specification limits during production tests. The assumption of calculating the UTE using the upper and lower limits of ADC_VREF with Δ VREF_ADC of ± 50 mV could be adjusted by measuring VREF_ADC, which is internally connected to analog input channel 3 of ADC controller 0 (ADC0_IN3) and 1 (ADC1_IN3).

Example

In order to measure the voltage from reference pin VREF_ADC, the ADC controller must be configured to use the analog core supply as a reference voltage and the ADC sequencer must carry out at least eight consecutive measurements to reduce the effect of noise caused by ripples in the analog reference.

Assuming the reference buffer ADC_VREF on pin VREF_ADC is measured and digitized for calculating the temperature value, Δ VREF_ADC determined by the TUE is ± 13 mV instead of ± 50 mV, which corresponds to a total error of ± 6 °C at lower temperatures and ± 5 °C at higher temperatures.

Remark The ADC controller requires 2 cycles for sampling and 12 cycles for conversion, i.e. in total 14 cycles for digitizing analog input signals sequentially. The sampling time must be settled to 12-bit precision, which for the thermal diode is worst case 1.2 µs. Therefore, depending on the programmed ADC clock, the sampling time with 2 cycles must be extended. Assuming the ADC clock period is 30 ns (default after reset), the sampling time with 2 cycles × adcclk_period + tt_add × 10 ns must be adjusted for 1.2 µs. The additional delay of ≥ 114 (recommended 128) must be programmed for tt_add.

Vector ARM_APP xPIC_APP 0 software software 1 timer_app0 timer_xpic_app0 2 timer_app1 timer_xpic_app1 3 timer_app2 timer_xpic_app2 4 timer_app_systime_s timer_xpic_app_systime_s 5 wdg_app wdg_xpic_app 6 dmac_app dmac_app 7 mcp_app mcp_xpic_app 8 uart uart 9 i2c_app i2c_app 10 i2c_xpic_app i2c_xpic_app 11 ecc_app ecc_app 12 xpic_debug_app xpic_debug_app_misalign 13 wdg_xpic_app_arm sw 14 nfifo_arm_app nfifo_xpic_app 15 io_link_irq_xpic_app io_link_irq_xpic_app 16 spi0_app spi0_app 17 spi1_app spi1_app 18 spi2_app spi2_app 19 spi_xpic_app spi_xpic_app 20 uart_app uart_app 21 uart_xpic_app uart_xpic_app 22 bod bod 23 clk_sup clk_sup 24 sqi sqi 25 hif_pio_arm hif_pio_xpic 26 eth eth 27 hash hash 28 aes aes 29 mtgy mtgy 30 hif_rdy_to hif_rdy_to 31 idpm_com_host idpm_com_host 32 hs_com_host_hsc0 hs_com_host_hsc0 33 hs_com_host_hsc1 hs_com_host_hsc1 34 hs_com_host_hsc2 hs_com_host_hsc2 35 hs_com_host_hsc3 hs_com_host_hsc3 36 hs_com_host_hsc4 hs_com_host_hsc4 37 hs_com_host_hsc5 hs_com_host_hsc5 38 hs_com_host_hsc6 hs_com_host_hsc6 39 hs_com_host_hsc7 hs_com_host_hsc7 40 hs_com_host_hsc8to15 hs_com_host_hsc8to15 41 endat_app0 endat_app0 42 endat_app1 endat_app1 43 biss_app0 biss_app0 netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 31/275

Vector ARM_APP xPIC_APP 44 biss_app1 biss_app1 45 madc_seq0 madc_seq0 46 madc_seq1 madc_seq1 47 madc_seq2 madc_seq2 48 madc_seq3 madc_seq3 49 mpwm mpwm 50 menc_app_irq_enc0 menc_app_irq_enc0 51 menc_app_irq_enc1 menc_app_irq_enc1 52 menc_app_irq_cap_mp menc_app_irq_cap_mp 53 menc_app_irq_err menc_app_irq_err 54 gpio_app0 gpio_xpic_app0 55 gpio_app1 gpio_xpic_app1 56 gpio_app2 gpio_xpic_app2 57 gpio_app3 gpio_xpic_app3 58 gpio_app4 gpio_xpic_app4 59 gpio_app5 gpio_xpic_app5 60 gpio_app6 gpio_xpic_app6 61 gpio_app7 gpio_xpic_app7 62 gpio_app_timer0 gpio_xpic_app_timer0 63 gpio_app_timer1 gpio_xpic_app_timer1 64 gpio_app_timer2 gpio_xpic_app_timer2 65 pio0_app pio0_app 66 pio1_app pio1_app 67 pio2_app pio2_app 68 pio3_app pio3_app 69 trigger_out_edge0 trigger_out_edge0 70 trigger_out_edge1 trigger_out_edge1 71 can_ctrl0_app can_ctrl0_app 72 can_ctrl1_app can_ctrl1_app 73 sqi0_app sqi0_app 74 sqi1_app sqi1_app 75 cti_arm_app0 software 76 cti_arm_app1 software 77 fpu_arm_app software 78 … 95 software software Table 8: Interrupt vectors

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 32/275 3.11 Timer 3.11.1 CPU timer The netX provides three 32-bit counters which can be configured:  to count from zero to a max. value and backward (symmetric mode)  to count from zero to a max. value and set back to zero (asymmetric mode)  to single shot or to count continuously  to generate an interrupt if it reaches zero  to count external events  to set back to zero by an external event  to capture the timer value by an external event  to generate a PWM signal by comparing the timer value with a threshold value

To indicate external events, you can use any GPIO. By setting the inverting bit at the GPIO configuration register, you can trigger rising or falling edge resp. high or low level. The counter value can be read and overwritten any time.

TIMERi_CTRL

CLK LEVEL/ SYM/ START/ SINGLE/ in/extern EDGE ASYM STOP CONT

TIMERi IN External Event TIMER-LOGIC CNT=0 CLK CLK_IN CNT=MAX

CLK_OUT CLR START/STOP UP/DOWN

TIMERi_CNT

TIMERi_MAX

TIMERi IRQ 0

TIMERi OUT TIMERi_TH

Threshold Register is also used as Capture Register

Figure 9: Timer function diagram

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 33/275 3.11.2 IEEE 1588 system time The precision system time derives from a counter clocked with the 100 MHz system clock. From the view of the application it has a 10 ns resolution. Due to drift, aging or failure of the crystal, this time can differ from a system-wide master clock which is very often needed in a real-time Ethernet system. The system time is not realized by a standard counter. It uses an adder which increases the current time value by a programmable number (nominally 10) every clock period. If the 100 MHz clock deviates from the master clock, the added value will slightly differ by 10 with a resolution of 2-28 ns to compensate for the deviation. This can be calculated based on the protocol of IEEE 1588 or other real-time Ethernet functions. The system time is provided in two 32-bit registers. Register 1 represents the seconds, register 2 the nanoseconds from time zero. The application has to read the seconds value first because this will freeze the nanoseconds register to get a consistent system time.

D31 D0 D31 D0 D28 D0 SYSTIME seconds SYSTIME nanoseconds SYSTIME subnanoseconds SYSTIME at Time T

D31 D0 Time Difference in 2-28 ns DPLL Time Difference 10ns

D31 D0 D31 D0 D28 D0 SYSTIME seconds SYSTIME nanoseconds SYSTIME subnanoseconds SYSTIME at Time T+10ns

Figure 10: System time

Calculation of the system time The following diagram shows how the time clock compensation works. With a clock period of ∆T = 10 ns the value ∆CNT = 10 will be added continuously to the system time CNT1 to reach CNT 2 exactly at T2. If the clock runs too fast, CNT2 will be reached after T2fast. If the clock is too slow, CNT2 will be reached after T2slow. If ∆CNT is calculated exactly, CNT2 will be reached at T2. The procedure of an ongoing correction prevents the problems of a one-step correction resulting in a large step of the system time.

CNT

2 CNT2

CNT

T 1 CNT1

T1 T2 T2 T2 Time fast slow Figure 11: Ongoing correction of time failure

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 34/275 3.12 Watchdog 3.12.1 Function For system supervision, the netX is equipped with 4 internal 2-stage watchdog counters, i.e. one for each CPU. Once the watchdog is active, the timeout counter has to be triggered continuously. The watchdog works in two stages: When the IRQ timeout counter has reached zero, an interrupt is generated to indicate that the watchdog will soon perform a reset and needs attention. As soon as the reset timeout counter reaches zero as well, the watchdog, WDG_COM, will reset the netX. All others generate an IRQ to higher prioritized watchdog as defined in Table 9 (see Figure 12).

Watchdog signals WDG_RES WDG_IRQ WDG_ACT WDG_COM RST to WDG_SYS IRQ to ARM_COM WDG_ACT via MMIO WDG_xPIC_COM IRQ to ARM_COM IRQ to xPIC_COM n.c. (not connected) WDG_APP IRQ to ARM_COM IRQ to ARM_APP n.c. WDG_xPIC_APP IRQ to ARM_APP IRQ to xPIC_APP n.c. Table 9: Watchdog counters and signals

Whenever the watchdog is triggered, the timeout register values are reloaded to the watchdog timer by setting the watchdog trigger bit. This will also clear an active interrupt request flag (timeout, stage 1 is reached). Writing to the timeout register is possible only if the write enable timeout flag is set. This prevents undesired access to the timeout registers.

Figure 12: Internal structure of the watchdog logic

3.12.2 WDG_ACT signal This signal shows that the watchdog supervision is active and has not expired. After reset, this signal is low. By activating the watchdog, the signal changes to high state. As soon as the watchdog timeout expires, this signal will be cleared. If the watchdog is not enabled, this signal will remain low.

Figure 13: Timing diagram of WDG_ACT

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 35/275 3.13 Internal memory 3.13.1 Internal Flash The netX 90 features 3 identical 512 KB flash memory blocks for program code and data storage (1024 KB Com and 512 KB App). In total up to 1.5 MB. Each Flash memory block incorporates:  Dedicated Flash memory controller for program/erase (P/E) operations  Equipped Error Correcting Code (ECC) logic with 1-bit error correction / 2-bit error detection  Efficient memory buffers with hardware prefetch function  Instruction prefetch buffer: 8 lines x 128-bit  Data prefetch buffer: 2 lines x 128-bit  Read and write protection mechanism

3.13.2 Internal RAM The internal RAM is an SRAM with ECC: 64 KB (Application).

3.14.1 Overview Serial Flash can be connected to netX 90:  SPI  QSPI (XiP) Parallel external memory can be connected to the netX 90. The types to be connected are:  SDRAM,  SRAM or NOR Flash. The external memory controller supports 8 and 16-bit SRAM devices and 8 or 16-bit SDRAM devices. The SDRAM controller in the netX must be deactivated when operating Flash memory to avoid wrong address mapping causing data errors.

Important: For netX 90 it is absolutely NOT recommendable to use SRAM together with SDRAM because the max. IO load for valid SDRAM timing is strictly limited. Using both will lead to a swapping of the address lines EXT_A14 to EXT_A17.

Important: Never connect a parallel Flash memory to the memory interface when using SDRAM memory.

Note: If more than one memory device is connected, the allowed maximum load capacity has to be considered, to ensure stable operation throughout the whole temperature and operating voltage range!

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 37/275 3.14.2 Features  Supported devices  SDRAM (single data rate)  SRAM-based devices like SRAM, NVRAM, Flash with fix access times  SRAM-based devices with external wait state generation  8 or 16 data bits for SRAM and 8 or 16 data bits for SDRAM  SDRAM features  All typical SDRAM devices supported: 2 or 4 banks, 256 to 4 K columns, 2 K to 8 K rows  Widely configurable timing parameters  Intelligent refresh controlling  Power down function  CAS Latency 2 or 3  16 byte read and write cache  SRAM-based device features:  Up to 17 address lines for 8 or 16 bit data  Up to 3 chip-select signals available  Widely configurable signal timing: pre, post and wait state pauses  Asynchronous Page mode (APM) supported  Optional ready/wait signal for external wait state generation providing signal filtering and timeout logic

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 38/275 3.14.3 SDRAM interface 3.14.3.1 Overview The external memory controller interfaces Single-Data-Rate (SDR) SDRAM. The SDRAM data bus can be 8 or 16-bit wide. For max. memory performance, we recommend using 16-bit. However, depending on your performance requirements, 8-bit may still be the better choice for some applications due to the reduced requirements of the PCB layout and smaller board size. The following parameters can be set:

Parameter Option Number of banks 2 or 4 Number of rows 2 K, 4 K or 8 K Number of columns 256, 512, 1 K, 2 K or 4 K Data widths 8-bit or 16-bit Refresh-mode High or low priority Power save mode SDRAM-self-refresh-mode with disabled clock switch on/off Table 10: SDRAM parameters

The following table shows a list of SDRAM types with memory size and organization.

SDRAM memory size Organization Configuration Total memory size 64 Mbit 4 Mbit x 16 1 x 16 8 Mbytes 128 Mbit 8 Mbit x 16 1 x 16 16 Mbytes 16 Mbit x 8 1 x 8 16 Mbytes 256 Mbit 16 Mbit x 16 1 x 16 32 Mbytes 512 Mbit 32 Mbit x 16 1 x 16 64 Mbytes Table 11: SDRAM memory size and organization

3.14.3.2 Split mode The SDRAM controller can operate in split mode equally dividing the memory in two halves: The lower SDRAM half is accessible via the COM side, the upper half via the APP side. From a software point of view, in split mode as well as non-split mode, the internal addressing is the same, only the memory capacity is cut in half. When the SDRAM is used in split mode, the physical address to the SDRAM device is remapped: This allows both APP side and COM side using the global SDRAM address base as start address of their SDRAM-half while working on their own physical SDRAM-half.

Use case If the software on the communication side requires SQI Flash, we recommend you not to use this SQI Flash via the application side (it can be locked by the peripheral's firewall). Should the application software exceed the on-chip memory, the ROM loader ensures that the full application firmware is loaded after power-up (SQI Flash to SDRAM). The SDRAM interface can operate in split mode which equally splits the memory between communication and application side (same addressing in split and non-split mode).

Pin Signal SDRAM Comment Signal C5 HIF_A0 SD_A0 Shared SDRAM/FLASH/SRAM address lines, small SDRAM devices do not need all lines (sel_hif_a_width). B5 HIF_A1 SD_A1 A5 HIF_A2 SD_A2 C4 HIF_A3 SD_A3 B4 HIF_A4 SD_A4 A4 HIF_A5 SD_A5 C3 HIF_A6 SD_A6 B3 HIF_A7 SD_A7 A3 HIF_A8 SD_A8 C2 HIF_A9 SD_A9 B2 HIF_A10 SD_A10 C1 HIF_A11 SD_A11 D1 HIF_A12 SD_A12 D2 HIF_A13 SD_BA0 Only during SDRAM access, usable as FLASH/SRAM A13+14 simultaneously. D3 HIF_A14 SD_BA1 D5 HIF_A16 SD_CASN Only during SDRAM access, usable as FLASH/SRAM A16 simultaneously. E3 HIF_RDY SD_CKE ExtBus Ready never available when SDRAM enabled F1 HIF_SDCLK SD_CLK HIF SDRAM clock, ExtBus CS2 not available D6 HIF_A17 SD_DQM0 Only during SDRAM access, usable as FLASH/SRAM A17 simultaneously. D7 HIF_BHEN SD_DQM1 Only during SDRAM access, usable as FLASH/SRAM BHEN simultaneously. D8 HIF_CSN SD_CSN ExtBus CS0 not available E10 MII1_RXER SD_D0 Shared SDRAM/FLASH/SRAM data lines. E9 MII1_CRS SD_D1 E8 MII1_COL SD_D2 E7 PHY0_LED_LINK_IN SD_D3 E6 PHY1_LED_LINK_IN SD_D4 F5 MII0_TXEN SD_D5 E5 MII0_COL SD_D6 E4 MII0_CRS SD_D7 B11 HIF_D0 SD_D8 C10 HIF_D1 SD_D9 B10 HIF_D2 SD_D10 A10 HIF_D3 SD_D11 C9 HIF_D4 SD_D12 B9 HIF_D5 SD_D13 A9 HIF_D6 SD_D14 C8 HIF_D7 SD_D15 D4 HIF_A15 SD_RASN Only during SDRAM access, usable as FLASH/SRAM A15 simultaneously. E1 HIF_WRN SD_WEN Only during SDRAM access, usable as FLASH/SRAM nWR simultaneously. Table 12: netX 90 SDRAM (Synchronous Dynamic Random Access Memory interface)

SD_CSN Chip Select SD_A[12:0](1) Row/Column Address(1) SD_BA[1:0](1) Bank Address(1) SD_RASN SDRAM RAS SD_CASN SDRAM CAS SD_WEN SDRAM Write SD_DQM0 Low-Byte Enable SD_DQM1 High-Byte Enable SD_D[15:0] Data[15:0] SD_CLK SDRAM Clock SD_CKE SDRAM Clock Enable 16-bit SDRAM netX 90

Figure 14: 16-bit SDRAM connection of netX 90

For SDRAM component connection 8Mx16 and 16Mx8, see reference [2].

Notes 1. The width of row/column (rc) and bank address (ba) depends on the size of the SDRAM device. The width can be configured in the SDRAM controller configuration registers. For row/column addressing, lines SD_A0 to SD_A10 are always used while the use of SD_A11 and SD_A12 depends on the device size. For bank addressing, line HIF_A13 is always used for BA0 and typically (for devices with 4 banks) also HIF_A14 for BA1 (ba in figure above). Take the appropriate values from the data sheet of the used SDRAM device. 2. You can use several small SDRAM devices instead of a single big one, e.g. you can use two 8-bit devices to make up one 16-bit memory. If you do this, always observe the max. loads and timing.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 41/275 3.14.3.5 SDRAM access optimization To benefit from the high-performance netX-external memory interface SDRAM controller, software memory mapping of all system masters running applications in SDRAM must be realized very accurately considering SDRAM properties. For netX 90, this basically means:  different masters should not work on SDRAM simultaneously  separate code and data to different banks if both must be located in SDRAM  accesses should be optimized (avoid random access, use generated address incrementing or decrementing accesses instead)

3.14.3.5.1 SDRAM access introduction In SDRAM devices 4 banks can typically be addressed by a bank address (device address MSBs). Each bank contains up to 8 K pages addressable by a row address (1 K = 1024). Each page contains up to 4 K data words. To access a certain data word of a certain page of a certain bank, the page first must be opened by the ACTIVATE command to the corresponding bank and row address. When the page is open, data of this page can be addressed by the READ or WRITE command. Read data will be delivered from the SDRAM CAS-latency clocks after a READ command was set up. If a page of a certain bank is already open and access to another page inside this bank is required, the current page must be closed and the new one opened by the PRECHARGE command first. SDRAM (non DDR, QDR) devices are always connected by an address bus, a data bus, some control signals and one clock signal to a host device e.g. netX. SDRAM action is always performed at the rising edge of the clock signal. I.e. time base of all SDRAM action is SDRAM clock period.

Note: netX family always runs SDRAM on system frequency (100 MHz if not stepped down)

Min. cycle times are specified for SDRAM devices between different SDRAM commands. The SDRAM controller is initialized with these timings and generates appropriate pauses (idle cycles) on the SDRAM interface. These timings depend on used SDRAM device.

3.14.3.5.2 SDRAM data mapping optimization Typically one SDRAM page contains 256 to 2048 words (word size is data bus width). As long as you do not leave the page (access within an address boundary appropriate to the page size), PRECHARGE and ACTIVATE are not required. This is very important as the SDRAM controller must insert pauses of several clock cycles on the external memory interface to avoid SDRAM timing violations. The following two figures show the difference between read accesses within one page boundary and accesses exceeding this boundary (write case is similar).

SDRAM Clock

Command pre nop nop activ nop read nop nop nop read nop nop nop nop nop nop

Bank addr ba ba ba ba

Row/Col addr ra caA caB

Data dA0 dA1 dA2 dA3 dB0 dB1 dB2 dB3

CAS latency 2 read data A read data B

Figure 15: Read access from different SDRAM banks

SDRAM Clock

Command pre nop nop activ nop read nop nop nop pre nop nop activ nop read nop nop nop nop nop nop

Bank addr ba ba ba ba ba ba

Row/Col addr raA caA raB caB

Data dA0 dA1 dA2 dA3 dB0 dB1 dB2 dB3

CAS latency 2 read data A read data B

Figure 16: Read access from the same SDRAM banks

To avoid decreasing memory performance by PRECHARGE and ACTIVATE periods the following rules must be attended:  Applications should keep addressing in page boundary.  No multi-master SDRAM usage

3.14.3.6 SDRAM data caches issues There is a 4 Dword read cache and a 4 Dword write cache implemented in netX 90 SDRAM memory interface to avoid burst runaways.

Note: Caches are always enabled and cannot be disabled in the netX 90 memory interface. Bursts of 4 Dwords are always performed externally i.e. burst length 8 for 8-bit external data bus, burst length 8 for 16-bit external data bus.

Access between 4 Dword caches and external SDRAM devices is always performed by a 4 Dword burst externally. These bursts are never terminated. In the worst case, a whole 4 Dword write burst is performed if only one byte is written to the SDRAM device. All other data is unmasked by the SDRAM DQM-signals (Data Qualifying Mask). To reach good performance, data should be read or written with incrementing or decrementing addresses. Random access should be avoided.

Example 1 (bad): Example 2 (good): load reg0, [addr] load reg0, [addr] load reg1, [addr+16] load reg2, [addr+4] load reg2, [addr+4] load reg4, [addr+8] load reg3, [addr+20] load reg1, [addr+16] load reg4, [addr+8] load reg3, [addr+20] load reg5, [addr+24] load reg5, [addr+24]

3.14.3.6.1 SDRAM timing parameters The following list provides an overview of timing parameters which can be programmed in netX 90 SDRAM controller configuration registers. Programming values depend on the SDRAM device used and must be taken from SDRAM device data sheet.

Note: Compared with earlier netX chips, the existing timing parameters have remained unchanged.

Timing requirement Pause (100 MHz) ACTIVATE to READ or WRITE (same bank) 1 ... 3 clocks ACTIVATE bank A to ACTIVATE bank B 1 ... 3 clocks WRITE recovery time (last written data to PRECHARGE) 1 ... 3 clocks CAS latency (read data on bus after READ command setup) 2 ... 3 clocks PRECHARGE to command time 1 ... 3 clocks ACTIVATE to PRECHARGE time 3 ... 10 clocks REFRESH to command time 4 ... 19 clocks Table 13: SDRAM timing requirement

3.14.3.6.2 SDRAM refresh generation SDRAM refresh cycles (PRECHARGE ALL, AUTO REFRESH, ACTIVATE) typically take 120 ns (12 clocks) or more. To minimize worst case access time for SDRAM, refresh priority is lower than access priority. The netX external memory controller can collect up to 2048 refreshes which will be performed when no master requests access. To avoid refresh errors, refresh will automatically be changed to high priority mode if it is not possible to perform enough refreshes in low-priority mode. 4096 refreshes must typically be performed within one all-rows refresh cycle time (64 ms) i.e. refresh period of 15.6 µs. The SDRAM controller sets the status flag if refresh collecting might become critical in low priority refresh mode. E.g. the memory interface is busy for a long time (typically 2048*(64 ms/4096) i.e. 32 ms). In this case, the hardware will automatically change the refresh generation to high priority mode. As soon as refresh collecting is no longer critical, the mode will change again. The hardware will thus avoid errors caused by missing refreshes.

Note: In the following diagrams SDRAM signals RAS, CAS, WE are combined as “Command”.

Initialization Figure 17 shows the SDRAM power-up initialization performed by the netX SDRAM controller.

7 times repeated (8 AUTO REFRESH in total)

tCP

SD_CLK

tCKS tCH tCL

SD_CKE

tCMS

SD_CSN

tCMS tCMH tCMH tCMH tCMH tCMH

PRE- AUTO AUTO LOAD NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP ACTIVE Command CHARGE REFRESH REFRESH MR

tCMS tCMS tCMS tCMS tCMS

SD_DQM0..1

tAS tAH tAS tAH

SD_A0..9, MR Row SD_A11..12 Data Bank

tA10S tA10H tA10S tA10H tA10S tA10H all Banks MR Row SD_A10 Data

High-Z SD_D0..15

tinitP tinitRP tinitRFC tinitRFC tinitMRD

tinit

Figure 17: SDRAM power-up and mode register initialization

Auto refresh cycles Figure 18 shows the SDRAM Auto refresh cycles performed by the netX SDRAM controller.

tCP

SD_CLK

tCH tCL

SD_CKE

tCMH tCMH tCMH tCMH

PRE- AUTO AUTO NOP NOP NOP NOP NOP NOP ACTIVE Command CHARGE REFRESH REFRESH

tCMS tCMS tCMS tCMS

SD_DQM0..1

tAS tAH

SD_A0..9, Row SD_A11..15 Bank

tA10S tA10H tA10S tA10H

all/ Row SD_A10 single

SD_D0..31

tRP tRFC tRFC

Figure 18: SDRAM auto refresh generation

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 46/275 Self refresh mode, entry and exit For SDRAM power save without data loss, netX SDRAM controller can set SDRAM devices to self refresh mode. After the self refresh mode entry, the SDRAM controller switches off SD_CLK until the software requests exit from the self refresh mode.

tCP

SD_CLK

tCH tCL tCKS tCKH tCKS

SD_CKE

tCMS tCMS SD_CSN

tCMH tCMH tCMH

PRE- AUTO AUTO NOP NOP NOP NOP NOP NOP NOP NOP ACTIVE Command CHARGE REFRESH REFRESH

tCMS tCMS tCMS

SD_DQM0..1

tAS tAH

SD_A0..9, Row SD_A11..15 Bank

tA10S tA10H tA10S tA10H

all/ Row SD_A10 single

SD_D0..15

tRP tRFC tSR tXSRP tXSR tRFC

Figure 19: SDRAM self refresh mode entry and exit

Write access Figure 20 shows a single bank SDRAM write cycle. SD_CKE is always high and thus not shown.

tCP tCH tCL

SD_CLK

tCMS tCMH

PRE- ACTIVE NOP NOP WRITE NOP NOP NOP NOP ACTIVE Command CHARGE

tDQMS tDQMH

SD_DQM0..1 DQM(n) DQM(n+1) DQM(n+2) DQM(n+3)

tAS tAH

SD_A0..9, Row Column n Row Bank SD_A11..15 Bank Bank Bank

tA10S no AUTO PRECHARGE all/ Row Row SD_A10 single

tDS tDH tDH tDH tDH

SD_D0..15 Dout(n) Dout(n+1) Dout(n+2) Dout(n+3)

tDE tDS tDS tDS tDD tRCDW tWR tRP

tRAS

tRC

Figure 20: SDRAM write timing (SD_CKE is always high)

tCP tCH tCL

SD_CLK

tCMS tCMH

PRE- ACTIVE NOP READ NOP NOP NOP NOP ACTIVE Command CHARGE

tDQMS tDQMH

SD_DQM0..1 DQM(n) DQM(n+1) DQM(n+2) DQM(n+3)

tAS tAH

SD_A0..9, Row Column n Row Bank SD_A11..15 Bank Bank Bank

tA10S no AUTO PRECHARGE all/ Row Row SD_A10 single

tLZ tHZ

SD_D0..15 Din(n) Din(n+1) Din(n+2) Din(n+3)

tOH tOH tOH tOH tAC tAC tAC tAC tRCDR CAS Latency

tRAS tRP

tRC

Figure 21: SDRAM read timing (SD_CKE is always high)

Symbol Parameter Min Typ Max Unit

tRAS ACTIVE to PRECHARGE time 3..10 tCP (1) tRC ACTIVE to ACTIVE (same bank) time 4..13 tCP (2) tRCDR ACTIVE to READ (same bank) time 1..3 tCP (2) tRCDW ACTIVE to WRITE (same bank) time 2..4 tCP (3) (3) (3) tREFI Average periodic REFRESH interval (Refresh period divided by rows 3.9 7.8 31.2 us to refresh within refresh period) 15.6(3)

tRFC AUTO REFRESH period 4..19 tCP

tRP PRECHARGE command period 1..3 tCP (4) tRRD ACTIVE to ACTIVE different bank time 1..3 tCP

tWR WRITE recovery time 1..3 tCP

tSR Self Refresh period 1 tCP

tXSRP Self Refresh Clock active to exit period exit 4 tCP (5) tXSR Self Refresh exit to command period 4..19 tCP

Notes

1. Minimum tRC is tRAS + tRP. 2. ACTIVE to WRITE (same bank) time is ACTIVE to READ (same bank) time plus 1 additional cycle from memory controller internal arbitration. 3. Expecting 100 MHz system clock.

4. netX 50 SDRAM controller uses tRCDR for tRP.

5. Programmed tRFC settings will be used for tXSR.

SDRAM initialization and power-up timing characteristics:

Symbol Parameter Min Typ Max Unit

tinit Whole SDRAM initialization time till first ACTIVE 20317 20317 tCP

tinitP SDRAM Power Up time (NOP till first PRECHARGE) 20050 20050 tCP

tinitRP Initialization PRECHARGE command period 16 16 tCP

tinitRFC Initialization AUTO REFRESH period 23 32 tCP (1) tinitMRD Load MR to first command period 4 tCP

Note: (1) If more tinitMRD time is required, software can wait until flag sdram_ready is set in register sdram_general_ctrl before the first SDRAM memory access.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 49/275 3.14.3.8 IO timing parameters for SDRAM All timings are related to the following SDRAM clock phase settings (to be set by programming register sdram_timing_ctrl of area hif_sdram_ctrl): hif_sdram_ctrl_sdram_general_ctrl.mem_sdclk_phase: 3 hif_sdram_ctrl_sdram_general_ctrl.data_sample_phase: 0

Electrical characteristics of netX 90 SDRAM part (CL 30 pF):

Symbol Parameter Min Typ Max Unit (1) (1) (1) tCP SDRAM clock (SD_CLK) cycle time 10.0 10.0 ns

tCH SDRAM clock (SD_CLK) high level width 3.5 4.7 ns

tCL SDRAM clock (SD_CLK) low level width 3.8 4.8 ns (2) tCKS Clock enable (SD_CKE) setup time 3.1 ns (2) tCKH Clock enable (SD_CKE) hold time 3.0 ns

tCMS Command setup time ns CSN 3.2 WEN 3.7 RASN 3.3 CASN 3.0

tCMH Command hold time ns CSN 2.8 WEN 2.5 RASN 2.8 CASN 3.0 (3) tAS Address (without A10) setup time 2.9 ns (3) tAH Address (without A10) hold time 2.4 ns

tA10S A10 setup time 3.7 ns

tA10H A10 hold time 2.5 ns (3) tDQMS Data Qualifier Mask setup time 3.1 ns (3) tDQMH Data Qualifier Mask hold time 2.5 ns (3) tDS netX Data-out setup time 2.7 ns (3) tDH netX Data-out hold time 1.3 ns (3) tDE netX Data-out enable (Low Z) time (write) 6.2 ns (3) tDD netX Data-out disable (High Z) time (write) 4.2 ns (3) tAC SDRAM Access time (read) 6.0 ns (3) tOH SDRAM Data-out hold time (read) 0.0 ns (3) tLZ SDRAM Data-out enable (Low Z) time (read) 0.0 ns (3) tHZ SDRAM Data-out disable (High Z) time (read) 11.9 ns

Notes 1. HIF_SDCLK always runs at the same frequency as netX-internal system clock. 2. CKE is only used for SDRAM power-down (self refresh mode or SDRAM disabled). 3. HIF-IO setup, HIF memory interface signal mapping for DQMs, address and data lines (HIF_IO_CTRL) requires knowledge for proper configuration.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 50/275 3.14.4 SRAM/Flash interface to memory interface controller The SRAM/FLASH interface provides a total of three memory areas which provide their own chip select signals and three independent configuration registers. They allow you to set memory bus width and wait state parameters separately for each area. The parameters allow bus width configurations of 8 or 16 bit and wait states of up to 63 clock cycles. The 16-bit bus width of the respective memory component, the 18-bit address bus allows access up to 256 Kbyte of static memory per memory area. For 8-bit areas, address lines EXT_A24:0 represent the byte address.

Note: The interface does not support Burst or Page mode, as provided by many FLASH memory devices.

3.14.4.1 SRAM access generation The netX 90 external memory interface controller provides functions to connect 8 or 16-bit devices. An optional configurable ready signal allows devices to generate wait states dynamically.

Note: Many devices are based on the SRAM protocol apart from standard SRAM devices – e.g. NVRAM or parallel Flash. In the following text, “SRAM” stands for all of them.

The netX 90 extension bus memory controller splits an internal access to the SRAM, which is wider than the external SRAM device, into a sequence of external accesses. E.g. a 32-bit access to an 8- bit SRAM device is split into 4 external byte accesses; a 32-bit access to a 16-bit SRAM device is split into 2 external 16-bit accesses.

3.14.4.1.1 SRAM access timing SRAM access timing is widely configurable for each chip-select individually. Chip-select 0 can additionally be configured for Asynchronous Page Mode (APM, see section Asynchronous page mode (APM) bursts on page 54).

Note: APM is only available for chip select 0, not for the other chip-selects. The external memory interface controller and host interface memory controller both support this.

All access timing can be configured in steps of netX 90 clock cycle i.e. 10 ns if not stepped down.

Pause Comment pre-pause Access setup phase: 0 to 3 cycles This phase can be used to match setup timing requirements of the connected device. Read enable and write enable signal will be inactive during this phase. They will be changed to active state when changing to wait state phase or access cycle. All other netX-driven signals are active and valid during this phase. wait states Device access time wait phase: 0 to 63 cycles During read access this is read enable signal active low phase. (can be extended by During write access this is write enable signal active low phase. ready signal) All netX-driven signals are active and valid during this phase. access cycle Read data is sampled during this cycle and must be valid. Read enable and write enable 1 cycle signal will become inactive at the end of this cycle when followed by a post-pause. post-pause Access hold phase: 0 to 3 cycles This phase can be used to match hold (for write) or output disable (for read) timing requirements of the connected device. Read enable and write enable signal will be inactive during this phase. All other netX-driven signals are active and valid during this phase. For write accesses at least 1 cycle post-pause will always be inserted to generate a positive edge on the write enable signal.

Chip-select Chip-select

Read-Enable Read-Enable

Write-Enable Write-Enable

Address valid address Address valid address

Byte-Enable valid Byte-Enable valid

Data rdata Data write data

pre-p. ws-p. ac post-p. pre-p. ws-p. ac post-p. 0..3 0..63 1 0..3 0..3 0..63 1 1..3

Figure 22: Single read (left) and single write (right) access

Between sequential reads pre and post-pause can be disabled for burst generation. Between sequential writes pre and post-pause will always be performed as configured. For sequential reads and writes, the chip-select signal will remain active between subsequent accesses.

Chip-select

Read-Enable

Write-Enable

Address Address Address Addr Addr

Byte-Enable valid valid valid valid

Data rdata rdata rdata

pre-p. ws-p. ac post-p. pre-p. ws-p. ac post-p. pre-p. ws-p. ws-p. ac post-p. 0..3 0..63 1 0..3 0..3 0..63 1 0..3 0..3 0..63 0..63 1 0..3

Figure 23: Sequential read pre and post pause not disabled (compatible with netX 50, 100, 500, default)

Chip-select

Read-Enable

Write-Enable

Address Address Address Addr Addr

Byte-Enable valid valid valid valid

Data rdata rdata rdata

pre-p. ws-p. ac ws-p. ac ws-p. ws-p. ac post-p. 0..3 0..63 1 0..63 1 0..63 0..63 1 0..3

Figure 24: Sequential read pre and post pause disabled (recommended for memory devices)

Note: Memory devices like flash or NVRAM normally do not need pre and post-pauses between sequential reads (for details see device datasheet). To achieve good performance, set the disable-bits (no_p_pre_seq_rd, no_p_post_seq_rd) in the eMI configuration register for the related chip-select. For consecutive reads, addresses can be used in any order, i.e. addresses need not be incrementing.

Chip-select

Read-Enable

Write-Enable

Address Address Address Addr Addr

Byte-Enable valid valid valid valid

Data write data n write data n+1 wD n+2 wD n+m

pre-p. ws-p. ac post-p. pre-p. ws-p. ac post-p. pre-p. ws-p. ws-p. ac post-p. 0..3 0..63 1 1..3 0..3 0..63 1 1..3 0..3 0..63 0..63 1 1..3

Figure 25: Sequential write

When data direction is changed (read after write or write after read access) at least one cycle pre- pause will be inserted.

Chip-select

Read-Enable

Write-Enable

Address write Address write Address read Address read Addr read Addr

Byte-Enable valid valid valid valid valid

Data write data write data rdata rdata

ws-p. ac ws-p. ac ws-p. ac ws-p. ws-p. ac 0..63 1 1 0..63 1 1 1 0..63 1 0..63 0..63 1

always at least 1 cycle always at least 1 cycle pre-pause at post-pause after write read after write or write after read

Figure 26: Insertion of pre and post-pause at write and data direction change when 0 is configured

Also at least one pre-pause will be inserted when chip-select is changed. However, access sequences with changing chip-select as described in Figure 27 and Figure 28 are very unlikely. They can be produced only by  different netX masters running on different external devices simultaneously or  a single master which, when running burst, exceeds the chip-select address area borders.

always at least 1 cycle pre-pause at chip-select change

Chip-select A

Chip-select B

Read-Enable

Write-Enable

Address write Address write Address read Address read Addr read Addr

Byte-Enable valid valid valid valid valid

Data write data write data rdata rdata

ws-p. ac ws-p. ac ws-p. ac ws-p. ws-p. ac 0..63 1 1 1 0..63 1 1 1 0..63 1 1 0..63 0..63 1

always at least 1 cycle always at least 1 cycle pre-pause at post-pause after write read after write or write after read

Figure 27: Insertion of pre and post-pause at chip-select change if 0 is configured

Note: If pre or post-pause is not configured to 0, no additional pauses will be inserted. The programmed values will be used if data direction or chip-select is changed.

The following figure shows an example in which:  Chip-select A is configured for 3 cycle pre-pause, 2 cycle post-pause and disabled pauses during sequential reads.  Chip-select B is configured for 2 cycle pre-pause, 1 cycle post-pause.

always at least 1 cycle no chip-select active

Chip-select A 1 1

Chip-select B

Read-Enable

Write-Enable

Address write Address write Address read Address read A read Addr

Byte-Enable valid valid valid valid valid

Data write data write data rdata rdata

ws-p. ac post-p. pre-p. ws-p. ac post-p. pre-p. ws-p. ac ws-p. ws-p. ac post-p. 0..63 1 2 2 0..63 1 1 3 0..63 1 0..63 0..63 1 2

config. of config. of config. of chip-select A chip-select B chip-select A

Figure 28: Pre and post-pause at chip-select or data direction change if 0 is not configured

3.14.4.1.2 Asynchronous page mode (APM) bursts For chip-select 0 APM read bursts can be configured additionally to standard access timing described in section SRAM access timing on page 50. An APM read burst consists of a longer initial access followed by shorter access operations for data inside a certain page. The burst is restarted with the initial access after chip-select has been inactive, after write or when the address changes to another page. Pages are addressed by higher address lines, data words inside a page by lower address lines. Page boundary can be configured to 4, 8, 16, 32, 64 or 128 for 8-bit devices and to 2, 4, 8, 16, 32 or 64 for 16-bit devices. The initial access is defined by the wait-phase programmed in chip-select 0 configuration register. For the faster access operations following the initial access an APM-wait-phase of 0 to 15 cycles (i.e. 0 to 150 ns) can be configured.

Chip-select

Read-Enable

Write-Enable

Page-Address Page A Page B Page B

Word-Address Word A Word B Word C Word A Word B Addr

Byte-Enable valid valid valid valid valid valid

Data rdata rdata rdata rdata rdata rdata

pre-p. ws-p. ac apmws-p. ac apmws-p. ac ws-p. ac apmws-p. ac apmws-p. ac post-p. 0..3 0..63 1 0..15 1 0..15 1 0..63 1 0..15 1 0..15 1 0..3

Figure 29: APM read burst

Note: APM is available for read access operations only.

Note: To keep the output enable signal low for the whole APM burst, disable pre and post- pause for sequential reads of chip-select 0 (no_p_pre_seq_rd, no_p_post_seq_rd configuration bits).

For APM-related performance issues, see section SRAM burst related performance issues on page 56.

3.14.4.1.3 Ready signal – external wait state generation To allow an external device dynamic wait state generation, netX 90 provides a ready signal input. Ready signal usage can be configured for each chip-select individually. Ready activity level and signal filtering must be configured collectively for all chip-selects. Several ready generating devices can be combined by using pull-up or pull-down resistors to generate a ready-state. In this case, devices must drive the signal in wait state only. However, to obtain good timing results, we recommend using only one ready generating device. Ready status information is available for all chip-selects. A timeout-detection is implemented. Timeout errors can be associated with a system IRQ. In case of an error, the corresponding address and chip-select will be logged for debugging or error handling. Timeout is fixed: 10 µs (1024 netX cycles).

Note: Ready signal timeout-detection can be disabled, but be careful when doing so.

When enabled; ready signal must be set to wait state before the wait-phase ends. The access cycle will be performed upon detection of the ready-state, but not before the programmed wait phase has passed completely. Ready state detection may take up to 6 cycles depending on the ready filter setting (reference [1], register ext_rdy_cfg).

Chip-select

Read-Enable

Write-Enable

Address valid address

Byte-Enable valid

Data rdata

Ready ready wait ready

pre-p. ws-p. ext. generated wait-phase sample/filter ac post-p. 0..3 0..63 0..1024 2..6 1 0..3

Figure 30: Read access with external wait state generation

Chip-select

Read-Enable

Write-Enable

Address valid address

Byte-Enable valid

Data write data

Ready ready wait ready

pre-p. ws-p. ext. generated wait-phase sample/filter ac post-p. 0..3 0..63 0..1024 2..6 1 0..3

Figure 31: Read access with external wait state generation

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Core 56/275 3.14.4.2 SRAM burst related performance issues Memory devices like Flash or NVRAM normally do not need pre and post-pauses between sequential reads (see section SRAM access timing on page 50). To achieve good performance, it is recommended to set the disable-bits (no_p_pre_seq_rd, no_p_post_seq_rd) in the eMI configuration register for the related chip-select (see reference [1]). To reach the max. data bandwidth for APM devices, avoid idle cycles between read accesses. If there are idle cycles between subsequent read access operations, the SRAM controller will deselect the external device. That leads to long initial access on the next read start (see section Asynchronous page mode (APM) bursts on page 54.

Note: To avoid idle cycles, use the ARM LDM (load multiple) instruction or the mem_copy C function.

Note: Memory devices like Flash or NVRAM normally do not need pre and post-pauses between sequential reads (see device datasheet for details). To achieve good performance, set the disable bits (no_p_pre_seq_rd, no_p_post_seq_rd) in the eMI configuration register of the related chip-select (see reference [1]). For consecutive reads, addresses can be used in any order, i.e. addresses need not be incrementing.

tCSSr tCSHr tCSI

next read or Chip-Select write access

Read-Enable tRI tRSb tRAb tRSr tRSb tRAb tRSr

Ready/Busy busy busy ready busy busy ready

tASr tRBsp tRba tAHr tASr tRBsp tRba tAHr

Address Address Address Byte-Enables byte-enable byte-enable

tDSr tDHr tDSr tDHr

tLZ read tLZ read Data Data Data

tAC tHZ tAC tHZ

Figure 32: Read, pre and post-pauses enabled for sequential reads (write enable always high)

tCSSr tCSHr tCSI

next read or Chip-Select write access

Read-Enable

tRSb tRAb tRSr tRSb tRAb tRSr

Ready/Busy busy busy ready busy busy ready

tASr tRBsp tRba tAchg tRBsp tRba tAHr

Address Address Address Byte-Enables byte-enable byte-enable

tDSr tDHr tDSr tDHr

tLZ read read Read Data Data Data

tAC tAC tHZ

Figure 33: Read, pre and post-pauses disabled for sequential reads (write enable always high)

tCSSr tCSHr tCSI

next read or Chip-Select write access

Read-Enable

tASr tAchg tAchg tAHr

Address Address Page A, Word A Page A Address Page B Byte-Enables byte-enable Word B byte-enable

tLZ tDSr tDHr tDSr tDHr tDSr tDHr

read read read Read Data Data Data Data

tAC tAPM tAC tHZ

Figure 34: APM read burst, pre and post-pauses disabled between sequential reads

tCSSw tCSHw tCSI

next read or Chip-Select write access

tWA tWI tWA

Write-Enable

tRSb tRAb tRSr tRSb tRAb tRSr

Ready/Busy busy busy ready busy busy ready

tASw tRBsp tRba tAHw tASw tRBsp tRba tAHw

Address Address Address Byte-Enables byte-enable byte-enable

tDSw tDHw tDSw tDHw

Data write Data write Data

tDDw

Figure 35: Write (read enable always high)

Note: Byte enable signals have address character. The address timing parameters cover the byte enable signals.

Timings of netX 90 SRAM interface are widely configurable by software. Detailed timings depend on the following programmable parameters that can be set for each chip-select area individually (exception: Ready filter time) by software.

Symbol Parameter Min Typ Max Unit (1) (1) tSYS netX system clock cycle time 10.0 10.0 ns

tpr programmable pre-pause wait phase (10 ns steps) 0.0 n* tSYS 3*tSYS ns

tpo programmable post-pause wait phase (10 ns steps) 0.0 n* tSYS 3*tSYS ns

tpw programmable wait state phase (10 ns steps) 0.0 n* tSYS 63*tSYS ns (2) tpaw programmable APM wait state phase (10 ns steps) 0.0 n* tSYS 15*tSYS ns

trf programmable ready filter time 0.0 n* tSYS 3* tSYS ns

Notes 1. Default is 100 MHz frequency as netX-internal system clock, but this can be decreased to save power. 2. APM bursts are only supported for chip-select 0.

3.14.4.4 IO timing parameters for SRAM

All electrical characteristics of netX 90 SRAM MEM-eMI part are related to CL: 30 pF. For read access, device access times must match the following conditions:

Symbol Parameter Min Typ Max Unit

tAC Data Access time tpw+tsys-7.0 ns

tAPM APM Data Access time tpaw+tsys-8.7 ns

Note: Access times can be extended by ready signal usage.

Symbol Parameter Min Typ Max Unit (1) tCSSr Chip-Select Setup time (read) tpr-2.1 ns (2) tCSHr Chip-Select Hold time (read) tpo-1.7 ns

tCSSw Chip-Select Setup time (write) tpr+tpw+tSYS-1.4 ns

tCSHw Chip-Select Hold time (write) ns post-pause 0 tsys-1.5 post-pause > 0 tpo-1.5

tCSI Chip-Select Idle time tsys-3.4 ns (1) tASr Address Setup time (read) tpr-3.3 ns (2) tAHr Address Hold time (read) tpo-3.0 ns

tASw Address Setup time (write) tpr+tpw+tsys-2.5 ns

tAHw Address Hold time (write) ns post-pause 0 tsys-2.8 post-pause > 0 tpo-2.8

tAchg Address Change time (read burst) 3.6 ns

tDSr Data Setup time (read) 8.2 ns (2) tDHr Data Hold time (read) -4.9 ns

tLZ Data Low-Z time (read) 0.0 ns

tHZ Data High-Z time (read) ns pre-pause 0 tsys-3.1 pre-pause > 0 tpr-3.1

tDSw Data Setup time (write) tpr+tpw+tsys-2.7 ns

tDHw Data Hold time (write) ns post-pause 0 tsys-2.8 post-pause > 0 tpo-2.8

tDDw Data-Disable time (write) ns post-pause 0 tsys-3.8 post-pause > 0 tpo-3.8

tRI Read-Enable Idle time tpr+tpo-2.7 ns

tWI Write-Enable Idle time ns post- and pre-pause 0 tsys-2.7 post- or pre-pause > 0 tpr+tpo-2.7

tWA Write-Enable Active time tpw+tsys-0.5 ns

Notes

1. For pre-pause setting 0 (tpr is 0) chip-select and address setup time could become negative at read access start. That means they could change while read enable has already become low in the first 2.7 ns of an access. This can be avoided by setting pre-pause to 1 or more. However, this will increase the total access time by 10 ns.

2. For post-pause setting 0 (tpo is 0) chip-select and address hold time could become negative at read access end. That means they could already change while read enable still is low in the last 3.0 ns (tAHr) of an access. However, that will not cause read data problems as read data is already sampled at least 4.9 ns (tDHr) before read access end. To guarantee stable chip-select and address signals at read access end post-pause can be set to 1 or more. However, this will increase total access time by 10 ns.

The following table provides timing parameters for optional ready signal. Wait state-pause (tpw) must be set at least to 1 when ready is used.

Symbol Parameter Min Typ Max Unit

tRSb Ready Setup Busy time tpw-0.5*tsys -6.8 (1) tRAb Ready Active Busy time 1024 tsys ns

tRSr Ready Setup Ready time trf+1.5*tsys -8.0

tRAr Ready Active Ready time trf+tsys +0.6

tRbsp Ready Busy Spike time trf-0.6

Note: (1) Ready timeout. Timeout can be disabled by software. However, netX will be stalled if ready signal is permanently set to busy state.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Booting and SYS LED 61/275 4 Booting and SYS LED 4.1 Boot sequence and boot mode Every power-on cycle starts by executing the ROM code (which is responsible for booting the device in a secure and reliable manner) and starting the firmware thereafter. The ROM code features a ROM loader that automatically recognizes the operating mode settings and the initial state of the device. Figure 36 shows the flow chart of the ROM code boot sequence. Reset Start ROM code

Console mode Software Alternative boot mode command

Console mode Mode Alternative boot mode selection RDY/RUN No

No Yes Valid Valid loadable maintenance firmware firmware

Yes

Enter No console mode (mode settings SQI)

Standard boot mode Boot and start Software reset firmware

Figure 36: ROM code boot sequence

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Booting and SYS LED 62/275 The ROM loader features a console mode and an alternative boot mode that enable the handling of firmware programming depending on the use case. As shown in Figure 36, the ROM code enters either the console mode or the alternative boot mode in the following ways:  After a software reset cycle if the firmware has initiated the mode before  After a hardware reset while the mode pins RDY and RUN have been set before  After a hardware reset cycle if no valid firmware image has been found

Note: Hardware reset means either power cycle or chip reset pin.

3.3 V 3.3 V

netX 90 SYS LED YELLOW GREEN 3.3 V Optional SQI_SIO0/MOSI SQI Flash DI(IO0) DO(IO1) SQI_SIO1/MISO VCC WP(IO2) SQI_SIO2 HOLD(IO3) SQI_SIO3 Console Mode CS SQI_CS0 RDY GND CLK SQI_CLK RUN GND Alternative Boot Mode GND

GND Figure 37: Pin configuration operating modes

4.1.1 Overview

Boot mode RDY RUN Details Standard boot mode High High See section Standard boot mode (page 62). Console mode Low High or Low See section Console mode (page 63). Alternative boot mode High Low See section Alternative boot mode (page 63). Table 14: Boot modes (RDY and RUN signal)

4.1.2 Standard boot mode In standard boot mode, the ROM code starts a firmware if available. In this mode, the boot sequence is: The ROM code searches for a valid firmware and if found, starts the firmware. Otherwise, the ROM code starts a valid maintenance firmware (see section Alternative boot mode) or in case no maintenance firmware is available, the ROM code enters the console mode (see section Console mode).

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Booting and SYS LED 63/275 4.1.3 Console mode The purpose of the console mode is to enable the handling of firmware programming and chip- level security settings. The console mode interface is determined by pin configuration settings SQI_SOI0, SQI_SIO1, and SQI_SOI2 as shown in Figure 37 and summarized in Table 15. The console mode for the host interface enables firmware programming through the application host if the device is used as a companion chip. The console mode for the Ethernet interface enables firmware programming by using utility tools or via DHCP/TFTP server. In addition, the ROM code provides an Ethernet switch and a web server for software updates.

Note: A valid firmware image passes the verification sequence of the ROM code. If the image is incomplete or defect, for whatever reason, the ROM code follows the flow chart in Figure 36. If the device is blank, MAC addresses derive from unique chip identifiers coupled with random numbers generated by the on-chip RNG. In this case, IP addresses are assigned dynamically via either DHCP or IPv4 Link-Local.

Console mode Chip interface SQI_SIO2 SQI_MISO/SQI_SIO1 SQI_MOSI/SQI_SIO0 Default, 7 UART and Ethernet High High High (by internal pull-up) (by internal pull-up) (by internal pull-up) Reserved, 6 Reserved High High Low (by internal pull-up) (by internal pull-up) (by external pull-down) Reserved, 5 Reserved High Low High (by internal pull-up) (by external pull-down) (by internal pull-up) 4 UART and 8-bit DPM High Low Low (by internal pull-up) (by external pull-down) (by external pull-down) 3 UART and 16-bit DPM Low High High (by external pull-down) (by internal pull-up) (by internal pull-up) 2 UART and SPM0 Low High Low (by external pull-down) (by internal pull-up) (by external pull-down) 1 UART and SPM1 Low Low High (by external pull-down) (by external pull-down) (by internal pull-up) 0 UART Low Low Low (by external pull-down) (by external pull-down) (by external pull-down) Table 15: Pin configuration console modes

4.1.4 Alternative boot mode The alternative boot mode is used to start a maintenance firmware, which provides the following use cases:  Firmware updates: A new firmware received via a web server or the host interface is stored either on-chip in intflash1 or off-chip in an externally connected SQI Flash. A software reset cycle initiated by a software command starts the maintenance firmware which then programs the new firmware.  Multiple firmware versions: The netX 90 has a maintenance firmware stored in intflash1 and holds multiple firmware versions for different real-time Ethernet protocols in an externally connected SQI Flash. The maintenance firmware programs the selected firmware by the system integrator, e.g. selected via a rotary DIP switch (or other ways).

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Booting and SYS LED 64/275 4.2 System LED The SYS LED at RDY and RUN displays the operating status of the netX 90. We recommend using a dual LED as shown in Figure 37. The ROM code uses the System LED with the following states:

LED Color State Meaning SYS Yellow Flashing 1 Hz Wait for connection in console mode (UART, DPM, Ethernet). Yellow Flashing Waiting for DPM connection 1* long and 2* short Yellow Flashing Waiting for Ethernet link up 1* long and 4* short Yellow Flashing System reset by clock supervisor 1* long and 5* short Off Off 1. After reset and during boot start. 2. Power supply for the device is missing or hardware defect. Table 16: States of system LED (used from the ROM code)

LED State Definition Flashing 1 Hz The indicator turns on and off with a frequency of 1 Hz: “on” for 0.5 s, followed by “off” for 0.5 s. Flashing The indicator shows a sequence of one long and two short flashes. 1* long and 2* short The sequence is one long flash (1.5 s on and 0.5 s off), followed by two short flashes (each 0.25 s on and 0.75 s off), finished by a long off phase (1 s). Blinking The indicator shows a sequence of one long and four short flashes. 1* long and 4* short The sequence is one long flash (1.5 s on and 0.5 s off), followed by four short flashes (each 0.25 s on and 0.75 s off), finished by a long off phase (1 s). Blinking The indicator shows a sequence of one long and five short flashes. 1* long and 5* short The sequence is one long flash (1.5 s on and 0.5 s off), followed by five short flashes (each 0.25 s on and 0.75 s off), finished by a long off phase (1 s). Table 17: LED state definitions of system LED (used from the ROM code)

The ROM code starts an executable software. The netX executes the loaded software which then controls the system LED, i.e. more states are possible than described in Table 16.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 65/275 5 Interfaces 5.1 MMIO - Multiplex Matrix MMIO signals (Multiplex Matrix I/O) enable you to select and configure the interfaces you need for your application. Table 18 lists the signals possible for an MMIO pin. netX 90 offers 18 MMIOs which can be configured as follows:  MMIO0…7 are double-bonded with ADCxxx signals. If ADC is not used, these pins can be used as MMIO or other shared signals e.g. IO-Link0/1, Biss0/1, Endat0/1.  MMIO8-18 are part of the host interface. Host interface signals not required can be used as MMIO or other shared signals SQI1_APP, MLED4-11, IO-Link4-7, ETH, DPM0_SPI, UART_XPIC, or UART_APP.

Function Direction Description GPIOs GPIO0-GPIO7 IO General Purpose IOs I2C I2C_XPIC_APP_SCL IO I2C Interface Clock Signal I2C_XPIC_APP_SDA IO I2C Interface Data Signal I2C_APP_SCL IO I2C Interface Clock Signal I2C_APP_SDA IO I2C Interface Data Signal SPI SPI_XPIC_APP_CLK IO Clock signal of SPI xpic app interface SPI_XPIC_APP_CS0N IO Chip select 0 signal of SPI xpic app interface SPI_XPIC_APP_CS1N IO Chip select 1 signal of SPI xpic app interface SPI_XPIC_APP_CS2N IO Chip select 2 signal of SPI xpic app interface SPI_XPIC_APP_MISO IO Master In / Slave Out signal of SPI xpic app interface SPI_XPIC_APP_MOSI IO Master Out / Slave In signal of SPI xpic app interface SPI1_APP_CLK IO Clock signal of SPI app interface SPI1_APP_CS0N IO Chip select 0 signal of SPI app interface SPI1_APP_CS1N IO Chip select 1 signal of SPI app interface SPI1_APP_CS2N IO Chip select 2 signal of SPI app interface SPI1_APP_MISO IO Master In / Slave Out signal of SPI app interface SPI1_APP_MOSI IO Master Out / Slave In signal of SPI app interface UART UART_XPIC_APP_CTSN I UART xpic application clear to send UART_XPIC_APP_RTSN O UART xpic application request to send UART_XPIC_APP_RXD I UART xpic application receive data UART_XPIC_APP_TXD O UART xpic application transmit data UART_APP_CTSN I UART application clear to send UART_APP_RTSN O UART application request to send UART_APP_RXD I UART application receive data UART_APP_TXD O UART application transmit data

Function Direction Description CAN CAN0_APP_RX I CAN receive data CAN0_APP_TX O CAN transmit data CAN1_APP_RX I CAN receive data CAN1_APP_TX O CAN transmit data MII ETH_MDC O MDC ETH_MDIO IO MDIO WDG WDG_ACT O System watchdog Other EN_IN I HIF pio input sampling enable XC XC_SAMPLE0 I Trigger/latch unit XC_SAMPLE1 I Trigger/latch unit XC_TRIGGER0 O Trigger/latch unit XC_TRIGGER 1 O Trigger/latch unit Table 18: Multiplex matrix signals

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 67/275 5.2 Host interface 5.2.1 Overview The dual-port memory (DPM) interface allows data transfer between the netX and an external host system. Unlike standard DPM, the netX 90 DPM is a virtual DPM which appears as a linear memory to the host side. The netX DPM interface can be  a Parallel dual-port memory interface (DPM0) or  two high speed Serial dual-port memory interfaces (DPM0_SPI, DPM1_SPI). The DPM interface is located on the HIF-IOs which are widely shared. They can also be used as memory interface instead of a host interface, see section Pin table sorted by signals on page 239 For configuration use the netX Studio CDT software, see reference [3]. This configuration software allows you to select between serial and parallel DPM and to control unused DPM signals (in the hif_io_ctrl register area).

5.2.2 Block diagram

DPM0 Serial DPM SPI or SQI Slave (SPM0) HIF_D[15:0]

Parallel Addr and Ctrl DPM HIF_A[17:0] Data HIF_BHEN Ready

config HIF_CSN

DPM1 Top HIF_RDN Serial DPM MUX (SPM1) SPI or SQI Slave HIF_WRN config HIF_RDY Multiplexmatrix MMIO[16:8] … HIF_DIRQ Peripherals Peripherals HIF_SDCLK

config

netX 90

Figure 38: Host interface block diagram

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 68/275 5.2.3 Features The following list provides an overview of the Dual-port memory features:  Parallel or serial DPM modes widely configurable by software.  Parallel dual-port memory (DPM0)  8 or 16-bit data width.  Separated address and data busses or multiplexed A/D bus.  11 to 15 address-lines (external address range: 2 KB to 32 KB).  SRAM modes.  Optional Ready/Busy Output  Motorola and Intel modes (byte strobes and one data direction signal).  Programmable active levels of control signals (as byte, address or chip enables).  55 ns read access time for random intram access.  35 ns burst read access time to intram using read ahead.  Configurable address setup time for read (0 ns to 30 ns in steps of 10 ns).  Configurable read data setup time (0 ns to 70 ns in steps of 10 ns).  Optional widely configurable ready/busy/acknowledge signal.  Optional input signal filtering (tolerating hazards < 10 ns).  Read burst support (address change without chip-select/read signal toggling).  Optional address-enable and address-latch.  Serial dual-port memory (DPM0_SPI, DPM1_SPI)  Standard 1-bit SPI supporting all 4 SPI modes (clock polarity / phase) up to 125 MHz.  4-bit Quad-SPI/QSPI supporting all 4 SPI modes (clock polarity / phase) up to 33 MHz (i.e. data-rates up to 133 Mbit/s, 16.6 Mbyte/s).  The selected SPI mode is identical for DPM0_SPI and DPM1_SPI.  Serial frame format optimized for CPU or DMA interaction.  DPM0_SPI can be used with a 16-bit external memory.  DPM1_SPI can be used with an 8-bit external memory only.  Serial status byte for quick error handling.  Timing of serial read-data from netX can be configured.  Configurable external visible address ranges  2 K (A[10:0])  4 K (A[11:0])  8 K (A[12:0])  16 K (A[13:0])  32 K (A[14:0])  Hardware endianness modes  little endian (e.g. ARM)  16-bit big endian (e.g. Motorola 16-bit CPUs)  Enhanced access error detection

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 69/275  Interrupt generation for external host device  Two optional interrupt signals (normal, fast IRQ) for both parallel and serial DPM  Interrupt active level programmable  Interrupt drive programmable (always-active, pull-up, pull-down or inverted active level)  Unused DPM signals can be used as programmable IOs (HIF_PIOs)  Up to 8 programmable IOs for APP CPU (PIO_APP)

Note: Like all other digital I/Os of the netX 90, the DPM interface uses 3.3 V signaling voltage only. 5 V signals cannot be used!

5.2.4 Dual-port memory interface structure The internal structure of netX 90 is a synchronous design running on netX system clock (typically 100 MHz). Each external DPM access is converted to an internal netX system access using synchronous 100 MHz logic. For parallel DPM modes, all input signals are synchronized by at least two stages of sample flip- flops to avoid propagating invalid signal states into the internal logic of the netX. In serial DPM mode, serial clock input is directly used for serial to parallel input and parallel to serial output shift register stages. That allows serial clock rates even above netX-internal 100 MHz system clock, but requires high signal quality. All netX-internal data paths between serial clock and netX system clock domain are synchronized by two stage synchronization flip-flops.

Important: Signals of serial DPM, especially serial clock (DPMx_SPI_CLK) and chip select (DPMx_SPI_CSN) signals must be free of hazards as they are directly used for clock and reset signals.

Serial and parallel DPM I/Os are shared. Serial communication is performed by a special serial protocol containing address, data direction and data size information (section Serial 1-bit DPM protocol on page 87). A protocol converter transforms serial data frames to standard parallel accesses.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 70/275 5.2.5 Parallel dual-port memory interface This section provides an overview of netX 90 parallel function and features. This includes a guide (section Parallel DPM mode and setup guide on page 73) to determine a required setting if a host CPU cannot be found in the list of Supported parallel DPM modes on page 72. For detailed information on parallel DPM modes, connections, signal mapping, access timing depending on type of access, and internal netX 90 properties, see reference [1].

Important: There are several programmable timing parameters for parallel DPM (e.g. signal filtering, address setup time, read data setup time). By default these parameters are set in such a way that the function of the DPM is guaranteed even with unusual host timings (e.g. unstable address at access start). However, this leads to longer access times than typically required. For good performance it is absolutely necessary to change default timing to timings according to the application and host used. This is explained in section Programmable parallel DPM timing parameters and signal filtering on page 77.

Important: DPM provides an optional ready/busy/acknowledge signal. Not using this signal could lead to reduced performance especially when host is accessing netX address areas beyond internal memories (intrams). Non-intram-areas (e.g. peripheral registers or XC memories) require longer access times which must be observed to avoid data loss.

Note: In the following description, pDPM stands for parallel DPM, pDPM8 for parallel DPM with 8-bit data and pDM16 for parallel DPM with 16-bit data.

Pin function Direction Parallel DPM function Related config registers Notes DPM_A[15:0] input address lines dpm_addr_cfg.addr_range 1, 2 dpm_cfg0x0.mode dpm_if_cfg.addr_sh dpm_if_cfg.be_sel DPM_D[15:0] input data lines dpm_cfg0x0.mode - DPM_CSN input chip-select dpm_if_cfg.cs_ctrl 3 DPM_RDN input read or data direction control dpm_if_cfg.dir_ctrl - DPM_WRN input write control (or low byte write strobe) dpm_if_cfg.dir_ctrl - dpm_if_cfg.be_sel DPM_WRHN input write control high byte dpm_if_cfg.dir_ctrl - dpm_if_cfg.be_sel DPM_BHEN input byte enable or strobe for pDPM8 dpm_if_cfg.be_sel 4 dpm_if_cfg.be_wr_dis dpm_if_cfg.be_rd_dis DPM_ALE input address latch or enable for pDPM8 and pDPM16 dpm_cfg0x0.mode - dpm_if_cfg.aen_pol DPM_RDY output ready/busy for host dpm_rdy_cfg 5 dpm_pio_cfg1.sel_rdy_pio DPM_DIRQ output IRQ 1 for host (e.g. for data-IRQ) dpm_io_cfg_misc.irq_oec 5, 6 dpm_io_cfg_misc.irq_pol dpm_pio_cfg1.sel_dirq_pio DPM_SIRQ output IRQ 2 for host (e.g. for service-IRQ) dpm_io_cfg_misc.fiq_oec 5, 6 dpm_io_cfg_misc.fiq_pol dpm_pio_cfg1.sel_sirq_pio Table 19: Pin functions of parallel DPM

Notes 1. Address lines 0 to 10 are mandatory for non-multiplexed DPM modes, higher lines are optional. For multiplexed modes (i.e. address and data are applied to dpm_d lines; selection is made by address latch signal) address lines 8 to 10 are mandatory for pDPM8 and unused for pDPM16. 2. DPM address bus can be byte-oriented with byte enables on low address lines or word- oriented (i.e. byte address is right-shifted according to used data size) without byte enables. 3. DPM can be configured with 1 or even without chip select signals, but omitting chip select is not recommended. 4. Byte enables have many different functions. Various different signal mappings are possible, they can be used as byte strobes, active-polarity can be configured, etc. 5. Signal is in PIO mode by default and must be set to functional mode first. 6. Attention: HIF IOs used for IRQs differ for serial and parallel DPM mapping, but the IRQ function is the same.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 72/275 5.2.5.2 Supported parallel DPM modes Modes are selected by configuring the function of control signals e.g. byte enables, read and write controlling or chip-selects. This leads to a wide range of supported DPM modes: The following modes are supported by netX 90 parallel DPM without any external glue logic.  SRAM or Intel 8-bit selectable in netX Studio CDT: DPM8, Non-multiplexed Intel (SRAM) byte-enable.  SRAM, 16-bit, byte-enable selectable in netX Studio CDT: DPM16, Non-multiplexed Intel (SRAM) byte-enable.  SRAM or Intel, 8-bit multiplexed  SRAM, 16-bit multiplexed (netX 50: Intel, no byte-enables)  SRAM, 16-bit multiplexed 2 byte-enables, byte-address  SRAM, 16-bit multiplexed 2 byte-enables, word-address  Intel, 16-bit, byte-write  Intel, 16-bit multiplexed byte-write  TI OMAP, 16-bit non-multiplexed  TI OMAP, 16-bit multiplexed  Motorola, 8-bit (6800)  Motorola, 16-bit  Motorola, 16-bit (68000)  Motorola, 8-bit multiplexed  Motorola, 16-bit multiplexed netX 50: byte-address  Motorola, 16-bit multiplexed word-address

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 73/275 5.2.5.3 Parallel DPM mode and setup guide The following steps must be performed to configure the netX 90 DPM according to the host requirements. The description of register bits dpm_if_cfg provides an overview of the settings for the modes listed above. If a desired mode is not in the list, step through the following guide to determine whether the netX 90 DPM is applicable at all. 1. Determine the required data width (i.e. 8 or 16-bit data) and the mode to be used, multiplexed or non-multiplexed (register bit dpm_cfg_0x0.mode). 2. Determine the required data direction protocol of the interface used (register bit dpm_if_cfg.dir_ctrl). There are 3 possibilities: A. SRAM-like interface with 2 separated low-active lines: Read enable or output enable (RDn, OEn) and write enable (WRn, WEn). B. Intel-like interface with 1 data direction line. High level flags a write access; low level flags a read access. C. Motorola-like interface with 1 data direction line. High level flags a read access; low level flags a write access. 3. Determine the use of the chip-select signal and the use of internal address-decoding (address comparator). For details, see the description of register bit dpm_if_cfg.cs_ctrl. 4. Determine the active-level of byte enable, byte strobe or byte-write signals. The enable for each data-byte can be controlled separately by register bit dpm_if_cfg.be_pol. If no byte enables are required (e.g. for 8-bit data interfaces), this step can be ignored. 5. Select the IO allocation of byte enable or byte strobe signals. For details, see the description of register bit dpm_if_cfg.be_sel. If no byte enables are required (e.g. for 8-bit data interfaces), this step can be ignored. 6. Determine the use of byte enable or byte strobe during read access; they can be ignored by register bit dpm_if_cfg.be_rd_dis. When ignored, a read access is always performed according to the full data bus width and all data bus lines are always driven. 7. Determine the use of byte enable or byte strobe during write access; they can be ignored by register bit dpm_if_cfg.be_wr_dis. When ignored, a write access is always performed according to the full data-bus width. Writing single bytes while using a 16-bit data bus is not possible. 8. Determine whether byte or word addresses are used, i.e. whether an address which is right- shifted according to the used data width is used or not. For details, see description of register bit dpm_if_cfg.addr_sh. 9. If an address-enable or address-latch signal is used (i.e. always for multiplexed modes), select this signal by register bit dpm_if_cfg.aen_sel and configure the active level by register bit dpm_if_cfg.aen_pol.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 74/275 5.2.5.4 Parallel DPM ready generation DPM access time could vary e.g. depending on the internal state of the DPM or netX target address. To avoid errors, the host devices must always observe the worst case access time. However, running any DPM access with worst case timing could lead to a significantly lower performance than running any access with an optimum access length. To avoid wasting performance there is a widely configurable ready signal. During an access it is set to not-ready state when netX cannot receive or deliver new data. The host must insert wait cycles then and stretch the current access until netX releases it to ready state. As soon as this signal is set to ready-state again, the host device can finish the access.

The read data setup time tRDS is the time before data becomes valid. This timing parameter can be programmed by DPM timing configuration register dpm_timing_cfg, see section Read data setup time - tRDS on page 78.

Important: The read data setup time is set by default to 70 ns, designed for very slow hosts. This results in a bad performance for faster hosts because time is wasted with each read access. To improve performance, set the tRDS parameter according to the host used.

The ready signal (DPM_RDY) behavior of the netX DPM interface is widely programmable:  programmable signal polarity:  ready/acknowledge/not-wait high, wait/busy low  ready/acknowledge/not-wait low, wait/busy high  2 programmable signal modes:  wait/busy mode  ready/acknowledge mode  4 programmable driving modes  High-impedance output (mode 0)  Push-pull output (mode 1)  Sustained-tristate output (mode 2)  Open-drain/open-source output (depending on the configured polarity, mode 3) In wait/busy mode, the DPM_RDY signal is set to active state (i.e. netX is busy) immediately after the start of access. The host must wait and extend the current access while the DPM_RDY remains active. After release to inactive or high impedance state the access can be finished by host device. The signal then remains inactive until the next access. In ready/acknowledge mode DPM_RDY does not changed at access start. The active-state rather generates an acknowledge pulse at access end. A host must wait and extend the current access until the signal becomes active.

Note: The DPM_RDY signal is always set to busy state for a read access. In contrast single write accesses are usually accepted without setting DPM_RDY to busy state.

Note: In multiplexed DPM modes, DPM_RDY is never set to wait/busy state during address phase, only during data phase.

Note: The ready/acknowledge mode is not only an inverted version of the wait/busy mode as shown by the figures below.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 75/275 The following figures give an overview of ready signal behavior and different access types supported by the netX DPM interface. In wait/busy mode the drive active level is the inverted programmed ready signal polarity (as the active phase is the wait-phase).

access cycle wait phase data valid phase t RDS ~10ns ~10ns 10..70ns

DPM_CSn

DPM_RDn

DPM_WRn

DPM_A, DPM_BE A0

DPM_D Data.A0

DPM_RDY if wait/busy mode is selected

mode 0 high Z

mode 1 drive inactive drive active drive inactive

mode 2 high Z drive active drive inactive high Z

mode 3 high Z drive active high Z

DPM_RDY if ready/acknowledge mode is selected

mode 0 high Z

mode 1 drive inactive drive active drive inactive

mode 2 high Z drive active drive inactive high Z

mode 3 high Z drive active high Z

Figure 39: Non-multiplexed mode read access and ready generation (SRAM mode example)

access cycle address phase data phase wait phase data valid phase t RDS ~10ns ~10ns 10..70ns

DPM_CSn

DPM_RDn

DPM_WRn

DPM_ALEn

DPM_BE valid

DPM_A(high) high Address (above A/D)

DPM_D(A/D bus) low Address Data.A0

DPM_RDY if wait/busy mode is selected

mode 0 high Z

mode 1 drive inactive drive active drive inactive

mode 2 high Z drive active drive inactive high Z

mode 3 high Z drive active high Z

DPM_RDY if ready/acknowledge mode is selected

mode 0 high Z

mode 1 drive inactive drive active drive inactive

mode 2 high Z drive active drive inactive high Z

mode 3 high Z drive active high Z

Figure 40: Multiplexed mode read access and ready generation (SRAM mode example)

access cycle wait phase data valid phase: ~10ns min 10ns ~10ns

DPM_CSn

DPM_RDn

DPM_WRn

DPM_A, DPM_DQM A0

DPM_D Data.A0

DPM_RDY if wait/busy mode is selected

mode 0 high Z

mode 1 drive inactive drive active drive inactive

mode 2 high Z drive active drive inactive high Z

mode 3 high Z drive active high Z

DPM_RDY if ready/acknowledge mode is selected

mode 0 high Z

mode 1 drive inactive drive active drive inactive

mode 2 high Z drive active drive inactive high Z

mode 3 high Z drive active high Z

Figure 41: Non-multiplexed mode write access ready generation (SRAM mode example)

access cycle address phase data phase wait phase data valid phase: ~10ns min 10ns ~10ns

DPM_CSn

DPM_RDn

DPM_WRn

DPM_ALEn

DPM_BE valid

DPM_A(high) high Address (above A/D)

DPM_D low Address Data.A0

DPM_RDY if wait/busy mode is selected

mode 0 high Z

mode 1 drive inactive drive active drive inactive

mode 2 high Z drive active drive inactive high Z

mode 3 high Z drive active high Z

DPM_RDY if ready/acknowledge mode is selected

mode 0 high Z

mode 1 drive inactive drive active drive inactive

mode 2 high Z drive active drive inactive high Z

mode 3 high Z drive active high Z

Figure 42: Multiplexed mode write access ready generation (SRAM mode example)

Note: Single write accesses are usually accepted without setting the DPM_RDY signal to busy state. In wait/busy mode the signal does not become active then. In ready/acknowledge mode the signal becomes active state immediately at access start.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 77/275 Under abnormal conditions netX could be internally busy for an unpredictable time. To avoid stalling of the host, a busy-timeout prevents the access from being blocked. In case of a timeout, the current access will be aborted by setting the ready signal to ready state. The host is now able to terminate the access and prevents system lock up conditions. The data of the aborted access is invalid. A flag in the netX DPM status registers indicates an access termination. This indication requires an action of the host. Additionally, an interrupt can be generated.

Note: Long access times and timeouts can generally be avoided by a DPM window setup that allows access to zero wait state address areas only.

Note: The timeout can be configured to 256 netX clock cycles (i.e. 2.56 us), to 2048 clock cycles (i.e. 20.48 us) or completely disabled (which is not recommended).

5.2.5.5 Programmable parallel DPM timing parameters and signal filtering

The timing parameters read data setup time (tRDS) and address setup time (tOSA) can be set in register dpm_timing_cfg. Signal filtering can be enabled or disabled.

Important: Changing timing configuration will have impact on parallel DPM access timing. After power on reset, the timing parameter values are set by default to work with very slow hosts. For good performance these values have to be set according to the host access generation (see host data sheet) and signal quality which depends on PCB wiring and operating environment.

The following figures show the configurable timing parameters:

tOSA tRDS

Address, nBE A0

CSn

RDn

WRn

Data Data.A0

Ready ready wait ready

read access error detected if access terminates before tRDS passed

Figure 43: Read data setup time and read address setup time (SRAM read)

5.2.5.5.1 Read data setup time - tRDS The read data setup time parameter can control the read access timing. In ready signal mode, the read data setup time parameter specifies the time that elapses before the read data become valid on the external data bus. As soon as they have become valid, the ready signal changes from wait to ready state. If the host device terminates an access before the read data setup time has elapsed, the netX DPM interface will detect a read access error. Read data setup time can be set in steps of 10 ns (1 system clock cycle) between 0 ns and 70 ns. Default after power-on reset is 20 ns.

Important: The set read data setup time will extend the total read cycle time.

Note: The read data setup timing parameter has no impact on any write access.

Note: Read access error detection does not depend on the use of the ready signal.

5.2.5.5.2 Address setup time - tOSA In SRAM modes address lines and byte enables (data qualifier signals, nBE) are typically stable at access start (chip-select and read or write enable have both become low). However, some host devices simultaneously generate control signals and the address. In this case address lines on the external bus can become valid later than the control signals (e.g. due to the higher capacitive load by PCB wiring). Invalid (or unstable) address or byte enables (data qualifier signals) at start of a read access will lead to a false internal access address when internal access is started immediately after read and chip select signals are detected active. To avoid that, read address setup time can be configured. Internal access will not be started until address setup time has elapsed. Address setup time can be programmed in steps of 10 ns (1 system clock cycle) between 0 ns and 30 ns. Default after power-on reset is 30 ns.

Important: Programmed address setup time will extend total read and write cycle time.

Note: In Motorola and Intel modes (i.e. modes using 1 data direction signal instead of 2 separated SRAM-like read and write enable signals), the byte enables must not become active while the direction signal is unstable. To prevent the byte enable from becoming active although the direction signal is still unstable, increase the address setup time. This will force the DPM to wait for a stable direction signal.

5.2.5.5.3 Input signal filtering Signal filtering is implemented in netX DPM to suppress short term hazards (e.g. caused by crosstalk on PCB). When enabled, hazards shorter than 10 ns (1 netX system clock cycle) are filtered off. When filtering is disabled, all signals must be clear of hazards or spikes. Signal filtering can be enabled (default after power-on reset) or disabled.

Important: Enabling signal filtering will cause 1 additional system clock cycle for each signal sampling. One system clock period must be added to all access cycle times (including min. write cycle time, min. idle time between access operations and min. address or data phase in multiplexed mode) when filtering is enabled.

Address, nBE A0 A1

CSn

RDn

WRn

Data D0 D1

Ready ready wait ready

Figure 44: Hazards and spikes which will be suppressed when signal filtering is enabled

Note: Signal filtering cannot always eliminate all hazards, especially if overall signal quality is bad.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 80/275 5.2.5.6 Access timing without using the ready signal If the host does not use the DPM ready signal, the host must not access the netX address areas with internal wait states.

Note: Accessing netX wait state areas without using the ready signal is possible, but access timing calculation becomes very complex and could result in inacceptable timings.

To avoid internal wait states, access must be limited to the following netX target areas:  intrams  handshake cells

Access timing always depends on the programmed setting of tOSA and on whether input filtering is enabled (5.2.5.5). The access timing can be calculated by:

tAC = 4.5 system clock cycles + 10 ns + tOSA + tfilter That leads to the following table:

DPM access time for 0 wait state areas Register setting of dpm_timing_cfg

intram, handshake cells filter t_osa 55 ns (4.5 system clock cycles + approx. 10 ns) 0 0 65 ns (5.5 system clock cycles + approx. 10 ns) 0 1 75 ns (6.5 system clock cycles + approx. 10 ns) 0 2 85 ns (7.5 system clock cycles + approx. 10 ns) 0 3 65 ns (5.5 system clock cycles + approx. 10 ns) 1 0 75 ns (6.5 system clock cycles + approx. 10 ns) 1 1 85 ns (7.5 system clock cycles + approx. 10 ns) 1 2 95 ns (8.5 system clock cycles + approx. 10 ns) 1 3

Note: The values are approximate values. Real timings are a little faster (about 2 ns). For exact values, see timing characteristics in section on page 93.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 81/275 5.2.5.7 DPM interrupt signals The netX DPM interface provides two IRQ signals:  DPM_SIRQ  DPM_DIRQ The polarity and drivability of each IRQ signal can be configured. Figure 45 shows configurable IRQ driving modes.

3 system clocks 3 system clocks

netX internal IRQ

netX system clock

external IRQ signals (DPM_DIRQ, DPM_SIRQ)

oec=0, pol=0 active high

oec=0, pol=1 active low slow RC-IRQ release if oec==1 oec=1, pol=0 pull up

oec=1, pol=1 pull down

IRQ inactive IRQ active IRQ inactive

Figure 45: IRQ signal driving modes

Any IRQ event takes three system clock cycles (i.e. 30 ns at 100 MHz) being propagated from DPM internal interface part to external IRQ signals. IRQ signals are always level-oriented. The DPM interface simply propagates netX-internal IRQ levels to external IRQ signals after masking them. For clearing the IRQ signal, the requesting IRQ source has to be cleared by its mask inside DPM interface.

Important: IRQ signals are mapped to different netX 90 IO depending on whether serial or parallel DPM mode is selected, see section Pin table sorted by signals on page 239.

The two independent IRQ signals provide IRQ handling on two different priority levels on the host CPU. E.g. system status events like DPM errors or watchdog timeouts can be mapped on one IRQ signal while functional IRQs for data flow control can be mapped on the other IRQ signal. If an IRQ is generated inside netX and its related mask bit is set, the respective DPM_IRQ signal will be set. Resetting the mask will immediately change the DPM_IRQ signal from active to inactive state (3 system clocks latency).

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 82/275 5.2.5.8 Data mapping For high performance data handling netX DPM interface provides hardware endianness data mapping. Data endianness means orientation of single byte inside a 16-bit data word. Most common endianness modes are:

Little endian: The most significant byte is stored on the highest address inside the word, the least significant byte on the lowest address inside the word. Example for a 16-bit word at address A:

16-bit word at A Byte at A+0 Byte at A+1 0x5678 0x78 0x56

Big endian: The most significant byte is stored on the lowest address inside the word, the least significant byte on the highest address inside the word. Example for a 16-bit word at address A:

16-bit word at A Byte at A+0 Byte at A+1 0x5678 0x56 0x78

Note: 8-bit CPUs using bytes and byte addresses only do not require endianness mapping. netX data is 32-bit organized internally with little endian format. Data exchange with host devices with different data orientation (e. g. big endian oriented Intel CPUs) requires data mapping. netX DPM hardware supports endianness data mapping. Data width setting and endianness configuration is carried out by access to register dpm_cfg0x0. The netX DPM interface provides two data mapping modes:  netX connection to all 8-bit host devices or little endian 16-bit host device  netX connection to 16-bit big endian host device

Note: There is no relation between endianness width and DPM interface data width. E. g. it is possible to connect a 16-bit big endian host to netX by an 8-bit DPM interconnection.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 83/275 5.2.6 Serial dual-port memory interface 5.2.6.1 Overview Apart from standard parallel DPM interface modes (5.2.4) netX DPM supports a high speed serial DPM interface based on Motorola SPI (Serial Peripheral Interface). All four Motorola standard SPI frame formats are supported (SPI clock polarity 0 or 1, SPI clock phase 0 or 1). A hardware protocol converting unit inside netX DPM interface transforms serial data to netX- internal accesses.

Note: The serial DPM mode must be configured in the registers of hif_io_ctrl.

In contrast to netX 51/52, the netX 90 has two serial DPMs (DPM0_SPI and DPM1_SPI) for communication between host and netX. In addition to the 4 standard SPI signals (CLK, CSN, MISO, MOSI) netX 90 has two optional interrupt signals DIRQ and SIRQ. For Quad SPI (6 lines), signals SIO2 and SIO3 signals are available. Serial connections of netX 90 DPM interface consist of 4 standard SPI signals for data transfers. Serial mode is configured in the hif_io_ctrl registers, not in DPM registers. Clock polarity and phase can also be configured there according to the SPI mode provided by the host device used.  DPM0_SPI_... stands for serial dual-port memory 0 (SPM0)  DPM1_SPI_... stands for serial dual-port memory 1 (SPM1) Using DPM0 together with DPM1_SPI is not allowed. Using DPM0_SPI together with DPM1_SPI is allowed, but this is possible only after the deactivation of DPM0.

DPM signals Pins SPI function SQI function DPM0 DPM0_SPI_MOSI (_SIO0) HIF_D9 master out slave in data input serial data bit 0 DPM0_SPI_MISO (_SIO1) HIF_D8 master in slave out data output serial data bit 1 DPM0_SPI_CSN HIF_D10 chip-select input DPM0_SPI_CLK HIF_D11 serial clock input DPM0_SPI_DIRQ HIF_D12 optional DIRQ for host (e.g. for data IRQ) DPM0_SPI_SIRQ HIF_D13 optional SIRQ for host (e.g. for service IRQ) DPM0_SQI_SIO2 HIF_D14 - serial data bit 2 DPM0_SQI_SIO3 HIF_D15 - serial data bit 3 DPM1-signals DPM1_SPI_MOSI (_SIO0) HIF_D1 master out slave in data input serial data bit 0 DPM1_SPI_MISO (_SIO1) HIF_D0 master in slave out data output serial data bit 1 DPM1_SPI_CSN HIF_D2 chip-select input DPM1_SPI_CLK HIF_D3 serial clock input DPM1_SPI_DIRQ HIF_D4 optional DIRQ for host (e.g. for data IRQ) DPM1_SPI_SIRQ HIF_D5 optional SIRQ for host (e.g. for service IRQ) DPM1_SQI_SIO2 HIF_D6 - serial data bit 2 DPM1_SQI_SIO3 HIF_D7 - serial data bit 3 Table 20: netX 90 DPM0+1_SPI signals and DPM0+1_SQI signals

For connecting a host CPU, see reference [2].

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 84/275 5.2.6.2 Functional description (Motorola SPI introduction) SPI (Serial Peripheral Interface) is a full-duplex 4-wire interface defined by Motorola. Transfers are serial, 8-bit oriented and bidirectional between master and slaves. Slave devices are selected by a chip-select signal. Data is transferred MSB first.

Note: Motorola SPI standard does not specify 8-bit data frames. Though netX serial DPM always works byte-oriented.

Motorola SPI signals are:  SPI_CLK: Clock signal, master driven  SPI_MOSI: Master transmit, slave receive data signal, master driven  SPI_MISO: Master receive, slave transmit data signal, slave driven  SPI_CSN: Active low chip-select signal, master driven

Note: Chip-select signal is also called slave-select signal (SPI_SS or SPI_FSS). For clock signal you frequently find the abbreviation SPI_SCK.

5.2.6.2.1 Frame formats Four different Motorola SPI frame formats are provided. For netX DPM they can be configured by software.

SPI clock polarity (SPO) SPI clock polarity is the idle state of SPI clock signal SPI_CLK when no data is transferred.

SPI clock phase (SPH) SPI clock phase controls SPI data generation and sample timing. If SPH 0 is selected, data on SPI_MOSI and SPI_MISO will be sampled on the first clock edge of SPI_CLK. If SPH 1 is selected, the signal will be sampled on the second edge. Data will be generated one edge before.

SPI_MOSI read data generation To realize fast SPI_MISO generation, read data is always generated early by netX DPM interface. That means SPI_MISO is set to the state of the next bit at master sampling edge i.e. one edge before master data (SPI_MOSI) generation. This is necessary to compensate runtime latencies of SPI_CLK and SPI_MISO signal. These latencies exceed several nanoseconds. Read data on SPI_MISO will thus always be stable at the host device MISO input when the sampling clock edge is generated.

Note: SPI_MISO changes are always related to the sampling clock edge. The following figures (Figure 46 to Figure 49) show fast SPI_CLK clock behavior where the next SPI_CLK edge has been generated before SPI_MISO change propagated to the host device. For slow clock frequencies SPI_MISO state changes a short time after the sampling clock edges.

5.2.6.2.2 SPI frame format with SPO=0 and SPH=0 Clock idle state is low and data is sampled on the first (rising) edge of any SPI_CLK period. MSB data is generated when chip-select is activated. SPI_MOSI changes on the falling SPI_CLK edge.

Note: SPI_MISO generation is explained above.

SPI_CLK transfer start byte: 8 bits transfer end byte: 8 bits SPI_CS_N

SPI_MOSI MSB LSB MSB LSB

SPI_MISO MSB LSB MSB LSB

Figure 46: SPI SPO=0 and SPH=0 transfer

5.2.6.2.3 SPI frame format with SPO=0 and SPH=1 Clock idle state is low and data is sampled on the second (falling) edge of any SPI_CLK period. MSB data is generated on the first (rising) SPI_CLK edge. SPI_MOSI changes on the rising SPI_CLK edge.

Note: SPI_MISO generation is explained above.

SPI_CLK transfer start byte: 8 bits transfer end byte: 8 bits SPI_CS_N

SPI_MOSI MSB LSB MSB LSB

SPI_MISO MSB LSB MSB LSB

Figure 47: SPI SPO=0 and SPH=1 transfer

5.2.6.2.4 SPI frame format with SPO=1 and SPH=0 Clock idle state is high and data is sampled on the first (falling) edge of any SPI_CLK period. MSB data is generated when chip-select is activated. SPI_MOSI changes on the rising SPI_CLK edge.

Note: SPI_MISO generation is explained above.

SPI_CLK transfer start byte: 8 bits transfer end byte: 8 bits SPI_CS_N

SPI_MOSI MSB LSB MSB LSB

SPI_MISO MSB LSB MSB LSB

Figure 48: SPI SPO=1 and SPH=0 transfer

5.2.6.2.5 SPI frame format with SPO=1 and SPH=1 Clock idle state is high and data is sampled on the second (rising) edge of any SPI_CLK period. MSB data is generated on the first (falling) SPI_CLK edge. SPI_MOSI changes on the falling SPI_CLK edge.

Note: SPI_MISO generation is explained above.

SPI_CLK transfer start byte: 8 bits transfer end byte: 8 bits SPI_CS_N

SPI_MOSI MSB LSB MSB LSB

SPI_MISO MSB LSB MSB LSB

Figure 49: SPI SPO=1 and SPH=1 transfer

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 87/275 5.2.6.3 Serial 1-bit DPM protocol All serial DPM transfers consist of a header (3 to 5 bytes) followed by a byte-oriented address- incrementing data stream. All bytes (header and data) are serial transmitted MSB first (i.e. standard SPI). The chip-select signal must permanently remain active during an access sequence (an inactive chip-select will terminate a transfer). The transfer header always consists of a direction bit (read/not-write bit), three command (cmd) bits and a 20-bit address. The following stream type is provided (other settings for cmd are reserved and must not be used):

stream type cmd transfer length for n bytes read for n bytes write 0: straight 000 4+n 3+n All headers of a read-sequence are extended by an additional length-byte before the first data byte. This is necessary to avoid problems with read-sensitive addresses (e.g. FIFOs) as read accesses must be performed as read ahead internally. If a read sequence is not terminated after bytes, invalid read data will be returned. No read access will be performed inside netX then.

Note: Byte streams can always be performed, even if they target WBC or RDL windows. In that case, dummy cycles or ready polling inside a Dword are/is not required. This helps decrease overhead. In contrast to that, applying Dword-streams to byte areas will fail. When addressing byte areas, byte streams must be used.

MISO line will be driven as soon as chip-select is active (never floating), but the driving state is not always predictable. The current ready-state can be used for debugging or trying out access timing. During the first byte of the header the current serial DPM status) will always be clocked out on MISO. The current serial DPM status provides information on the current DPM error states and can be used if access timing is unpredictable.

1-bit SPI stream type 0: straight stream

Write access: Write until chip-select becomes idle and terminates sequence: Rd/nWr 6 CMD 4 3 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 MOSI 0 0 0 0 A[19:16] A[15:8] A[7:0] Data(A)[7:0] Data(A+1)

MISO sDPM status 0 X X X

Read access with undefined length: Read until chip-select becomes idle and terminates sequence, send 0 for length: Rd/nWr 6 CMD 4 3 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 MOSI 1 0 0 0 A[19:16] A[15:8] A[7:0] 00000000 X X

MISO sDPM status 0 X X Data(A)[7:0] Data(A+1)

Read access with length: Read ‚length’ bytes (or until chip-select becomes idle) – e.g. FIFO read: Rd/nWr 6 CMD 4 3 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 If continued after ‚length’ MOSI 1 0 0 0 A[19:16] A[15:8] A[7:0] Length[7:0] X X X X bytes access will be ignored and invalid data MISO sDPM status 0 X X Data(A)[7:0] Data(A+1) D(A+length-1) X will be returned.

X: don’t care/undefined

Figure 50: Serial DPM protocol: straight stream, type 0

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 88/275 5.2.6.4 Serial 4-bit DPM netX 90 DPM provides a 4-bit SPI (Quad-SPI, SQI) mode consisting of the 4 standard SPI signals plus 2 additional data lines. The way in which signal mapping is performed allows a default 1-bit SPI interconnection which can be switched to 4-bit. For connecting a host CPU, see reference [2]. 4-bit SQI is only half-duplex (in contrast to SPI which is full-duplex): Data uses the same lines for receive and transmit. Data can be sent or received, but not simultaneously (as it is possible with full-duplex SPI). Therefore all data lines are bidirectional. Data direction could change during one transfer (e.g. for read a command is usually sent first, then the data direction is changed and read data is received). All other SQI behavior like clock-phase, clock-polarity or chip-select is the same as standard SPI. Max. clock rate is 33 MHz which is limited by netX-internal access times and not by IO-timing.

5.2.6.4.1 SQI frame formats SQI needs only 2 clock periods to transfer one byte (as there are 4 data lines). Data is organized MSB-first like standard SPI. Figure 51 shows this for serial mode 0 (clock polarity is low and master generating clock-phase is 0).

SQI_CLK

SQI_CSN

SQI_SIO3 bit7 bit3 bit7 bit3 bit7 bit3 bit3

SQI_SIO2 bit6 bit2 bit6 bit2 bit6 bit2 bit2

SQI_SIO1 bit5 bit1 bit5 bit1 bit5 bit1 bit1

SQI_SIO0 bit4 bit0 bit4 bit0 bit4 bit0 bit0 2 byte master to slave data 1 dummy byte slave to master data driven by master non-driven driven by slave (command write) (turnaround) (read) Figure 51: Serial mode 0 QSPI frame format example

Note: Due to latencies of clock signal and data generating logic inside slave device, slave- driven data typically appears later on external lines as master-driven data. Slave data must be valid before the next sampling clock edge.

Due to SPI mode 0 clock idle state is low. The first data is generated when chip-select is activated, all further data is generated by the falling clock edges of any clock period. Data is sampled (received) on each rising clock edge.

Note: Relation between clock polarity/phase and data generation/sampling is the same for SPI and SQI. For details, see the description of the SPI frame formats.

Due to half-duplex character of SQI a transfer typically is started by a command sent by master (the first 2 bytes in the example of Figure 51). This informs the slave about the further data direction i.e. whether it is a read or a write transfer. In case of a read transfer (as shown by Figure 51) a turnaround dummy byte is typically inserted before the slave starts driving read data to avoid collisions on data lines (which could cause permanent hardware damage).

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 89/275 5.2.6.4.2 Serial 4-bit DPM protocol The serial 4-bit DPM protocol is very similar to the 1-bit serial DPM protocol. However, the half- duplex character of SQI causes some differences:  DPM status cannot be returned at the first transfer-byte for 4-bit serial DPM. A special status read can be performed instead. A new stream type needing only a 1-byte header is provided therefore.  A turnaround-byte is inserted for read-transfers between header and first byte of read data to avoid collisions on data lines. The following issues are identical for both protocols:  All data is transferred MSB first.  Chip-select signal must remain active all time during a transfer (inactive chip-select will terminate it).  All data transfers (not status read stream) start with a header (3 to 5 bytes) followed by a byte-oriented address-incrementing data stream. The transfer header always consists of a direction bit (read/not write bit), three command (cmd) bits, and a 20-bit address. Headers of read transfers are extended by a length byte before the first data byte. The following stream type is provided (other settings for cmd are reserved and must not be used):

stream type cmd transfer length for n bytes read for n bytes write 0: straight 000 5+n 3+n

5.2.6.4.3 4-bit serial DPM stream type 0: Straight stream 4-bit serial DPM straight stream is similar to 1-bit serial DPM straight stream, but a non-driven turnaround byte is inserted between header and data for read and serial status cannot be returned (due to half-duplex character).

Write access: Write until chip-select becomes idle and terminates sequence: Rd/nWr 6 CMD 4 3 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 SIO 0 0 0 0 A[19:16] A[15:8] A[7:0] Data(A)[7:0] Data(A+1)

driver host

Read access with undefined length: Read until chip-select becomes idle and terminates sequence, send 0 for length: Rd/nWr 6 CMD 4 3 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 SIO 1 0 0 0 A[19:16] A[15:8] A[7:0] 00000000 turnaround Data(A)[7:0] Data(A+1)

driver host non netX If continued after ‚length’ Read access with length: Read ‚length’ bytes (or until chip-select becomes idle) – e.g. FIFO read: bytes access will be Rd/nWr 6 CMD 4 3 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 7 ... 0 ignored and invalid data SIO 1 0 0 0 A[19:16] A[15:8] A[7:0] Length[7:0] dummy Data(A)[7:0] Data(A+1) D(A+length-1) X will be returned.

driver host non netX

X: don’t care/undefined

Figure 52: SQI Serial DPM protocol: straight stream, type 0

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 90/275 5.2.7 Handshake registers To allow the synchronization of the data transfer between host system and netX (com-side), a total of 16 handshake cell pairs with interrupt capability are available. Handshake cells can be 8 or 16- bit wide and are thus available for all selectable DPM bus widths. A cell pair is always located inside a 32-bit DWORD. While both cells of a pair can always be read by host and netX, the upper cell of the pair can only be written by the host and the lower cell can only be written by the netX. In 8-bit mode the lower 16 bits of the 32-bit DWORD behave like a standard SRAM.

32-bit area of a 16-bit Handshake cell pair 31 16 15 0 DPM write data netX write data netX read-only DPM read-only

32-bit area of a 8-bit Handshake cell pair 31 24 23 16 15 0 DPM write data netX write data RAM area netX read-only DPM read-only

Figure 53: Handshake cell DWORD

Writing to a handshake cell from the host side can generate an interrupt to the netX side. Writing from the netX side can generate an interrupt to the host (by the signals DPM_DIRQ or DPM_SIRQ). After receiving an interrupt the processor (host CPU resp. netX) will read the changed data of the IRQ generating cell. This will automatically clear the IRQ. Before reading the changed data, the IRQ generating cell must be determined by the status registers of the handshake_ctrl unit or for host CPUs additionally by the firmware_irq registers of DPM configuration and status window 0. An interrupt vector and a status flag for each handshake cell are available there.

Note: Instead of reading the cell, a handshake IRQ can also be cleared by writing ‘1’ to the flag bit.

ARM

(clears IRQ) (generates IRQ) read write Handshake cell pair 31 16 15 0 high word low word IRQ (Host to netX) (netX to Host) IRQ R/W for host, Read only for ARM R/W for ARM, Read only for host

(generates IRQ) (clears IRQ) netX write read

Host

Figure 54: Handshake cell dataflow (16-bit)

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 91/275 Handshake cells must be configured in the HANDSHAKE_CTRL unit. Each handshake cell pair can be enabled individually. The width (8 or 16-bit) can be programmed for each pair separately.

Note: There is no default handshake cell mapping after a power-on reset, i.e. the netX firmware must configure the desired handshake cells before they can be used.

The handshake cells are physically located in the internal netX memory intramhs. Intramhs (32 KB for netX 90) is dedicated to the data exchange between netX and host. Due to this, intramhs is typically mapped to external DPM address space and available for a host. The location of the 16 handshake cell pairs inside intramhs can be programmed to any 256 byte offset (bit-field base256 of register handshake_base_addr of handshake_ctrl area). The address offset inside intramhs for handshake cell N is: 8-bit cell pair Host  netX: handshake cell offset = 256*base256 + 4*N + 3 netX  Host: handshake cell offset = 256*base256 + 4*N + 2 16-bit cell pair Host  netX: handshake cell offset = 256*base256 + 4*N + 2 netX  Host: handshake cell offset = 256*base256 + 4*N + 0

Note: If a cell pair is not enabled, the related DWORD behaves like a standard SRAM. All bytes can be written by ARM (com-side) and host then.

Note: An 8-bit or serial DPM typically requires 8-bit handshake cells as otherwise two access operations are needed to read or write 16-bit cells. However, if Read-Data-Latching (RDL) and Write-Byte-Collecting (WBC) of the DPM module are used, 8-bit or serial DPM can also behave like a 32-bit interface.

Handshake IRQs are set and cleared by a special logic which monitors any access to intramhs. If a write access to the address of an enabled cell is detected, an IRQ will be generated. If a read access is detected, an IRQ will be cleared.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 92/275 The selection of the correct IRQ target for setting or clearing an IRQ is not directly derived from the component (ARM com-side or host) which initiated an access. Instead of deriving it directly, there are several mirrors of intramhs netX inside, at least one for each IRQ target. An access to intramhs via one of these mirrors behaves like the related component which initiated the access.

Important: The IRQ target of the handshake cell access is derived only from the intramhs mirror used. E.g. if ARM (com-side) uses a DPM mirror of intramhs, IRQs will be generated as if DPM initiated the access. If DPM uses an ARM mirror, IRQs behave as if ARM initiated the access. This could be used during development e.g. to test host functions on the ARM. Usually the ARM should use ARM mirrors and the host should use DPM mirrors for handshake cell access.

netX internal address space 0xFFFFFFFF IRQs to DPM IRQs to ARM

Logic for INTRAMHS handshake ARM-mirror cell access monitoring INTRAMHS and IRQ DPM-mirror generation physical INTRAMHS: 32 kB INTRAMHS 32 bit wide straight-mirror 0x7FFF

HANDSHAKE_CTRL Handshake Cell pair 15 HSC configuration registers Handshake Cell pair 14 HSC configuration Handshake Cell pair 2 IRQ ctrl and status Handshake Cell pair 1 Offset inside INTRAMHS Handshake Cell pair 0 programmable address offset: n x 0x100

INTRAMHS 0x0000

INTRAM8

INTRAM0

0x00000000

Figure 55: Handshake cell monitoring of intramhs

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 93/275 5.2.8 Parallel dual-port memory timing The difference between SRAM modes and Intel or Motorola modes is that SRAM modes have 2 dedicated enable signals for read and write (DPM_RDn and DPM_WRn) while Intel or Motorola modes have only 1 direction signal (located on DPM_RDn). The direction modes require byte strobe signals which become active when all other signals are already valid and stable. All other signals (with the exception of read-data and ready) must remain stable until the byte strobes become inactive at access end. For SRAM modes byte enables have address character and must be valid before the activation of read enable or the deactivation of write enable. In multiplexed mode an additional signal DPM_ALE (Address-Latch, Address-Enable) flags the state of multiplexed address/data bus. Address part multiplexed on data lines must be valid around the change from address to data phase. Only the data phase will be extended by setting DPM_RDY to wait state. Then address phase will never be extended.

Note: The ready signal is optional only. If used, it will always become active for read access. For write it will be set only if the internal part of the DPM interface is busy.

Note: Polarity and IO mapping of signal DPM_ALE is programmable by the bits aen_sel and aen_pol of register dpm_if_cfg.

5.2.8.1 SRAM modes with separated read and write enable signals This section is dedicated to the following modes:  INTEL_8BIT_SRAM  INTEL_16BIT_SRAM  TIOMAP_16BIT_NON_MULTIPLEXED

Note: Byte enable signals (DPM_BE signals) have address character for SRAM modes. They are treated like address lines here. Byte enables can be selected by register dpm_if_cfg.be_sel.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 94/275 5.2.8.1.1 SRAM mode read access DPM read accesses can be read or chip-select signal controlled. Moreover, netX 90 DPM supports read bursts without the necessity of read or chip-select signal toggling between each access.

DPM_A, Address n Address m DPM_BE tASr tASr DPM_CSn tAHr

tRDI DPM_RDn

DPM_WRn

tDHr tAC tDLZ tDLZ DPM_D Data(Address n)

tRA tDVR tDHZ tRA DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive drive active

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z drive active

tRHZm03 tRLZ tRLZ mode 3 High Z drive active High Z drive active

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 56: Detailed timing of DPM SRAM mode read access DPM_RDn controlled

DPM_A, Address n Address m DPM_BE tASr tAHr tASr DPM_CSn

tRDI DPM_RDn

DPM_WRn

tDHr tAC tDLZ tDLZ DPM_D Data(Address n)

tRA tDVR tDHZ tRA DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive drive active

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z drive active

tRHZm03 tRLZ tRLZ mode 3 High Z drive active High Z drive active

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 57: Detailed timing of DPM SRAM mode read access DPM_CSn controlled.

DPM_A, Address n const Address m DPM_BE tASr tACHGB DPM_CSn

DPM_RDn

DPM_WRn

tAC tDHr tAC tDLZ DPM_D Data(Address n) Data(Address m)

tRA tDVR tRArb tDVR DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive drive active drive inactive

DPM_RDY (ack) tRHrb mode 1 drive inactive drive active drive inactive drive active

Figure 58: Detailed timing of DPM read burst access (DPM_A or DPM_DQM change without DPM_CSn or DPM_RDn toggling)

Note: Read burst support must be enabled by programming register dpm_timing_cfg.

Note: Since undriven idle states of ready drive modes 2 and 3 are too slow for read bursts, they are omitted in Figure 58.

Time tACHGB is the maximum time of stable addresses, but invalid addresses occur on the address bus when burst addresses change.

5.2.8.1.2 SRAM mode write access DPM write cycles always end with a positive edge of active low DPM write signal (DPM_WRn).

DPM_A, Address n DPM_BE tASw tAHw DPM_CSn

tCSHw DPM_RDn

tWC DPM_WRn

tWRI tDSw tDHw DPM_D Data(Address n)

DPM_RDY (busy)

mode 1 drive inactive

mode 2 High Z

mode 3 High Z

DPM_RDY (ack) tRA tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRLZ tRHZm13 mode 3 High Z drive active High Z

Figure 59: Detailed timing of DPM SRAM mode write access when internal netX DPM side is idle (no insertion of wait cycles)

After the end of an external write access (positive edge of signal DPM_WRn) the internal access to the netX address area will start. If a new external DPM write access is initiated before the internal write access is finished, external wait cycles will be inserted by setting the signal DPM_RDY.

DPM_A, Address n DPM_BE tASw tAHw DPM_CSn

DPM_RDn

tCSHw DPM_WRn

tWRI tDSw tDHw DPM_D Data(Address n)

tWWP tRWE tRA DPM_RDY (busy) tRA mode 1 drive inactive drive active drive inactive drive active

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z drive active

tRLZ tRHZm03 tRLZ mode 3 High Z drive active High Z drive active

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 60: Detailed timing of DPM SRAM mode write access when internal netX DPM side busy (insertion of wait cycles)

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 98/275 5.2.8.2 Multiplexed SRAM modes with separated read and write enable signals This section is dedicated to the following modes:  INTEL_8BIT_MULTIPLEXED  INTEL_16BIT_MUL_2BE_BYTE_ADDR (SRAM-like with 2 byte enables)  INTEL_16BIT_MUL_2BE_WORD_ADDR (SRAM-like with 2 BEs and shifted address)  INTEL_16BIT_MUL_NO_BES (no byte enables, for netX 50-compatibility)  TIOMAP_16BIT_MULTIPLEXED

Note: Mode naming comes from the netX 51/52 documentation, but “INTEL” modes are rather SRAM-like modes there. The difference between SRAM modes and Intel modes is that SRAM modes have 2 dedicated enable signals for read and write (DPM_RDn and DPM_WRn) while Intel modes have only 1 direction signal (located on DPM_RDn). The Intel modes require byte strobe signals at least for write. They must become active after direction signal DPM_RDn is valid and stable. DPM_RDn must remain stable until the byte strobes become inactive at the end of access. For SRAM modes byte enables have address character and must be valid before activating read enable or deactivating write enable.

Note: For multiplexed Intel-like modes with byte strobes, see section 5.2.8.4.

Note: Byte enable signals (DPM_BE signals) have address character for multiplexed SRAM modes, but they are always available on dedicated signals (i.e. they are not part of the multiplexed address on the A/D-bus). They are treated similar to the high address lines here. Byte enables can be selected by register dpm_if_cfg.be_sel.

5.2.8.2.1 Multiplexed SRAM mode read access In multiplexed mode read bursts are not supported. The read enable signal must become inactive between subsequent access operations.

DPM_CSn tCSSm

DPM_RDn

DPM_WRn

tASr tAHr DPM_BE valid

tALEact tALEDS tALEDH DPM_ALE address phase data phase a.p.

tDAS tDAH tRDI DPM_A[high] high Address n

tDHr tDAS tDAH tAC DPM_D tDLZ low Address n Data(Address n) (A/D bus)

tRA tDVR tDHZ DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z

tRHZm03 tRLZ mode 3 High Z drive active High Z

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 61: Detailed timing of multiplexed SRAM mode read access

The address phase could also overlap with the read active phase, i.e. DPM_ALE could remain in address phase state while DPM_RDn is already set to active. However, the data phase never starts before DPM_ALE changes to data state, i.e. ready and read data will never be driven while DPM_ALE is in the address state. However, the host must make sure that the addresses are not driven too long for read access. Otherwise netX will drive read data against addresses driven by the host.

Important: If the address phase overlaps with the read active phase, the address hold time tDAH must be shorter than the read data enable time tDLZ to avoid damage to netX or host.

DPM_CSn

DPM_RDn

DPM_WRn

tAHr DPM_BE valid

tALEact tALEDH DPM_ALE address phase data phase a.p.

tDAS tDAH tRDI DPM_A[high] high Address n

tDHr tDAS tDLZ tAC DPM_D tDAH low Address n Data(Address n) (A/D bus)

tRA tDVR tDHZ DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z

tRHZm03 tRLZ mode 3 High Z drive active High Z

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 62: Detailed timing of multiplexed SRAM mode read access with address phase overlapping into read-active phase

5.2.8.2.2 Multiplexed SRAM mode write access DPM write cycles always end with a positive edge of an active low DPM write signal (DPM_WRn).

DPM_CSn tCSSm tCSHw

DPM_RDn

tWC DPM_WRn

tASr tAHr DPM_BE valid

tALEact tALEDS tALEDH DPM_ALE address phase data phase addr.ph.

tWRI tDAS tDAH DPM_A[high] low Address n h.a.

tDAS tDAH tDSw tDHw DPM_D low Address n Data(Address n) l.a. (A/D bus)

DPM_RDY (busy)

mode 1 drive inactive

mode 2 High Z

mode 3 High Z

DPM_RDY (ack) tRA tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRLZ tRHZm13 mode 3 High Z drive active High Z

Figure 63: Detailed timing of multiplexed SRAM mode write access when internal netX DPM side is idle (no insertion of wait cycles)

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 102/275 The internal access to the netX address area will starts after the end of an external write access (positive edge of DPM_WRn signal). If a new external DPM write access is initiated before the internal write access is finished, external wait cycles will be inserted by setting signal DPM_RDY during the data phase.

DPM_CSn tCSSm tCSHw

DPM_RDn

DPM_WRn

tASr tAHr DPM_BE valid

tALEact tALEDS tALEDH DPM_ALE address phase data phase addr.ph.

tDAS tDAH tWRI DPM_A[high] low Address n h.a.

tDAS tDAH tDSw tDHw DPM_D low Address n Data(Address n) l.a. (A/D bus)

tWWP tRWE DPM_RDY (busy) tRA mode 1 drive inactive drive active drive inactive

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z

tRLZ tRHZm03 mode 3 High Z drive active High Z

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 64: Detailed timing of multiplexed SRAM mode write access when internal netX DPM side busy (insertion of wait cycles)

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 103/275 The address phase could also overlap with the write-active phase, i.e. DPM_ALE could remain in the address phase state while DPM_WRn is already set to active. However, the data phase never starts before DPM_ALE changes to data state, i.e. ready will never be driven while DPM_ALE is in the address state.

DPM_CSn tCSHw

DPM_RDn

DPM_WRn

tAHr DPM_BE valid

tALEact tALEDH DPM_ALE address phase data phase addr.ph.

tDAS tDAH tWRI DPM_A[high] low Address n h.a.

tDAS tDAH tDSw tDHw DPM_D low Address n Data(Address n) l.a. (A/D bus)

tWWP tRWE DPM_RDY (busy) tRA mode 1 drive inactive drive active drive inactive

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z

tRLZ tRHZm03 mode 3 High Z drive active High Z

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 65: Detailed timing of multiplexed SRAM mode write access with address phase overlapping into write-active phase

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 104/275 5.2.8.3 Intel-like modes with data direction byte strobe signals (byte writes) This section is dedicated to the following mode: INTEL_16BIT_BYTE_WRITE (read is not using byte enables) Byte enable signals (DPM_BE signals) have strobe character for Intel-like modes i.e. are byte strobes here. They must become active after the direction signal DPM_RDn is already valid and stable. To avoid an illegal data direction change, DPM_RDn must not change before the byte strobes become inactive at access end.

Important: Intel-like microprocessor interfaces often provide separated byte enable (or byte strobe) signals for read and write (i.e. byte write enable lines and byte read enable lines). This is not supported by netX DPM. It is recommended to connect byte write lines to netX DPM byte enables and to disable byte enables for read by programming bit be_rd_dis of register dpm_if_cfg to 1 (5.2.8.3.2). Byte write access will be possible while read access will always deliver data of the full programmed data bus width (by bits dpm_cfg0x0.mode). Observe the RDL and WBC rules.

Note: Byte strobe signals (on DPM_BE signals) can be selected using register dpm_if_cfg.be_sel.

Note: The address enable signal could also be used in non-multiplexed Intel modes, but this is unlikely. When used it must behave like an additional chip-select. Both signals, chip- select and address enable, must be active during an access.

5.2.8.3.1 Intel-like mode read access using byte enables A read access using byte enables is started when byte enables (byte enable controlled) or chip- select (chip-select controlled) signals become active at access start. Address and data direction (RDn) signals must be stable then.

Note: Access detection will wait for stable byte enables of at least 1 netX system clock cycle at access start (tBEchg). This could be extended using the programmable tOSA timing parameter. Further changes of the byte enable signals will be ignored during the access until they all become inactive. The access is terminated as soon as all byte enables have returned to inactive state.

DPM_A Address n Address m

tASr tAHr tASr DPM_CSn tRDnH tRDnS tRDnS DPM_RDn

tBEchg tRDI tBEchg DPM_BE inactive active inactive active

tDHr tAC tDLZ tDLZ DPM_D Data(Address n)

tRA tDVR tDHZ tRA DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive drive active

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z drive active

tRHZm03 tRLZ tRLZ mode 3 High Z drive active High Z drive active

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 66: Detailed timing of an Intel-like byte enable controlled read access

DPM_A Address n Address m

tASr tAHr tASr DPM_CSn tRDI tRDnS DPM_RDn tRDnH tRDnS

tBESr tBEHr DPM_BE active active

tDHr tAC tDLZ tDLZ DPM_D Data(Address n)

tRA tDVR tDHZ tRA DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive drive active

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z drive active

tRHZm03 tRLZ tRLZ mode 3 High Z drive active High Z drive active

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 67: Detailed timing of an Intel-like chip-select controlled read access with read byte enables

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 106/275 5.2.8.3.2 Intel-like mode read access not using byte enables Read byte enables can be ignored by programming bit be_rd_dis of register dpm_if_cfg to 1 (e.g. to support interconnection with separated byte enables for read and write). A read access starts if RDn and chip-select signal becomes low at access start. Address lines must be stable then.

Note: Figure 68 shows Intel-like read access controlled by chip-select or RDn which can be used instead of Intel-like read access with byte enables. However, at least one of those two signals must become inactive between access operations. The idle time tRDI is the time when at least one signal is inactive.

DPM_A Address n Address m

tASr tAHr tASr DPM_CSn

tRDI DPM_RDn

DPM_BE

tDHr tAC tDLZ tDLZ DPM_D Data(Address n)

tRA tDVR tDHZ tRA DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive drive active

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z drive active

tRHZm03 tRLZ tRLZ mode 3 High Z drive active High Z drive active

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 68: Detailed timing of an Intel-like read access not using read byte enables

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 107/275 5.2.8.3.3 Intel-like mode write access A write access is performed when byte enables become inactive at access end. Address, chip- select, data and RDn signals must be stable then.

Note: Byte enables are always required for write in Intel mode. Disabling them by programming bit be_wr_dis of register dpm_if_cfg to 1 is not allowed.

DPM_A Address n

tASw tAHw DPM_CSn

DPM_RDn tRDnH tRDnS

tRDnS DPM_BE inactive active inactive active

tWRI tDSw tDHw DPM_D Data(Address n)

tWWP tRWE tRA DPM_RDY (busy) tRA mode 1 drive inactive drive active drive inactive drive active

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z drive active

tRLZ tRHZm03 tRLZ mode 3 High Z drive active High Z drive active

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 69: Detailed timing of an Intel-like write access with write byte enables

Note: For write, wait phase occurs only if DPM is busy internally. Acknowledge is always generated when DPM_RDY is in acknowledge mode (ack). This is similar to normal SRAM mode (Figure 59 and Figure 60).

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 108/275 5.2.8.4 Intel-like multiplexed modes with data direction byte strobe signals This section is dedicated to the following modes:  INTEL_16BIT_MUL_BYTE_ADDR  INTEL_16BIT_MUL_BYTE_WRITE

Note: The multiplexed 8-bit Intel mode (INTEL_8BIT_MULTIPLEXED) and the netX 50/51/52- compatible multiplexed 16-bit Intel mode without byte enables (INTEL_16BIT_MUL_NO_BES) are rather multiplexed SRAM modes. To avoid confusion by mode naming, see the beginning of section 5.2.8.2.

Byte enable signals (DPM_BE signals) have strobe character for multiplexed Intel-like modes i.e. are byte strobes here. They must become active after the direction signal DPM_RDn is already valid and stable. To avoid an illegal data direction change, DPM_RDn must not change before the byte strobes become inactive at access end.

Note: Byte strobe signals (on DPM_BE signals) are always available on dedicated signals for multiplexed Intel modes (i.e. are not part of the multiplexed address on the A/D-bus). They can be selected by register dpm_if_cfg.be_sel.

5.2.8.4.1 Intel-like multiplexed mode read access using byte enable

tCSHw DPM_CSn tCSSm

tRDnS tRDnH DPM_RDn

tBEchg DPM_BE inactive active inactive

tALEact tALEDS tRDI DPM_ALE address phase data phase addr.ph.

tDAS tDAH tALEDH DPM_A[high] high Address n h. a.

tDHr tDAS tDAH tAC DPM_D tDLZ low Address n Data(Address n) l.a. (A/D bus)

tRA tDVR tDHZ DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z

tRHZm03 tRLZ mode 3 High Z drive active High Z

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 70: Detailed timing of an Intel-like multiplexed mode read access netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 109/275 The address phase could also overlap with the read-active phase, i.e. DPM_ALE could remain in address phase state while DPM_RDn and byte enables are already set to active. However, the data phase never starts before DPM_ALE changes to data state, i.e. ready and read data will never be driven while DPM_ALE is in address state. The host must make sure that the addresses are not driven too long for read access. Otherwise netX will drive read data against addresses driven by the host.

Important: If the address phase overlaps with the read-active phase, the address hold time tDAH must be shorter than the read-data-enable time tDLZ to prevent damage to netX or host.

tCSHw DPM_CSn

tRDnH DPM_RDn

DPM_BE inactive active inactive

tALEact tRDI DPM_ALE address phase data phase addr.ph.

tDAS tDAH tALEDH DPM_A[high] high Address n h. a.

tDHr tDLZ tAC DPM_D low Address n Data(Address n) l.a. (A/D bus) tDAS tDAH tRA tDVR tDHZ DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z

tRHZm03 tRLZ mode 3 High Z drive active High Z

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 71: Detailed timing of an Intel-like multiplexed mode read access with address phase overlapping with read-active phase

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 110/275 5.2.8.4.2 Intel-like multiplexed mode read access not using byte enable Read byte enables can be ignored by programming bit be_rd_dis of register dpm_if_cfg to 1 (e.g. to support interconnection with separated byte enables for read and write). A read access is started then when RDn and chip-select signal become low at access start. Address lines must be stable then.

Note: Figure 72 shows Intel-like read access controlled by chip-select or RDn which can be used instead of Intel-like read access with byte enables. However, at least one of those two signals must become inactive between access operations. The idle time tRDI is the time when at least one signal is inactive.

tCSHw DPM_CSn tCSSm

DPM_RDn

DPM_BE

tALEact tALEDS tRDI DPM_ALE address phase data phase addr.ph.

tDAS tDAH tALEDH DPM_A[high] high Address n h. a.

tDHr tDAS tDAH tAC DPM_D tDLZ low Address n Data(Address n) l.a. (A/D bus)

tRA tDVR tDHZ DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z

tRHZm03 tRLZ mode 3 High Z drive active High Z

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 72: Detailed timing of an Intel-like multiplexed mode read access without byte enables

Note: If byte enables are ignored, the address phase could also overlap with the read-active phase. This is similar to Figure 71.

DPM_CSn tCSSm tCSHw

tRDnS tRDnH DPM_RDn

tBEchg DPM_BE inactive active inactive

tALEact tALEDS tWRI DPM_ALE address phase data phase addr.ph.

tDAS tDAH tALEDH DPM_A[high] high Address n h. a.

tDAS tDAH tDSw tDHw DPM_D low Address n Data(Address n) l. a. (A/D bus)

tWWP tRWE DPM_RDY (busy) tRA mode 1 drive inactive drive active drive inactive

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z

tRLZ tRHZm03 mode 3 High Z drive active High Z

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 73: Detailed timing of an Intel-like multiplexed mode write access when internal netX DPM side busy (insertion of wait cycles)

Note: Also for write address phase could overlap with write-active phase. This is similar to Figure 71.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 112/275 5.2.8.5 Motorola-like modes with data direction byte strobe signals This section is dedicated to the following modes:  MOTOROLA_16BIT  MOTOROLA_16BIT_68000  MOTOROLA_8BIT_6800

Byte enable signals (DPM_BE signals) have strobe character for Motorola-like modes i.e. are byte strobes here. They must become active after the direction signal DPM_RDn is already valid and stable. To avoid an illegal data direction change, DPM_RDn must not change before the byte strobes become inactive at access end.

Note: Byte strobe signals (on DPM_BE signals) can be selected by register dpm_if_cfg.be_sel.

Note: The address enable signal is not mandatory. It could be used e.g. for Motorola 68000.

Note: Motorola 6800 is 8-bit with byte enable.

5.2.8.5.1 Motorola-like mode read access A read access starts when byte enables (byte enable controlled) or chip-select (chip-select controlled) signals become active at access start. Address and data direction (RDn) signals must be stable then.

Note: Byte enables are always required for read in Motorola mode. Disabling them by programming bit be_rd_dis of register dpm_if_cfg to 1 is not allowed.

Note: Access detection will wait for stable byte enables of at least 1 netX system clock cycle at access start (tBEchg). This could be extended using the programmable tOSA timing parameter. Further changes of the byte enable signals will be ignored during access until they all become inactive. When all byte enables return to inactive state, access is terminated.

DPM_A Address n Address m

tASr tAHr tASr

DPM_AEn active active

tAES tAEH tAES

DPM_BE inactive active inactive active

tBEchg tRDI tBEchg DPM_CSn tRDnH tRDnS tRDnS DPM_RDn

tDHr tAC tDLZ tDLZ DPM_D Data(Address n)

tRA tDVR tDHZ tRA DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive drive active

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z drive active

tRHZm03 tRLZ tRLZ mode 3 High Z drive active High Z drive active

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 74: Detailed timing of a Motorola-like byte enable controlled read access

DPM_A Address n Address m

tASr tAHr tASr

DPM_AEn active active

tAES tAEH tAES

DPM_BE active active

tBESr tBEHr tRDI DPM_CSn tRDnH tRDnS tRDnS DPM_RDn

tDHr tAC tDLZ tDLZ DPM_D Data(Address n)

tRA tDVR tDHZ tRA DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive drive active

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z drive active

tRHZm03 tRLZ tRLZ mode 3 High Z drive active High Z drive active

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 75: Detailed timing of a Motorola-like chip-select controlled read access netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 114/275 5.2.8.5.2 Motorola-like mode write access A write access is performed when byte enables become inactive at access end. Address, chip- select, data and RDn signals must be stable then.

DPM_A Address n

tASw tAHw

DPM_AEn active active

DPM_BE inactive active inactive active

tWRI DPM_CSn

DPM_RDn tRDnH tRDnS

tRDnS tDSw tDHw DPM_D Data(Address n)

tWWP tRWE tRA DPM_RDY (busy) tRA mode 1 drive inactive drive active drive inactive drive active

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z drive active

tRLZ tRHZm03 tRLZ mode 3 High Z drive active High Z drive active

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 76: Detailed timing of a Motorola-like write access with write byte enables

Note: Write byte enables could be ignored by programming bit be_wr_dis of register dpm_if_cfg to 1 for Motorola mode (e.g. to support interconnection with separated byte enables for read and write). Write data is stored at the positive edge of RDn in this case. All other DPM input signals must be valid and stable then.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 115/275 5.2.8.6 Motorola-like multiplexed modes with data direction byte strobe signals This section is dedicated to the following modes:  MOTOROLA_8BIT_MULTIPLEXED  MOTOROLA_16BIT_MUL_BYTE_ADDR  MOTOROLA_16BIT_MUL_WORD_ADDR

Byte enable signals (DPM_BE signals) have strobe character for multiplexed Motorola-like modes i.e. are byte strobes here. They must become active after the direction signal DPM_RDn is already valid and stable. To avoid an illegal data direction change, DPM_RDn must not change before the byte strobes become inactive at access end.

Note: Byte strobe signals (on DPM_BE signals) are always available on dedicated signals for multiplexed Motorola modes (i.e. are not part of the multiplexed address on the A/D- bus). They can be selected by register dpm_if_cfg.be_sel.

5.2.8.6.1 Motorola-like multiplexed mode read access

tCSHw DPM_CSn tCSSm

tRDnS tRDnH DPM_RDn

tBEchg DPM_BE inactive active inactive

tALEact tALEDS tRDI DPM_ALE address phase data phase addr.ph.

tDAS tDAH tALEDH DPM_A[high] high Address n h. a.

tDHr tDAS tDAH tAC DPM_D tDLZ low Address n Data(Address n) l.a. (A/D bus)

tRA tDVR tDHZ DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z

tRHZm03 tRLZ mode 3 High Z drive active High Z

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 77: Detailed timing of a Motorola-like multiplexed mode read access

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 116/275 The address phase could also overlap into read-active phase, i.e. DPM_ALE could remain in address phase state while DPM_RDn and byte enables are already set to active. However, the data phase never starts before DPM_ALE changes to data state, i.e. ready and read data will never be driven while DPM_ALE is in the address state. The host must make sure that the addresses are not driven too long for read access. Otherwise netX will drive read data against addresses driven by host.

Important: If the address phase overlaps with the read-active phase address, the hold time tDAH must be shorter than the read data enable time tDLZ to prevent damage to netX or host.

tCSHw DPM_CSn

tRDnH DPM_RDn

DPM_BE inactive active inactive

tALEact tRDI DPM_ALE address phase data phase addr.ph.

tDAS tDAH tALEDH DPM_A[high] high Address n h. a.

tDHr tDLZ tAC DPM_D low Address n Data(Address n) l.a. (A/D bus) tDAS tDAH tRA tDVR tDHZ DPM_RDY (busy)

mode 1 drive inactive drive active drive inactive

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z

tRHZm03 tRLZ mode 3 High Z drive active High Z

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 78: Detailed timing of a Motorola-like multiplexed mode read access with address phase overlapping with read- active phase

5.2.8.6.2 Motorola-like multiplexed mode write access

DPM_CSn tCSSm tCSHw

DPM_RDn tRDnS tRDnH

tBEchg DPM_BE inactive active inactive

tALEact tALEDS tWRI DPM_ALE address phase data phase addr.ph.

tDAS tDAH tALEDH DPM_A[high] high Address n h. a.

tDAS tDAH tDSw tDHw DPM_D low Address n Data(Address n) l. a. (A/D bus)

tWWP tRWE DPM_RDY (busy) tRA mode 1 drive inactive drive active drive inactive

tRPm02 tRHZm02 drive mode 2 High Z drive active inactive High Z

tRLZ tRHZm03 mode 3 High Z drive active High Z

DPM_RDY (ack) tRH mode 1 drive inactive drive active drive inactive

tRHZm12 tRPm12

drive mode 2 High Z drive active inactive High Z

tRHZm13 mode 3 High Z drive active High Z

Figure 79: Detailed timing of an Intel-like multiplexed mode write access when internal netX DPM side busy (insertion of wait cycles).

Note: Also for write address phase could overlap with the write-active phase. This is similar to Figure 78.

Configurable timing parameters IO timings are derived from

Symbol Parameter Min Typ Max Unit 1) tsys Main system clock period 10.0 ns 2) tOSA Programmable DPM address setup time parameter 0.0 3tsys ns 2) tRDS Programmable DPM read data setup time parameter 0.0 7tsys ns 2) tf Delay time of programmable input signal filter ns filtering disabled 0.0 0.0

filtering enabled tsys tsys

Notes

1. tsys is a netX-internal system clock period (by default 10.0 ns). The system clock period affects DPM IO timing since sample and output register stages run on this clock. The system clock speed could be decreased (e.g. for power-down) by configuration registers in the netX asic_ctrl address area 2. Configurable by register dpm_timing_cfg.

Standard timing parameters The following standard timing parameters can be applied for SRAM mode and access to netX address areas without wait states (i.e. intram, handshake cells, DPM configuration, and status window 0). They are valid for normal netX operation (i.e. a netX running with 100 MHz system clock which is not stepped down). For all other cases the more complex general timing parameters (provided below) must be applied.

Symbol Parameter Min Max Unit

tASr Address setup time (read cycle) 2.9 ns 1)2) 2.9-tOSA

tAHr Address hold time (read cycle) 0.0 ns

tASw Address setup time (write cycle) 12.8 ns 1) tf+12.8

tAHw Address hold time (write cycle) 2.9 ns

tAES Address enable setup time 0 ns

tAEH Address enable hold time 0 ns

tDSw Data setup time (write cycle) 12.8 ns 1) tf+12.8

tDHr Data hold time (read cycle) 2.1 ns

tDHw Data hold time (write cycle) 2.8 ns

tDLZ Data enable low-Z time (read cycle) 5.7 ns 1) tOSA+tf+5.7

tDHZ Data high-Z time (read cycle) 4.9 ns

tAC Access time (read cycle) 55.0 ns 1) 55.0+ tOSA+tf

tRDI Read inter access idle time 12.5 ns 1) tWRI Write inter access idle time tf+12.5

tWC Write cycle time 12.5 ns 1) tf+12.5

tCSHw Chip-select hold time (write cycle) 0.0 ns

tWWP Write access wait phase 0.0 ns

tRWE Ready to write cycle end time 0.0 ns

Notes 1. This time is influenced by a DPM timing setting that can be programmed by software (5.2.5.5 and first table of this section).

2. The read address setup time can be decreased by the programmable timing parameter tOSA (0..3 system clock cycles. The setup time becomes negative, e.g. tOSA=1 leads to tAS=-9.1 ns. That means a stable address is required 9.1 ns after chip-select and read enable have become active. That avoids problems caused by different signal runtimes if host devices simultaneously activate read enable, chip-select and address signals.

General timing parameters

Symbol Parameter Min Max Unit

tASr Address setup time (read cycle) 2.9 ns 1) 2.9-tOSA

tAHr Address hold time (read cycle) 0.0 ns

tASw Address setup time (write cycle) 12.8 ns tSYS+tf+2.8

tAHw Address hold time (write cycle) 2.9 ns

tAES Address enable Setup time 0 ns

tAEH Address enable hold time 0 ns

tBES Byte enable setup time 0 ns

tBEH Byte enable hold time 0 ns

tBEchg Byte enable change time tSYS+tOSA ns

tRDnS Data direction (RDn) setup time ns

tRDnH Data direction (RDn) hold time ns

tDSw Data setup time (write cycle) 12.8 ns tSYS+tf+2.8

tDHr Data hold time (read cycle) 2.1 ns

tDHw Data hold time (write cycle) 2.8 ns

tDLZ Data enable low-Z time (read cycle) 5.7 ns tSYS+tOSA+tf-4.3 2tSYS+tOSA-3.1

tDHZ Data high-Z time (read cycle) 4.9 ns

tAC Access time (read cycle) ns 2) 6) Read-data latched 33.7 2048tsys 2) 2tSYS+tOSA+tf+13.7 3) 6) Read data not latched 53.2 2048tsys 4) not shared (4+w)tSYS+tOSA+tf+13.2 5) shared (3+wm)tSYS+tOSA+tf+13.2

tRDI Read inter access idle time 12.5 ns 7) tWRI Write inter access idle time tsys+tf+2.5

tWC Write cycle time 12.5 ns tsys+tf+2.5

tCSHw Chip-select hold time (write cycle) 0.0 ns 6) tWWP Write access wait phase 0.0 2048tsys ns

tRWE Ready to write cycle end time 0.0 ns

Notes

1. The read address setup time can be decreased by the programmable timing parameter tOSA (0..3 system clock cycles). The setup time becomes negative, e.g. tOSA =1 leads to tAS = - 9.1 ns. That means a stable address is required 9.1 ns after chip-select and read enable have become active. That avoids problems caused by different signal runtimes if host devices simultaneously activate read enable, chip-select and address signals. 2. This timing is valid when requested read data is already latched inside the DPM module or when the read access targets the read ahead address area and the read access matches read ahead address 3. Standard read access to netX address area with 0 wait states (e.g. intram, handshake cells). It has no effect whether a 0 wait state AHB slave is shared with other system masters or not. This timing is valid for first read after 4-byte address boundary changed or for read ahead mismatch. netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 121/275 4. Standard read access to netX address area with w wait states when netX AHB slave target is not shared with another netX system master. If access targets netX address area with w wait states, access time will be extended by 1 system clock for each wait state (netX wait state areas, system memory intram and handshake cells run with 0 wait states.) 5. Standard read access to netX address area with w wait states when netX AHB slave target is shared with another netX system master. Example: DPM access to intlogic area (e.g. to xC Pointer FIFO) when netX ARM CPU also performs access to intlogic area (e.g. SPI controller). Max. wait states is wm=wo+wDPM where wo are max. internal wait states of other master and wDPM are max. internal wait states of DPM access. (netX wait state areas: system memory intram and handshake cells run with 0 wait states.) 6. Ready timeout if access permanently targets busy netX address area. 7. If read burst support is not enabled.

Multiplexed mode timing parameters

Note: There is no CS dependency for address-phase in multiplexed modes. Address sampling (also for high address lines, but not for SRAM mode byte enables) is performed around the change from address to data phase of the DPM_ALE signal also while chip-select is inactive.

Symbol Parameter Min Type Max Unit

tALEact Address phase active time 12.7 ns tSYS+tf+2.7 1) tALEDS ALE data phase setup time 0.0 ns

tALEDH ALE data phase hold time 0.0 ns

tCSSm Chip-select setup time for multiplexed modes 0.0

tDAS Data multiplexed address setup time 12.6 ns tSYS+tf+2.6

tDAH Data multiplexed address hold time 3.0 ns

Note 1. Address phase could even overlap with the active read or write enable phase. For read, netX will never drive data lines while ALE is active even if read enable is already activated by host.

Ready signal timing parameters

Symbol Parameter Min Type Max Unit 1) tDVR Data valid to ready time (read cycle) tRDS -2.2 ns

tRA Ready active time 5.7 ns

tRLZ Ready enable low-Z time 2.8 ns 2) 2) tRHZ Ready high-Z time

tRH Ready hold time 2.6 ns

Notes 1. Data valid to ready time can be increased by programmable timing parameter t_RDS (0..7 system clock cycles, see reference [1]). For tRDS = 0, DPM_RDY will be set 0.7 ns before read data is valid. For a correct tRDS setting, see host device requirements and data sheet. 2. Ready high-Z times differ depending on the programmed ready mode. For information, see the following tables.

Special ready timing for ready signal mode 0 and drive mode 2

Symbol Parameter Min Type Max Unit

tRPm02 Ready pulse width 8.0 ns tsys+tf-2.0

tRHZm02 Ready high-Z time 10.4 ns tsys+tf+0.4

Ready timing for ready signal mode 0 and drive mode 3

Symbol Parameter Min Type Max Unit

tRHZm03 Ready high-Z time 1.3 ns

Ready timing for ready signal mode 1 and drive mode 2

Symbol Parameter Min Type Max Unit

tRPm12 Ready pulse width 5.3 ns tsys+tf-4.7

tRHZm12 Ready high-Z time 19.4 ns 2tsys+tf-0.6

Ready timing for ready signal mode 1 and drive mode 3

Symbol Parameter Min Type Max Unit

tRHZm13 Ready high-Z time 3.8 ns

Important: In 4-bit mode the SIO lines are used bidirectionally for both, read and write data. This could lead to driving conflicts which may cause permanent damage to netX and host. To avoid driving conflicts the host must not drive the SIO lines while they are driven by the netX. For details refer to the serial quad DPM protocol, section 5.2.6.4.1.

The serial dual-port memory provides the programmable timing parameter sdpm_miso_early. This parameter controls the generation of serial output data. Timing parameter sdpm_miso_early is not active by default and serial dual-port memory behaves like standard SPI: Read data is changed on the clock edge following the sampling edge, i.e. it works on both serial clock edges. In this case, valid setup and hold times can always be reached by decreasing the serial clock rate. However, it is not possible to reach high clock rates then as there is only a half serial period margin for read data generation. The timing parameter sdpm_miso_early must be set to reach fast serial data rates. Read data is generated on the sampling edge (i.e. half a period earlier). However, this could lead to critical hold timing: Due to the delay times of serial clock and data signals, the hold time will always be positive but can be very short. For serial clock rates above 33 MHz, we recommend setting sdpm_miso_early to ‘1’. Default setting ‘0’ should be used for lower clock rates. The 4-bit mode is limited to 33 MHz, thus, sdpm_miso_early should not be activated for the 4-bit mode.

Setting of Setup timing Hold timing Comment sdpm_miso_early 0 can be relaxed by decreasing can be relaxed by decreasing Standard SPI timing, the serial clock rate. the serial clock rate. recommended for serial clock rates below 33 MHz. 1 can be relaxed by decreasing cannot be relaxed. Early read data generation, the serial clock rate. recommended for serial clock rates above 33 MHz.

Note: In 1-bit mode, the serial status is returned with the first header byte at transfer start. The first 3 bits of that are always 0.

header data

dv dv dv dv dv dv dv Serial Clock SPM_CLK QPM_CLK

tSPMCSDH tSPMCSS tSPMCP tSPMCSH tSPMCSIW Chip-Select SPM_CSN QPM_CSN

tSPMIS tSPMIH Serial Input Data SPM_MOSI MSB LSB MSB LSB QPM_SIO[3:0]

tSPMOV tSPMOH tSPMOHZ Serial Output Data tSPMOLZ (sdpm_miso_early==0) highZ LSB MSB LSB highZ SPM_MISO QPM_SIO[3:0] tSPMOV tSPMOH tSPMOHZ Serial Output Data tSPMOLZ (sdpm_miso_early==1) highZ LSB MSB LSB highZ SPM_MISO QPM_SIO[3:0] Figure 80: DPM SPI slave timing SPO=0 and SPH=0 transfer (data valid on positive edge of serial clock)

header data

dv dv dv dv dv dv dv Serial Clock SPM_CLK QPM_CLK

tSPMCSDH tSPMCSS tSPMCP tSPMCSH tSPMCSIW Chip-Select SPM_CSN QPM_CSN

tSPMIS tSPMIH Serial Input Data SPM_MOSI MSB LSB MSB LSB QPM_SIO[3:0]

tSPMOV tSPMOH tSPMOHZ Serial Output Data tSPMOLZ (sdpm_miso_early==0) highZ LSB MSB LSB highZ SPM_MISO QPM_SIO[3:0] tSPMOV tSPMOH tSPMOHZ Serial Output Data tSPMOLZ (sdpm_miso_early==1) highZ LSB MSB LSB highZ SPM_MISO QPM_SIO[3:0] Figure 81: DPM SPI slave timing SPO=0 and SPH=1 transfer (data valid on negative edge of serial clock)

header data

dv dv dv dv dv dv dv Serial Clock SPM_CLK QPM_CLK

tSPMCSDH tSPMCSS tSPMCP tSPMCSH tSPMCSIW Chip-Select SPM_CSN QPM_CSN

tSPMIS tSPMIH Serial Input Data SPM_MOSI MSB LSB MSB LSB QPM_SIO[3:0]

tSPMOV tSPMOH tSPMOHZ Serial Output Data tSPMOLZ (sdpm_miso_early==0) highZ LSB MSB LSB highZ SPM_MISO QPM_SIO[3:0] tSPMOV tSPMOH tSPMOHZ Serial Output Data tSPMOLZ (sdpm_miso_early==1) highZ LSB MSB LSB highZ SPM_MISO QPM_SIO[3:0] Figure 82: DPM SPI slave timing SPO=1 and SPH=0 transfer (data valid on positive edge of serial clock)

header data

dv dv dv dv dv dv dv Serial Clock SPM_CLK QPM_CLK

tSPMCSDH tSPMCSS tSPMCP tSPMCSH tSPMCSIW Chip-Select SPM_CSN QPM_CSN

tSPMIS tSPMIH Serial Input Data SPM_MOSI MSB LSB MSB LSB QPM_SIO[3:0]

tSPMOV tSPMOH tSPMOHZ Serial Output Data tSPMOLZ (sdpm_miso_early==0) highZ LSB MSB LSB highZ SPM_MISO QPM_SIO[3:0] tSPMOV tSPMOH tSPMOHZ Serial Output Data tSPMOLZ (sdpm_miso_early==1) highZ LSB MSB LSB highZ SPM_MISO QPM_SIO[3:0] Figure 83: DPM SPI slave timing SPO=1 and SPH=1 transfer (data valid on negative edge of serial clock)

Symbol Timing parameter Min Type Max Unit 1)2) tSPMCP Serial clock period 1 bit 8.0 ns 4 bit 30.0 1)

tSPMIS Serial input data setup time 1 bit 0.0 ns 4 bit 1.4

tSPMIH Serial input data hold time 1 bit 1.8 ns 4 bit 2.0 3) tSPMOV Serial output data valid time sdpm_mosi_early 1 bit 8.0 ns programmed to 0 4 bit 8.0 3) sdpm_mosi_early 1 bit 7.0 3) programmed to 1 4 bit 8.0 3) 4)5) tSPMOH Serial output data hold time 2.5 ns

tSPMOLZ Chip select to serial output data low-Z time 2.0 ns

tSPMOHZ Chip select to serial output data high-Z time 3.0 ns

tSPMCSS Chip select to serial clock setup time 3.0 ns

tSPMCSDH Chip select from deselected serial clock edge hold time 3.0 ns

tSPMCSH Serial clock to chip deselect hold time 3.0 ns

tSPMCSIW Chip select idle width 7.0 ns

Notes 1. Serial clock duty cycle is 30% (due to the fact that the sdpm_miso_early parameter must be set by software for fast serial clock rates and the serial logic is working only on rising or falling clock edges then, but not on both). 2. Minimum serial clock period is limited by internal logic, not by serial data setup or hold times. If using serial clock rates above 66 MHz, observe the netX-internal access times (e.g. non intram access, see section Serial 1-bit DPM protocol on page 87). 3. The serial output data valid timing refers to the output data generating clock edge. This can be controlled by the programmable timing parameter sdpm_miso_early. By default (sdpm_miso_early = ’0’) the timing refers to the serial clock edge before the data is sampled (i.e. half a serial clock period before it is sampled). For high serial clock rates with early output data generation (sdpm_miso_early set to ’1’) the timing refers to the serial clock edge when the preceding data bit is sampled (a full serial clock period before it is sampled). 4. The serial output data hold timing refers to the output data generating clock edge. This can be controlled by the programmable timing parameter sdpm_miso_early. By default (sdpm_miso_early = ’0’) the timing refers to the serial clock edge after the data is sampled (i.e. half a serial clock period after it is sampled). For high serial clock rates with early output data generation (sdpm_miso_early set to ’1’) the timing refers to the serial clock edge when the current data bit is sampled (sampling and generation take place on the same clock edge). 5. For all modes (1-bit, 4-bit, does not depend on programmable sdpm_miso_early parameter).

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 126/275 5.2.9.1 SQI timing The SQI module I/O timing depends on pad delays and the internal module structure. All timings are related to an internal system clock running at 100 MHz. The following figures show the timing for standard SPI mode. Regarding the transfer direction, timing parameters are identical for Dual and Quad SPI mode: In receive mode timing for SPI_MISO can be applied to all I/O lines. In transmit mode timing for SPI_MOSI can be applied to all I/O lines. In SQIROM mode timing from SPI mode 0 (SPO=0, SPH=0) can be applied, but the max. SPI_CLK frequency is increased to 133 MHz.

tCH tCL tCP SPI_CLK

tCSS tF tR tCSH tCSW SPI_CS_N

tR tF tMOSIS tMOSIS tMOSIS SPI_MOSI MSB LSB MSB SIO[3:0] tx tMOSIH tMOSIH tMOSIH tMOSIHZ tMISOS tMISOS tSPW tMISOS SPI_MISO MSB LSB MSB SIO[3:0] rx tMISOH tMISOH tMISOH

Figure 84: SPI timing SPO=0 and SPH=0 transfer (data generation on falling edge, sampling on rising edge of SPI_CLK)

tCH tCL tCP SPI_CLK

tCSS tF tR tCSH tCSW SPI_CS_N

tR tF tMOSIS tMOSIS tMOSIS SPI_MOSI MSB LSB MSB SIO[3:0] tx tMOSIH tMOSIH tMOSIH tMOSIHZ tMISOS tMISOS tSPW tMISOS SPI_MISO MSB LSB MSB SIO[3:0] rx tMISOH tMISOH tMISOH

Figure 85: SPI timing SPO=0 and SPH=1 transfer (data generation on rising edge, sampling on falling edge of SPI_CLK)

tCL tCH tCP SPI_CLK

tCSS tR tF tCSH tCSW SPI_CS_N

tR tF tMOSIS tMOSIS tMOSIS SPI_MOSI MSB LSB MSB SIO[3:0] tx tMOSIH tMOSIH tMOSIH tMOSIHZ tMISOS tMISOS tSPW tMISOS SPI_MISO MSB LSB MSB SIO[3:0] rx tMISOH tMISOH tMISOH

Figure 86: SPI timing SPO=1 and SPH=0 transfer (data generation on rising edge, sampling on falling edge of SPI_CLK)

tCL tCH tCP SPI_CLK

tCSS tR tF tCSH tCSW SPI_CS_N

tR tF tMOSIS tMOSIS tMOSIS SPI_MOSI MSB LSB MSB SIO[3:0] tx tMOSIH tMOSIH tMOSIH tMOSIHZ tMISOS tMISOS tSPW tMISOS SPI_MISO MSB LSB MSB SIO[3:0] rx tMISOH tMISOH tMISOH

Figure 87: SPI timing SPO=1 and SPH=1 transfer (data generation on falling edge, sampling on rising edge of SPI_CLK)

The following values are valid for netX 90 when the module is in normal peripheral mode (not in SQIROM/ XiP mode, i.e. the enable bit of register sqi_sqirom_cfg is not set). They refer to worst case operating conditions: VDD: 3.0 ... 3.6 V, Tj: -40 ... +125°C, CL: 20 pF.

Symbol Parameter Min Typ Max Unit (1) tCP SPI_CLK period 20.0 10*4096/N 40960 ns (1) fCP SPI_CLK frequency 0.025 50.0 MHz

tCH SPI_CLK high phase 0.5*tCP-3.0 ns

tCL SPI_CLK low phase 0.5*tCP-3.0 ns (2) tR Signal rise time 0.4 3.4 ns (2) tF Signal fall time 0.3 2.0 ns

tCSS SPI_CSN to first SPI_CLK edge setup time 0.5*tCP-3.0 ns

tCSH last SPI_CLK edge to SPI_CSN ns inactive time (3) - SPH 0 modes 7.0 - SPH 1 modes 0.5*tCP+7.0 (3) tCSW SPI_CSN minimum high pulse width 0.5*tCP-3.0 ns

tMOSIS SPI_MOSI (SPI_SIO3:0] transmit) to SPI_CLK setup 0.5*tCP-3.4 ns time

tMOSIH SPI_MOSI (SPI_SIO[3:0] transmit) hold time 0.5*tCP-3.0 ns

tMOSIHZ SPI_MOSI (SPI_SIO[3:0] transmit) high-Z time 3.5 ns

tMISOS SPI_MISO (SPI_SIO[3:0] receive) to SPI_CLK setup 2.5 ns time

tMISOH SPI_MISO (SPI_SIO[3:0] receive) hold time ns - without input filtering 4.5 - with input filtering(4) 14.5

tSPW Tolerated spike pulse width ns - without input filtering 0.0 - with input filtering(4) 9.0

Notes: 1. N is programmed by register spi_cr0/sqi_cr0, bits sck_muladd. N = 1..2048 2. Signal rise and fall times differ considerably depending on the external capacitive load. For approximation, use the following formula:

Rise times: tr = 0.350 + 0.150 * CL [ns]; CL: External capacitive load

Fall times: tf = 0.237 + 0.087 * CL [ns]; CL: External capacitive load netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 128/275 3. Only for automatic chip-select generation (if bit fss_static is not set in register spi_cr1/sqi_cr1). 4. Input filtering can be enabled/disabled in register spi_cr0/sqi_cr0 by bit filter_in. The following values are valid for netX 90 when the module is in SQIROM/XiP mode (not in normal peripheral mode, i.e. the enable bit of register sqi_sqirom_cfg is set). They refer to worst case operating conditions: VDD: 3.0 ... 3.6 V, Tj: -40 ... +125°C, CL: 20 pF. Only mode 0 and 3 are supported in SQIROM/XiP mode.

Symbol Parameter Min Typ Max Unit (1) tCP SPI_CLK period 7.5 (N+3)*2.5 645 ns (1) fCP SPI_CLK frequency 1.55 133.0 MHz

tCH SPI_CLK high phase 0.5*tCP-3.0 ns

tCL SPI_CLK low phase 0.5*tCP-3.0 ns (2) tR Signal rise time 0.4 3.4 ns (2) tF Signal fall time 0.3 2.0 ns (3) tCSSr SPI_CSN active to first rising SPI_CLK edge setup time tCP-1.0 ns (3) tCSHr last rising SPI_CLK edge to SPI_CSN inactive time tCP-1.0 ns (4) tCSW SPI_CSN minimum high pulse width tCP-3.0 I*tCP-3.0 4*tCP-3.0 ns

tMOSIS SPI_MOSI (SPI_SIO[3:0] transmit) to SPI_CLK setup time 0.5*tCP-2.6 ns (6) tMOSIH SPI_MOSI (SPI_SIO[3:0] transmit) hold time 0.5*tCP-1.2 ns

tMOSIHZ SPI_MOSI (SPI_SIO[3:0] transmit) high-Z time 3.5 ns

tMISOS SPI_MISO (SPI_SIO[3:0] receive) to SPI_CLK setup time 0.3 ns (7) tMISOH SPI_MISO (SPI_SIO[3:0] receive) hold time 2.1 ns (5) tSPW Tolerated spike pulse width 0.0 ns

Notes: 1. N is programmed by bits clk_div_val of register sqi_sqirom_cfg. N = 0...255. This leads to a frequency up to 133 MHz. 2. Signal rise and fall times differ greatly depending on external capacitive load. For approximation, see note 2 of the peripheral mode IO timing above, page 127. 3. The chip-select timing of QSPI devices is typically related to the rising edge (as described). However, for mode 0 a falling edge is generated 0.5*tCP before chip-select becomes inactive (at transfer end) and for mode 1 and a falling edge is generated 0.5*tCP after chip select becomes active (at transfer start). 4. The min. chip-select idle time can be programmed by bit t_csh of register sqi_sqirom_cfg. Between 1 and 4 SPI clock cycles can be selected (I). The device will not be deselected if no XiP access is desired. The SPI_CLK line will be held inactive instead. To disable the chip- select for longer times (e.g. for power save) switch to peripheral mode. A device will always be selected at least until the first 4 byte of data have been received in quad-IO-read (i.e. at least for 14 serial clock periods with a running serial clock). 5. Input filtering is not available in SQIROM/XiP mode.

6. The tMOSIH value 0.5*tCP-3.0 ns of earlier versions of this document was too pessimistic and has been corrected in this version.

7. The tMISOH value 1.2 ns of earlier versions of this document was too optimistic and has been corrected in this version. This should have no impact on existing designs as the SPI protocol guarantees a hold time of the half clock period which also exceeds the correct values.

Figure 88: SPI slave signal timing (SPO=0 and SPH=0)

Figure 89: SPI slave signal timing (SPO=0 and SPH=1)

Figure 90: SPI slave signal timing (SPO=1 and SPH=0)

Figure 91: SPI slave signal timing (SPO=1 and SPH=1)

SPI slave timing for worst case operating conditions: VDD: 3.0..3.6 V, Tj: -40..+125°C, CL: 20 pF. Values in brackets apply if input filtering is enabled.

Symbol Slave mode parameter Min Typ Max Unit (1,4) tSCP SPI_CLK high phase 30.0(60.0) ns

tSCH SPI_CLK high phase 10.0(30.0) ns

tSCL SPI_CLK low phase 10.0(30.0) ns

tR Signal rise time 9.0(9.0) ns

tF Signal fall time 9.0(9.0) ns

tSMOSIS SPI_MOSI to SPI_CLK setup time 2.0(12.0) ns

tSMOSIH SPI_MOSI hold time 12.0(22.0) ns (3) tSMISOS SPI_CLK to SPI_MISO setup time 29.9(39.9) ns

tSMISOS1 SPI_CSN to SPI_MISO MSB setup time 33.9(43.9) ns (3) tSMISOH SPI_MISO hold time 17.3(27.3) ns

tSMISOLZ SPI_CSN to SPI_MISO MSB Low-Z time 17.5(27.5) ns

tSMISOHZ SPI_CSN to SPI_MISO LSB High-Z time 28.5(38.5) ns

tSCSS SPI_CSN to SPI_CLK setup time ns - SPH=0 modes tSMISOS1 - SPH=1 modes 0.5

tSCSDH SPI_CSN hold from deselected SPI_CLK edge time 40.0 ns

tSCSH SPI_CSN hold time 10.5 ns

tSPW Tolerated spike pulse width ns - with input filtering 9.0 - without input filtering 0.0

Notes

1. Min. SPI_CLK period results from max. MISO data setup time (tSMISOS) for valid read data. 2. Using SPH=0 modes SPI chip select falling edge is MSB data out trigger. Hence, SPI chip select must toggle between each transferred word. Using SPH=1 modes SPI chip select may remain active between transferred words. 3. For fast SPI clock rates early SPI_MISO signal generation can be enabled by bit slave_sig_early of register spi_cr0. SPI_MISO will then be generated one SPI_CLK edge before. For SPH=0 modes tSMISOS and tSMISOH will be related to SPI_CLK edges 1, 3, 5,... instead of 2, 4, 6,… (SPH=1 modes: SPI_CLK edges 2, 4, 6,... instead of 3, 5, 6,…).

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 132/275 5.3 SQI/SPI 5.3.1 Overview Apart from the I2C, the SPI is the most common serial interface for peripheries and memory components. SPI (Serial Peripheral Interface) is a full-duplex interface defined by Motorola. Transfers are serial, typically 8-bit oriented and bidirectional between master and slaves. Slave devices are selected by a chip select signal. Beside the full-duplex interface (Standard SPI), netX 90 offers a Single SPI, Dual SPI and Quad SPI interface which is half-duplex. netX 90 offers the following modes:

SQI SPI0…2_APP SQI0_APP SPI_XPIC_APP SQI1_APP Mode: Standard SPI Mode: Standard SPI Mode: Quad SPI full-duplex, FIFO, Master only full-duplex, FIFO, Master or Slave half-duplex, FIFO, Master only? Mode: Quad SPI, Dual SPI or Single SPI; half-duplex, FIFO, Master only Mode: XiP (Quad SPI) Execution of programs, Master only Shared with COM CPU Accessed by APP CPU only Accessed by APP CPU only Quantity: 1 Quantity: 4 Quantity: 2 Table 21: netX 90 – SQI/SPI modes

The following table lists all netX 90 SQI/SPI signals sorted according to mode: Signal name Pin Option Description SQI signals SQI_CLK H2 - Clock signal of SQI interface SQI_CS0N G1 - Chip select 0 signal of SQI interface SQI_CS1N K7 3 Chip select 1 signal of SQI interface SQI_CS2N H3 1 Chip select 2 signal of SQI interface SQI_MOSI (_SIO0) H1 - SPI: Master Out / Slave In signal of SQI interface SQI: Serial input output data bit 0 signal SQI_MISO (_SIO1) G2 - SPI: Master In / Slave Out signal of SQI interface SQI: Serial input output data bit 1 signal SQI_SIO2 G3 - SQI (only): Serial input output data bit 2 signal SQI_SIO3 H3 - SQI (only): Serial input output data bit 3 signal SPI0_APP-signals SPI0_APP_CLK C1 2 Clock signal of SPI0 app interface SPI0_APP_CS0N D2 2 Chip select 0 signal of SPI0 app interface SPI0_APP_CS1N D1 2 Chip select 1 signal of SPI0 app interface SPI0_APP_MOSI D3 2 Master Out / Slave In signal of SPI0 app interface SPI0_APP_MISO D4 2 Master In / Slave Out signal of SPI0 app interface SPI1_APP-signals SPI1_APP_CLK MMIO - Clock signal of SPI1 app interface SPI1_APP_CS0N MMIO - Chip select 0 signal of SPI1 app interface SPI1_APP_CS1N MMIO - Chip select 1 signal of SPI1 app interface SPI1_APP_CS2N MMIO - Chip select 2 signal of SPI1 app interface SPI1_APP_MOSI MMIO - Master Out / Slave In signal of SPI1 app interface SPI1_APP_MISO MMIO - Master In / Slave Out signal of SPI1 app interface netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 133/275

SPI2_APP-signals SPI2_APP_CLK A10 2 Clock signal of SPI2 app interface SPI2_APP_CS0N B10 2 Chip select 0 signal of SPI2 app interface SPI2_APP_CS1N C9 2 Chip select 1 signal of SPI2 app interface SPI2_APP_CS2N B9 2 Chip select 2 signal of SPI2 app interface SPI2_APP_MOSI C10 2 Master Out / Slave In signal of SPI2 app interface SPI2_APP_MISO B11 2 Master In / Slave Out signal of SPI2 app interface SPI_XPIC_APP-signals SPI_XPIC_APP_CLK MMIO - Clock signal of SPI xpic application interface SPI_XPIC_APP_CS0N MMIO - Chip select 0 signal of SPI xpic app interface SPI_XPIC_APP_CS1N MMIO - Chip select 1 signal of SPI xpic app interface SPI_XPIC_APP_CS2N MMIO - Chip select 2 signal of SPI xpic app interface SPI_XPIC_APP_MOSI MMIO - Master Out/Slave In signal of SPI xpic app interface SPI_XPIC_APP_MISO MMIO - Master In/Slave out signal of SPI xpic app interface SQI0_APP-signals (configuration 1) SQI0_APP_CLK_B J9 5 Clock signal (B) of SQI app interface SQI0_APP_CS0N_B J8 5 Chip select signal (B) of SQI app interface SQI0_APP_MOSI_B(_SIO1) H8 5 SPI: Master Out / Slave In signal of SQI app interface SQI: Serial input output data bit 1 signal SQI0_APP_MISO_B(_SIO0) H9 5 SPI: Master In / Slave Out signal of SQI app interface SQI: Serial input output data bit 0 signal SQI0_APP_SIO2_B G8 5 SQI (only): Serial input output data bit 2 signal (B) SQI0_APP_SIO3_B F9 5 SQI (only): Serial input output data bit 3 signal (B) SQI0_APP-signals (configuration 2) SQI0_APP_CLK A10 1 Clock signal of SQI app interface SQI0_APP_CS0N B10 1 Chip select signal of SQI app interface SQI0_APP_CS1N G8 4 Chip select signal of SQI app interface SQI0_APP_CS2N F9 4 Chip select signal of SQI app interface SQI0_APP_MOSI (_SIO0) C10 1 SPI: Master Out / Slave In signal of SQI app interface SQI: Serial input output data bit 0 signal SQI0_APP_MISO (_SIO1) B11 1 SPI: Master In / Slave Out signal of SQI app interface SQI: Serial input output data bit 1 signal SQI0_APP_SIO2 C9 1 SQI (only): Serial input output data bit 2 signal SQI0_APP_SIO3 B9 1 SQI (only): Serial input output data bit 3 signal SQI1_APP-signals SQI1_APP_CLK C6 1 Clock signal of SQI app interface SQI1_APP_CS0N A7 1 Chip select signal of SQI app interface SQI1_APP_MOSI (_SIO0) A6 1 SPI: Master Out / Slave In signal of SQI app interface SQI: Serial input output data bit 0 signal SQI1_APP_MISO (_SIO1) B6 1 SPI: Master In / Slave Out signal of SQI app interface SQI: Serial input output data bit 1 signal SQI1_APP_SIO2 E2 1 SQI (only): Serial input output data bit 2 signal SQI1_APP_SIO3 F2 1 SQI (only): Serial input output data bit 3 signal Table 22: netX 90 – SQI/SPI signal names listed according to mode

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 134/275 5.3.2 SQI 5.3.2.1 Overview The SQI_XIP module provides standard Motorola-based SPI (serial port interface) with one receive and one transmit data line, Dual SPI (2-bit data lines) and “Serial Quad IO” (SQI, i.e. Quad SPI; 4- bit data lines). All modes support master functionality only. Slave functionality is not available. Several new features like dummy cycles or half-duplex modes (necessary for Dual and Quad SPI operation) are also provided for standard SPI. For Quad SPI devices an additional high-speed eXecute-in-Place (XiP, SQIROM) mode is implemented. In this mode, data from an SQI device is readable similar to a linear external memory (e.g. a parallel FLASH device) instead of being read from a single data register with a FIFO. Reading an SQI device becomes fully transparent then: The SQI device is mapped into a linear 64 Mbyte memory area and can be treated like a standard Flash. It can thus be used for direct code execution without hard runtime requirements. Copying the data into a RAM before code execution is not necessary. Depending on the code style, SQIROM provides similar performance or can even outperform parallel Flash devices. The SQI_XIP module consists of two submodules which separate the standard SQI peripheral operation mode (SQI submodule) from the SQIROM/XiP operation mode (SQIROM submodule).

mode RX FIFO control TX FIFO I/Os APB config Config and

SQI (peripheral mode) FIFO interface ext. I/O stat cfg I/Os mux

control I/Os AHBL prefetch buffer address space

SQIROM (XiP mode) Linear memory

SQI_XIP

Figure 92: Block diagram: Separate SQI peripheral mode and SQIROM/XiP mode

Note: While the signals of SPI0_APP and SPI2_APP are directly available on dedicated pins, the signals of SPI1_APP are mapped via the multiplex matrix (see section MMIO - Multiplex Matrix on page 65.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 135/275 5.3.2.2 Features  Standard SPI full-duplex master mode:  Programmable data word size from 4 to 16-bit (default: byte), MSB first transferred.  16-word deep FIFOs for transmit and receive data.  SPI, Dual SPI and Quad SPI (1, 2 and 4-bit) half-duplex master modes:  Byte-oriented, LSB or MSB first, programmable 32-bit endianness.  64-byte deep FIFO for receive or transmit data (1-bit FIFO depths: 16 words).  High-speed eXecute-in-Place (XiP/SQIROM) mode for Quad SPI Flash devices:  Mapped as 26-bit (64 Mbyte) linear address range for system masters.  Widely configurable to support many different devices up to 512 Mbit (64 Mbyte).  SQI read sequences including instruction and chip-select generation performed completely without CPU interaction.  Optimized SQI sequence generation: Continuous streams for address-incrementing reads (read bursts), 4-byte read-ahead buffer.  Linear code data rate: 320 Mbit/s @ 80 MHz (16-bit parallel FLASH @ 70 ns: 220 Mbit/s).  Supported SPI modes:  All modes (clock polarity high or low and clock phase 0 or 1) in non-XiP mode  Mode 0 and 3 in eXecute-in-Place (XiP/SQIROM)  Serial clock rates up to:  50 MHz in non-XiP mode  133 MHz in eXecute-in-Place (XiP/SQIROM) mode  IRQ based FIFO interaction possible.  DMA interface for receive and transmit data to minimize system CPU load.  Input signal over-sampling and filtering for hazard suppression.  Static or dynamic chip-select controlling in standard SPI mode.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 136/275 5.3.2.3 Typical applications Today’s market offers many SPI devices. Typical low-bandwidth devices are:  Serial Flashes  MMC cards  various types of sensors  microcontroller interfaces Figure 93 and Figure 94 show different possibilities of external SPI interconnection to SPI slave devices.

sqi_sck SPI_CLK sqi_mosi SPI_MOSI sqi_miso SPI_MISO sqi_fss0 SPI_CS SPI Slave 0 sqi_fss1 sqi_fss2 SPI_CLK SQI_XIP SPI_MOSI (Master) SPI_MISO SPI_CS SPI Slave 1

SPI_CLK SPI_MOSI SPI_MISO SPI_CS SPI Slave 2

Figure 93: Standard external SPI interconnection

SPI_CLK SPI_MOSI SPI_MISO SPI_CS SPI Slave 0

sqi_sck sqi_mosi sqi_miso sqi_fss0 0 0 1 sqi_fss1 1 2 SPI_CLK 3 sqi_fss2 2 4 SPI_MOSI

DMUX 5 6 SPI_MISO SQI_XIP 7 (Master) SPI_CS SPI Slave 6

SPI_CLK SPI_MOSI SPI_MISO SPI_CS SPI Slave 7

Figure 94: Extended external SPI interconnection with DMUX

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 137/275 Figure 95 shows an interconnection to a high-bandwidth SQI Flash in 4-bit mode. In 2-bit mode sqi_sio2 and sqi_sio3 are left unconnected (in this case, XiP mode cannot be used).

sqi_sck SPI_CLK sqi_mosi SPI_SIO0 (MOSI) sqi_miso SPI_SIO1 (MISO) sqi_sio2 SPI_SIO2 sqi_sio3 SPI_SIO3 sqi_fss0 SPI_CS SQI_XIP SQI Slave (Master)

Figure 95: Quad SPI (SQI) and XiP/SQIROM interconnection

5.3.2.4 Functional description Section Standard Motorola SPI mode on page 138 describes the entire SQI_XIP module function which is based on standard Motorola SPI. Dual and Quad SPI are enhanced versions of Motorola SPI for higher data rates. Section Dual and Quad I/O interface – SQI mode on page 141 provides related module properties. For Quad SPI eXecute-in-Place (XiP/SQIROM) function and device requirements, see section XiP (eXecute-in-Place) SQIROM mode on page 144. The SQI_XIP module consists of two submodules (see Figure 95) which separate the standard SQI peripheral operation mode (SQI submodule) from the SQIROM/XiP operation mode (SQIROM submodule). The I/Os of each sub-module are multiplexed. For this reason peripheral SQI mode (FIFO- controlled) and SQIROM/XiP mode cannot be used at the same time. This is no limitation because it is not recommended to connect additional SPI components in parallel to an SQI Flash device (in XiP mode, e.g. for code execution) due to performance reasons. The standard SQI peripheral mode allows connecting standard SPI devices (1-bit I/O mode; standard Motorola SPI) as well as devices that support 2-bit and 4-bit I/O modes (Dual and Quad SPI). It is possible to read and write to such devices using a FIFO-based interface. The SQIROM/XiP mode can be used to access SQI Flash devices in a high-performance 4-bit mode. This mode supports only read operations that are transparently mapped to a linear address space (e.g. code execution). Write operations to Flash devices can be performed in the standard SQI peripheral mode.

Note: To use the SQIROM/XiP mode, the following sequence has to be observed: A vendor- defined command sequence has to be sent to the SQIROM/XiP-capable Flash device in standard SQI peripheral mode, before the SQI_XIP module can be switched to the high-performance SQIROM/XiP mode.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 138/275 5.3.2.5 Standard Motorola SPI mode This section gives a brief overview of the Motorola SPI (serial peripheral interface). SPI is a full- duplex 4-wire interface. Transfers are serial, typically 8-bit oriented, and bidirectional between master and slaves. Slave devices are selected by a chip-select signal. SPI devices are master or slave devices. The SQI_XIP module provides master functionality only. Motorola SPI signals are:  SQI_CLK: Clock signal, master driven  SQI_MOSI: Master transmit, slave receive data signal, master driven  SQI_MISO: Master receive, slave transmit data signal, slave driven  SQI_CSN: Active low chip-select signal, master driven

Note: Chip-select signal is also called slave-select signal (SPI_SS or SPI_FSS). For clock signal you frequently find the abbreviation SPI_SCK.

5.3.2.5.1 SPI transfer format SPI data transfer is activated by a low active chip-select signal. Transfers are full-duplex, bidirectional, and always serialized MSB first. SPI signal generation, sampling states and timing can be selected by programmable SPO (serial clock polarity) and SPH (serial clock phase). SPI clock polarity (SPO) is the idle state of SPI clock signal SQI_CLK when chip-select is inactive. SPI clock phase (SPH) controls SPI data generation and sample timing. If SPH 0 is selected, data on SQI_MOSI and SQI_MISO will be sampled on the first clock edge of SQI_CLK. If SPH 1 is selected, sampling will be performed on the second edge. Data is always generated one edge earlier than sampling. Clock polarity and clock phase often are combined to the SPI mode: SPO is interpreted as bit 1 and SPH as bit 0 of the mode (e.g. SPO = 0, SPH = 1 is mode 1). The SQI module supports the generation of all four modes, but the SQIROM mode supports modes 0 and 3 only.

5.3.2.5.2 Chip-select generation Slave devices require a chip-select signal staying low for a whole transfer. This is reached by static chip-select controlling: Chip-select can be activated and deactivated by software like a programmable IO. However, some devices require a chip-select signal that becomes inactive between each transferred word. This is reached by dynamic chip-select generation: The chip- select signal will be driven inactive automatically for at least half a serial clock period between each word.

Note: Chip-select generation can be controlled by bit fss_static of register sqi_cr1.

5.3.2.5.3 SPI frame format with SPO=0 and SPH=0 (mode 0) The clock idle state is low and the data is sampled on the first (rising) edge of any SQI_CLK period. MSB data is generated when chip-select is activated. To generate the MSB data bit of the next word, chip-select toggling would be required after each data word. Since this is not suitable for many slaves, the MSB of a new data word is generated by the last (falling) edge of the preceding word instead.

sqi_sck 4 to 16 bit 4 to 16 bit sqi_fss0

sqi_mosi MSB LSB MSB LSB

sqi_miso MSB LSB MSB LSB

Figure 96: SPI SPO=0 and SPH=0 transfer (mode 0)

sqi_sck 4 to 16 bit (1st word) 4 to 16 bit (2nd word) sqi_fss0

sqi_mosi MSB LSB MSB (2nd word) LSB

sqi_miso MSB LSB MSB (2nd word) LSB

Figure 97: SPI SPO=0 and SPH=0 transfer (mode 0) without chip-select toggling

5.3.2.5.4 SPI frame format with SPO=0 and SPH=1 (mode 1) Clock idle state is low and data is sampled on the second (falling) edge of any SQI_CLK period. MSB data is generated on the first (rising) SQI_CLK edge. Slave devices do not need chip-select toggling at transfer start to generate the MSB data bit.

sqi_sck 4 to 16 bit 4 to 16 bit sqi_fss0

sqi_mosi MSB LSB MSB LSB

sqi_miso MSB LSB MSB LSB

Figure 98: SPI SPO=0 and SPH=1 transfer (mode 1)

5.3.2.5.5 SPI frame format with SPO=1 and SPH=0 (mode 2) Clock idle state is high and data is sampled on the first (falling) edge of any SQI_CLK period. MSB data is generated when chip-select is activated. To generate the MSB data bit of the next word, chip-select toggling would be required after each data word. Since this is not suitable for many slaves, the MSB of a new data word is generated by the last (rising) edge of the preceding word instead.

sqi_sck 4 to 16 bit 4 to 16 bit sqi_fss0

sqi_mosi MSB LSB MSB LSB

sqi_miso MSB LSB MSB LSB

Figure 99: SPI SPO=1 and SPH=0 transfer (mode 2)

sqi_sck 4 to 16 bit (1st word) 4 to 16 bit (2nd word) sqi_fss0

sqi_mosi MSB LSB MSB (2nd word) LSB

sqi_miso MSB LSB MSB (2nd word) LSB

Figure 100: SPI SPO=1 and SPH=0 transfer (mode 2) without chip-select toggling

5.3.2.5.6 SPI frame format with SPO=1 and SPH=1 (mode 3) Clock idle state is high and data is sampled on the second (rising) edge of any SQI_CLK period. MSB data is generated on the first (falling) SQI_CLK edge. Slave devices do not need chip-select toggling at transfer start to generate the MSB data bit.

sqi_sck 4 to 16 bit 4 to 16 bit sqi_fss0

sqi_mosi MSB LSB MSB LSB

sqi_miso MSB LSB MSB LSB

Figure 101: SPI SPO=1 and SPH=1 transfer (mode 3)

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 141/275 5.3.2.6 Dual and Quad I/O interface – SQI mode Dual and Quad SPI are enhanced SPI modes that provide higher data rates by using 2 or 4 data lines for each data direction instead of just one (standard SPI). Contrary to standard SPI, Dual and Quad SPI work in half-duplex mode, i.e. data can either be written to or read from a slave. A simultaneous data exchange in both directions is not possible. The difference between Dual SPI and Quad SPI is that Dual SPI is physically identical with the standard SPI (i.e. it requires only four wires) while SQI requires two additional data lines. Dual SPI needs 4 serial clock periods to transfer one byte while SQI needs 2 periods only. Dual and Quad SPI signal timing is identical with the standard SPI mode. All four SPI modes (clock polarity 0 or 1 and clock phase 0 or 1) are available.

Note: The following text describes only the Quad SPI mode. For Dual SPI consider that transferring one byte takes 4 serial clock periods instead of 2 and that only 2 data lines are required.

5.3.2.6.1 SQI signals In SQI mode all data signals can be used for transmit and receive. The SPI names MOSI and MISO are thus no longer used. The signals are simply named Serial IO 0 to 3 (SIO0…3) instead. For backward compatibility to standard SPI, the SIO0 function is located on SQI_MOSI and the SIO1 function is located on SQI_MISO. In total, the Quad IO SQI interface uses six signals, the Dual SPI only the 4 standard SPI signals:  Clock signal (SQI_CLK)  Low active chip-select signal (SQI_CSN)  Serial I/O  Quad SPI: Serial IO (SIO) 0 to 3 (SQI_MOSI, SQI_MISO, SQI_SIO2, SQI_SIO3)  Dual SPI: Serial IO (SIO) 0 to 1 (SQI_MOSI, SQI_MISO)

5.3.2.6.2 SQI transfers SQI is typically used to access serial memories (Flash devices). Data exchange with such devices is transfer-oriented. The chip-select signal is used to separate transfers from each another: During a transfer it must remain stable and active. Between transfers it must become inactive. SQI transfers typically require a transfer header always generated by the SQI master. The header contains at least a command word, but often more information, e.g. an access address. Data will be transferred after the header. It is quite common for Flash devices to transfer some dummy cycles between header and data. Dummy cycles do not transfer any data, but clocking is needed. This operation is also supported in a special mode in order not to fill the transmit/receive FIFOs with unneeded/unused data.

Mode 3 Mode 3

sqi_sck Mode 0 Mode 0

sqi_fss[0]

sqi_sio[3:0] CMD1 CMD0 A5 A0 D0_hi D0_lo D1_hi D(n-1)_lo

2 command cycles 6 address cycles 2 dummy cycles 2n data cycles

Figure 102: SQI mode 0 and 3 transfer example

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 142/275 The SQI module can perform three different types of transfers:  Dummy transfer  No FIFO interaction  Data lines can be controlled (driven high, driven low or high impedance)  Purpose: Device-required dummy cycles between header and data or to write constant data (e.g. all bytes 0xFF or 0x00)  SQI module is transmitter – half-duplex transmit mode  Data from TX-FIFO will be sent  Purpose: Send header or write data.  SQI module is receiver – half-duplex receive mode  Data is stored in RX FIFO  Purpose: Read data from SQI devices. The SQI mode does not support the automatic chip-select generation (bit fss_static is ignored). A full transfer sequence can thus be combined between falling and rising chip-select by several sub- transfers of different transfer types. The status bit busy or the IRQ trans_end can detect the end of each sub-transfer. The transfer size can be programmed for each sub-transfer up to 524288 bytes or dummy cycles. Each sub-transfer must be started by a software trigger (bit start_transfer). To start immediately, bit start_transfer can be programmed together with the transfer size. Transfers requiring FIFO interaction (i.e. non-dummy transfers) will be paused in case of imminent FIFO errors (i.e. RX-FIFO full in receive mode or TX FIFO empty in transmit mode). They will be continued as soon as the related FIFO is capable of receiving or transmitting again without producing an error (i.e. a full RX-FIFO must be read or new data must be stored in an empty TX- FIFO).

Note: SQI transfers use a transfer mechanism that differs from the old transfer scheme (which is still the default for standard SPI operation): In SQI modes and standard SPI half-duplex modes transfers are not started immediately when data is stored in the TX FIFO. The old scheme is not possible because SQI mode uses half-duplex transfers. Therefore, the number of bytes to be transferred has to be programmed. However, standard SPI mode can be programmed to use the SQI transfer scheme by setting bit spi_trans_ctrl of register sqi_cr1.

SQI data is typically serialized MSB (Most Significant Bit) first. This module additionally supports LSB (Least Significant Bit) first serialization.

Note: To select MSB and LSB first data serialization, use bit ms_bit_first of register sqi_tcr. MSB first is commonly used and selected by default.

Note: Standard SPI does not support LSB first data serialization. The configuration mode bit ms_bit_first will be ignored even in standard SPI half-duplex modes.

Most Significant Bit first Least Significant Bit first

Mode 3 Mode 3

sqi_sck Mode 0 sqi_sck Mode 0

sqi_fss sqi_fss

sqi_mosi Byte0.bit4 Byte0.bit0 Byte1.bit4 sqi_mosi Byte0.bit3 Byte0.bit7 Byte1.bit3

sqi_miso Byte0.bit5 Byte0.bit1 Byte1.bit5 sqi_miso Byte0.bit2 Byte0.bit6 Byte1.bit2

sqi_sio2 Byte0.bit6 Byte0.bit2 Byte1.bit6 sqi_sio2 Byte0.bit1 Byte0.bit5 Byte1.bit1

sqi_sio3 Byte0.bit7 Byte0.bit3 Byte1.bit7 sqi_sio3 Byte0.bit0 Byte0.bit4 Byte1.bit0

Figure 103: Transfer bit order: MSB or LSB first

Additionally, SQI mode allows you to select the byte order within a 32-bit word:  little-endian (least significant byte first) or  big-endian (most significant byte first) To switch between little and big-endian byte order, use bit ms_byte_first of register sqi_tcr. Little endian byte order is selected by default.

Note: Byte and bit order can be configured separately and have nothing to do with each other, i.e. selecting big-endian byte order will also respect the bit order selected by bit ms_bit_first.

Mode 3

sqi_sck Mode 0

sqi_fss

sqi_sio[3:0]

little endian Byte0.hi Byte0.lo Byte1.hi Byte1.lo Byte2.hi Byte2.lo Byte3. hi Byte3.lo Byte4. hi Byte4.lo Byte5. hi Byte5.lo

big endian Byte03.hi Byte03.lo Byte12.hi Byte12.lo Byte21.hi Byte21.lo Byte30. hi Byte30.lo Byte47. hi Byte47.lo Byte56. hi Byte56.lo

Figure 104: Transfer byte order: Little or big endianness, MSB first

For max. performance, the SQI FIFO is organized in 32-bit words. This means first read data is available when at least 4 bytes have been received. If less than 4 bytes are transferred, data is available as soon as the programmed number of bytes has been received. Due to the 32-bit-word organization of the FIFO in Dual and Quad SPI modes, the fill level also represents the number of 32-bit-words stored in the corresponding FIFO. If you transfer data that is not a multiple of 4 bytes, the last word contains only the remaining bytes, but it also counts as a 32-bit-word in the FIFO. Since SQI modes transfer data in a half-duplex manner, the FIFO normally used for the opposite direction (i.e. the RX FIFO when transmitting data) will be held in reset. Consequently, the corresponding fill level remains zero. The following example will clarify the relation between the data seen on the wire and the organization in the FIFO: 6 bytes will be transferred (either received or transmitted). Most significant bit first transmission is assumed. Figure 105 shows the data on the wire.

Mode 3

sqi_sck Mode 0

sqi_fss

sqi_sio[3:0] Byte0x01.hi Byte0x02.lo Byte0x13.hi Byte0x14.lo Byte0x25.hi Byte0x26.lo Byte0x37. hi Byte0x38.lo Byte0x49. hi Byte0xa4.lo Byte0xb5. hi Byte0xc5.lo

Figure 105: Data on the wire for data placement example of a 6-byte transfer netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 144/275 Table 23 shows the data received in the FIFO (or the data transmitted by writing to the FIFO). The table shows the byte order within 32-bit-words for little endian (least significant byte first) and big endian (most significant byte first) transmission.

Word in Least significant byte first (little endian) Most significant byte first (big endian) FIFO Byte 3 Byte 2 Byte 1 Byte 0 Byte 3 Byte 2 Byte 1 Byte 0 0 0x78 0x56 0x34 0x12 0x12 0x34 0x56 0x78 1 - - 0xbc 0x9a - - 0x9a 0xbc Table 23: Data placement example of a 6-byte transfer

Assuming the module has been configured and the data transfer has already been set up, the example data could be transmitted as follows:  In little endian mode:  s_ptSqiArea->ulSqi_dr = 0x78563412  s_ptSqiArea->ulSqi_dr = 0x0000bc9a  In big endian mode:  s_ptSqiArea->ulSqi_dr = 0x12345678  s_ptSqiArea->ulSqi_dr = 0x00009abc

Note: In big endian mode the remaining data of the last 32-bit word is also aligned correctly as in the little endian mode, i.e. upper bytes are not used when not transferring a full 32-bit word at the end.

5.3.2.7 XiP (eXecute-in-Place) SQIROM mode The SQIROM mode is designed for eXecute-in-Place (XiP) operation on SQI Flash devices. Read access to an SQI device is fully transparent to the user in this mode, i.e. the data of the SQI device is mapped into a linear system memory area of 64 Mbytes. The SQIROM address area can thus be used for the direct code execution without hard runtime requirements. Depending on the code style, the SQIROM provides similar performance or can even outperform parallel Flash devices. From the point of view of the software, the XiP part of the SQIROM module is a standard system slave which behaves like a read-only memory. Master modules (e.g. CPUs or DMA controllers) can read data from the external SQI Flash device by load operations. The whole related serial transfer to the SQI device including the generation of the read command, the address and the chip-select signal will be performed by the SQIROM module without any further CPU interaction.

Note: Only SPI modes 0 (clock polarity and phase, both 0) and 3 (clock polarity and phase, both 1) are supported for SQIROM usage.

Note: The use of the linear address range for programming a serial Flash is not supported. A Flash device must be programmed by a standard SPI or SQI peripheral function.

Standard SPI and SQI transfer generation (section section Standard Motorola SPI mode on page 138 and Dual and Quad I/O interface – SQI mode on page 141) is not available when SQIROM mode is enabled. SQIROM function is available only for devices connected to chip-select signal 0.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 145/275 5.3.2.7.1 SQIROM access generation The first read access to the SQIROM XiP address area will be transformed into a SQI transfer including a header consisting of a 4-bit (Quad-IO) read command. For the following access a new header is generated only if data is not read with incrementing addresses. Address-incrementing read access will continue the external transfer without overhead of a new header if there is no access to SQIROM, the last serial transfer will be stretched by deactivating the external clock but not by deactivating the chip-select signal.

Note: The SQIROM access header depends on the 4-bit read-command, the address-format and the timing requirements of the used SQI device. These parameters must be taken from the data sheet of the used SQI device. All configurations beside SPI mode selection can be performed in register sqi_sqirom_cfg.

Chip select will be deactivated only if new addressing is required. The min. chip-select idle time between deactivating and activating the chip-select signal can be configured between 1 and 4 serial clock periods. Serial clock rates can be configured by a programmable 8-bit divider of a 400 MHz clock. The min. divider is 3. The following serial clock rates are available: 400 MHz / 3 = 133 MHz, 400 MHz / 4 = 100 MHz, 80 MHz, … 1.55 MHz.

5.3.2.7.2 SQIROM device requirements There are many devices on the market which work together with this module (e.g. SST 26 series, Winbond W25 series, Macronix MX25 series). Yet, there is no real SQI device standard and devices vary in detail. The following list shows the requirements for using an SQI device as SQIROM XiP device:  The device must provide a 4-bit Quad-IO-read command which  provides a linear continuous burst  consists of a command/mode byte followed by 5 to 8 address nibbles (Figure 106) or which consists of 5 to 8 address nibbles followed by a command/mode byte (Figure 107). The address nibbles must be ordered most-significant nibble first.  is generated completely in 4-bit / Quad-IO mode and does not fall back to any other mode when the chip-select signal becomes inactive.  can be repeated immediately after the chip-select signal has become inactive and active again without requiring another command in between.  requires max. 7 (0 to 7) dummy cycles for a turnaround / before data cycles start.  SPI mode 0 or 3 must be supported  Serial clock freezing must be allowed  The minimum chip-select idle time must not exceed 4 serial clock periods. To support a wide range of available SQI devices, two header (Quad-IO-Read-command) formats are supported: The first byte of a transfer usually is a device-specific command byte which is followed by 5 address nibbles. However, there are some devices requiring a special mode byte after the address nibbles instead of a command byte before the address. This module supports both header types controlled by bit addr_before_cmd.

sqi_sck Mode 0

sqi_fss0

sqi_sio[3:0] CMD1 CMD0 An A0 D0_hi D0_lo D1_hi

2 command cycles 5 to 8 address cycles 0 to 7 dummy cycles data cycles

Figure 106: SQIROM header starting with command byte (bit addr_before_cmd not set)

sqi_sck Mode 0

sqi_fss0

sqi_sio[3:0] An A0 CMD1 CMD0 D0_hi D0_lo D1_hi

5 to 8 address cycles 2 command cycles 0 to 7 dummy cycles data cycles

Figure 107: SQIROM header starting with address bytes (bit addr_before_cmd set)

5.3.2.7.3 SQIROM data organization For XiP, the data organization inside the SQI Flash device is byte-organized. From the user’s point of view, it is similar to a little-endian-organized 8-bit parallel Flash. Transferring one byte requires 2 serial clocks. The higher nibble (bits 4 to 7) is transferred during the first cycle, the lower nibble (bits 0 to 3) during the second cycle. SIO0 always carries the least significant bit of a nibble, SIO3 the most significant bit.

Mode 3

Mode 0

sqi_fss0

sqi_sio0 Byte0.bit4 Byte0.bit0 Byte1.bit4

sqi_sio1 Byte0.bit5 Byte0.bit1 Byte1.bit5

sqi_sio2 Byte0.bit6 Byte0.bit2 Byte1.bit6

sqi_sio3 Byte0.bit7 Byte0.bit3 Byte1.bit7

Figure 108: SQIROM data organization

Note: In 1-bit SPI mode, SQI_SIO0 is SQI_MOSI (Master Out Slave In) and SQI_SIO1 is SQI_MISO (Master In Slave Out).

Example: The bytes stored in an SQI Flash device, starting at address 0x1000 with incrementing addresses, are: 0x21, 0x43, 0x65, 0x87, ... Reading out a 32-bit data word using XiP from address 0x1000 will deliver on HRDATA of the internal AHB interface: 0x87654321

5.3.2.7.4 SQIROM data rate estimation SQIROM access generation is implemented to produce a minimized non-data overhead. Moreover, the module performs read-ahead access and has a 4 byte cache to enhance performance. Reached data rates depend on physical SQI device properties and on address sequences performed on the AHB channel of the SQIROM module. Physical SQI device properties are:  f serial clock frequency in MHz (up to 133 MHz)  a number of address cycles in Quad-IO-Read-command (5 to 8)  d number of dummy cycles between command and first data (0 to 7)  I chip-select idle time in serial clock cycles (1 to 4) The following estimation provides rules for the mean data rate D considering the typical 32-bit CPU traffic or DMA block reading. These rules do not match traffic like byte reading from random addresses. The less data is read from incrementing addresses, the worse the data rate becomes due to increasing transfer restart overhead (chip-select toggling, Quad-IO-Read command generation).

Note: Data synchronization, command cycles and proper chip-select timing always require 7 serial clock cycles.

 Best case (BC): sustained address-incrementing fetches (long linear code, data copy)  D = n*4*8 * f / (i+a+d+7+n*4*2) = f*4 (as n >> i+a+d+7)  Typical case (TC): 32-bit code execution: 8 subsequent 32-bit fetches, then address change (jump)  D = 8*4*8 * f / (i+a+d+7+8*4*2) = 256*f*(i+a+d+71)  Worst case (WC): 32-bit code execution: 3 subsequent 32-bit fetches, then address change (operation, conditional jump, pipeline mis-fetch).  D = 3*4*8 * f / (i+a+d+7+3*4*2) = 96*f*(i+a+d+31) The following chart provides an overview of different serial clock rates with devices with typical parameters (e.g. SST26VF016/032): a=5, d=2, i=1. An 8-bit and a 16-bit parallel Flash with 70 ns access time are also included for comparison.

450,0 Best Case 400,0 Typi cal Case 350,0 Worst Case

300,0

250,0

200,0

150,0 Data Data Rate [MBit/sec)

100,0

50,0

0,0 SQI 40MHz SQI 80MHz SQI 100MHz Flash8 Flash16

Device

Figure 109: 32-bit CPU code execution related to data rate estimation (2 dummy cycles, 5 address cycles, 1 SCK min chip-select idle time)

Note: 10 ns are additionally expected for the data sampling and external signal generation of parallel Flash devices (which still is very optimistic and typically takes rather 30 ns or even more).

5.3.2.7.5 SQIROM access error detection SQIROM-related error cases are flagged in module status register sqi_sr and can be set to an IRQ event. The SQIROM module part is able to detect 3 different error types:  Access-while-disabled-error: This error will be flagged if a system master is trying to access the SQIROM address area while the SQIROM function is not enabled. In this case the master will receive invalid data, but it will not be stalled.  Write-access-error: This error will be flagged if a system master is trying to write to the read-only SQIROM address area. Write data will be ignored.  Timeout-error: The receive part of the SQIROM logic uses a feedback of the external serial clock. If no feedback can be detected, the timeout error will be generated. In this case the master will receive invalid data but it will not be stalled. Possible reasons for the missing clock feedback: The serial clock IO is clamped to fix level externally or a wrong programming of the global IO configuration.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 149/275 5.3.2.8 I/O timing The SQI_XIP module I/O timing depends on pad delays and the internal module structure. All timings are related to an internal system clock running at 100 MHz. The following figures show the timing for standard SPI mode. Regarding the transfer direction, timing parameters are identical for Dual and Quad SPI mode: In receive mode, timing for SQI_MISO can be applied to all I/O lines. In transmit mode, timing for SQI_MOSI can be applied to all I/O lines. In SQIROM mode, timing from SPI mode 0 (SPO=0, SPH=0) can be applied, but the max. SQI_CLK frequency is increased to 133 MHz.

tCH tCL tCP sqi_sck

tCSS tF tR tCSH tCSW sqi_fss

tR tF tMOSIS tMOSIS tMOSIS

sqi_mosi MSB LSB MSB

tMOSIH tMOSIH tMOSIH tMOSIHZ tMISOS tMISOS tSPW tMISOS sqi_miso MSB LSB MSB

tMISOH tMISOH tMISOH

Figure 110: SPI timing SPO=0 and SPH=0 transfer (data sampling on positive edge, generation on negative edge of SQI_CLK)

tCH tCL tCP sqi_sck

tCSS tF tR tCSH tCSW sqi_fss

tR tF tMOSIS tMOSIS tMOSIS

sqi_mosi MSB LSB MSB

tMOSIH tMOSIH tMOSIH tMOSIHZ tMISOS tMISOS tSPW tMISOS sqi_miso MSB LSB MSB

tMISOH tMISOH tMISOH

Figure 111: SPI timing SPO=0 and SPH=1 transfer (data sampling on negative edge, generation on positive edge of SQI_CLK)

tCL tCH tCP sqi_sck

tCSS tR tF tCSH tCSW sqi_fss

tR tF tMOSIS tMOSIS tMOSIS

sqi_mosi MSB LSB MSB

tMOSIH tMOSIH tMOSIH tMOSIHZ tMISOS tMISOS tSPW tMISOS sqi_miso MSB LSB MSB

tMISOH tMISOH tMISOH

Figure 112: SPI timing SPO=1 and SPH=0 transfer (data sampling on negative edge, generation on positive edge of SQI_CLK)

tCL tCH tCP sqi_sck

tCSS tR tF tCSH tCSW sqi_fss

tR tF tMOSIS tMOSIS tMOSIS

sqi_mosi MSB LSB MSB

tMOSIH tMOSIH tMOSIH tMOSIHZ tMISOS tMISOS tSPW tMISOS sqi_miso MSB LSB MSB

tMISOH tMISOH tMISOH

Figure 113: SPI timing SPO=1 and SPH=1 transfer (data sampling on positive edge, generation on negative edge of SQI_CLK)

SPI timing for worst case operating conditions: VDD: 3.0 ... 3.6 V, Tj: -40 … +125°C, CL: 20 pF. Values in brackets apply if input filtering is enabled.

Symbol Parameter Min Typ Max Unit (1) (1) (1) tCP SQI_CLK period 20.0 40960/N 40960 ns

tCH SQI_CLK high phase 0.5*tCP-3.0 ns

tCL SQI_CLK low phase 0.5*tCP-3.0 ns (2) (2) tR Signal rise time 0.4 3.4 ns (2) (2) tF Signal fall time 0.3 2.0 ns

tCSS SQI_CSN to first SQI_CLK edge setup time 0.5*tCP ns

tCSH last SQI_CLK edge to SQI_CSN inactive time ns - SPH 0 modes 10.0 11.5 - SPH 1 modes 0.5*tCP+10.0 0.5*tCP+11.5 (3,4) tCSW SQI_CSN minimum high pulse width 0.5*tCP-3.0 ns

tMOSIS SQI_MOSI to SQI_CLK setup time 0.5*tCP-3.4 ns

tMOSIH SQI_MOSI hold time 0.5*tCP ns

tMOSIHZ SQI_MOSI High-Z time 3.5 ns (5) tMISOS SQI_MISO to SQI_CLK setup time 2.5(12.5) ns (5) tMISOH SQI_MISO hold time 6.5(16.5) ns

tSPW Tolerated spike pulse width ns - with input filtering 9.0 - without input filtering 0.0 Table 24: I/O timing parameters

Notes: 1. N is programmed by bits sck_muladd of register spi_cr0. N = 1 ... 2048 2. Signal rise and fall times differ greatly depending on the external capacitive load. For approximation, use the following formula:

rise times: tr = 0.350 + 0.150 * CL [ns]; CL: External capacitive load

fall times: tf = 0.237 + 0.087 * CL [ns]; CL: External capacitive load 3. If bit fss_static of register spi_cr1 is set, SQI_CSN will not toggle between data words, but a half clock pause will be inserted anyway before the next word MSB. 4. In SPH=1 modes SQI_CSN does not become inactive during continuous transfers between LSB and next word MSB. 5. Input filtering can be enabled / disabled by bit filter_in of register spi_cr0.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 151/275 5.3.3 SPI0…2_APP and SPI_XPIC_APP netX 90 has 4 standard SPI interfaces: SPI0…2_APP and SPI_XPIC_APP. The mode is full- duplex (FIFO, Master or Slave) and can be accessed by the APP CPU only.

5.3.3.1 Features  Full master and slave functionality.  SPI_CLK clock rates up to:  50 MHz in master mode  33 MHz in slave mode  All four Motorola SPI modes supported in master and slave mode:  Clock polarity high or low  Clock phase 0 or 1  Flexible data frame size from 4 to 16-bit data words  16-word deep FIFO for transmit data  16-word deep FIFO for receive data  IRQ generation FIFO interaction  DMA interface for receive and transmit data to minimize system CPU load  Input signal oversampling and filtering for hazard suppression  Extended chip select controlling:  Three individual external chip selects (may be demultiplexed externally to 8 signals)  Static or dynamic chip select handling configurable  netX 100-compatibility mode and register set

5.3.3.2 Functional description 5.3.3.2.1 Block diagram

serial clock spi_sck_out transmit generation rate logic spi_sck_oe

transmitdata 16 parallel spi_mosi_out transmit to serial logic spi_mosi_oe irq Interrupt generation spi_miso_out IRQ set transmit logic spi_miso_oe

controll spi_fss_out 3 SPI sequence controller transmit 3 (clock polarity , phase, logic spi_fss_oe status data transfers , chipselect generation, slave access detection) sample spi_fss_in 3 register logic, block filter

sample spi_sck_in logic, filter master/ sample slave spi_mosi_in logic, serial to filter parallel sample spi_miso_in 16 logic, receivedata clk filter nres receive 16bit wide 16 word FIFO cs highspeed FIFO memory controller write modulebus addr interface wdata transmit 16bit wide 16 word rdata FIFO FIFO memory controller

DMA handshake DMA interface

Figure 114: Block diagram of SPI module

5.3.3.2.2 SPI signals Motorola SPI signals are:  SPI_CLK: Clock signal, master driven  SPI_MOSI: Master transmit, slave receive data signal, master driven  SPI_MISO: Master receive, slave transmit data signal, slave driven  SPI_CSN: Active low chip-select signal, master driven

Note: The chip-select signal is also called slave-select signal (SPI_SS or SPI_FSS). For the clock signal you frequently find the abbreviation SPI_SCK.

Data transfers are full duplex bidirectional. Data is always serialized MSB first.

5.3.3.3 SPI transfer format SPI data transfer is activated by low active chip select signal. SPI signal generation and sampling states and timing can be selected by programmable SPO and SPH.

Note: For more flexibility in master mode, chip select can be dynamic (generated by the SPI module state machine) or static (generated by register spi_cr1.fss_static).

SPI clock polarity (SPO) SPI clock polarity is the idle state of SPI clock signal SPI_CLK when no data is transferred.

SPI clock phase (SPH) SPI clock phase controls SPI data generation and sample timing. If SPH 0 is selected, data on SPI_MOSI and SPI_MISO will be sampled on the first clock edge of SPI_CLK, if SPH 1 is selected the signal will be sampled on the second edge. Data is generated one edge before.

SPI frame format with SPO=0 and SPH=0 Clock idle state is low and data is sampled on the first (rising) edge of any SPI_CLK period. MSB data is generated when chip select is activated. Slave devices need chip select toggling at start of transfer to generate MSB data bit.

SPI_CLK 4 to 16 bit 4 to 16 bit SPI_CSn

SPI_MOSI MSB LSB MSB LSB

SPI_MISO MSB LSB MSB LSB

Figure 115: SPI SPO=0 and SPH=0 transfer (mode 0)

SPI frame format with SPO=0 and SPH=1 Clock idle state is low and data is sampled on the second (falling) edge of any SPI_CLK period. MSB data is generated on the first (rising) SPI_CLK edge. Slave devices do not need chip select toggling at start of transfer to generate MSB data bit.

SPI_CLK 4 to 16 bit 4 to 16 bit SPI_CSn

SPI_MOSI MSB LSB MSB LSB

SPI_MISO MSB LSB MSB LSB

Figure 116: SPI SPO=0 and SPH=1 transfer (mode 1)

SPI frame format with SPO=1 and SPH=0 Clock idle state is high and data is sampled on the first (falling) edge of any SPI_CLK period. MSB data is generated when chip select is activated. Slave devices need chip select toggling at start of transfer to generate MSB data bit.

SPI_CLK 4 to 16 bit 4 to 16 bit SPI_CSn

SPI_MOSI MSB LSB MSB LSB

SPI_MISO MSB LSB MSB LSB

Figure 117: SPI SPO=1 and SPH=0 transfer (mode 2)

SPI Frame Format with SPO=1 and SPH=1 Clock idle state is high and data is sampled on the second (rising) edge of any SPI_CLK period. MSB data is generated on the first (falling) SPI_CLK edge. Slave devices do not need chip select toggling at start of transfer to generate MSB data bit.

SPI_CLK 4 to 16 bit 4 to 16 bit SPI_CSn

SPI_MOSI MSB LSB MSB LSB

SPI_MISO MSB LSB MSB LSB

Figure 118: SPI SPO=1 and SPH=1 transfer (mode 3)

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 155/275 5.3.3.4 Typical applications There are many SPI devices on the market today. Typical are low bandwidth devices as:  Serial FLASHs  MMC cards  Various types of sensors  Microcontroller Interface The following figures show different possibilities of external SPI interconnection to SPI slave and master devices.

SPI_CLK SPI_CLK SPI_MOSI SPI_MOSI SPI_MISO SPI_MISO SPI_CS0 SPI_CS SPI Slave 0 SPI_CS1 SPI_CS2 netX 90 (master) SPI_CLK SPI_MOSI SPI_MISO SPI_CS SPI Slave 1

SPI_CLK SPI_MOSI SPI_MISO SPI Slave 2 SPI_CS Figure 119: Standard external SPI interconnection

SPI_CLK SPI_MOSI SPI_MISO SPI_CS SPI Slave 0

SPI_CLK SPI_MOSI SPI_MISO SPI_CS0 0 0 1

SPI_CS1 1 X 2 SPI_CLK

U 3

SPI_CS2 2 M 4 SPI_MOSI

D 5 6 SPI_MISO netX 90 7 (master) SPI_CS SPI Slave 6

SPI_CLK SPI_MOSI SPI_MISO SPI Slave 7 SPI_CS Figure 120: Extended external SPI interconnection with DMUX

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 156/275 5.3.4 SQI0…1 Apart from the full-duplex interface (Standard SPI), netX 90 offers two Quad SPI interfaces, SQI0 and SQI1. The mode is half-duplex (FIFO, Master only) and can be accessed by the APP CPU only. The SQI0…1 interface has no XiP function.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 157/275 5.4 I2C 5.4.1 Overview The I2C interface is a 2-wire interface providing a clock and a data line. Transfers are serial, 8-bit oriented, half-duplex, and bidirectional between master and slaves. Each device connected to the I2C interface is addressable by a unique address. Compared to other I2C implementations this module reduces the CPU load by running complex I2C sequences (jobs) like acknowledge polling followed by a data transfer in hardware without CPU interaction. The module includes a standard ARM DMA interface together with a 16-byte master data FIFO and a 16-byte slave data FIFO. The module provides interrupts for the most important events:  slave selection  FIFO requests and errors  I2C bus collision detection  end-of-transfer As some devices demand sequences that are not covered by the Philips I2C-bus specification (e.g. SCL toggling without data transfers for initializing a device), an additional PIO-mode is provided. The PIO mode allows the direct programming of SDA and SCL.

serial clock SCL (out, enable) serial clock-rate generation PIO mode transmit data 8 parallel to serial SDA (out, enable) IRQ Interrupt generation IRQ set

I2C sequence controller (START, STOP, control data transfers, Acknowledge (ACK) generation, status ACK-polling) configuration sample logic, register spike SCL(in) block suppression, slave clock stretch I2C slave address request START/ detection detection STOP 8 detection sample logic, spike ACK SDA(in) suppression, 8 detection collision serial to detection parallel 8 receive data 8

slave FIFO controller CPU highspeed FIFO memory bus modulebus FIFO single port, interface access 32x 8 bit arbiter (16 byte master master FIFO 16 bytes slave) controller

DMA handshake DMA interface

Figure 121: I2C module block diagram

Note: For normal I2C-function, SDA and SCL are switched by their output/drive-enables only, i.e. the low level of these signals is realized by active-low driving, the high level by an undriven signal pulled up by a resistor (ASIC-internal or -external pull-up depending on the ASIC IO). In PIO mode, the output level can be driven active-high and active-low.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 159/275 5.4.3 Features  Generation of complete complex I2C sequences without CPU interaction, e.g.:  Automatic acknowledge polling including (r)START  Continued and not-continued transfers (automatic acknowledge generation)  Timeout watchdog that detects a stalling of the I2C bus (if SCL permanently low)  Supports the Philips I2C-bus specification, version 2.1 (01.2001)  Master and slave functionality (simultaneous)  SCL clock rates from 50 kHz up to 3.4 MHz  7- and 10-bit addressing  Multi-master arbitration  Clock stretching  General call detection  Signal filtering and spike suppression  Two 16-byte FIFOs: one for master, one for slave  Standard ARM DMA interface (one for master and one for slave FIFO handling)  PIO mode for direct signal stimulation (e.g. for special init-sequences)

5.4.4 Typical applications There are many I2C devices on the market today. Typical are low bandwidth devices as:  EEPROMs  display controllers  card readers  various types of sensors  microcontrollers  various types of ICs with I2C configuration channel

5.4.5 Functional description For detailed I2C standard description, see Philips I2C-bus specification (version 2.1, 01.2001). The following section gives a brief overview.

5.4.6 I2C devices I2C devices are master, slave or master-and-slave devices. This device is a master-and-slave device.

5.4.7 I2C signals The I2C interface contains two signals:  SCL: Serial clock  SDA: Serial data To avoid signal driving conflicts, both signals are never actively driven high. High level is realized by pad pull-up resistors. netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 160/275 5.4.8 I2C signal conditions A master initiates a transfer with a start condition (START) or a repeated start condition (rSTART). The start condition is represented by a falling edge of SDA while SCL is high. At the end of a transfer, the master must set a stop condition (STOP). The stop condition is represented by a rising edge of SDA while SCL is high. During data transfers, SDA is valid and must not change while SCL is high. transfer transfer

SDA

SCL

START SDA SDA rSTART STOP valid change

Figure 122: I2C signal conditions

Note: START stands for a START condition generated after the generation of a STOP condition (or after the I2C bus started operation after power-on).

rSTART stands for a repeated START condition meaning a START that is generated directly after a transfer without a STOP in between.

(r)START, with the “r” enclosed in brackets, stands for “START or rSTART” meaning a START condition which follows a previous STOP condition or a transfer.

5.4.9 I2C transfers An I2C transfer always transmits eight bits of data (MSB first) followed by an active low acknowledge bit generated by the receiving device. The first transferred byte after (r)START is always generated by a master. It contains a 7-bit slave address (addr) and a R/nW-bit which indicates the transfer direction (“Read/not-Write” bit: 0: write transfer master to slave, 1: read transfer master from slave). Every I2C slave device has its own slave ID. If any ID matches the address generated by the master during the first byte after (r)START, the respective slave will acknowledge the first byte. For detailed I2C address range specification, see Philips I2C-bus specification.

slave select transfer data transfer read no ACK

SDA R/nW addr[6] addr[5] addr[0] write ACK data[7] data[6:0] ACK

SCL 1 2 7 8 9 1 2..8 9

START Acknowledge Acknowledge rSTART by slave by receiver or STOP

Figure 123: I2C 1-byte transfer

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 161/275 5.4.10 I2C acknowledge handling The low active acknowledge bit is always generated by the receiving device (during write transfers by the slave, during read transfers by the master) after each transferred byte. If a slave does not acknowledge a byte, the master has to generate (r)START or STOP.

R/ P/ S slave address A data A data A data A/A nW rS 0 transfered data (write) (repeated until no ACK or rSTART or STOP)

from master to slave A = acknowledge S = START A = not acknowledge rS = repeated START from slave to master P = STOP

Figure 124: I2C write transfer (master to slave)

After the last byte of a read transfer, the master (as receiver) must not generate an acknowledge to mark the end of the transfer to the slave. Otherwise, the slave will continue sending data and produce a bus error.

R/ P/ S slave address A data A data A data A nW rS 1 transfered data (read) (no ACK by master after last byte)

from master to slave A = acknowledge S = START A = not acknowledge rS = repeated START from slave to master P = STOP

Figure 125: I2C read transfer (master from slave)

Note: After an acknowledged (r)START with set read bit, at least one byte must be transferred from slave to master.

In case of a transfer direction change an rSTART condition must be generated.

R/ R/ P/ S slave address A data A data A rS slave address A data A data A nW nW rS 0 1 transfered read data transfered write data (write) (read) (no ACK by master after last byte)

from master to slave A = acknowledge S = START A = not acknowledge rS = repeated START from slave to master P = STOP

Figure 126: I2C transfer with direction change

5.4.11 I2C 10-bit addressing The Philips I2C-bus specification (reference [6]) describes an extended 10-bit addressing mode that is entered by a 2-byte start sequence. The first byte after (r)START contains a 7-bit address matching the reserved pattern “11110XX”. “XX” are the two MSB bits of the requested 10-bit address.

Note: For detailed I2C address ranges and pattern, see Philips I2C-bus specification.

If a 10-bit slave device is on the I2C-bus with the appropriate MSB address bits, it will acknowledge the first byte. netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 162/275 Note: As long as the address is incomplete, several slaves can acknowledge the first byte.

The master will then transfer the second start byte containing the lower eight address bits.

Note: Only one device will acknowledge the last address part.

slave address R/ slave address rS/ S A A data A data A/A 1st 7 bits nW 2nd byte P 11110XX 0 address LSBs transfered data (10-bit pattern (write) (repeated until no ACK or rSTART or STOP) + MSBs)

from master to slave A = acknowledge S = START A = not acknowledge rS = repeated START from slave to master P = STOP

Figure 127: I2C 10-bit addressing

Since the second byte of a 10-bit start sequence is always transferred from master to slave, the read bit in the first transferred byte must always be 0. A read transfer from a 10-bit addressed slave is initiated by a write start sequence followed by an rSTART and the first start byte containing the 10-bit address pattern, the slave address MSBs and the read bit set to 1. The second start byte will not be transferred again.

slave address R/ slave address slave address R/ rS/ S A A rS A data A data A/A 1st 7 bits nW 2nd byte 1st 7 bits nW P 11110XX 0 address LSBs 11110XX 1 transfered data (10-bit pattern (write) (10-bit pattern (read) (repeated until no ACK or rSTART or STOP) + MSBs) + MSBs)

from master to slave A = acknowledge S = START A = not acknowledge rS = repeated START from slave to master P = STOP

Figure 128: I2C initializing a read transfer from a 10-bit address slave

Various types of transfers can be combined as described in the Philips I2C-bus specification. E.g. write data may be inserted before restarting in Figure 128. 5.4.12 I2C general call The I2C general call function is provided by the reserved 7-bit address pattern “0000000” transferred after START initiating a write transfer (read bit set to 0).

Note: For detailed I2C address ranges and pattern, see Philips I2C-bus specification.

5.4.13 I2C cycle stretching I2C slaves may stretch SCL periods by holding the SCL signal low after a master has generated a falling SCL edge. This module supports period stretching: It will wait for a positive SCL edge on the external I2C bus before it continues the SCL cycle. To escape from permanently low-tied SCL, register i2c_mcr.en_timeout can activate an SCL timeout detection.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 163/275 5.4.14 I/O timing The I2C module IO timing depends on pad delays and internal module structure. All timings are related to an internal system clock running at 100 MHz.

tfCL trCL tLOW tHIGH tsp tsp

SCL

tHD;STA tHD;DAT tSU;DAT tSU;STA tHD;STA tSU;STO tBUF SDA

S Sr P S tfDA trDA tSP

Figure 129: Timing on I2C bus

Symbol Parameter Min Typ Max Unit (1) (1) fSCL SCL clock frequency 50 - 3333 kHz (1) (1) tSCL SCL clock period (1/ fSCL) 300 - 20000 ns (2) tfCL SCL fall time 3.1 ns (3) trCL SCL rise time 15.9 - 250 ns (2) tfDA SDA fall time 3.1 ns (3) trDA SDA rise time 15.9 - 250 ns (1) tLOW Low period of SCL clock tSCL/2- tfCL - - ns

tHIGH High period of SCL clock tSCL/2- trCL - tSCL/2 ns

tHD;DAT SDA hold time 30 - 630 ns

tSU;DAT SDA setup time tSCL/2-trDA - - ns

tHD;STA SCL hold time after (repeated) START condition tSCL/2 - - ns

tSU;STA SCL setup time before repeated START condition tSCL/2-trCL - - ns

tSU;STO SCL setup time before STOP condition tSCL/2-trCL - - ns

tBUF I2C bus idle time between STOP and START tSCL/2-trDA - - ns

tSP Pulse width of spikes suppressed by input filters - - tSCL/32 ns Table 25: I/O timing parameters

Notes: 1. SCL clock frequency may decrease (period may increase) if other devices hold SCL low. SCL frequency is set by mode bits of register i2c_mcr (0). 2. Signal fall times are typical only. For approximation, use the following formula:

Fall times: tf = 0.197 + 0.058 * CL [ns]; CL: External capacitive load 3. Signal rise times depend on pull-up resistor and capacitive bus load. Specified rise times are for 500 Ohm pull-up resistor and 400 pF load. For I2C high-speed mode and high capacitive load external driver devices can be used to reach faster rise times.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 164/275 5.5 Multi LED 5.5.1 Overview The Multi-LED modules MLED_CTRL and MLED_CTRL_APP provide a means to drive two LEDs that are connected to a single output pin. For this purpose, the LEDs are driven in a time-multiplex fashion. Each LED is driven by a PWM signal and therefore individually dimmable. There are several options to drive the LEDs: A module internal blink generator, a line register, and a fixed value input. The com-side MLED_CTRL module also has netX system signals available, e.g. Ethernet PHY status signals, etc.

system * blink from netX line[n] 0 output control

blink line[n+1] 0 0..m

MLED blink PWM counter generator & prescaler

line register config MLED

Figure 130: Block diagram (signals marked with [*] are valid for com-side Multi-LED module only)

Figure 130 shows the simplified internal structure of the Multi-LED modules. The com-side MLED_CTRL module contains four output stages, but only one of them is illustrated here. The module also offers several netX system signals. The app-side MLED_CTRL_APP module contains eight output stages, but no netX system signals.

5.5.2 Features  time-multiplexed drive of two LEDs on a single output pin  individually dimmable outputs  configurable input signal selection and inversion  module-internal synchronized blink generator  module-internal line output register for simultaneous LED switching  configurable fixed output value  netX system signals (com-side only)  com-side: 4 output pins (8 LEDs)  app-side: 8 output pins (16 LEDs)

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 165/275 5.5.3 Typical applications Multi-LED modules allow one pin to control two LEDs. This achieves a reduction of the number of pins required to connect LEDs compared with traditional solutions (one LED per pin). A Multi-LED module is designed for use with LEDs as status indicators. Typical applications include for example:  I/O status indication  Ethernet PHY link/activity LEDs  Board status LEDs

+3V3 +3V3

Figure 131: External connection examples

Figure 131 shows two typical external connection variants. Whether the common resistor variant is usable or not depends on the forward voltages of the LEDs used. Turning the LEDs off safely when the output pin is in high-z state must be possible.

5.5.4 Functional description The Multi-LED module offers two operation modes:  time-multiplexed PWM mode and  pass-through mode An additional section describes the global module features that can be used in both modes. There are several Multi-LED module internal signals as well as netX system signals (com-side only). The Multi-LED internal signals include an always-off state, a state defined by a line register and a signal generated by a module internal blink generator. You can invert each input signal. For details, see the description of bit field sel of register mled_ctrl_output_sel[0] of the corresponding Multi-LED module (com-side or app-side).

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 166/275 5.5.5 Time-multiplexed PWM mode The time-multiplexed PWM mode is the standard mode of the module. Each output drives two LEDs:  the low-side LED and  the high-side LED Three states of the output pin are possible:  high (i.e. the low-side LED is on)  low (i.e. the high-side LED is on)  high-z (i.e. both LEDs are off)

The PWM period (tPWM) is identical for all outputs and determined by bit field prescale_counter_max in the global configuration register mled_ctrl_cfg. The prescale counter will be increased by the netX system clock (i.e. fclk = 100 MHz or tclk = 10 ns). The PWM period is divided in two phases of identical length: High-side phase (tH) and low-side phase (tL).

tPWM = tclk * 512 * (prescale_counter_max + 1)

fPWM = fclk / (512 * (prescale_counter_max + 1))

prescale_counter_max = (fclk / (512 * fPWM)) - 1

tH = tL = tPWM / 2 Figure 132 shows the internal generation of the output signal. Both input signals are on. The example uses prescale_counter_max = 1, i.e. tPWM = 10.24 µs or fPWM ≈ 97.7 kHz. Configurable PWM frequency range: ≈ 191 Hz to ≈ 195 kHz.

tPWM tH tL tONH tONL VDD Pin high-z GND

pwm_cnt 511 0 1 2 252 253 254 255 256 257 258 508 509 510 511 0

prescale_cnt 0 1 0 1 0 0 1

tclk tpre

Figure 132: Example of internal generation of the output pin

A second counter (the PWM counter) will be increased when the prescale counter reaches its configured max. value. The PWM counter is a fixed-width counter and always counts from 0 to 511.

If the PWM counter is in the range of 0 - 255 (tH), the high-side LED will be driven depending on the configured switch-on time (registers on_time[x], with x being an even number; tONH). The output pin will be driven low when the high-side phase starts. If the PWM counter reaches on_time[x] - 1 (on_time[x] = 253 in the example above), the output pin will switch to high-z state.

If the PWM counter is in the range of 256 - 511 (tL), the low-side LED will be driven depending on the configured switch-on time (registers on_time[y], with y being an odd number; tONL). The output pin will be driven high when the low-side phase starts. If the PWM counter reaches 256 + on_time[y] - 1 (on_time[y] = 255 in the example above), the output pin will switch to high-z state.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 167/275 The state of an LED depends on the input value selected by the input multiplexer. For a list of selectable signals, see register mled_ctrl_output_sel[0]. When the selected input signal is off, the output signal will be high-z during the entire corresponding PWM phase. The simultaneous use of two LEDs implies that each LED is on for max. half the PWM period (minus one). This is important for determining the LED series resistors. The separately configurable switch-on time can be used for dimming effects or for compensating differences in the brightness of different (colored) LEDs.

5.5.6 Pass-through mode This mode uses a configured input signal as a direct or inverted output signal and disables the time-multiplexed PWM mode. This mode is active when all bits of field sel of the output phase 0 configuration registers (high-side LED) are set to ‘1’. The output phase 1 configuration registers (low-side LED) configure which input signal (and inversion) is to be used. The output can be forced to high-z state if the corresponding low-side LED on_time register is set to ‘0’. As soon as a value unequal to ‘0’ is written to the on_time register, the regular pass-through operation is active (i.e. the output will be driven high or low depending on the input signal).

5.5.7 Features for both modes

Multi-LED module internal blink generator The Multi-LED module has a blink generator with a configurable blink frequency. The blink frequency is the same for all output LEDs configured to use the blink signal, i.e. these LEDs all blink in a synchronized manner. Bit field blink_counter_max of register mled_ctrl_cfg determines the blink frequency which can be configured within a range of ≈ 0.1 Hz to 50 Hz:

fblink= 50 Hz / (blink_counter_max + 1)

blink_counter_max = (50 Hz / fblink) – 1

Common line register This register allows changing all LEDs at once to a new value (using line mode).

Note: The change will take effect at the start of the next PWM period (when the output operates in time-multiplexed PWM mode). In pass-through mode, the change will take effect immediately.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 168/275 5.6 GPIO 5.6.1 Overview The netX 90 provides separate GPIO modules for com-side and app-side. The GPIO module on the com-side has 4 IO pins (GPIO11:8) and 1 counter, whereas the GPIO_APP provides 8 IO pins (GPIO7:0) and 3 counters. The main idea of the netX GPIO was to combine an IO pin with one 32-bit data register (gpio_tcX) and a counter. This enhances the basic IO functionality known from nearly all SoC chips by many different PWM, capture or supervising functions. One config register (gpio_cfgX) per IO pin defines the mode used at this pin: The basic modes are to program each IO individually as input or output, inverted or non-inverted. The outputs can be set individually or by a common register (gpio_line). The enhanced modes of the GPIO module are related to one of the internal counters/timers or the global system time which is synchronized with a Real-Time network. This combination allows functions like:  Capture counter on edge or level  Capture counter once or continuously  Count external events (edges or duration of level)  Generate PWM with symmetric (triangle) or asymmetric PWM counter (sawtooth)  Generate PWM with schedule registers updated at counter=0 (hazard-free, requires a pair of GPIO pins)  DC-DC PWM: Generate PWM signal depending on the level of other GPIO input  Blink mode: Output of a predivided signal sequence (length: 1 to 32)  Watchdog mode: Generate IRQ, if input does not change in programmed time  Generate interrupt on external edge or level

The GPIO_APP module is accessible via 2 CPU busses on 2 address ranges. This allows ARM and xPIC to work fully parallel and without the influence of the other processor on different GPIOs. The interrupt registers exist twice: Visible registers in INTLOGIC_APP are connected to the ARM, visible registers in XPIC_APP_SYSTEM are connected to the xPIC. The registers of the GPIO_COM module are accessible via one CPU bus only. The ARM or XPIC can use these 4 IOs, but never simultaneously. Physical pad features like pull-up/down resistor, driving strength and input enable (should be low at floating inputs) are not part of the GPIO module. They will be configured in the PAD_CTRL module of the netX 90.

GPIO_APP gpio_cfg7 gpio_tc7 gpio_line GPIO_CTRL7

gpio_cfg6 gpio_tc6 irq_raw irq_mask GPIO_CTRL6 ARM IRQ_ARM

gpio_cfg5 gpio_tc5 irq_raw irq_mask GPIO_CTRL5 xPIC IRQ_XPIC

gpio_cfg4 gpio_tc4 GPIO_CTRL4 MATRIX SystemTime - gpio_cfg3 gpio_counter2_ctrl gpio_tc3 gpio_counter2_max gpio_counter2_cnt GPIO_CTRL3

GPIO_COUNTER2 CONNECT gpio_cfg2 gpio_tc2

gpio_counter1_ctrl GPIO_CTRL2 gpio_counter1_max gpio_counter1_cnt gpio_cfg1 GPIO_COUNTER1 gpio_tc1 GPIO_CTRL1

gpio_counter0_ctrl gpio_counter0_max gpio_cfg0 gpio_counter0_cnt gpio_tc0 GPIO_COUNTER0 GPIO_CTRL0

Figure 133: GPIO block diagram

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 170/275 5.6.2 Features  One GPIO module behaves as if each CPU had its own GPIO module, i.e. all registers of the GPIO module are accessible by different busses for different CPUs allowing a completely independent handling of sets of GPIO pins dedicated to different CPUs. Moreover, interrupt handling is duplicated for each CPU accessing the GPIO module.  You can combine GPIO pins with a set of counters within the GPIO module or global IEEE1588 system time, thus, allowing enhanced GPIO functionalities like PWM, capture, sequencing modes.  A single configuration bit can invert any GPIO functionality.  GPIO pin modes:  Read: Simply read a value.  Capture continuous: Capture a counter value at rising or falling edge of GPIO pin, generate an IRQ for each edge.  Capture once at edge: Capture a counter value at rising or falling edge of GPIO pin, wait for the CPU to reset the IRQ before next capture.  Capture once at level: Capture a counter value at high or low level or GPIO pin, wait for the CPU to reset the IRQ before next capture.  Write: Simply set to 0 or 1 (use read mode to set output to high-z).  Line mode: Set value to the respective bit in register gpio_line for an exactly synchronous change of multiple GPIO pins.  PWM: Use gpioX_tc registers as threshold value in combination with one of the internal counters for direct generation of PWM signal.  PWM2: Combine 2 gpioX_tc registers using one as shadow register for a hazard-free PWM generation.  Blink sequencer: Use one of the internal counters as clock divider to define a blinking frequency while a blink sequence is configured (length 1 to 32) in register gpioX_tc.  GPIO counter modes:  Maximum counter value is programmable.  Counter value is readable and writable at any time for use as system timer.  Count once (single shot) or count continuous mode programmable.  Symmetric (triangle: up - down) or asymmetric (sawtooth: up - reset) counting.  Interrupt generation programmable at zero crossing.  Count only on external level (0 or 1) of assigned GPIO pin.  Count only on external edge (rising or falling, not both) of assigned GPIO pin.  Watchdog mode: Assigned GPIO pin event (rising/falling edge or high/low level) resets counter, overflow generates an IRQ.  Automatic run mode: Assigned GPIO pin event (e.g. low level) starts counter for one period. This may be used for DC-DC PWM for assigning another GPIO pin in PWM mode to this counter.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 171/275 5.6.3 Typical applications  System timer  General purpose IO handled by software  IRQ generation based on external signals  Event counter  Event time capture  Active time measurement  PWM generation  Simple DC-DC PWM  Blink sequence generator (e.g. for LED signaling)  Sequence generator (e.g. transmission of UART packets)

5.6.4 Functional description The GPIO module consists of a set of GPIO pins and a set of GPIO counters. GPIO pins can be assigned to GPIO counters, and vice versa, allowing many enhanced modes that will be explained in the following chapters.

5.6.5 Simple read/write modes The simple IO-modes are "read", "set to 1", "set to 0" and "set to gpio_line". To switch the modes, write to the mode bits of the config register (gpio_cfgX.mode) of the GPIO pin. In read mode, the pad is not driving actively. This is the default mode after reset. The respective bit position of register address gpio_in always shows the pad input value. You can invert the input value by setting the bit gpio_cfgX.inv. The read values of all GPIO pins are collected in this register allowing exactly parallel read of multiple values. As gpio_in is a read-only register, it cannot conflict with other CPUs that may be accessing this register at the same time. The pad value is properly sampled with the system clock so that the register value will change with a delay of 15..25 ns in addition to the physical delay of input buffers and logic (~3 ns). In the modes "set to 0" and "set to 1", the single GPIO pad is set to output (zero or one). The mode "set to gpio_line" is similar, but set to the respective value of register gpio_line. The mode "set to gpio_line" is used to access multiple GPIO pads in parallel (as one word of data). The mode "set to gpio_line" should not be used (or with great care only) if several tasks or CPUs share the same GPIO module (s. chapter 5.6.15). The invert bit (gpio_cfgX.inv) may invert inputs and output functions. This inversion works in all modes, i.e. it is the function with the highest priority or closest to the physical pad.

GPIO GPIO_CTRLx

gpio_cfgX mode inv

gpio_in

0 1 gpio_line others 0 1 others

Figure 134: Simple IO logic

5.6.6 Counter as system timer The first netX versions (netX 500, netX 100, netX 50) used the GPIO counters as system timers. This is still possible, but we recommend using the GPIO_COUNTER modules for the enhanced functions of GPIO pins because all newer netX chips provide separate CPU timer modules. For a simple system timer function, you can program the GPIO_COUNTER to count up to a max. value (gpio_counterX_max) and to restart from zero thereafter. The counter runs at a system frequency of 100 MHz, i.e. for a typical system tick at 1 ms, set gpio_counterX_max to 99999. Activate bits run and irq_en in gpio_counterX_ctrl to generate an interrupt at every zero crossing (i.e. every 1 ms). You can set bit “once” in gpio_counterX_ctrl to let the counter stop after reaching zero and generate an interrupt (single shot mode). In this case you should restart the counter (e.g. after the interrupt routine is finished) by writing 1 to bit run again. As an alternative to internal GPIO counters, you can combine the global system time (sys_time) with all enhanced functionalities of GPIO pins. The global system time (a 32-bit value in ns) comes from the netX 90 SYSTIME_COM module. It is synchronized via Real-Time Ethernet according to IEEE1588.

5.6.7 Event time capture Each GPIO pin can be programmed for one of the three different capture modes which capture the time of an external event in register gpioX_tc. The following sections will explain the three capture modes and the different methods to be used by the CPUs. The time typically is the global system time (sys_time), but all internal GPIO counters can be captured (gpio_cfgX.count_ref) as well. All capture modes refer to the rising edge event. By inverting the GPIO pin (gpio_cfgX.inv) they work in the same way but referring to a falling edge event.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 173/275 5.6.7.1 Capture continued at rising edge In the mode "capture continued at rising edge" (gpio_cfgX.mode=1), the time is captured at every rising edge, regardless of whether the CPU has read the value. In other words, the CPU always gets the time of the last rising edge at this GPIO pin.

tCYC clk

GPIO0

tSAMPLE tSAMPLE tSAMPLE tSAMPLE gpio0_sampled

gpio_cfg.mode 0 1

gpio_irq_raw[0]

sys_time 10 20 31 41 51 61 71 81 91 101 111 121 131 141 151 161 171

tCYC gpio0_tc 61 111 161

Figure 135: Capture continued at rising edge

External GPIOx pins are sampled in a flip-flop running on the falling edges of 100 MHz system clock (tCYC = 10 ns) followed by a second flip-flop running on the rising edges. Assuming a pad input delay of 0..3 ns, the total sampling time tSAMPLE is between 5 ns and 18 ns. Register gpio_tcX will be updated in the following cycle of system clock.

5.6.7.2 Capture once at rising edge In the mode "capture once at rising edge" (gpio_cfgX.mode=2), the time is captured at the first rising edge and an interrupt bit (gpio_irq_raw[X]) is set. Further rising edges will be ignored until the CPU resets that interrupt bit. In other words, the CPU always gets the time of the first rising edge at this GPIO pin.

tCYC clk

GPIO0

tSAMPLE tSAMPLE tSAMPLE tSAMPLE gpio0_sampled

gpio_cfg.mode 0 2

gpio_irq_raw[0]

sys_time 10 20 31 41 51 61 71 81 91 101 111 121 131 141 151 161 171

tCYC gpio0_tc 61 161

Figure 136: Capture once at rising edge

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 174/275 5.6.7.3 Capture once at high level In the mode "capture once at high level" (gpio_cfgX.mode=3), the time is captured when the GPIO is on high level for the first time. The CPU has to reset the interrupt bit (gpio_irq_raw[X]) before the next capture can take place. If the CPU activates the sampling (switch to this mode or reset the interrupt) while GPIOx is low, there is no difference compared to the "capture once at rising edge" mode.

tCYC clk

GPIO0

tSAMPLE tSAMPLE tSAMPLE tSAMPLE gpio0_sampled

gpio_cfg.mode 0 3

gpio_irq_raw[0]

sys_time 10 20 31 41 51 61 71 81 91 101 111 121 131 141 151 161 171

tCYC gpio0_tc 20 161

Figure 137: Capture once at high level

5.6.8 Event counting For counting external events, the GPIO configuration register (gpio_cfgX) keeps its default values (read mode); only signal inversion may be set up there. The correlation of GPIO pin and counter is configured in the GPIO counter configuration register (gpio_counterX_ctrl.gpio_ref). In this register, bit field event_act must be set to 1 and bit sel_event to 1 (count rising edges, set gpio_cfgX.inv to count falling edges).

Note: The software always starts and finishes the counting of external events. A mode combining two counters for counting events within a given period of time is currently not implemented in the GPIO module.

tCYC clk

GPIO0

tSAMPLE tSAMPLE tSAMPLE tSAMPLE gpio0_sampled

gpio_counter0_ctrl.run

counter0_cnt 0 1 2 Figure 138: Counting rising edges of GPIO0

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 175/275 5.6.9 Active time measurement Each GPIO_COUNTER can be referenced to a GPIO (gpio_counterX_ctrl.gpio_ref). It can count only if the external signal is active (gpio_counterX_ctrl.event_act=1 and gpio_counterX_ctrl.sel_event=0). This is a simple implementation because the total time of this measurement cannot be programmed, i.e. the software must start and stop this measurement. To calculate the ratio of on/off time (tacho mode), we recommend using a second GPIO_COUNTER that counts continuously (gpio_counterX_ctrl.event_act=0) and that is started and stopped in parallel. Unfortunately, you cannot access the run bits of both counters (gpio_counterX_ctrl.run) with one single access. Therefore, the software should ensure that both accesses are performed in direct succession without interruption. In this case the GPIO structure with separate busses for each CPU is helpful, predictable, and accurate.

tCYC clk

GPIO0

tSAMPLE tSAMPLE tSAMPLE tSAMPLE gpio0_sampled

gpio_counter0_ctrl.run

counter0_cnt 0 1 2 3 4 5

gpio_counter1_ctrl.run

counter1_cnt 0 1 2 3 4 5 6 7 8 9 10 11 12 13

Figure 139: Active time measurement (e.g. GPIO0 is active in 5 of 13 clk cycles)

5.6.10 Watchdog mode To check for events at the pin within a defined time, combine an input pin with a counter. If the event does not appear within the programmed time, an IRQ will be generated. The event used to reset the counter can be one of rising edge, falling edge, high level, low level. To activate this mode, set the GPIO to input mode (gpio_cfgX.mode=0) and refer the counter to gpio_counterX_ctrl.gpio_ref. Select the event in gpio_counterX_ctrl.sel_event and gpio_cfgX.inv. Program the time within which the event is to occur to gpio_counterX_max (in steps of 10 ns). Activate interrupt (gpio_cnt_irq_mask_set) and watchdog mode (gpio_counterX_ctrl.event_act="10").

tCYC clk

GPIO0

tSAMPLE tSAMPLE gpio0_sampled

counter0_max 4

counter0_cnt 0 1 2 0 1 2 3 4 0 1 2 3 4 0

gpio_counter0_irq

5.6.11 Standard PWM Combining an output pin with a counter leads to a PWM function. The counter can count in the mode sawtooth (standard) or triangle (up-down). The gpio_tcX value defines the threshold when the GPIO output is switched on or off. You can reference multiple GPIOs to the same counter.

CLK

GPIO_COUNTER0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1

GPIO_TC0 2 5

GPIO0

GPIO_COUNTER1 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 0 1

GPIO_TC1 2 5

GPIO1

Figure 141: Triangle (GPIO1/COUNTER1) versus sawtooth (GPIO0/COUNTER0)

Figure 141 shows that the pulse width length is the same for triangle and sawtooth mode for same GPIO_TC values. GPIO_TC always defines the number of inactive cycles within a PWM period, regardless of the counter mode. In the mode sawtooth, this is quite simple: If GPIO_COUNTER is bigger than GPIO_TC (threshold), the GPIO output will be active. If it is smaller, the output will be inactive. To achieve the same relation of active phase length and GPIO_TC value, keep in mind that (compared with the mode sawtooth) the mode triangle internally works as follows: In the mode triangle, the GPIO_TC value is not directly compared with the counter, but its value is divided by 2. The LSB of GPIO_TC is relevant only at the rising edge of the GPIO_COUNTER, i.e. the LSB of GPIO_TC extends the inactive phase (see Figure 141).

Note: The PWM unit of the GPIO uses a greater-equal-comparator of counter and threshold value. Other PWM implementations may use only equal-comparator of counter and threshold value to reduce the amount of logic gates. Even though, the user should consider the states of PWM-output and counter when changing the threshold value or other PWM parameters during runtime.

5.6.12 PWM with shadow registers To ensure the intended behavior when changing the threshold, the GPIO_TC value should occur at the zero crossing of the related GPIO_COUNTER. Otherwise, a pulse length differing from the expected length may occur in the PWM period during which GPIO_TC is changed. As the intended behavior is difficult to ensure in software, the GPIO module has a second PWM mode (PWM2 mode) using shadow registers. To keep up the main idea of the GPIO module, this behavior is not realized by adding a second 32-bit register to every GPIO pin. Instead, the PWM with shadow register mode combines two GPIOs, using the other GPIO_TC register as an intermediate value which can be written by software at any time and which is updated at every zero crossing of the related GPIO_COUNTER.

gpio_cfg2 gpio_tc2

GPIO_CTRL2

gpio_cfg1 gpio_tc1

from GPIO_COUNTER PWM

GPIO_CTRL1

Figure 142: PWM with shadow register: GPIO1 used GPIO_TC register of GPIO2

Figure 142 shows an example of PWM with shadow register mode. GPIO1 performs a PWM function while GPIO_TC2 (at every zero crossing) is updating the GPIO_TC1 value. In this case, GPIO2 can still be used for standard GPIO functions, i.e. for all modes that do not use GPIO_TC2 register. The GPIO pins that can be combined for PWM with shadow register mode are fixed. The following tables show the assignment of GPIO performing the PWM and register GPIO_TC for shadow mode.

GPIO_APP performing PWM uses GPIO_APP_TC register

0 1

1 2

2 3

3 4

4 5

5 6

6 7

7 0 Table 26: Combinations of GPIO_APP pins in "PWM with shadow register mode"

GPIO performing PWM uses GPIO_TC register

0 1

1 2

2 3

3 0 Table 27: Combinations of GPIO pins in "PWM with shadow register mode"

Note: The combinations of GPIOs that can be used for PWM with shadow register mode differ from those used in earlier netX chips. In other netX chips it is not always the following GPIO.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 178/275 5.6.13 DC-DC PWM The DC-DC PWM mode combines two GPIO pads. One output is generating PWM pulses while another input is at (in)active level. From a hardware point of view, this is only a GPIO_COUNTER mode in which the counter is automatically restarted when the referenced GPIO input is (in)active (set gpio_counterX_ctrl bits: gpio_ref , event_act=3, once=1, sel_event=0). This mode was intended to supply a potential-free area with power as illustrated in Figure 143, but it has never been tested in a real application.

VDDA

gpio_cfg1 gpio_tc1

PWM

GPIO_COUNTER0 GPIO_CTRL1 GNDA

GNDB

gpio_cfg2 gpio_tc2 VDDB

GPIO_CTRL2 Vref GPIO GNDA GNDB GNDB netX

Figure 143: DC-DC PWM

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 179/275 5.6.14 Sequencer In the mode sequencer, a fixed sequence of max. 32 bits is output. The sequence is stored in register gpioX_tc. The register gpioX_cfg contains the length and the setting of the sequence which may be automatically repeated or not. The related counter defines the changing frequency within the programmed sequence.

gpio_cfg1 gpio_tc1

blink_sequence blink_len blink_once SEQ zero_crossing

GPIO_COUNTER0 GPIO_CTRL1

GPIO

netX

Figure 144: Sequencer logic

This mode was originally intended to generate LED blinking sequences using very slow (<42 s) changing sequences. Nevertheless, the mode sequencer works at frequencies up to 100 MHz (change output every 10 ns) and may be used for any kind of output sequences, e.g. UART frames.

CLK

GPIO_COUNTER0 -1 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2

counter_zero

gpio_blink_state1 0 1 2 3 4 5 6 7 8 9

GPIO1_TC "0100101101"

GPIO1 startbit 0 1 1 0 1 0 0 1 stopbit

Figure 145: Example sequencer output (UART frame "0x69" in 8n1@33 MHz)

Figure 145 shows the transfer of a single sequence (gpio_cfgX.blink_once=1). To start the next sequence (e.g. another UART frame), proceed as follows: 1. To reset the internal gpio_blink_state, change the mode to any other mode (gpio_cfgX.mode != "1000"). In this example the mode "set to 0" (gpio_cfgX.mode = "0100") would be a good choice. 2. Activate the blink mode by writing gpio_cfgX.mode = "1000". This directly starts the next single sequence.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 180/275 5.6.15 Sharing between different CPUs GPIO_APP is designed for different CPUs working on the same GPIO module without interference. For this purpose, each CPU has to use its own CPU bus selected by the address range used. In other words: If xPIC works on GPIO0..3 via address range gpio_xpic_app and ARM works on GPIO4..7 via address range gpio_app, ARM and xPIC can access independently and fully parallel.

xPIC gpio_cfg0

gpio_cfg1 ARM

gpio_tc0

data multiplexing gpio_tc1 / data multiplexing /

gpio_counter0_ctrl xPIC address decoding gpio_counter1_ctrl ARM address decoding

GPIO

Figure 146: Access of ARM and xPIC via separate CPU busses

When you work with different CPUs on the same GPIO module, the software has to make sure that each GPIO register is used by one CPU only. Should the faulty case occur that different CPU busses access a GPIO register in parallel, the access with the lower priority will get lost (xPIC has a higher priority than ARM).

Note: The present chapter and parts of the following chapter are irrelevant for netX 90 gpio_com and the old netX 50/100/500 GPIO modules because they are accessible by one CPU only.

5.6.16 Interrupt handling All interrupt registers of netX (except those in some very few modules not developed by Hilscher) use the same interrupt register scheme. In this scheme, up to 32 interrupts are handled in one set of interrupt registers. A set of interrupt registers consists of two physical registers (IRQ and mask register) that are accessed by four addresses, as described in the following text: The IRQ register will store incoming interrupts until the software processes them. This register is set automatically with the incoming interrupt. Once the software has handled an interrupt (incl. clearing the reason in case of level interrupts), it can reset bits of this register by writing '1' to the respective bit positions within the irq_raw address. Reading this address shows the status of the IRQ register. The mask register decides which interrupts are to be enabled, i.e. forwarded to the CPU. The addresses irq_mask_set and irq_mask_rst access the mask register because different software tasks may handle single bits of it. Writing '1' to bit positions of the irq_mask_set address sets the respective bit positions of the mask register. Writing '1' to bit positions of the irq_mask_rst address resets the respective bit positions of the mask register.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 181/275 Reading the address irq_mask_set or irq_mask_rst shows the status of the mask register. irq_masked is a read-only address and shows the status of interrupts enabled for the CPU (bitwise-AND of IRQ register and mask register).

IRQs from system

cpu_cs cpu_we_irq_mask_set cpu_we cpu_we_irq_mask_rst address cpu_a decoder cpu_we_irq_raw cpu_din

r s r s r s r s r s r s r s r s IRQ mask

q q q q q q q q

cpu_dout

cpu_irq

Figure 147: netX IRQ logic (exists once for each CPU address area)

As the GPIO is designed for different CPUs that use this GPIO module, a separate set of interrupt registers exists for each CPU. This set allows each CPU to enable or disable the desired interrupt events and to reset the interrupt after the software handled it. The interrupt registers for different CPUs have the same offset addresses. The address range (gpio_app or xpic_gpio_app) determines which set of interrupt registers becomes active.

5.6.17 I/O timing The I/O timing of the GPIO module strongly depends on the used mode. All modes are based on a 100 MHz system clock, sampling input data at falling edge, while data output is at rising edge. Additional pad delays should be negligible. However, they depend on operating conditions, pad position and external circuitry. The following table shows values for worst case operating conditions: VDD: 3.0 ... 3.6 V, Tj: -40 … +125°C and CL: 20 pF.

Symbol Parameter Min Typ Max Unit

tPin pad input delay 0 3 ns

tPout pad output delay 0 8 ns

tSAMPLE sample time incl. sample flip-flops 5 18 ns Table 28: I/O timing parameters

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 182/275 5.7 PIO (application) The netX 90 provides several programmable input / output lines for the APP CPU. Each of the PIO signals can be used as simple input or output.

Features  29 programmable input / output (application)  One input register, one output register  Input value can be inverted  Interrupt generation for input  rising edge  high level  Interrupt masking

Mapping The netX 90 PIO signals are mapped via pin sharing options:

PIO signal Option Pin HIF/MII signal PIO_APP0 3 B11 HIF_D0 PIO_APP1 3 C10 HIF_D1 PIO_APP2 3 B10 HIF_D2 PIO_APP3 3 A10 HIF_D3 PIO_APP4 3 C9 HIF_D4 PIO_APP5 3 B9 HIF_D5 PIO_APP6 3 A9 HIF_D6 PIO_APP7 3 C8 HIF_D7 PIO_APP8 6 F4 MII0_RXCLK PIO_APP9 6 J4 MII0_RXD1 PIO_APP10 6 H5 MII0_RXD2 PIO_APP11 6 G5 MII0_TXCLK PIO_APP12 6 J7 MII0_TXD0 / ADC2_IN7 PIO_APP13 6 J6 MII0_TXD1 / ADC3_IN4 PIO_APP14 6 H7 MII0_TXD2 / ADC2_IN4 PIO_APP15 6 H6 MII0_TXD3 / ADC3_IN5 PIO_APP16 6 D9 MII1_RXCLK PIO_APP17 6 G8 MII1_RXD1 / LVDS1_TXP PIO_APP18 6 F9 MII1_RXD2 / LVDS1_RXP PIO_APP19 6 H10 MII1_TXCLK / ADC2_IN2 PIO_APP20 6 J9 MII1_TXD0 / LVDS0_RXN PIO_APP21 6 J8 MII1_TXD1 / LVDS0_RXP PIO_APP22 6 H9 MII1_TXD2 / LVDS0_TXN PIO_APP23 6 H8 MII1_TXD3 / LVDS0_TXP PIO_APP24 6 K9 MII1_TXEN / ADC2_IN3 PIO_APP25 6 K8 MII_MDC / ADC2_IN5 PIO_APP26 6 L8 MII_MDIO / ADC2_IN6 PIO_APP27 6 L3 RST_OUT_N PIO_APP28 6 L9 CLK25OUT Table 29: PIO netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 183/275 5.8 BiSS/SSi 5.8.1 Overview The netX 90 provides two independent BiSS master modules. These BiSS modules are third party IPs customized for the netX 90. The additional logic they need is implemented in two BISS_CTRL modules, one for each BiSS module. This documentation describes the BISS_CTRL modules and the interconnection of the BiSS modules. For details on the BiSS master and its operation, see reference [7].

5.8.2 Functional description The configuration of both BiSS modules is identical:  32-bit APB (Advanced Peripheral Bus) slave bus interface for register and data access  Support of a single channel of up to 3 slaves (per BiSS module)  2 banks of sensor data  16-byte storage for register transfers  100 MHz input clock (netX system clock)

Since both BiSS modules (and their BISS_CTRL modules) are part of the App-side of the netX 90, they are connected to the App-side data switch. The BISS_CTRL modules implement interrupt logic and synchronization mechanisms for the two BiSS modules as well as the synchronization with the protocol stacks. The interrupt outputs of the BISS_CTRL modules are connected to the global interrupt logic which routes them to the ARM and xPIC CPUs of the App-side. For details, see the netX 90 interrupt documentation. Figure 130 shows an overview of the integration of one BiSS IP and the control module (BISS_CTRL) into the system.

protocol stack xc_trigger_out 0/1/inv GETSENS xc_sample_in 0/1/inv edge detector counter_zero[0..2] GPIO_APP BISS NER EOT manual trigger &

irq config regs & & interrupt logic BISS_CTRL

Figure 148: Block diagram

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 184/275 5.8.3 Trigger sources The BiSS module has internal triggering sources. For a description, see reference [7]. Additionally, the BiSS module has a trigger input signal (GETSENS). The BISS_CTRL module is able to route different kinds of trigger event signals to this input. The signals originate from the running protocol stack (either from netX-internal or external signals) and the counter of the App-side GPIO module. To trigger the BiSS module manually, write to a register in the BISS_CTRL module. The following signals are available for selection as trigger sources:  manual trigger  xc_trigger_out[1:0] (non-inverted & inverted)  xc_sample_in[1:0] (non-inverted & inverted)  gpio_app_counter_zero[2:0] The edge detector all signals run through reacts to rising edges only. The xc_trigger_out[1:0] and xc_sample_in[1:0] signals can thus be inverted right before the detector.

5.8.4 Interrupt logic The BiSS module provides two interrupt signals:  The active-low NER signal is set upon detection of an error  The active-high EOT signal is set upon completion of a transmission

The netX interrupt controllers are level-sensitive, but the EOT signal remains set as long as no further transmission starts. The NER signal shows a similar behavior. Since it is problematic to handle and clear such interrupts without re-triggering the interrupt immediately, the BISS_CTRL module detects edges on both signals (falling edges on NER and rising edges on EOT) and sets the corresponding interrupt bits in the standard netX interrupt logic. The logic consists of the following registers:  irq_raw  irq_masked  irq_msk_set  irq_msk_reset

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 185/275 5.9 EnDat 5.9.1 Overview The netX 90 provides two independent EnDat 2.2 basic master modules. These EnDat modules are third party IPs customized for the netX 90. The additional logic they need is implemented in two ENDAT_CTRL modules, one for each EnDat module. This documentation describes the ENDAT_CTRL modules and the interconnection of the EnDat IP modules. For details on the EnDat basic master and its operation, see reference [8].

5.9.2 Functional description The configuration of both EnDat modules is identical:  32-bit APB slave bus interface for register and data access  Support for recovery time measurement (RTM)  100 MHz input clock (netX system clock)

Since both EnDat modules (and their ENDAT_CTRL modules) are part of the App-side of the netX 90, they are connected to the App-side data switch. The ENDAT_CTRL modules implement synchronization mechanisms for the two EnDat modules as well as the synchronization with the protocol stacks. The interrupt outputs of the EnDat modules are connected to the global interrupt logic which routes them to the ARM and xPIC CPUs of the App-side. For details, see the netX 90 interrupt documentation. Figure 130 shows an overview of the integration of one EnDat IP and one trigger control module (ENDAT_CTRL) into the system. It also shows the cross-connection to the other EnDat module and the corresponding trigger control module.

Figure 149: Block diagram

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 186/275 5.9.3 Trigger sources The EnDat IP has internal triggering sources. For documentation, see reference [8]. Additionally, the EnDat IP has a trigger input signal (nstr). The ENDAT_CTRL module is able to route different kinds of trigger event signals to this input. The signals originate from the running protocol stack (either from netX-internal or external signals), the counter of the App-side GPIO module, and the other EnDat module. To trigger the EnDat module manually, write to a register in the ENDAT_CTRL module. The following signals are available for selection as trigger sources:  manual trigger  xc_trigger_out[1:0] (non-inverted & inverted)  xc_sample_in[1:0] (non-inverted & inverted)  gpio_app_counter_zero[2:0]  n_si and ntimer of the other EnDat module

5.9.4 Edge detector and pulse former The EnDat module meets the requirements on the form of the signal connected to the trigger input (nstr). An edge detector and a pulse former convert the netX system signals. The n_si and ntimer signals of the other EnDat module will be routed directly to the nstr signal if one of them is selected. The edge detector is used to prevent a multiple triggering in case of level-based trigger signals. The detector reacts to rising edges only. The xc_trigger_out[1:0] and xc_sample_in[1:0] signals can thus be inverted right before the detector. The output of the edge detector is connected to the pulse former. The ENDAT_CTRL module has two bit fields to configure the shape of the output of the pulse former. These bit fields must be configured to comply with the requirements of the nstr signal of the EnDat module. For details on the requirements, see reference [8], and the description of register strobe_cfg.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 187/275 5.10 CAN controller On the App-side of the netX 90 there are two integrated CAN controllers. They are designed to be compatible with SJA 1000. PeliCAN mode is supported, Basic mode is not.

5.10.1 Features  SJA1000 compatibility with PeliCAN mode  Extended receive buffer (64-byte FIFO)  CAN 2.0B protocol compatibility  Supports 11-bit and 29-bit identifier  Bit rates up to 1 Mbits/s  PeliCAN mode:  Error counters with read/write access  Programmable error warning limit  Last error code register  Error interrupt for each CAN-bus error  Arbitration lost interrupt with detailed bit position – Single-shot transmission (no re-transmission)  Listen only mode (no acknowledge, no active error flags)  Hot plugging support (software driven bit rate detection)  Acceptance filter extension (4-byte code, 4-byte mask)  Reception of message to be sent (self reception request)  CAN signals programmable to MMIO pin  BasicCAN of SJA1000 is not supported

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 188/275 5.11 UART The UARTs on the App-side are 16550-compliant with 16 bytes transmit and receive FIFOs. They can be configured to support speeds of up to 3.125 Mbaud. In mass production netX 90 will support speeds of up to 6.25 Mbaud. 1 of the 3 UARTs can either be accessed by the COM or the APP-side. The interface supports configurations of:  five, six, seven or eight data bit transfers  one or two stop bits  even, odd or no parity  IrDA SIR encoding and decoding The request-to-send (RTS) and clear-to-send (CTS) modem control signals also are available with the interface for hardware flow control. Special features like stick parity and adjustable FIFO trigger level are implemented. Since UART0 is commonly used as a diagnostic port, we do not recommend using it for other purposes, especially when using loadable Hilscher firmware.

SEL

TXD 0 Transmitt FIFO SIROUTn UART_TXD Transmitter 1 Bus Inter- 16 x 8Bit face, Access to all UART SEL registers RXD 0 Receive FIFO SIRIN UART_RXD Receiver 1 16 x 11Bit

BAUD16 RDALPBAUD16 UART_RTSn RTS/CTS IRQ_UART Interrupt Logic Control UART_CTSn

Baud Rate Generator

Figure 150: Block diagram of the UART

The ARM CPU reads and writes data and control/status information via the peripheral bus interface. The UART module can generate four individually-maskable interrupts which are combined to a single interrupt so that the output is activated if any of the individual interrupts are activated and unmasked. If a framing, parity or break error occurs during reception, the corresponding error bit is set and stored in the FIFO. If an overrun condition occurs, the overrun register bit will be set immediately and FIFO data will be prevented from being overwritten.

Baud rate generator The baud rate generator contains free-running counters which generate the internal Baud16 or IrLP-Baud16 signal. Baud16 or IrLPBaud16 provide timing information for UART transmit and receive control. Baud16 is a stream of pulses with a width of 10 ns and a frequency of sixteen times the baud rate.

Transmit FIFO The transmit FIFO is an 8-bit wide, 16-bit deep, first-in, first-out memory buffer. CPU data written across the bus interface is stored in the FIFO until read out by the transmit logic. The transmit FIFO can be disabled to act as a one-byte holding register.

Receive FIFO The receive FIFO is an 11-bit wide, 16-bit deep, first-in, first-out memory buffer. Received data and corresponding error bits are stored in the receive FIFO by the receive logic until read out by the CPU across the bus interface. The FIFO can be disabled to act as a one-byte holding register.

Transmitter The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. Control logic outputs the serial bit stream which begins with a start bit, data bits, least significant bit (LSB) first, followed by a parity bit, and stop bits according to the configuration programmed in the control registers.

Receiver The receive logic performs serial-to-parallel conversion on the received bit stream after the detection of a valid start pulse. Parity, frame error checking and line break detection are also performed, and the data with associated parity, framing and break error bits is written to the receive FIFO.

Interrupt logic Four individual maskable active HIGH interrupts are generated in the UART module and combined to one interrupt output. This output is generated as an OR function of the individual interrupt requests. The single combined interrupt is used with the system interrupt controller that provides another level of masking on a peripheral basis. This allows you to use modular device drivers which always know where to find the interrupt source control register bits.

IrDA SIR Endec The transmitter and receiver block contain an IrDA SIR protocol Endec. The SIR protocol Endec can be enabled for serial communication via signals nSIROUT and SIRIN to an infrared transducer instead of using the signals TXD and RXD. The SIR protocol Endec can both receive and transmit, but it is half-duplex only, so it cannot receive while transmitting, or vice versa. The SIR transmit encoder modulates the Non Return-to-Zero (NRZ) transmit bit stream. The IrDA SIR physical layer specifies the use of a Return to Zero, Inverted (RZI) modulation scheme which represents the logic 0 as an infrared light pulse. The modulated output pulse stream is transmitted to an external output driver and an infrared LED. In normal mode the transmitted pulse width is specified as three times the period of the internal x16 clock (Baud16), that is, 3 / 16 of a bit period. Low-power mode of the transmitted infrared pulse is set to 3 times the period of the internal generated IrLPBaud16 signal. The frequency of IrLPBaud16 signal is set by writing the appropriate divisor value to UARTILPR. The active low encoder output is normally LOW for the marking state (no light pulse). The encoder outputs a high pulse to generate an infrared light pulse representing a logic 0 or a spacing state. The SIR receive decoder demodulates the return-to-zero bit stream from the infrared detector and outputs the received NRZ serial bit stream to the internal logic. The decoder input is normally HIGH (marking state) in the idle state (the transmit encoder output has the opposite polarity to the decoder input).

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 190/275 A start bit is detected when the decoder input is LOW. Regardless of being in normal or low-power mode, a start bit is deemed valid if the decoder is still LOW, one period of IrLPBaud16 after the LOW was first detected.

UART communication Data received or transmitted is stored in two 16-byte FIFOs, the receive FIFO has 3 extra bits per character for status information. For transmission, data is written into the transmit FIFO. This causes a data frame to start transmission with the parameters indicated in UARTLCR. Data transmission continues until there is no data left in the transmit FIFO. The BUSY signal goes HIGH as soon as data is written to the transmit FIFO (that is, the FIFO is non-empty) and remains set to HIGH while data is being transmitted. BUSY is negated only when the transmit FIFO is empty and the last character has been transmitted from the shift register including the stop bits. BUSY can be set to HIGH even though the UART module may no longer be enabled. When the receiver is idle (RXD continuously 1, in the marking state) and a LOW is detected on the data input (a start bit has been received), the receive counter, with the clock enabled by Baud16, begins running and data is sampled on the 8th cycle of that counter (half way through a bit period). The start bit is valid if RXD is still LOW on the 8th cycle of Baud16, otherwise a false start bit will be detected and ignored. If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. If parity mode is enabled, the parity bit will be checked. Finally, if RXD is HIGH, a valid stop bit will be confirmed, if not, a framing error has occurred. If a full word has been received, the data will be stored in the receive FIFO, with any error bits associated to that word.

Error bits The three error bits are stored in bits 10:8 of the receive FIFO, and are associated to a particular character. There is an additional error which indicates an overrun error, but it is not associated with a particular character in the receive FIFO. The overrun error is set when the FIFO is full and the next character has been completely received in the shift register. The data in the shift register is overwritten, but it is not written into the FIFO. FIFO bits 7:0: received data FIFO bit 8: framing error FIFO bit 9: parity error FIFO bit 10: break error

Disabling the FIFOs Moreover, the FIFOs can be disabled. In that case, the transmit and receive sides of the UART module have 1-byte holding registers (the bottom entry of the FIFOs). The overrun bit will be set when a word is received and the previous word has not yet been read.

5.12.1 Introduction IO-Link is a new communication standard interface for sensors and actuators. IO-Link allows an inexpensive point-to-point connection between sensor/actuator and the I/O assembly for the "last meter to the process". IO-Link allows diagnosis and parameter information to be exchanged between sensor/actuator and the automation system in addition to the measurement signal through the specified communication mechanism, maximizing the performance of state-of-the-art intelligent sensors and actuators. The “IO-Link working group” under the umbrella of PROFIBUS International (PI) has initiated the specification for a “fieldbus-independent” communication interface for intelligent sensors and actuators in industrial automation. This document is based on version 0.96 of the IO-Link specification which is still stable regarding hardware requirements. An IO-Link Interface always uses a point-to-point topology and supports two or three physical wire interface (incl. power). It supports the following baud rates:

Port baud rates (fCLK) bit time (Tbit) Com1 4800 Baud 208.33 us Com2 38400 Baud 26.04 us Com3 230400 Baud 4.34 us Table 30: IO-Link Baud rates

IO-Link was designed as an open interface and can be integrated in all current communication systems in automation.

IO-LINK tx_oe 8 Byte TX Buffer controller wake_up (FSM) rxd TX/RX 4 Byte shifter txd RX Buffer ARM BUS Interface status / config register

int Interrupt generation

Figure 151: IO-Link: Block diagram of a single port

netX 90 IO-Link Master port 1 2 3 4 5 6 7 8 slave 8 slave 7 slave 6 slave 5 slave 3 slave 4 slave 2 slave 1

Figure 152: netX 90 with 8 IO-Link ports

Highlights of IO-Link:  Dynamical update of sensors parameters by an SPS  Service and online exchange of sensors  Uniform wiring of variable sensors / actuators  Uniform tools for parameterization

Industrial Ethernet / PROFINET Fieldbus

netX90

IO-LINK

sensors actuators

Figure 153: netX 90 IO-Link master interfacing

Features:  8 IO-Link ports (master)  TX-buffer size programmable to up to 8 byte  RX-buffer size programmable to up to 4 byte  Programmable interrupt capabilities (frame finished, tx finished, rx finished, wake up finished)  Loop frame transfer mode for continuous data transmission  Single frame transfer mode for debug and analysis  Automatic wake up generation

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 193/275 5.13 ADC Figure 154 shows the four 12-bit single-ended SAR ADC units of netX 90. Each of the 4 units operates independently. VSS_REF and VADC_REF supply the reference voltage for the analog-to-digital conversion. The selection of the reference voltage is programmable and can optionally be provided by the internal reference buffer (see electrical specification of ADC on page 225). For rail-to-rail operations, the reference voltage must be supplied externally.

3.3 V Bandgap REF_VBG ADC_REF Voltage netX 90 optional VREF_ADC

0 ADC1/2_IN0 1 ADC1/2 2 ADC1/2_IN1 S&H MUX 3 Internal

VSS_REF 0 ADC2/3_IN0 ADC2/3 ... MUX S&H 7 ADC2/3_IN7 GND

Figure 154: ADC block diagram

Each ADC unit consists of a controller, a sample & hold (S&H) circuit, and a multiplexer for analog inputs.

Unit Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7

ADC0 ADC0_IN0 ADC0_IN1 TSENS VREF_ADC - - - -

ADC1 ADC1_IN0 ADC1_IN1 VDDIO/2 VREF_ADC - - - - ADC2 ADC2_IN0 ADC2_IN1 ADC2_IN2 ADC2_IN3 ADC2_IN4 ADC2_IN5 ADC2_IN6 ADC2_IN7 ADC3 ADC3_IN0 ADC3_IN1 ADC3_IN2 ADC3_IN3 ADC3_IN4 ADC3_IN5 ADC3_IN6 ADC3_IN7 Table 31: Analog input channels

The ADC controller needs 14 cycles for the sequential digitizing of analog input signals: 2 for sampling and 12 for conversion. Users can program the ADC clock which determines the overall sampling rate. The sampling time, however, must be settled to 12-bit precision i.e. min 9τ (R x C) (input capacitance and serial resistance) is required. Depending on the selected ADC clock, the sampling time of 2 cycles may be insufficient and, therefore, requires extending. Example: The ADC input is driven by a low-ohmic shunt resistor, e.g. 200 mΩ. The RC-network needs a min. time of (Rin + Rext) x Cin x 9, with Rin being ADC_MUX_RSER and Cin being ADC_MUX_CIN. Assuming the ADC clock period is 30 ns (default setting is 70 ns), the settle time is (1.5 kΩ + 0.2 Ω) x 10 pF x 9 = 135 ns. The sampling time by default is 2 cycles, i.e. 2 x 30 ns = 60 ns. As a result, the sampling time must be extended. The additional delay can be programmed by register and calculated with tt_add = ceil( ( (Rint + Rext) x 9 x Cin / Period) - 2) = 3.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 194/275 5.14 Motion / motor control As illustrated in Figure 155, the netX 90 supports three-phase motor control applications. The on- chip peripherals enable the precise measurement of current, position, and speed as well as the synchronous driving of the 3-phase bridge inverter. The Cortex-M4 with DSP and FPU support, coupled with a dedicated xPIC, provides the bandwidth and infrastructure to perform all necessary operations and advanced algorithms for the closed-loop control system.

netX 90 Application Brake Chopper CPU & Memory Motion Peripherals u, nu u xPIC 100 MHz v, nv 3-Phase v MPWM Motor Inverter 8 KB D-TCM w, nw w 8 KB I-TCM FAULT 3x I

ADC0 ARM Cortex-M4 FPU 100 MHz ADC1 ... ADC ... DMA ADC2 sin Position, RAM Speed: 64 KB ECC cos Sensorless, Encoder, ADC3 ... HAL

Flash 2x QEI 512 KB ECC 2x SSI / BiSS iDPM to netX 90 Communication 2x EnDat2.2

Figure 155: MPWM motion icons

5.14.1 Target applications  Motors with integrated electronics  Basic frequency inverters / drives

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 195/275 5.14.2 Features  Two separate CPUs for motor control tasks  100 MHz ARM Cortex-M4F  Hardware FPU and DSP extension  512 KB Flash and 64 KB RAM Faster development and qualification of control algorithms in floating point  100 MHz xPIC 32-bit RISC  8x shadow registers for FIQ  32x32 single cycle MUL  2x 8 KB TCM High update rates e.g. for current controller  Internal DPM for data exchanges with communication protocol stack Single-cycle access to real-time data eliminates access latencies Hardware-assisted synchronization based on the distributed clock  6 + 1 channel motor PWM  10 ns resolution  “classic” center aligned mode  Automatic dead-time insertion, 0% and 100% duty cycle support  Software defined free form mode  Arbitrary dead time compensation algorithms  Update every half, full or nth period  Low to high PWM frequency with single IRQ per current control loop  Synchronization to Real-Time Ethernet, i.e. automatic (hard) or software controlled  FAULT input independent of clk  4x ADC with sample & hold  12-bit resolution and up to 2 MS/s  20 input channels (2+2+8+8)  Simultaneous measurement of 2 of 3 motor currents and one SinCos encoder 2 SinCos encoders  4x ADC controller with DMA  8 triggers per ADC  Triggers on PWM phase, 6 dead times or network Up to 32 (8x4) measurements per PWM (half) cycle with a single IRQ per current loop, e.g. motor currents, phase voltages, DC-Link, 2x SinCos, temperature, etc.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 196/275 5.14.3 Motion Pulse-Width Modulation (Motion PWM) 5.14.3.1 Overview On the application side, the netX 90 has a 10 ns resolution Motion Pulse-Width Modulation (Motion PWM) unit with 6 compare channels and 1 brake chopper channel. 3 dead time generator channels generate high and low-side signals from the direct output signals of compare channel 0, 1, and 2. The 6 output sections map the signals of the compare channels and dead time generators to the outputs of the Motion PWM unit. As a subcomponent of the Motion PWM, the prescaler serves to divide and determine the clock cycles during which the 16-bit configurable MPWM counter works. The Motion PWM enables the configuration of 4 modes: Sawtooth mode, inverse sawtooth mode, triangle mode, and inverse triangle mode. The shadow register mechanism enables synchronous updates of PWM periods and parameters. The MPWM unit is coupled with ADC and encoder units for motor current measurement, position measurement or encoder capture. The Motion PWM unit has a PWM counter, an event counter and an error condition input section.

5.14.3.2 Block diagram The Motion PWM unit is a peripheral device that enables the generation of pulse-width-modulated signals for the gates / gate drivers of a three-phase inverter that is typically used for driving a three- phase motor.

Figure 156: Motion PWM block diagram

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 197/275 5.14.3.3 Features  Six PWM output channels to control high-side / low-side drivers for three-phase motor control applications  Flexible dead time control: Automatic dead time generation or free-form mode  Powerful compare channels with two compare channels and user-configurable output multiplexer  Asynchronous and synchronous shutoff path for external error condition  Various interrupt sources: counter events, error conditions, rising/falling edges on output signals  Glitch-free configurable PWM parameter updates through shadow register mechanism  Brake chopper output

5.14.3.4 Prescaler The prescaler can be used to divide the system clock frequency by an integer for an effective counting frequency of the MPWM counter. The prescaler_step output signal of the prescaler determines the system clock cycles during which the MPWM counter will count. The prescaler does not generate any new clock signals. The prescaler consists of registers mpwm_cnt_ps_max and mpwm_cnt_ps. Register mpwm_cnt_ps_max specifies the max. value of register mpwm_cnt_ps.  If mpwm_cnt_ps is zero, the prescaler_step event will be active and mpwm_cnt_ps will be reset to mpwm_cnt_ps_max.  If mpwm_cnt_ps is not zero, mpwm_cnt_ps will be decremented and prescaler_step will be inactive. The CPU cannot write mpwm_cnt_ps. To reset mpwm_cnt_ps, use the restart bit of register mpwm_cmd. Example values for mpwm_cnt_ps_max:

Prescaling Counter will be updated 0 no prescaling with every clock cycle 1 by a divisor of 2 with every 2nd clock cycle 2 by a divisor of 3 with every 3rd clock cycle The prescaler is mainly of interest for long PWM periods which might otherwise be limited by the 16-bit length of mpwm_cnt and mpwm_cnt_max.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 198/275 5.14.3.5 PWM counter The PWM counter is a 16-bit wide configurable counter. The current value can be read from register mpwm_cnt. The value of mpwm_cnt is also used as an input for the 6 compare channels. The PWM counter can be configured for different counting modes via bits cnt_mode of register mpwm_cfg:  Sawtooth mode (Figure 157) The counter counts from 0 to mpwm_cnt_max and starts again from 0.  Inverse sawtooth mode (Figure 158) The counter counts down from mpwm_cnt_max to 0 and starts again at mpwm_cnt_max.  Triangle mode (Figure 159) The counter counts up from 0 to mpwm_cnt_max and then down to 0 again.  Inverse triangle mode (Figure 160) The counter counts down from mpwm_cnt_max to 0 and then up to mpwm_cnt_max again. Register mpwm_cnt_max can be written by the user to configure the counter range.

Periodic events The figures included in this document show the correct timings of the periodic events, but do not yet distinguish between the beginning and middle of a periodic event.  BOP (Beginning Of Period) BOP events occur at the beginning of each PWM period.  MOP (Middle Of Period) MOP events:  occur in triangle mode when mpwm_cnt is mpwm_cnt_max  occur in inverse triangle mode when mpwm_cnt is 0  do not occur in sawtooth  do not occur in inverse sawtooth mode  ECZ (Event Counter Zero) Event counter register mpwm_evt_cnt can be used to reduce the frequency of BOP events emitted by the MPWM module. If the field evt_cnt_top of register mpwm_cfg is set to a value N, an ECZ event will be sent every N+1 period. Underlying mechanism:  If a BOP event occurs and mpwm_evt_cnt is zero, an ECZ event will be emitted and mpwm_evt_cnt will be reset to evt_cnt_top.  If a BOP event occurs and mpwm_evt_cnt is not zero, no ECZ event will be emitted and mpwm_evt_cnt will be decremented.

Figure 157: Sawtooth mode Figure 158: Inverse sawtooth mode

Figure 159: Triangle mode Figure 160: Inverse triangle mode

5.14.3.6 Compare channels There are six compare channels: ch0...ch5. Each compare channel has two compare registers chx_cmp0 and chx_cmp1. Both compare registers are compared with mpwm_cnt to select the value of the direct PWM output signal.  If (cnt < chx_cmp0) and (cnt < chx_cmp1), the direct PWM output signal will be equal to chx_muxin.bl (counter value is below both compare values).  If (cnt >= chx_cmp0) and (cnt >= chx_cmp1), the direct PWM output signal will be equal to chx_muxin.ab (counter value is above both compare values).  If neither is the case, cnt is between chx_cmp0 and chx_cmp1 and the direct PWM output signal will be equal to chx_muxin.bt.

Figure 161: Compare channels

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 201/275 5.14.3.7 Dead time registers Three dead time generators generate high-side (HS) and low-side (LS) signals from the direct PWM output signals of the compare channels ch0, ch1, and ch2. The dead time generator generates a high-side signal whose polarity is identical with that of the direct PWM output signal and a low-side signal of the opposite polarity. In case of a rising or falling edge on the direct PWM output signal, the HS and LS signals will both be set to low for a number of cycles that is controllable by the user. The time during which both HS and LS signals are low is called dead time and can be configured via register mpwm_dt. The dead times for rising edges (transition from LS active to HS active) and falling edges (transition from HS active to LS active) may be different. The dead time generators generate an output only if the counter is running, otherwise HS and LS are 0.

Figure 162: Dead time generators

The edge detector compares the current value of the direct PWM signal with the value of the direct PWM signal at the previous prescaler step. If a rising edge occurs, bit rise_val of register mpwm_dt will be written to the dead time counter. If a falling edge occurs, bit fall_val of register mpwm_dt will be written to the dead time counter. The dead time counter is updated once per prescaler step. If no edge occurs on the direct PWM signal, it counts down until it reaches zero. The counter is continuously compared with zero. If the counter value is not equal to zero, the LS signal and the HS signal are both low.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 202/275 5.14.3.8 Shadow registers Shadow registers provide a mechanism to update all PWM periods synchronously with the beginning of a new PWM period or a similar event. This enables glitch-free and well controllable transitions in PWM parameters. Many registers of the MPWM module have corresponding shadow registers. If a shadow copy event occurs, all shadow registers (that have been written since the last shadow copy event) will simultaneously be loaded into their respective destination registers. The value of a shadow register that has not been written since the last shadow copy event will not be copied to the destination register.

Sources for shadow copy events sce_src_bop BOP1) If bit sce_src_mop of register mpwm_cfg is set, every MOP1) event will also be a shadow copy event. sce_src_ecz ECZ1) 1) Explanation, see Periodic events, section PWM counter on page 198.

5.14.3.9 Output sections The output sections map the direct PWM output signals of the compare channels and the high-side and low-side output signals from the dead time generators to the six outputs of the MPWM module.  To control the mapping, use the bits oe of register mpwm_ocfg.  To invert the polarity of each output, use the bits oinv of register mpwm_ocfg.

Figure 163: Output sections

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 203/275 Error condition input The output sections have an asynchronous and a synchronous shutoff mechanism. The asynchronous shutoff path is shown in red in the block diagram below The synchronous error condition unit has the following structure:

Figure 164: Error condition input

Edge detection circuits Each output section contains an edge detection circuit that can emit interrupts on rising or falling edges of each output.

5.14.3.10 Synchronization input Takes the sync_in input. A negative edge on the sync_in input is interpreted as a synchronization input event. The purpose of the sync_in input is to provide a mechanism to synchronize the PWM period to an external time reference, e.g., from a field bus. There are two mechanisms to achieve synchronization:  When bit sync_in_restart of register mpwm_cfg is set: The counter will be restarted (set to 0 or cnt_max depending on cnt_mode) if a synchronization event occurs.  When bit cnt_en_rs (enable read sync) of register mpwm_cfg is set: The values of counter and prescaler will be transferred to the appropriate fields in register mpwm_cnt_rs (read sync) if a synchronization event occurs. In this case the software can use this register to adjust the PWM period length to slowly compensate a clock drift.

5.14.3.11 Brake chopper output The brake chopper output BC is a single general purpose output bit with a shadow register bc_s.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 204/275 5.14.3.12 Interrupts and interrupt controller The Motion PWM module outputs a single IRQ signal to the host CPU. Internally it has multiple interrupt sources which can be enabled/disabled and checked via the interrupt controller of the module. This controller can be configured and queried via the IRQ_… registers. The following event-based interrupt sources are provided:  oede0, oede1, … oede5: Output section edge detector event bits  evt_ctr reaches zero (ECZ)  BOP  MOP The following level-based interrupt sources are provided:  eci_val (see error condition input diagram)  eci_ks_state (see error condition input diagram)

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 205/275 5.14.3.13 netX90 Motion PWM signals The netX 90 has 18 MMIO signals and 8 MPWM shared-with signals that are mapped via:  MII0_TXCLK  MII1_RXCLK  MII1_RXDV  MII1_TXD0 / LVDS0_RXN  MII1_TXD1 / LVDS0_RXP  MII1_TXD2 / LVDS0_TXN  MII1_TXD3 / LVDS0_TXP  RST_OUT_N

Pin Signal Shared with

Default Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8+9

G5 MII0_TXCLK MII0_TXCLK - - - IO_LINK2_OUT ETH_B_TXCLK PIO_APP11 MPWM_BRAKE -

F10 MII1_RXDV MII1_RXDV - - - IO_LINK6_IN - - MPWM_FAIL - D9 MII1_RXCLK MII1_RXCLK PHY1_FSD XM1_ECLK FB1CLK - - PIO_APP16 MPWM0 - J9 MII1_TXD0 / LVDS0_RXN MII1_TXD0 - XM1_TXOE XM1_TXOE_ECLK - SQI0_APP_CLK_B PIO_APP20 MPWM1 -

J8 MII1_TXD1 / LVDS0_RXP MII1_TXD1 - XM1_IO1 - IO_LINK4_OE SQI0_APP_CS0N_B PIO_APP21 MPWM2 - H9 MII1_TXD2 / LVDS0_TXN MII1_TXD2 - XM1_IO2 - IO_LINK5_OUT SQI0_APP_MISO_B PIO_APP22 MPWM3 - H8 MII1_TXD3 / LVDS0_TXP MII1_TXD3 - XM1_IO3 - IO_LINK5_OE SQI0_APP_MOSI_B PIO_APP23 MPWM4 - L3 RST_OUT_N RST_OUT_N - - - IO_LINK7_OUT PIO_APP27 MPWM5 - Table 32: Motion PWM shared-with signals

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 206/275 5.14.3.14 Connection with ADC and encoder units This MPWM unit is directly coupled with ADC and encoder units for exact sampling and synchronization of any measurement device (e.g. ADCs for motor current measurement, position measurement or encoder capture). For detailed information, see sections  BiSS/SSi on page 183  EnDat on page 185  ADC on page 193  Motion Encoder Interface / Quadrature Decoder on page 206

5.14.4 Motion Encoder Interface / Quadrature Decoder 5.14.4.1 Overview The quadrature encoder interface (QEI), sometimes also called quadrature decoder (QuadDec), is referenced in [1] as Motion Encoder (MENC) module. The module operates at a clock speed of 100 MHz (i.e. min. 10 ns resolution).

5.14.4.2 Features  2 quadrature encoder units  3 input channels (A, B and N) per encoder module  2 encoder filters  4 capture units  High resolution for more accurate determination of position or speed  Zero reference input for the precise determination of an absolute reference position  A digital glitch filter to reduce the impact of system-generated noise

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 207/275 5.14.4.3 Functional description The incremental encoder disk of an optical quadrature encoder pulse module is patterned with a track of slots which produce a light/dark-sequence while the disk is rotating (Figure 165). At a permanent rotating speed, the duration of the light/dark-pulses is identical. To indicate the direction of rotation, two different photo-elements read the pulses. These elements have a mechanical shift of ¼ of the length of a light/dark pair and generate signals A and B (shifted 90° out of phase).  Positive (clockwise) direction when signal A comes first.  Negative (counter-clockwise) direction when signal B comes first (Figure 167). For the precise determination of an absolute position, a third signal N is added, also called marker, home position or zero reference (Figure 166).

Positive direction: Signal A comes first

A Figure 165: Incremental encoder disk

B A Negative direction: Signal B comes first Figure 167: Pos. + neg. sequences of signals A + B B

Figure 166: Signals A, B, and N

5.14.4.4 Block diagram  Encoder 0 and 1 (Figure 168)  Filters for A, B, and N inputs for encoders 0 and 1  Filters for measurement point 0 and 1 inputs  2 decoder units for encoders 0 and 1  4 capture units

Figure 168: Encoder module block diagram

normal signal

signal with noise

Figure 169: Noises in signal

To suppress noise glitches, the encoder signals pass a digital filter which samples the input signals, compares the last five values with each other, and delivers the signal level which has the majority of these five signals

Clock

Filter in 0 0 0 0 1 0 1 1 1 0 1 0 0 0 0 Internal 0 0 0 0 0 1 0 1 1 1 0 1 0 0 0 filter X 0 0 0 0 0 1 0 1 1 1 0 1 0 0 states X X 0 0 0 0 0 1 0 1 1 1 0 1 0 X X X 0 0 0 0 0 1 0 1 1 1 0 1

X X X 0 0 0 0 1 1 1 1 1 0 0 0 Filter out

Figure 170: Digital filter at the encoder input signals

To enable the adaption to the max. frequency of the encoder signals (in register menc_config), you can set the filter sample rate for pulses to 10 ns, 20 ns, 50 ns, 100 ns, 200 ns, 500 ns, 1 us or switch the filter off completely.

Encoder Encoder 0 position register module

enc0_ovfl_pos Encoder 0 pulse counter enc0_ovfl_neg

Encoder 0 filter enc0_edge enc0_a Encoder 0 quadrature enc0_dir_ro enc0_b decoder unit enc0_phase_error

enc0_n enc0_n

Figure 171: Encoder module

enc0_a

enc0_b

enc0_edge

enc0_dir_ro

enc0_phase_error

Figure 172: Encoder phase error

5.14.4.7 Estimating velocity Since the encoder disk makes one rotation per motor revolution, the velocity is proportional to the frequency of the encoder pulses. If you know the number of pulses per disk rotation, you can recalculate the pulse frequency in relation to the velocity.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 211/275 5.14.4.8 Method 1 Method 1 is the conventional approach to estimate frequency by counting the whole number of pulses n within a certain time T0. It is the same as getting the difference between positions Xi-1 and Xi at the beginning and at the end of time T0.

Equation 1: f ≈ n / T0 = ΔX / T0 = (Xi - Xi-1) / T0 The error of frequency estimation increases with the decrease of frequency. The true frequency:

Equation 2: f = N / T0 = (n + Δn) / T0 = n / T0 + Δn / T0 = f0 + Δf0 The error:

Equation 3: δf = 100% * Δf0 / f0

By one pulse within a time T0 the frequency will be estimated with an error of 100% (Figure 173).

Figure 173: The same “n = 1” by different frequencies

5.14.4.9 Method 2 Method 2 is a more accurate approach to estimate frequency by measuring the time T between two pulses. Equation 4: f = 1 / T Method 2 produces more accurate results at low speeds. However, when the motor is running at high speeds with a high encoder disk resolution, the frequency of pulse and timer is comparable. It provides errors up to 100%. Velocity calculation will fail if the pulse frequency is higher than the timer resolution. For systems with a large speed range it would be reasonable to use method 1 at low speeds and method 2 at high speeds.

Method 3 combines methods 1 and 2 to get an average Tav between two pulses for a group of pulses within a certain time T0 (Figure 174). To estimate the frequency using method 3, you need the sum of times ta and te (time before the first encoder pulse (number of periods) and time after the last encoder pulse (number of periods).

Equation 5: Tav = (T1 + T2 + T3) / 3 = (T0 - (ta + te)) / (n - 1)

Equation 6: f = 1 / Tav = (n - 1) / (T0 - (ta + te))

Figure 174: Estimating average frequency within time T0 using method 3

Equation 6 gives f = 0 / 0 if only one impulse comes within a period T0. In this case it would be reasonable to set frequency f = 1 / T0.

5.14.4.11 Method 4 Method 4 is used to get the average frequency considering the time since the last pulse in the previous period T0 to the time of the last pulse in the present period. The values tei-1 and tei are needed (time after the last encoder pulse in the previous period and time after the last encoder pulse in the present period). Figure 175.

Equation 7: Tav = (T1 + T2) / 2 = (T0 - tei + tei-1) / n

Equation 8: f = n / (T0 - tei + tei-1)

Figure 175: Estimating average frequency within time T0 using method 4

The disadvantage of method 4 is that the average frequency is calculated for the group of pulses that were one pulse earlier in time. In Figure 176 the average frequency is calculated at the end of period T0 by using method 3 for pulses within time t1 and method 4 for pulses within time t2.

Figure 176: Difference between method 3 and 4

5.14.4.12 Ta/Te mode

A special Ta/Te mode allows a very precise determination of rotary speeds, especially at low speeds. Counter An-1 An (10ns cycle) An-1 T0

ta T te

Encoder (x4)

In-1 In

Figure 177: Ta/Te mode of Motion Encoder unit

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 214/275 5.14.4.13 netX 90 Motion Encoder signals The netX 90 has 18 MMIO signals and 8 Motion Encoder shared-with signals that are mapped via:  CLK25OUT  MII0_RXD3  MII0_RXDV  MII0_RXER  MII1_RXD0 / LVDS1_TXN  MII1_RXD1 / LVDS1_TXP  MII1_RXD2 / LVDS1_RXP  MII1_RXD3 / LVDS1_RXN

Pin Signal Shared with

Default Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8+9

L9 CLK25OUT CLK25OUT IO_LINK7_OE PIO_APP28 MENC_MP1 -

H4 MII0_RXD3 MII0_RXD3 IO_LINK2_IN ETH_B_RXD3 MENC0_A - G4 MII0_RXDV MII0_RXDV IO_LINK3_IN ETH_B_RXDV MENC0_B - F3 MII0_RXER MII0_RXER IO_LINK4_IN ETH_B_RXER MENC0_N - G9 MII1_RXD0 / LVDS1_TXN MII1_RXD0 PHY1_FRX XM1_RX MENC1_A - G8 MII1_RXD1 / LVDS1_TXP MII1_RXD1 PHY1_FTX XM1_TX XM1_TX_ECLK SQI0_APP_SIO2_B PIO_APP17 MENC_MP0 - F9 MII1_RXD2 / LVDS1_RXP MII1_RXD2 PHY1_FXEN XM1_IO0 SQI0_APP_SIO3_B PIO_APP18 MENC1_N - F8 MII1_RXD3 / LVDS1_RXN MII1_RXD3 IO_LINK5_IN MENC1_B - Table 33: Motion Encoder shared-with signals

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 215/275 5.15 Ethernet interface The netX 90 contains two Ethernet MACs with integrated PHYs. They support:  10Base-T / 100Base-TX  100Base-FX with external drivers  Auto-Negotiation  Auto-Crossover  Auto-Polarity They are fully compliant with IEEE 802.3 / 802.3u to run the protocols:  PROFINET RT and IRT  EtherNet/IP  Open Modbus/TCP Additional the Ethernet MAC includes special logic to support:  Time synchronization based on IEEE 1588  POWERLINK  EtherCAT  Sercos third generation For a schematic about how to connect one or two Ethernet interfaces, see reference [2].

Important: With applications that do not make use of the Ethernet interface, the PHY power must be connected (power has to be supplied and reference resistor has to be connected)! The schematic is shown in reference [2].

Real-time Ethernet In addition to the standard Ethernet function, the netX Ethernet channels support all current real- time Ethernet protocols. The different protocols use special functions: POWERLINK uses the HUB function to forward Ethernet telegrams. The protocol stack running on the ARM CPU helps avoid access conflicts on the Ethernet. To increase performance, the xPEC immediately answers a poll-request telegram with a poll-response telegram, without the interrupt latency that would occur if the ARM CPU were involved. EtherCAT forwards the Ethernet data immediately from one port to another and takes out or fills in the local data. The xMACs are therefore directly connected with each other. Moreover, they have a special filter function to identify the local data within Ethernet frames. The xPEC is responsible for the transfer into and out of the ARM memory. Current features:  Slave implementation  6.5 KByte process data memory  8 SyncManager units  8 FMMUs (fieldbus memory management unit, support only byte-wise mapping)  Mailbox functionality for CANopen over EtherCAT, Ethernet over EtherCAT  Powerful AL controller integrated Sercos uses the same filters and the state machines which are defined by the sercos international e.V.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 216/275 EtherNet/IP uses only the standard Ethernet functions of one channel. However, for motion control with synchronization down to a microsecond, the distributed time according to the international Standard IEEE 1588 is used. This means, to measure transmit and receive time by hardware at the MII interface between xMAC and PHY, using a special protocol, this information is exchanged between the network devices and the local system time is adjusted to a common network time. The real-time communication of PROFINET uses a switch function and priority control according to IEEE 802.1Q. For this the xPECs owns local memory to manage the routing data and a state machine to control the telegram transfers. The transfer time through the internal switch is less than 3 µs. For motion control, PROFINET uses isochronous transmission. This requires synchronization of the local time by IEEE 1588 and transmission of the telegrams results according to a time table. This time control is another mode of the xPEC state machine. The netX is fully compliant to the PROFINET IRT specification. These features allow device manufactures to use a unified hardware, activating the special real- time Ethernet functions by appropriate software, as required. Ethernet Channel 0 Ethernet Channel 1

PHY PHY

IEEE 1588 Time Stamp

HUB

xMAC xMAC

Switch xPEC xPEC Memory

ARM CPU Peripheral Memory

Figure 178: Block diagram of the special real-time Ethernet features

Note: For a better understanding, the data switch is not shown.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Interfaces 217/275 5.16 Fieldbus interface The XMAC/XPEC units of the netX can operate as fieldbus controllers (one XMAC and one XPEC per fieldbus channel), for virtually any existing and future fieldbus system, like:  CANopen Slave  CC-Link Slave  DeviceNet Slave  PROFIBUS DP Slave Different systems can be combined. For schematics about how to connect a fieldbus interface, see reference [2].

JTAG debug interface The netX debug interface is based on the Joint Test Action Group (JTAG) IEEE Standard 1149.1 and supports debugging tools compliant with this standard. The chip supports 3 security levels:  development  authenticate  immutable

Symbol Parameter Conditions Min. Typ. Max. Unit

VDDIO Supply voltage IO - 3.0 3.3 3.6 V

VOH0 Output voltage, high Drive strength 4 mA 2.4 3.1 V

VOH1 Drive strength 8 mA 2.4 3.0 V

VOL0 Output voltage, low Drive strength 2 mA 0.15 0.4 V

VOL1 Drive strength 4 mA 0.2 0.4 V

VTH Input threshold (for all pads Pull-up/pull-down on or off 38 43 48 %VDDIO with Schmitt trigger)

VLH Rising edge threshold (for Pull-up/pull-down on or off 45 50 55 %VDDIO all pads with Schmitt trigger)

VHL Falling edge threshold (for Pull-up/pulldown on or off 32 37 42 %VDDIO all pads with Schmitt trigger)

RPU Intrenal pull-up resistor VDDIO = 3.3 V 56 77 116 kΩ

RPD Internal pull-down resistor VDDIO = 0 V 55 90 144 kΩ

IOZ Input/output leakage current VDDIO = 0…3.3 V -10 10 µA Table 34: Eletcrical specification

Absolute maximum ratings

Symbol Parameter Conditions Min Typ Max Unit

VDDIO – VSS - - -0.3 - 4 V Table 35: Absolute maximum ratings

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Electrical specification 220/275 7.2 Current consumption The supply current consumed by the netX 90 during normal operation depends on several factors such as applied device configurations, software uses cases and operating temperature conditions that determine for both segments of the chip the utilized CPU load, memory usage and peripheral set with I/O pin load switching.

Figure 179: Current consumption measurement

The current consumption as summarized in Table 36 was measured as outlined in Figure 179 under the following conditions:

Communication side  PROFINET IO-Device communication with a PROFINET IO-Controller  Cyclic real-time Ethernet communication  Dual Ethernet PHY operating in 100BASE-TX mode  Short cycle time with payload creating high CPU loads  Protocol stack execution  Instructions fetching from on-chip flash memory  Dynamic SRAM memory allocation for data handling  Synchronized internal DPM data exchange with application  DPM channel 0 for real-time protocol (PROFINET)  DPM channel 1 for standard TCP/IP (web server)

Application side  PROFINET IO-Device application profile with Hilscher cifX API  Real-time operating system with web server for I/O application  Instructions fetching from external 16-bit SDRAM  Operating at 100 MHz clock speeds  High I/O pin load switching  Synchronized internal DPM data exchange with communication  DPM channel 0 for real-time protocol (PROFINET)  DPM channel 1 for standard TCP/IP (web server)  Web browser session content streaming from SQI Flash  Clock-gated on-chip application peripheral units enabled

Note: The setup was selected to make those components visible that noticeably contribute to the overall power budget, i.e. I/O load external memory, dual-port Ethernet PHY, etc.

Supply Parameter Conditions Tj = 45 °C Tj = 105 °C

IVDDIO Supply current IO domain VDDIO = 3.3 V 130 mA 145 mA

IVDDC Supply current core domain VDDC = 1.2 V 155 mA 170 mA

IPHY_VDDIO Supply current IO dual Ethernet PHY PHY_VDDIO = 3.3 V 80 mA 80 mA

IPHY_VDDC Supply current core dual Ethernet PHY PHY_VDDC = 1.2 V 55 mA 60 mA Table 36: Measured current consumption

Electrical specification

Symbol Parameter Condition Min Typ Max Unit

VDD_PLL Supply voltage PLL - 1.14 1.2 1.32 V

VIL Input voltage, low Note 1 0.8 V

VIH Input voltage, high Note 1 2.0 V

VOL Output voltage, low +8 mA / Note 1 0.4 V

VOH Output voltage, high -8 mA / Note 1 2.4 V

VITH Input voltage, threshold - 38 43 48 %VDDIO

fCLK Crystal clock frequency Note 2 25 MHz

TCLK Clock cycle time - 40 ns

TCTL Clock tolerance - -100 +100 ppm

TCDC Clock duty cycle Note 2 40 50 60 %

TCJT Clock jitter tolerance - 20 ps [RMS

Rf Integrated feedback resistor - 0.97 1.2 1.46 MΩ

CIN Pin capacitance OSC_XTI - 3.4 4 4.6 pF

COUT Pin capacitance OSC_XTO - 1.7 2 2.3 pF Table 37: Eletcrical specification

Note: 1. These values are DC parameters that do not apply to the dynamical system of a crystal circuit. When using crystals, the circuit should be designed in a way that keeps the levels within the absolute maximum ratings (-0.3 V to VDDIO +0.3V).

2. fCLK must be supplied by crytsal or external oscillator. If external oscillator is used, make sure that the duty cycle is better than 46% to 54% with lower jitter performance.

Absolute maximum ratings

Symbol Parameter Conditions Min Typ Max Unit

VDD_PLL – VSS - - -0.3 - 1.4 V Table 38: Absolute maximum ratings

Figure 180: DC/DC converter with POR

General operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VDDIO Supply voltage IO Note 2 3.0 3.3 3.6 V

VDDC Supply voltage core 1.14 1.2 1.32 V POR_LH POR low to high Ramp from 0 to 3.3 V 2.7 2.77 2.87 V POR_HL POR high to low - 2.64 2.71 2.78 V POR_P Pulse length to pass the POR - 5 - 20 µs glitch filter POR_R Release pulse extension of - 150 - 300 µs POR glitch filter PWC_LH Power watch core low to high Ramp from 0 to 1.2 V 0.99 1.02 1.05 V PWC_HL Power watch core high to low - 0.92 0.97 1.00 V - Soft start-up ramp Note 1 2 3 4.5 V/ms - Start-up done threshold 99 % Table 39: General operating conditions

Note 1: The output voltage of the DC/DC converter rises slew-rate limited. To reduce the current needed to charge the output capacitor, the soft start-up ramp generator ensures that the digital core starts after the ramp reached 99% of VDDC, e.g. (0.99 × 1.2 V) / 2 V/ms = 594 µs.

Figure 181: Power up and down

Note 2: Please ensure that VDDIO is larger than VDDC during power up and down in case the integrated DC/DC converter is not used and VDDC is supplied separately using an external power supply. In this case, the DCDC_LX_OUT pin must be left unconnected.

Absolute maximum ratings

Symbol Parameter Conditions Min Typ Max Unit

VDDIO – VSS - - -0.3 - 4 V

VDDC – VSS - - -0.3 - 1.4 V

TJ Junction temperature - -40 - +125 °C Table 40: Absolute maximum ratings

7.5 BOD

Electrical specification

Symbol Parameter Conditions Min Typ Max Unit BOD DC voltage - 0 3.6 V BOD_T BOD threshold - 1.11 1.13 1.16 V BOD_H BOD hysteresis - 41 60 74 mV BOD_P Min. pulse length needed to - 5 20 µs pass the glitch filter of BOD Table 41: Electrical specification

Absolute maximum ratings

Symbol Parameter Conditions Min Typ Max Unit

BOD - VSS - - -0.3 - 4 V Table 42: Absolute maximum ratings

Electrical specification

Symbol Parameter Conditions Min Typ Max Unit ADC_RES Resolution 12 Bits

ADC_ENOB ENOB FIn = 50 kHz 10.5 Bits ADC_INL INL -2 2 LSB ADC_DNL DNL -1 2 LSB ADC_OFSERR Offset Error 1) -15 15 LSB ADC_GAINERR Fullscale Gain-Error 1) -5 5 LSB ADC_SRATE Minimal tracking phase of 2 1 / MSa/s cycles used (ADC_CLK×14) ADC_CLK ADC clock period Programmable 30 90 ns ADC_MUX_CIN Input Capacitance ADC0 and 10 pF ADC1 ADC_MUX_CIN Input Capacitance ADC2 and 12 pF ADC3 ADC_MUX_RSER Serial Resistance 1.5 kΩ ADC_WARMUP Warm Up Time ADC_ENABLE 0 →1 10 μs ADC_REF Intrenal Reference Voltage T=27 °C 2.55 2.6 2.65 V ADC_REF_TC Reference Voltage TC 110 ppm/K

VREF_ADC External Reference Voltage 3.3 V Table 43: Electrical specification

Note

1. Gain and Offset Error are measured against voltages on pins VREF_ADC and VSS_REF

Absolute maximum ratings

Symbol Parameter Conditions Min Typ Max Unit

VREF_ADC - VSS_REF - - -0.3 - 4 V Table 44: Absolute maximum ratings

Note: Devices are shipped with Flash memory erased.

Symbol Parameter Conditions Min Typ Max Unit

TPROG Byte programming time Tj = -40 to +125°C 20 - 40 µs

TERASE Page (4 KB) erase time Tj = -40 to +125°C 20 - 40 ms

TME Mass (512 KB) erase time Tj = -40 to +125°C 20 - 40 ms

IDDIO Supply current Write / Erase mode, VDDIO = 3.3V - - 3 mA Table 45: Flash memory block programming

Symbol Parameter Conditions Min Typ Max Unit - Endurance Tj = -40 to +125°C 10,000 - - cycles - Data retention 10,000 cycles at Tj = 125°C 10 - - years Table 46: Flash memory block characteristics

7.8 Ethernet PHY

Note: Power supplies must always be connected even if the dual PHY is not used.

Symbol Parameter Conditions Min. Typ. Max. Unit

PHY_VDDIO Supply voltage IO 3.0 3.3 3.6 V

PHY_VDDC Supply voltage core 1.14 1.2 1.32 V PHY_EXTRES Reference resistor Must always be connected, 6.49 kΩ / 1 % Table 47: Electrical specification

Absolute maximum ratings

Symbol Parameter Conditions Min Typ Max Unit

PHY_VDDIO – VSS - - -0.3 - 4 V

PHY_VDDC – VSS - - -0.3 - 1.4 V Table 48: Absolute maximum ratings

100BASE-TX

Symbol Parameter Conditions Min. Typ. Max. Unit

V100OUTH TX output, high level 0.95 1.05 V differential signal, TXP/TXN

V100OUTL TX output, low level -0.95 -1.05 V differential signal, TXP/TXN

V100OUTM TX output, mid. level -0.05 +0.05 V differential signal, TXP/TXN

V100INTHON RX input, turn-on threshold level 1.0 V differential signal, RXP/RXN

V100INTHOFF RX input turn-off threshold level 0.20 V differential signal, RXP/RXN

tr Rise time, TXP/TXN 3 5 ns

tf Fall time, TXP/TXN 3 5 ns - Duty cycle distortion, TXP/TXN 0 0.5 ns(pp) - Transmit jitter, TXP/TXN 0 1.4 ns(pp) These specs are compliant with ANSI/IEEE802.3 Std.

10BASE-T

Symbol Parameter Conditions Min. Typ. Max. Unit

V10OUT TX output amplitude 2.2 2.8 V differential signal, TXP/TXN

V10INTH RX input threshold level 0.30 0.585 V differential signal, RXP/RXN These specs comply with ANSI/IEEE802.3 Std.

MMIO level change: low to high MMIO level change: high to low

internal clock root

tHL tLH MMIOx

Figure 182: MMIO level change

MMIO output enable: hiZ to high MMIO output enable: hiZ to low

internal clock root

tenH tenL

MMIOx

Figure 183: MMIO output enable

MMIO output enable: hiZ to high MMIO output enable: hiZ to low

internal clock root

tdisH tdisH

MMIOx

Figure 184: MMIO output disable

Parameter Description Signal Min Typ. Max. Unit

tLH Output low to high level change time MMIO0 … MMIO15 7 16 ns

tHL Output high to low level change time MMIO0 … MMIO15 6 14 ns

tenH Output enable hiZ to high level time MMIO0 … MMIO15 7 16 ns

tenL Output enable hiZ to low level time MMIO0 … MMIO15 6 10 ns (1) (1) tdisH Output disable high level to hiZ time MMIO0 … MMIO15 3 6 ns (1) (1) tdisL Output disable low level to hiZ time MMIO0 … MMIO15 3 9 ns

tSH High level input sampling time MMIO0 … MMIO15 0.5 2 ns

tSL Low level input sampling time MMIO0 … MMIO15 0.5 2 ns Table 44: MMIO min./max. timing values

Note

1. Output driver disabling is externally propagated after tdisH (or tdisL). If no other device drives the corresponding MMIO line, a previously driven high level will persist for some time due to capacitive loads (depending on pull-up / pull-down resistors).

7.11 External SRAM / FLASH See sections SRAM / Flash timing (page 57) and IO timing parameters for SRAM (page 58).

7.12 Parallel dual-port memory See section Parallel dual-port memory timing on page 93.

7.13 Serial dual-port memory See section Serial dual-port memory timing (page 123).

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Electrical specification 230/275 7.14 QSPI The QSPI module I/O timing depends on pad delays and the internal module structure. All timings are related to an internal system clock running at 100 MHz. The following figures show the timing for standard SPI mode. Regarding the transfer direction, timing parameters are identical for Dual and Quad SPI mode: In receive mode timing for SPI_MISO can be applied to all I/O lines. In transmit mode timing for SPI_MOSI can be applied to all I/O lines. In SQIROM mode timing from SPI Mode 0 (SPO=0, SPH=0) can be applied, but the max. SPI_CLK frequency is increased to 133 MHz.

tCH tCL tCP SPI_CLK

tCSS tF tR tCSH tCSW SPI_CS_N

tR tF tMOSIS tMOSIS tMOSIS SPI_MOSI MSB LSB MSB SIO[3:0] tx tMOSIH tMOSIH tMOSIH tMOSIHZ tMISOS tMISOS tSPW tMISOS SPI_MISO MSB LSB MSB SIO[3:0] rx tMISOH tMISOH tMISOH

Figure 185: SPI timing SPO=0 and SPH=0 transfer (data generation on falling edge, sampling on rising edge of SPI_CLK)

tCH tCL tCP SPI_CLK

tCSS tF tR tCSH tCSW SPI_CS_N

tR tF tMOSIS tMOSIS tMOSIS SPI_MOSI MSB LSB MSB SIO[3:0] tx tMOSIH tMOSIH tMOSIH tMOSIHZ tMISOS tMISOS tSPW tMISOS SPI_MISO MSB LSB MSB SIO[3:0] rx tMISOH tMISOH tMISOH

Figure 186: SPI timing SPO=0 and SPH=1 transfer (data generation on rising edge, sampling on falling edge of SPI_CLK)

tCL tCH tCP SPI_CLK

tCSS tR tF tCSH tCSW SPI_CS_N

tR tF tMOSIS tMOSIS tMOSIS SPI_MOSI MSB LSB MSB SIO[3:0] tx tMOSIH tMOSIH tMOSIH tMOSIHZ tMISOS tMISOS tSPW tMISOS SPI_MISO MSB LSB MSB SIO[3:0] rx tMISOH tMISOH tMISOH

Figure 187: SPI timing SPO=1 and SPH=0 transfer (data generation on rising edge, sampling on falling edge of SPI_CLK)

tCL tCH tCP SPI_CLK

tCSS tR tF tCSH tCSW SPI_CS_N

tR tF tMOSIS tMOSIS tMOSIS SPI_MOSI MSB LSB MSB SIO[3:0] tx tMOSIH tMOSIH tMOSIH tMOSIHZ tMISOS tMISOS tSPW tMISOS SPI_MISO MSB LSB MSB SIO[3:0] rx tMISOH tMISOH tMISOH

Figure 188: SPI timing SPO=1 and SPH=1 transfer (data generation on falling edge, sampling on rising edge of SPI_CLK)

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Electrical specification 232/275 The following values are valid for the netX 90 when the module is in normal peripheral mode (not in SQIROM/ XiP mode, i.e. the enable bit of register sqi_sqirom_cfg is not set). They refer to worst case operating conditions: VDDIO: 3.0 ... 3.6 V, Tj: -40 ... +125°C, CL: 20 pF.

Symbol Parameter Min Typ Max Unit (1) tCP SPI_CLK period 20.0 10*4096/N 40960 ns (1) fCP SPI_CLK frequency 0.025 50.0 MHz

tCH SPI_CLK high phase 0.5*tCP-3.0 ns

tCL SPI_CLK low phase 0.5*tCP-3.0 ns (2) tR Signal rise time 0.4 3.4 ns (2) tF Signal fall time 0.3 2.0 ns

tCSS SPI_CS_N to first SPI_CLK edge setup time 0.5*tCP-3.0 ns

tCSH last SPI_CLK edge to SPI_CS_N ns inactive time (3) - SPH 0 modes 7.0 - SPH 1 modes 0.5*tCP+7.0 (3) tCSW SPI_CS_N minimum high pulse width 0.5*tCP-3.0 ns

tMOSIS SPI_MOSI (SPI_SIO3:0] transmit) to SPI_CLK setup 0.5*tCP-3.4 ns time

tMOSIH SPI_MOSI (SPI_SIO[3:0] transmit) hold time 0.5*tCP-3.0 ns

tMOSIHZ SPI_MOSI (SPI_SIO[3:0] transmit) high-Z time 3.5 ns

tMISOS SPI_MISO (SPI_SIO[3:0] receive) to SPI_CLK setup 2.5 ns time

tMISOH SPI_MISO (SPI_SIO[3:0] receive) hold time ns - without input filtering 4.5 - with input filtering(4) 14.5

tSPW Tolerated spike pulse width ns - without input filtering 0.0 - with input filtering(4) 9.0

Rise times: tr = 0.350 + 0.150 * CL [ns]; CL: External capacitive load

Fall times: tf = 0.237 + 0.087 * CL [ns]; CL: External capacitive load 3. Only for automatic chip-select generation (if bit fss_static is not set in register spi_cr1/sqi_cr1). 4. Input filtering can be enabled/disabled in register spi_cr0/sqi_cr0 by bit filter_in.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Electrical specification 233/275 The following values are valid for the netX 90 when the module is in SQIROM/XiP mode (not in normal peripheral mode, i.e. the enable bit of register sqi_sqirom_cfg is set). They refer to worst case operating conditions: VDDIO: 3.0 ... 3.6 V, Tj: -40 ... +125°C, CL: 20 pF. Only mode 0 and 3 are supported in SQIROM/XiP mode.

Symbol Parameter Min Typ Max Unit (1) tCP SPI_CLK period 7.5 (N+3)*2.5 645 ns (1) fCP SPI_CLK frequency 1.55 133.0 MHz

tCH SPI_CLK high phase 0.5*tCP-3.0 ns

tCL SPI_CLK low phase 0.5*tCP-3.0 ns (2) tR Signal rise time 0.4 3.4 ns (2) tF Signal fall time 0.3 2.0 ns (3) tCSSr SPI_CS_N active to first rising SPI_CLK edge setup time tCP-1.0 ns (3) tCSHr last rising SPI_CLK edge to SPI_CS_N inactive time tCP-1.0 ns (4) tCSW SPI_CS_N minimum high pulse width tCP-3.0 I*tCP-3.0 4*tCP-3.0 ns

tMOSIS SPI_MOSI (SPI_SIO[3:0] transmit) to SPI_CLK setup time 0.5*tCP-2.6 ns (6) tMOSIH SPI_MOSI (SPI_SIO[3:0] transmit) hold time 0.5*tCP-1.2 ns

tMOSIHZ SPI_MOSI (SPI_SIO[3:0] transmit) high-Z time 3.5 ns

tMISOS SPI_MISO (SPI_SIO[3:0] receive) to SPI_CLK setup time 0.3 ns (7) tMISOH SPI_MISO (SPI_SIO[3:0] receive) hold time 2.1 ns (5) tSPW Tolerated spike pulse width 0.0 ns

Notes: 1. N is programmed by sqi_sqirom_cfg register clk_div_val bits. N = 0...255. This leads to a frequency up to 133 MHz. 2. Signal rise and fall times differ greatly depending on external capacitive load. For approximation, see note 2 of the peripheral mode IO timing above. 3. The chip-select timing of QSPI devices is typically related to the rising edge (as described). However, for mode 0 a falling edge is generated 0.5*tCP before chip-select becomes inactive (at transfer end) and for mode 1 and a falling edge is generated 0.5*tCP after chip select becomes active (at transfer start). 4. The min. chip-select idle time can be programmed by bit t_csh of register sqi_sqirom_cfg. Between 1 and 4 SPI clock cycles can be selected (I). The device will not be deselected if no XiP access is desired. The SPI_CLK line will be held inactive instead. To disable the chip- select for longer times (e.g. for power save) switch to peripheral mode. A device will always be selected at least until the first 4 byte of data have been received in quad-IO-read (i.e. at least for 14 serial clock periods with a running serial clock). 5. Input filtering is not available in SQIROM/XiP mode.

6. The tMOSIH value 0.5*tCP-3.0 ns of earlier versions of this document was too pessimistic and has been corrected in this version.

Master mode

Figure 189: SPI master signal timing (SPO=0 and SPH=0)

Figure 190: SPI master signal timing (SPO=0 and SPH=1)

Figure 191: SPI master signal timing (SPO=1 and SPH=0)

Figure 192: SPI master signal timing (SPO=1 and SPH=1)

SPI master timing for worst case operating conditions: VDDIO: 3.0..3.6V, Tj: -40..+125°C, CL: 20 pF. Values in brackets apply if input filtering is enabled.

Symbol Master mode parameter Min Typ Max Unit (1) (1) (1) tCP SPI_CLK period 20.0 40960/N 40960 ns

tCH SPI_CLK high phase 0.5*tCP-3.0 ns

tCL SPI_CLK low phase 0.5*tCP-3.0 ns (2) (2) tR Signal rise time 0.4 3.4 ns (2) (2) tF Signal fall time 0.3 2.0 ns

tCSS SPI_CS_N to first SPI_CLK edge setup time 0.5*tCP ns

tCSH last SPI_CLK edge to SPI_CS_N inactive time ns - SPH 0 Modes 10.0 11.5 - SPH 1 Modes 0.5*tCP+10.0 0.5*tCP+11.5 (3,4) tCSW SPI_CS_N minimum high pulse width 0.5*tCP-3.0 ns

tMOSIS SPI_MOSI to SPI_CLK setup time 0.5*tCP-3.4 ns

tMOSIH SPI_MOSI hold time 0.5*tCP ns

tMOSIHZ SPI_MOSI High-Z time 3.5 ns (5) tMISOS SPI_MISO to SPI_CLK setup time 2.5(12.5) ns (5) tMISOH SPI_MISO hold time 6.5(16.5) ns

tSPW Tolerated spike pulse width ns - with input filtering 9.0 - without input filtering 0.0

Notes 1. N is programmed by register spi_cr0, bits sck_muladd. N = 1..2048 2. Signal rise and fall times differ considerably depending on the external capacitive load. For approximation, use the following formula:

Rise times: tr = 0.350 + 0.150 * CL [ns]; CL: External capacitive load

Fall times: tf = 0.237 + 0.087 * CL [ns]; CL: External capacitive load 3. If bit fss_static is set in register spi_cr1, SPI_CS_N will not toggle between data words but half clock pause before next word MSB will be inserted anyway. 4. In SPH=1 modes SPI_CS_N does not become inactive during continuous transfers between LSB and next word MSB. 5. Input filtering can be enabled / disabled by bit filter_in in register spi_cr0.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Electrical specification 237/275 7.16 I2C The I2C Module IO timing depends on pad delays and internal module structure. All timings are related to an internal system clock running at 100 MHz.

tfCL trCL tLOW tHIGH tsp tsp

SCL

tHD;STA tHD;DAT tSU;DAT tSU;STA tHD;STA tSU;STO tBUF SDA

S Sr P S tfDA trDA tSP

Figure 193: Timing on I2C bus

tHIGH High period of SCL clock tSCL/2 - trCL - tSCL/2 ns

tHD;DAT SDA hold time 0.0 - 0.0 ns

tSU;DAT SDA setup time tSCL/2 - trDA - - ns

tHD;STA SCL hold time after (repeated) START condition tSCL/2 - - ns

tSU;STA SCL setup time before repeated START condition tSCL/2 - trCL - - ns

tSU;STO SCL setup time before STOP condition tSCL/2 - trCL - - ns

tBUF I2C bus idle time between STOP and START tSCL/2 - trDA - - ns

tSP Pulse width of spikes suppressed by input filters - - tSCL/32 ns

Notes 1. SCL clock frequency may decrease (period may increase) if other devices hold SCL low. SCL frequency is set by mode-bits of i2c_mcr register. 2. Signal fall times are only typical. For approximation, use the following formula: Fall times: tf = 0.197 + 0.058 * CL [ns]; CL: External capacitive load Signal rise times depend on pull-up resistor and capacitive bus load. Specified rise times are for 500 Ohms pull-up resistor and 400 pF load. For I2C high-speed mode and high capacitive load external driver devices can be used to reach faster rise times.

Start bit Stop bit Start bit Stop bit

UART_TXD D01 D11 D21 D71 D02 D12 D22 D72 … …

t1 t2 t1 UART_RTSn

......

t3 UART_CTSn

Figure 194: UART

Symbol Description Condition Min Max Unit

t1 Programmable leading time Bit Time 0 255 Bit Times System Time 0 2.55 µs

t2 Programmable trailing time Bit Time 0 255 Bit Times System Time 0 2.55 µs

t3 Setup time before the end of stop bit 70 ns

Note: This example uses the following settings: - 1 start bit - 1 stop bit - 8 data bits - Mode = '1'

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 netX 90 package and signal information 239/275 8 netX 90 package and signal information 8.1 Pin table sorted by signals The pin sharing options shown in the following table are prioritized: Option 1 has the lowest priority, option 9 (SDRAM) has the highest. If, e.g., you select SPI2 (peripherals) while SDRAM is selected, the SDRAM option will have priority. Before you change the IO configuration, always deselect options of a higher priority.

Pin Signal Shared with Pad type Power-on Default Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 J3 BOD BOD ------ANA - L9 CLK25OUT CLK25OUT - - - IO_LINK7_OE - PIO_APP28 MENC_MP1 - - IOD48CS pd K7 COM_IO0 / GPIO8 I2C0_COM_SCL - SQI_CS1N ------IOD48CS / pd (deact) ADC3_IN2 ANA K6 COM_IO1 / GPIO9 I2C0_COM_SDA - - - ETH_B_TXER - - - - IOD48CS / pd (deact) ADC3_IN3 ANA K5 COM_IO2 / GPIO10 I2C1_COM_SCL UART_RTSN MII0_TXE ------IOD48CS / pd (deact) ADC3_IN6 R ANA K4 COM_IO3 / GPIO11 I2C1_COM_SDA UART_CTSN MII1_TXE ------IOD48CS / pd (deact) ADC3_IN7 R1 ANA K1 DCDC_LX_OU DCDC_LX_ ------ANA - T OUT C5 HIF_A0 DPM_A0 / IO_LINK0B_IN UART_XPIC_APP_ - - ETH_TXER - - EXT_A0 SD_A0 IOU48S pu BLEN TXD B5 HIF_A1 DPM_A1 IO_LINK0B_OUT CAN0_APP_RX - - ETH_COL - - EXT_A1 SD_A1 IOU48S pu A5 HIF_A2 DPM_A2 IO_LINK0B_OE CAN0_APP_TX - - ETH_CRS - - EXT_A2 SD_A2 IOU48S pu C4 HIF_A3 DPM_A3 IO_LINK0B_WAK GPIO0 - - ETH_RXD0 - - EXT_A3 SD_A3 IOU48S pu EUP B4 HIF_A4 DPM_A4 IO_LINK1B_IN GPIO1 - - ETH_RXD1 - - EXT_A4 SD_A4 IOU48S pu A4 HIF_A5 DPM_A5 IO_LINK1B_OUT GPIO2 - - ETH_RXD2 - - EXT_A5 SD_A5 IOU48S pu C3 HIF_A6 DPM_A6 IO_LINK1B_OE GPIO3 - - ETH_RXD3 - - EXT_A6 SD_A6 IOU48S pu B3 HIF_A7 DPM_A7 IO_LINK1B_WAK GPIO4 - - ETH_RXDV - - EXT_A7 SD_A7 IOU48S pu EUP A3 HIF_A8 DPM_A8 - GPIO5 - - ETH_TXD0 - - EXT_A8 SD_A8 IOU48S pu C2 HIF_A9 DPM_A9 - GPIO6 - - ETH_TXD1 - - EXT_A9 SD_A9 IOU48S pu B2 HIF_A10 DPM_A10 - GPIO7 - - ETH_TXD2 - - EXT_A10 SD_A10 IOU48S pu C1 HIF_A11 DPM_A11 - SPI0_APP_CLK - - ETH_TXD3 - - EXT_A11 SD_A11 IOU48S pu D1 HIF_A12 DPM_A12 - SPI0_APP_CS1N - - ETH_TXEN - - EXT_A12 SD_A12 IOU48S pu D2 HIF_A13 DPM_A13 - SPI0_APP_CS0N - - ETH_TXCLK - - EXT_A13 SD_BA0 IOU48S pu D3 HIF_A14 DPM_A14 - SPI0_APP_MOSI - - - - - EXT_A14 SD_BA1 IOU48S pu netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 netX 90 package and signal information 240/275

Pin Signal Shared with Pad type Power-on Default Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 D4 HIF_A15 DPM_A15 - SPI0_APP_MISO - - - - - EXT_A15 SD_RASN IOU48S pu D5 HIF_A16 DPM_ALE - I2C_APP_SCL - - - - - EXT_A16 SD_CASN IOU48S pu D6 HIF_A17 DPM_WRHN - I2C_APP_SDA - - - - - EXT_A17 SD_DQM0 IOU48S pu D7 HIF_BHEN DPM_BHEN - UART_APP_RXD - - ETH_RXER - - EXT_BHEN SD_DQM1 IOU48S pu D8 HIF_CSN DPM_CSN - UART_APP_TXD - - - - - EXT_CS0N SD_CSN IOU48S pu B11 HIF_D0 DPM_D0 SQI0_APP_MISO SPI2_APP_MISO PIO_APP0 - - - DPM1_SPI_MISO EXT_D8 SD_D8 IOU48S pu (_SIO1) C10 HIF_D1 DPM_D1 SQI0_APP_MOSI SPI2_APP_MOSI PIO_APP1 - - - DPM1_SPI_MOSI EXT_D9 SD_D9 IOU48S pu (_SIO0) B10 HIF_D2 DPM_D2 SQI0_APP_CS0N SPI2_APP_CS0N PIO_APP2 - - - DPM1_SPI_CSN EXT_D10 SD_D10 IOU48S pu A10 HIF_D3 DPM_D3 SQI0_APP_CLK SPI2_APP_CLK PIO_APP3 - - - DPM1_SPI_CLK EXT_D11 SD_D11 IOU48S pu C9 HIF_D4 DPM_D4 SQI0_APP_SIO2 SPI2_APP_CS1N PIO_APP4 - - - DPM1_SPI_DIRQ EXT_D12 SD_D12 IOU48S pu B9 HIF_D5 DPM_D5 SQI0_APP_SIO3 SPI2_APP_CS2N PIO_APP5 - - - DPM1_SPI_SIRQ EXT_D13 SD_D13 IOU48S pu A9 HIF_D6 DPM_D6 - CAN1_APP_RX PIO_APP6 - - - DPM1_SQI_SIO2 EXT_D14 SD_D14 IOU48S pu C8 HIF_D7 DPM_D7 - CAN1_APP_TX PIO_APP7 - - - DPM1_SQI_SIO3 EXT_D15 SD_D15 IOU48S pu B8 HIF_D8 DPM_D8 - MLED4 MMIO8 - - - DPM0_SPI_MISO - - IOU48S pu (_SIO1) A8 HIF_D9 DPM_D9 - MLED5 MMIO9 - - - DPM0_SPI_MOSI - - IOU48S pu (_SIO0) C7 HIF_D10 DPM_D10 - MLED6 MMIO10 IO_LINK2_WAKE - - DPM0_SPI_CSN - - IOU48S pu UP B7 HIF_D11 DPM_D11 - MLED7 MMIO11 IO_LINK3_WAKE - - DPM0_SPI_CLK - - IOU48S pu UP A7 HIF_D12 DPM_D12 SQI1_APP_CS0N MLED8 MMIO12 IO_LINK4_WAKE - - DPM0_SPI_DIRQ - - IOU48S pu UP C6 HIF_D13 DPM_D13 SQI1_APP_CLK MLED9 MMIO13 IO_LINK5_WAKE - - DPM0_SPI_SIRQ - - IOU48S pu UP B6 HIF_D14 DPM_D14 SQI1_APP_MISO MLED10 MMIO14 IO_LINK6_WAKE - - DPM0_SQI_SIO2 - - IOU48S pu UP A6 HIF_D15 DPM_D15 SQI1_APP_MOSI MLED11 MMIO15 IO_LINK7_WAKE - - DPM0_SQI_SIO3 - - IOU48S pu UP F2 HIF_DIRQ DPM_DIRQ SQI1_APP_SIO3 UART_XPIC_APP_ MMIO17 - - - - EXT_CS1N - IOU48S pu CTSN E2 HIF_RDN DPM_RDN SQI1_APP_SIO2 UART_APP_RTSN MMIO16 - ETH_MDC - - EXT_RDN - IOU48S pu E3 HIF_RDY DPM_RDY - UART_XPIC_APP_ - - ETH_RXCLK - - EXT_RDY SD_CKE IOU48S pu RXD F1 HIF_SDCLK DPM_SIRQ - UART_XPIC_APP_ XC_TRIG - - - - EXT_CS2N SD_CLK IOU48S pu RTSN GER0 netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 netX 90 package and signal information 241/275

Pin Signal Shared with Pad type Power-on Default Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 E1 HIF_WRN DPM_WRN / - UART_APP_CTSN - - ETH_MDIO - - EXT_WRN SD_WEN IOU48S pu WRLN D12 JT_TCK JT_TCK - SWDCLK ------IU24S pu C11 JT_TDI JT_TDI TRACECLK ------IOU48CS pu C12 JT_TDO JT_TDO TRACECTL ------OZU48C pu D11 JT_TMS JT_TMS - SWDIO ------IOU48CS pu D10 JT_TRST JT_TRST ------IU24S pu K8 MII_MDC / MII_MDC - - - IO_LINK6_OE ETH_B_MDC PIO_APP25 - - - IOD48CS / pd (deact) ADC2_IN5 ANA L8 MII_MDIO / MII_MDIO - - - IO_LINK7_IN ETH_B_MDIO PIO_APP26 - - - IOD48CS / pd (deact) ADC2_IN6 ANA E5 MII0_COL MII0_COL - XM0_IO5 - - ETH_B_COL - - EXT_D6 SD_D6 IOD48CS pd E4 MII0_CRS MII0_CRS - - - - ETH_B_CRS - - EXT_D7 SD_D7 IOD48CS pd F4 MII0_RXCLK MII0_RXCLK FO0_SD XM0_ECLK FB0CLK - ETH_B_RXCLK PIO_APP8 - - - IOD48CS pd J5 MII0_RXD0 MII0_RXD0 FO0_RX XM0_RX - - ETH_B_RXD0 - - - - ID24S pd J4 MII0_RXD1 MII0_RXD1 FO0_TX XM0_TX XM0_TX_ - ETH_B_RXD1 PIO_APP9 - - - IOD48S pd ECLK H5 MII0_RXD2 MII0_RXD2 FO0_EN_TX XM0_IO0 - - ETH_B_RXD2 PIO_APP10 - - - IOD48S pd H4 MII0_RXD3 MII0_RXD3 - - - IO_LINK2_IN ETH_B_RXD3 - MENC0_A - - ID24S pd G4 MII0_RXDV MII0_RXDV - - - IO_LINK3_IN ETH_B_RXDV - MENC0_B - - ID24S pd F3 MII0_RXER MII0_RXER - - - IO_LINK4_IN ETH_B_RXER - MENC0_N - - ID24S pd G5 MII0_TXCLK MII0_TXCLK - - - IO_LINK2_OUT ETH_B_TXCLK PIO_APP11 MPWM_BRAKE - - IOD48CS pd J7 MII0_TXD0 / MII0_TXD0 - XM0_TXOE XM0_TXO - ETH_B_TXD0 PIO_APP12 - - - IOD48CS / pd (deact) ADC2_IN7 E_ECLK ANA J6 MII0_TXD1 / MII0_TXD1 - XM0_IO1 - IO_LINK2_OE ETH_B_TXD1 PIO_APP13 - - - IOD48CS / pd (deact) ADC3_IN4 ANA H7 MII0_TXD2 / MII0_TXD2 - XM0_IO2 - IO_LINK3_OUT ETH_B_TXD2 PIO_APP14 - - - IOD48CS / pd (deact) ADC2_IN4 ANA H6 MII0_TXD3 / MII0_TXD3 - XM0_IO3 - IO_LINK3_OE ETH_B_TXD3 PIO_APP15 - - - IOD48CS / pd (deact) ADC3_IN5 ANA F5 MII0_TXEN MII0_TXEN - XM0_IO4 - - ETH_B_TXEN - - EXT_D5 SD_D5 IOD48CS pd E8 MII1_COL MII1_COL - XM1_IO5 - - - - - EXT_D2 SD_D2 IOD48CS pd E9 MII1_CRS MII1_CRS ------EXT_D1 SD_D1 IOD48CS pd D9 MII1_RXCLK MII1_RXCLK FO1_SD XM1_ECLK FB1CLK - - PIO_APP16 MPWM0 - - IOD48CS pd G9 MII1_RXD0 / MII1_RXD0 FO1_RX XM1_RX - - - - MENC1_A - - ID24S / LVDS open / - LVDS1_TXN G8 MII1_RXD1 / MII1_RXD1 FO1_TX XM1_TX XM1_TX_ - SQI0_APP_SIO PIO_APP17 MENC_MP0 - - IOD48S / LVDS open / - LVDS1_TXP ECLK 2_B netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 netX 90 package and signal information 242/275

Pin Signal Shared with Pad type Power-on Default Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 F9 MII1_RXD2 / MII1_RXD2 FO1_EN_TX XM1_IO0 - - SQI0_APP_SIO PIO_APP18 MENC1_N - - IOD48S / LVDS open / - LVDS1_RXP 3_B F8 MII1_RXD3 / MII1_RXD3 - - - IO_LINK5_IN - - MENC1_B - - ID24S / LVDS open / - LVDS1_RXN F10 MII1_RXDV MII1_RXDV - - - IO_LINK6_IN - - MPWM_FAIL - - ID24S pd E10 MII1_RXER MII1_RXER ------EXT_D0 SD_D0 ID24S pd H10 MII1_TXCLK / MII1_TXCLK - - - IO_LINK4_OUT - PIO_APP19 - - - IOD48CS / pd (deact) ADC2_IN2 ANA J9 MII1_TXD0 / MII1_TXD0 - XM1_TXOE XM1_TXO - SQI0_APP_CL PIO_APP20 MPWM1 - - IOD48CS / open / - LVDS0_RXN E_ECLK K_B LVDS J8 MII1_TXD1 / MII1_TXD1 - XM1_IO1 - IO_LINK4_OE SQI0_APP_CS PIO_APP21 MPWM2 - - IOD48CS / open / - LVDS0_RXP 0N_B LVDS H9 MII1_TXD2 / MII1_TXD2 - XM1_IO2 - IO_LINK5_OUT SQI0_APP_MI PIO_APP22 MPWM3 - - IOD48CS / open / - LVDS0_TXN SO_B LVDS H8 MII1_TXD3 / MII1_TXD3 - XM1_IO3 - IO_LINK5_OE SQI0_APP_MO PIO_APP23 MPWM4 - - IOD48CS / open / - LVDS0_TXP SI_B LVDS K9 MII1_TXEN / MII1_TXEN - XM1_IO4 - IO_LINK6_OUT - PIO_APP24 - - - IOD48CS / pd (deact) ADC2_IN3 ANA L10 MLED0 MLED0 TRACE_DATA0 ------OZD48C open K10 MLED1 MLED1 TRACE_DATA1 ------OZD48C open J10 MLED2 MLED2 TRACE_DATA2 ------OZD48C open K11 MLED3 MLED3 TRACE_DATA3 ------OZD48C open M7 MMIO0 / MMIO0 IO_LINK0_IN ENDAT0_IN BISS0_SL ------IOD48CS / pd (deact) ADC2_IN0 ANA L7 MMIO1 / MMIO1 IO_LINK0_OUT ENDAT0_OUT BISS0_M ------IOD48CS / pd (deact) ADC2_IN1 O ANA M6 MMIO2 / MMIO2 IO_LINK0_OE ENDAT0_OE ------IOD48CS / pd (deact) ADC3_IN0 ANA L6 MMIO3 / MMIO3 IO_LINK0_WAKE ENDAT0_CLK BISS0_MA ------IOD48CS / pd (deact) ADC3_IN1 UP ANA M5 MMIO4 / MMIO4 IO_LINK1_IN ENDAT1_IN BISS1_SL ------IOD48CS / pd (deact) ADC0_IN0 ANA L5 MMIO5 / MMIO5 IO_LINK1_OUT ENDAT1_OUT BISS1_M ------IOD48CS / pd (deact) ADC0_IN1 O ANA M4 MMIO6 / MMIO6 IO_LINK1_OE ENDAT1_OE ------IOD48CS / pd (deact) ADC1_IN0 ANA L4 MMIO7 / MMIO7 IO_LINK1_WAKE ENDAT1_CLK BISS1_MA ------IOD48CS / pd (deact) ADC1_IN1 UP ANA M9 OSC_XTI OSC_XTI ------XTAL - (XTALIN) (XTALIN) netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 netX 90 package and signal information 243/275

Pin Signal Shared with Pad type Power-on Default Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 M10 OSC_XTO OSC_XTO ------XTAL - (XTALOUT) (XTALOUT) G12 PHY_EXTRES PHY_EXTRE ------ANA - S K12 PHY_VDDC PHY_VDDC ------APWR - L11 PHY_VDDIO PHY_VDDIO ------APWR - E7 PHY0_LED_LI PHY0_LED_ ------EXT_D3 SD_D3 ID24S pd NK_IN LINK_IN H11 PHY0_RXN PHY0_RXN ------PHY - H12 PHY0_RXP PHY0_RXP ------PHY - J11 PHY0_TXN PHY0_TXN ------PHY - J12 PHY0_TXP PHY0_TXP ------PHY - E6 PHY1_LED_LI PHY1_LED_ ------EXT_D4 SD_D4 ID24S pd NK_IN LINK_IN F11 PHY1_RXN PHY1_RXN ------PHY - F12 PHY1_RXP PHY1_RXP ------PHY - E11 PHY1_TXN PHY1_TXN ------PHY - E12 PHY1_TXP PHY1_TXP ------PHY - J1 RDY_N RDY_N ------IOU48CS pu M3 RST_IN_N RST_IN_N ------IU24S pu L3 RST_OUT_N RST_OUT_N - - - IO_LINK7_OUT - PIO_APP27 MPWM5 - - IOD48CS pd J2 RUN_N RUN_N ------IOU48CS pu H2 SQI_CLK SQI_CLK - SQIROM_CLK ------IOU48S pu G1 SQI_CS0N SQI_CS0N - SQIROM_CSN ------IOU48S pu G2 SQI_MISO SQI_MISO - SQIROM_SIO1 ------IOU48S pu (_SIO1) H1 SQI_MOSI SQI_MOSI - SQIROM_SIO0 ------IOU48S pu (_SIO0) G3 SQI_SIO2 SQI_SIO2 - SQIROM_SIO2 ------IOU48S pu H3 SQI_SIO3 SQI_SIO3 SQI_CS2N SQIROM_SIO3 ------IOU48S pu G11 UART_TXD UART_TXD ------OZD48C pd G10 UART_RXD UART_RXD ------ID24S pd B1 VDDC VDDC ------VDD_CORE - B12 VDDC VDDC ------VDD_CORE - M2 VDDC VDDC ------VDD_CORE - M11 VDDC VDDC ------VDD_CORE - A2 VDDIO VDDIO ------VDD_IO - netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 netX 90 package and signal information 244/275

Pin Signal Shared with Pad type Power-on Default Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 A11 VDDIO VDDIO ------VDD_IO - L1 VDDIO VDDIO ------VDD_IO - L12 VDDIO VDDIO ------VDD_IO - M8 VDD_PLL VDD_PLL ------APWR - L2 VREF_ADC VREF_ADC ------ANA - K2 VSS_DCDC VSS_DCDC ------ANA - (GND) (GND) A1 VSS (GND) VSS (GND) ------GND - A12 VSS (GND) VSS (GND) ------GND - F6 VSS (GND) VSS (GND) ------GND - F7 VSS (GND) VSS (GND) ------GND - G6 VSS (GND) VSS (GND) ------GND - K3 VSS (GND) VSS (GND) ------GND - G7 VSS (GND) VSS (GND) ------GND - M12 VSS (GND) VSS (GND) ------GND - M1 VSS_REF VSS_REF ------GND - (GND) (GND) Table 49: netX 90 – Signals (pin table sorted by signals)

PAD Type and power-on explanation, see section on page 253.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 netX 90 package and signal information 245/275 8.2 Pin table sorted by pin number The pin sharing options shown in the following table are prioritized: Option 1 has the lowest priority, option 9 (SDRAM) has the highest. If, e.g., you select SPI2 (peripherals) while SDRAM is selected, the SDRAM option will have priority. Before you change the IO configuration, always deselect options of a higher priority.

Pin Signal Shared with Pad type Power-on Default Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 A1 VSS (GND) VSS (GND) GND - A2 VDDIO VDDIO VDD_IO - A3 HIF_A8 DPM_A8 GPIO5 ETH_TXD0 EXT_A8 SD_A8 IOU48S pu A4 HIF_A5 DPM_A5 IO_LINK1B_OUT GPIO2 ETH_RXD2 EXT_A5 SD_A5 IOU48S pu A5 HIF_A2 DPM_A2 IO_LINK0B_OE CAN0_APP_TX ETH_CRS EXT_A2 SD_A2 IOU48S pu A6 HIF_D15 DPM_D15 SQI1_APP_MOSI MLED11 MMIO15 IO_LINK7_WAKE DPM0_SQI_SIO3 IOU48S pu UP A7 HIF_D12 DPM_D12 SQI1_APP_CS0N MLED8 MMIO12 IO_LINK4_WAKE DPM0_SPI_DIRQ IOU48S pu UP A8 HIF_D9 DPM_D9 MLED5 MMIO9 DPM0_SPI_MOSI IOU48S pu A9 HIF_D6 DPM_D6 CAN1_APP_RX PIO_APP6 DPM1_SQI_SIO2 EXT_D14 SD_D14 IOU48S pu A10 HIF_D3 DPM_D3 SQI0_APP_CLK SPI2_APP_CLK PIO_APP3 DPM1_SPI_CLK EXT_D11 SD_D11 IOU48S pu A11 VDDIO VDDIO VDD_IO - A12 VSS (GND) VSS (GND) GND - B1 VDDC VDDC VDD_CORE - B2 HIF_A10 DPM_A10 GPIO7 ETH_TXD2 EXT_A10 SD_A10 IOU48S pu B3 HIF_A7 DPM_A7 IO_LINK1B_WAK GPIO4 ETH_RXDV EXT_A7 SD_A7 IOU48S pu EUP B4 HIF_A4 DPM_A4 IO_LINK1B_IN GPIO1 ETH_RXD1 EXT_A4 SD_A4 IOU48S pu B5 HIF_A1 DPM_A1 IO_LINK0B_OUT CAN0_APP_RX ETH_COL EXT_A1 SD_A1 IOU48S pu B6 HIF_D14 DPM_D14 SQI1_APP_MISO MLED10 MMIO14 IO_LINK6_WAKE DPM0_SQI_SIO2 IOU48S pu UP B7 HIF_D11 DPM_D11 MLED7 MMIO11 IO_LINK3_WAKE DPM0_SPI_CLK IOU48S pu UP B8 HIF_D8 DPM_D8 MLED4 MMIO8 DPM0_SPI_MISO IOU48S pu B9 HIF_D5 DPM_D5 SQI0_APP_SIO3 SPI2_APP_CS2N PIO_APP5 DPM1_SPI_SIRQ EXT_D13 SD_D13 IOU48S pu B10 HIF_D2 DPM_D2 SQI0_APP_CS0N SPI2_APP_CS0N PIO_APP2 DPM1_SPI_CSN EXT_D10 SD_D10 IOU48S pu B11 HIF_D0 DPM_D0 SQI0_APP_MISO SPI2_APP_MISO PIO_APP0 DPM1_SPI_MISO EXT_D8 SD_D8 IOU48S pu B12 VDDC VDDC VDD_CORE - C1 HIF_A11 DPM_A11 SPI0_APP_CLK ETH_TXD3 EXT_A11 SD_A11 IOU48S pu C2 HIF_A9 DPM_A9 GPIO6 ETH_TXD1 EXT_A9 SD_A9 IOU48S pu netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 netX 90 package and signal information 246/275

Pin Signal Shared with Pad type Power-on Default Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 C3 HIF_A6 DPM_A6 IO_LINK1B_OE GPIO3 ETH_RXD3 EXT_A6 SD_A6 IOU48S pu C4 HIF_A3 DPM_A3 IO_LINK0B_WAK GPIO0 ETH_RXD0 EXT_A3 SD_A3 IOU48S pu EUP C5 HIF_A0 DPM_A0 IO_LINK0B_IN UART_XPIC_APP_ ETH_TXER EXT_A0 SD_A0 IOU48S pu TXD C6 HIF_D13 DPM_D13 SQI1_APP_CLK MLED9 MMIO13 IO_LINK5_WAKE DPM0_SPI_SIRQ IOU48S pu UP C7 HIF_D10 DPM_D10 MLED6 MMIO10 IO_LINK2_WAKE DPM0_SPI_CSN IOU48S pu UP C8 HIF_D7 DPM_D7 CAN1_APP_TX PIO_APP7 DPM1_SQI_SIO3 EXT_D15 SD_D15 IOU48S pu C9 HIF_D4 DPM_D4 SQI0_APP_SIO2 SPI2_APP_CS1N PIO_APP4 DPM1_SPI_DIRQ EXT_D12 SD_D12 IOU48S pu C10 HIF_D1 DPM_D1 SQI0_APP_MOSI SPI2_APP_MOSI PIO_APP1 DPM1_SPI_MOSI EXT_D9 SD_D9 IOU48S pu C11 JT_TDI JT_TDI TRACECLK IOU48CS pu C12 JT_TDO JT_TDO TRACECTL OZU48C pu D1 HIF_A12 DPM_A12 SPI0_APP_CS1N ETH_TXEN EXT_A12 SD_A12 IOU48S pu D2 HIF_A13 DPM_A13 SPI0_APP_CS0N ETH_TXCLK EXT_A13 SD_BA0 IOU48S pu D3 HIF_A14 DPM_A14 SPI0_APP_MOSI EXT_A14 SD_BA1 IOU48S pu D4 HIF_A15 DPM_A15 SPI0_APP_MISO EXT_A15 SD_RASN IOU48S pu D5 HIF_A16 DPM_ALE I2C_APP_SCL EXT_A16 SD_CASN IOU48S pu D6 HIF_A17 DPM_WRHN I2C_APP_SDA EXT_A17 SD_DQM0 IOU48S pu D7 HIF_BHEN DPM_BHEN UART_APP_RXD ETH_RXER EXT_BHEN SD_DQM1 IOU48S pu D8 HIF_CSN DPM_CSN UART_APP_TXD EXT_CS0N SD_CSN IOU48S pu D9 MII1_RXCLK MII1_RXCLK FO1_SD XM1_ECLK FB1CLK PIO_APP16 MPWM0 IOD48CS pd D10 JT_TRST JT_TRST IU24S pu D11 JT_TMS JT_TMS SWDIO IOU48CS pu D12 JT_TCK JT_TCK SWDCLK IU24S pu E1 HIF_WRN DPM_WRN UART_APP_CTSN ETH_MDIO EXT_WRN SD_WEN IOU48S pu E2 HIF_RDN DPM_RDN SQI1_APP_SIO2 UART_APP_RTSN MMIO16 ETH_MDC EXT_RDN IOU48S pu E3 HIF_RDY DPM_RDY UART_XPIC_APP_ ETH_RXCLK EXT_RDY SD_CKE IOU48S pu RXD E4 MII0_CRS MII0_CRS ETH_B_CRS EXT_D7 SD_D7 IOD48CS pd E5 MII0_COL MII0_COL XM0_IO5 ETH_B_COL EXT_D6 SD_D6 IOD48CS pd E6 PHY1_LED_LI PHY1_LED_ EXT_D4 SD_D4 ID24S pd NK_IN LINK_IN E7 PHY0_LED_LI PHY0_LED_ EXT_D3 SD_D3 ID24S pd NK_IN LINK_IN E8 MII1_COL MII1_COL XM1_IO5 EXT_D2 SD_D2 IOD48CS pd netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 netX 90 package and signal information 247/275

Pin Signal Shared with Pad type Power-on Default Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 E9 MII1_CRS MII1_CRS EXT_D1 SD_D1 IOD48CS pd E10 MII1_RXER MII1_RXER EXT_D0 SD_D0 ID24S pd E11 PHY1_TXN PHY1_TXN PHY - E12 PHY1_TXP PHY1_TXP PHY - F1 HIF_SDCLK DPM_SIRQ UART_XPIC_APP_ XC_TRIG EXT_CS2N SD_CLK IOU48S pu RTSN GER0 F2 HIF_DIRQ DPM_DIRQ SQI1_APP_SIO3 UART_XPIC_APP_ MMIO17 EXT_CS1N IOU48S pu CTSN F3 MII0_RXER MII0_RXER IO_LINK4_IN ETH_B_RXER MENC0_N ID24S pd F4 MII0_RXCLK MII0_RXCLK FO0_SD XM0_ECLK FB0CLK ETH_B_RXCL PIO_APP8 IOD48CS pd K F5 MII0_TXEN MII0_TXEN XM0_IO4 ETH_B_TXEN EXT_D5 SD_D5 IOD48CS pd F6 VSS (GND) VSS (GND) GND - F7 VSS (GND) VSS (GND) GND - F8 MII1_RXD3 / MII1_RXD3 IO_LINK5_IN MENC1_B ID24S / LVDS open / - LVDS1_RXN F9 MII1_RXD2 / MII1_RXD2 FO1_EN_TX XM1_IO0 SQI0_APP_SI PIO_APP18 MENC1_N IOD48S / LVDS open / - LVDS1_RXP O3_B F10 MII1_RXDV MII1_RXDV IO_LINK6_IN MPWM_FAIL ID24S pd F11 PHY1_RXN PHY1_RXN PHY - F12 PHY1_RXP PHY1_RXP PHY - G1 SQI_CS0N SQI_CS0N SQIROM_CSN IOU48S pu G2 SQI_MISO SQI_MISO SQIROM_SIO1 IOU48S pu G3 SQI_SIO2 SQI_SIO2 SQIROM_SIO2 IOU48S pu G4 MII0_RXDV MII0_RXDV IO_LINK3_IN ETH_B_RXDV MENC0_B ID24S pd G5 MII0_TXCLK MII0_TXCLK IO_LINK2_OUT ETH_B_TXCL PIO_APP11 MPWM_BRAKE IOD48CS pd K G6 VSS (GND) VSS (GND) GND - G7 VSS (GND) VSS (GND) GND - G8 MII1_RXD1 / MII1_RXD1 FO1_TX XM1_TX XM1_TX_ SQI0_APP_SI PIO_APP17 MENC_MP0 IOD48S / LVDS open / - LVDS1_TXP ECLK O2_B G9 MII1_RXD0 / MII1_RXD0 FO1_RX XM1_RX MENC1_A ID24S / LVDS open / - LVDS1_TXN G10 UART_RXD UART_RXD ID24S pd G11 UART_TXD UART_TXD OZD48C pd G12 PHY_EXTRES PHY_EXTRE ANA - S H1 SQI_MOSI SQI_MOSI SQIROM_SIO0 IOU48S pu netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 netX 90 package and signal information 248/275

Pin Signal Shared with Pad type Power-on Default Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 H2 SQI_CLK SQI_CLK - SQIROM_CLK ------IOU48S pu H3 SQI_SIO3 SQI_SIO3 SQI_CS2N SQIROM_SIO3 ------IOU48S pu H4 MII0_RXD3 MII0_RXD3 - - IO_LINK2_IN ETH_B_RXD3 - MENC0_A - - ID24S pd H5 MII0_RXD2 MII0_RXD2 FO0_EN_TX XM0_IO0 - - ETH_B_RXD2 PIO_APP10 - - - IOD48S pd H6 MII0_TXD3 / MII0_TXD3 - XM0_IO3 - IO_LINK3_OE ETH_B_TXD3 PIO_APP15 - - - IOD48CS / pd (deact) ADC3_IN5 ANA H7 MII0_TXD2 / MII0_TXD2 - XM0_IO2 - IO_LINK3_OUT ETH_B_TXD2 PIO_APP14 - - - IOD48CS / pd (deact) ADC2_IN4 ANA H8 MII1_TXD3 / MII1_TXD3 - XM1_IO3 - IO_LINK5_OE SQI0_APP_M PIO_APP23 MPWM4 - - IOD48CS / open / - LVDS0_TXP OSI_B LVDS H9 MII1_TXD2 / MII1_TXD2 - XM1_IO2 - IO_LINK5_OUT SQI0_APP_MI PIO_APP22 MPWM3 - - IOD48CS / open / - LVDS0_TXN SO_B LVDS H10 MII1_TXCLK / MII1_TXCLK - - - IO_LINK4_OUT - PIO_APP19 - - - IOD48CS / pd (deact) ADC2_IN2 ANA H11 PHY0_RXN PHY0_RXN ------PHY - H12 PHY0_RXP PHY0_RXP ------PHY - J1 RDY_N RDY_N ------IOU48CS pu J2 RUN_N RUN_N ------IOU48CS pu J3 BOD BOD ------ANA - J4 MII0_RXD1 MII0_RXD1 FO0_TX XM0_TX XM0_TX_ - ETH_B_RXD1 PIO_APP9 - - - IOD48S pd ECLK J5 MII0_RXD0 MII0_RXD0 FO0_RX XM0_RX - - ETH_B_RXD0 - - - - ID24S pd J6 MII0_TXD1 / MII0_TXD1 - XM0_IO1 - IO_LINK2_OE ETH_B_TXD1 PIO_APP13 - - - IOD48CS / pd (deact) ADC3_IN4 ANA J7 MII0_TXD0 / MII0_TXD0 - XM0_TXOE XM0_TXO - ETH_B_TXD0 PIO_APP12 - - - IOD48CS / pd (deact) ADC2_IN7 E_ECLK ANA J8 MII1_TXD1 / MII1_TXD1 - XM1_IO1 - IO_LINK4_OE SQI0_APP_CS PIO_APP21 MPWM2 - - IOD48CS / open / - LVDS0_RXP 0N_B LVDS J9 MII1_TXD0 / MII1_TXD0 - XM1_TXOE XM1_TXO - SQI0_APP_CL PIO_APP20 MPWM1 - - IOD48CS / open / - LVDS0_RXN E_ECLK K_B LVDS J10 MLED2 MLED2 TRACE_DATA2 ------OZD48C open J11 PHY0_TXN PHY0_TXN ------PHY - J12 PHY0_TXP PHY0_TXP ------PHY - K1 DCDC_LX_OU DCDC_LX_O ------ANA - T UT K2 VSS_DCDC VSS_DCDC ------ANA - (GND) (GND) K3 VSS (GND) VSS (GND) ------GND - K4 COM_IO3 / GPIO11 I2C1_COM_SDA UART_CTSN MII1_TXE ------IOD48CS / pd (deact) ADC3_IN7 R1 ANA netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 netX 90 package and signal information 249/275

Pin Signal Shared with Pad type Power-on Default Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 K5 COM_IO2 / GPIO10 I2C1_COM_SCL UART_RTSN MII0_TXE ------IOD48CS / pd (deact) ADC3_IN6 R ANA K6 COM_IO1 / GPIO9 I2C0_COM_SDA - - - ETH_B_TXER - - - - IOD48CS / pd (deact) ADC3_IN3 ANA K7 COM_IO0 / GPIO8 I2C0_COM_SCL - SQI_CS1N ------IOD48CS / pd (deact) ADC3_IN2 ANA K8 MII_MDC / MII_MDC - - - IO_LINK6_OE ETH_B_MDC PIO_APP25 - - - IOD48CS / pd (deact) ADC2_IN5 ANA K9 MII1_TXEN / MII1_TXEN - XM1_IO4 - IO_LINK6_OUT - PIO_APP24 - - - IOD48CS / pd (deact) ADC2_IN3 ANA K10 MLED1 MLED1 TRACE_DATA1 ------OZD48C open K11 MLED3 MLED3 TRACE_DATA3 ------OZD48C open K12 PHY_VDDC PHY_VDDC ------APWR - L1 VDDIO VDDIO ------VDD_IO - L2 VREF_ADC VREF_ADC ------ANA - L3 RST_OUT_N RST_OUT_N - - - IO_LINK7_OUT - PIO_APP27 MPWM5 - - IOD48CS pd L4 MMIO7 / MMIO7 IO_LINK1_WAKE ENDAT1_CLK BISS1_MA ------IOD48CS / pd (deact) ADC1_IN1 UP ANA L5 MMIO5 / MMIO5 IO_LINK1_OUT ENDAT1_OUT BISS1_M ------IOD48CS / pd (deact) ADC0_IN1 O ANA L6 MMIO3 / MMIO3 IO_LINK0_WAKE ENDAT0_CLK BISS0_MA ------IOD48CS / pd (deact) ADC3_IN1 UP ANA L7 MMIO1 / MMIO1 IO_LINK0_OUT ENDAT0_OUT BISS0_M ------IOD48CS / pd (deact) ADC2_IN1 O ANA L8 MII_MDIO / MII_MDIO - - - IO_LINK7_IN ETH_B_MDIO PIO_APP26 - - - IOD48CS / pd (deact) ADC2_IN6 ANA L9 CLK25OUT CLK25OUT - - - IO_LINK7_OE - PIO_APP28 MENC_MP1 - - IOD48CS pd L10 MLED0 MLED0 TRACE_DATA0 ------OZD48C open L11 PHY_VDDIO PHY_VDDIO ------APWR - L12 VDDIO VDDIO ------VDD_IO - M1 VSS_REF VSS_REF ------GND - (GND) (GND) M2 VDDC VDDC ------VDD_CORE - M3 RST_IN_N RST_IN_N ------IU24S pu M4 MMIO6 / MMIO6 IO_LINK1_OE ENDAT1_OE ------IOD48CS / pd (deact) ADC1_IN0 ANA M5 MMIO4 / MMIO4 IO_LINK1_IN ENDAT1_IN BISS1_SL ------IOD48CS / pd (deact) ADC0_IN0 ANA M6 MMIO2 / MMIO2 IO_LINK0_OE ENDAT0_OE ------IOD48CS / pd (deact) ADC3_IN0 ANA netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 netX 90 package and signal information 250/275

Pin Signal Shared with Pad type Power-on Default Option 1 Option 2 Option 3 Option 4 Option 5 Option 6 Option 7 Option 8 Option 9 M7 MMIO0 / MMIO0 IO_LINK0_IN ENDAT0_IN BISS0_SL ------IOD48CS / pd (deact) ADC2_IN0 ANA M8 VDD_PLL VDD_PLL ------APWR - M9 OSC_XTI OSC_XTI ------XTAL - (XTALIN) (XTALIN) M10 OSC_XTO OSC_XTO ------XTAL - (XTALOUT) (XTALOUT) M11 VDDC VDDC ------VDD_CORE - M12 VSS (GND) VSS (GND) ------GND - Table 50: netX 90 – Pin A1 … M12 (pin table sorted by pin number)

PAD Type and power-on explanation, see section on page 253.

1 2 3 4 5 6 7 8 9 10 11 12

A VSS (GND) VDDIO HIF_A8 HIF_A5 HIF_A2 HIF_D15 HIF_D12 HIF_D9 HIF_D6 HIF_D3 VDDIO VSS (GND) A

B VDDC HIF_A10 HIF_A7 HIF_A4 HIF_A1 HIF_D14 HIF_D11 HIF_D8 HIF_D5 HIF_D2 HIF_D0 VDDC B

C HIF_A11 HIF_A9 HIF_A6 HIF_A3 HIF_A0 HIF_D13 HIF_D10 HIF_D7 HIF_D4 HIF_D1 JT_TDI JT_TDO C

D HIF_A12 HIF_A13 HIF_A14 HIF_A15 HIF_A16 HIF_A17 HIF_BHEN HIF_CSN MII1_RXCLK JT_TRST JT_TMS JT_TCK D

E HIF_WRN HIF_RDN HIF_RDY MII0_CRS MII0_COL PHY1_LED_ PHY0_LED_ MII1_COL MII1_CRS MII1_RXER PHY1_TXN PHY1_TXP E LINK_IN LINK_IN

F HIF_SDCLK HIF_DIRQ MII0_RXER MII0_RXCLK MII0_TXEN VSS (GND) VSS (GND) MII1_RXD3 MII1_RXD2 MII1_RXDV PHY1_RXN PHY1_RXP F LVDS1_RXN LVDS1_RXP

G SQI_CS0N SQI_MISO SQI_SIO2 MII0_RXDV MII0_TXCLK VSS (GND) VSS (GND) MII1_RXD1 MII1_RXD0 UART_RXD UART_TXD PHY_ G LVDS1_TXP LVDS1_TXN EXTRES

H SQI_MOSI SQI_CLK SQI_SIO3 MII0_RXD3 MII0_RXD2 MII0_TXD3 MII0_TXD2 MII1_TXD3 MII1_TXD2 MII1_TXCLK PHY0_RXN PHY0_RXP H ADC3_IN5 ADC2_IN4 LVDS0_TXP LVDS0_TXN ADC2_IN2

J RDY_N RUN_N BOD MII0_RXD1 MII0_RXD0 MII0_TXD1 MII0_TXD0 MII1_TXD1 MII1_TXD0 MLED2 PHY0_TXN PHY0_TXP J ADC3_IN4 ADC2_IN7 LVDS0_RXP LVDS0_RXN

K DCDC_LX_ VSS_DCDC VSS (GND) COM_IO3 COM_IO2 COM_IO1 COM_IO0 MII_MDC MII1_TXEN MLED1 MLED3 PHY_VDDC K OUT GND ADC3_IN7 ADC3_IN6 ADC3_IN3 ADC3_IN2 ADC2_IN5 ADC2_IN3

L VDDIO VREF_ADC RST_OUT_N MMIO7 MMIO5 MMIO3 MMIO1 MII_MDIO CLK25OUT MLED0 PHY_VDDIO VDDIO L ADC1_IN1 ADC0_IN1 ADC3_IN1 ADC2_IN1 ADC2_IN6

M VSS_REF VDDC RST_IN_N MMIO6 MMIO4 MMIO2 MMIO0 VDD_PLL OSC_XTI OSC_XTO VDDC VSS (GND) M (GND) ADC1_IN0 ADC0_IN0 ADC3_IN0 ADC2_IN0 (XTALIN) (XTALOUT)

Signal Color Red Green Blue HIF 255 255 204 MMIO0…7 / ADC0…3_IN0+1 255 204 102 PHY 251 98 105 MII / ADC2+3_IN2…7 / LVDS, CLK25OUT 255 153 204 SQI 0 204 255 BOD, DCDC_LX_OUT, VREF_ADC, 242 242 242 OSC_TXI (XTALIN) and OSC_XTO (XTALOUT) RDY_N, RUN_N, RST_IN_N, COM_IO0…3 / 178 178 178 ADC3_IN2,3,6,7, MLED0…3, RST_OUT_N, UART_RXD and UART_TXD Debug JT_TDI, JT_TDO, JT_TRST, JT_TMS, JT_TCK 153 153 255 Power VSS (GND) 0 153 0 VDDIO and PHY_VDDIO 255 0 0 VDDC, VDD_PLL, PHY_VDDC 237 125 49 Table 51: Pin overview netX 90: Colors

Symbol Description I Input O Output Z High impedance output S Schmitt trigger U Pull-up resistor D Pull-down resistor C Slew-rate-controlled 24 2/4 mA 48 4/8 mA XTAL Crystal input or output LVDS LVDS receive/transmit pad PHY PHY pad ANA Analog pin GND Analog ground APWR Analog power (3.3 V) VDD_CORE Core power supply (3.3 V) VDD_IO IO power supply (3.3 V) Table 52: PAD type explanation netX 90

Symbol Description pu pull-up resistor activated pd pull-down resistor activated open pull-up or pull-down resistor = deactivated - neither pull-up nor pull-down resistor deact “deactivation required” for analog signals Table 53: Power-on description

ID24S IOD48CS IOD48S

IE IE IE IN IN IN PD PD PD PAD PAD PAD DS DS DS OUT OUT OUT OEN OEN OEN

IOU48CS IOU48S IU24S

PU PU PU IE IE IE IN IN PAD IN PAD PAD DS DS DS OUT OUT OUT OEN OEN OEN

OZD48C XTAL OZU48C

IE PU IN XE XC IE PD IN PAD PAD DS DS OUT OUT XO XC OEN OEN

Figure 196: Schematic view of netX 90 PAD types

Explanation of the symbols used in the schematics above:

Symbol Description Symbol Description DS drive select OUT output signal IE input enable PD pull-down IN input signal PU pull-up OEN output enable

Figure 197: Packaging top, side, and bottom view

Dimensions, see next page.

Symbol Common dimensions min. nom. max. Package: LFBGA Body size: X E 10.000 Y D 10.000 Ball pitch: e 0.800 Total thickness: A - - 1.400 Mold thickness: M 0.650 Ref. Substrate thickness: S 0.260 Ref. Ball diameter: 0.400 Stand off: A1 0.270 - 0.370 Ball width: b 0.380 - 0.480 Package edge tolerance aaa 0.150 Mold parallelism: ccc 0.200 Coplanarity: ddd 0.120 Ball offset (package): eee 0.150 Ball offset (ball): fff 0.080 Ball count: n 144 Edge ball center to center: X E1 8.800 Y D1 8.800 Figure 198: Packaging dimensions

The estimated thermal resistance Rthja indicates a value of ~20 K/W.

The maximum junction temperature Tj is specified with 125 °C (absolute max. rating).

The standard ambient temperature range for industrial is Ta -40 °C ... +85 °C.

Figure 199: netX 90 thermal resistance

Note: The qualification of the device (thermal analysis and lifetime estimation for mission profiles with Ta up to 105 °C) requires the final design (mass production devices).

Use case with internal Ethernet PHYs Design target Standalone chip application*1) ≤ 1 W Companion chip (without SDRAM and APP side) ≤ 0.8 W *1) By default, the Cortex-M4 of the application side is held in reset and clock gated after power-on reset. The ROM loader (Mask ROM code) enables the Cortex-M4 of the application side during the boot sequence if a firmware image is in the application flash.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 netX 90 package and signal information 258/275 8.7 Handling standards The 144-Pin BGA is compliant with the standards:  IPC/JEDEC J-STD-020E, see reference [9]  IPC/JEDEC J-STD-033D, see reference [10]

Note: Both JEDEC documents can be downloaded free of charge after registration at https://www.jedec.org/user/register

8.7.1 Moisture sensitivity level The moisture sensitivity level (MSL) is 3. 168 hours, ≤ 30 °C / 60% RH (moisture soak level 3: 192 hours, 30 °C / 60 % RH)

Figure 200: netX 90 Moisture sensitivity levels

Source of Figure 200, see reference [9].

Storage The sealed dry packs must be stored at the following conditions:

Parameter Value Temperature < 40 °C Relative humidity < 90 % Table 54: Storage conditions

Floor life Unpacked devices have a floor life of 168 hours, i. e. before the soldering process, open dry packs can be stored for 7 days at the following conditions:

Parameter Value Temperature ≤ 30 °C Relative humidity ≤ 60 % Table 55: Floor life conditions

To stop the floor life clock, store unpacked devices in a dry cabinet (relative humidity ≤ 10 %).

Bake time If the max. floor life or the environmental conditions is exceeded or if the humidity indicator card (delivered with the dry pack) shows a moisture level of >10 % after the dry pack has been opened, the devices must be dried (baked) prior to soldering to avoid device damage during the soldering process (cracking or delamination). Min. baking time at 125 °C: 8 hours. Further applicable baking conditions, see Figure 201 on page 260.

Figure 201: netX 90 Reference conditions for drying

Source of Figure 201, see reference [10].

Profile feature Pb-free assembly Preheat/soak

Temperature min (Tsmin) 150 °C

Temperature max (Tsmax) 200 °C

Time (ts) from (Tsmin to Tsmax) 60-120 seconds

Ramp-up rate (TL to Tp) 3 °C/second max.

Liquidous temperature (TL) 217 °C

Time (tL) maintained above TL 60-150 seconds

Peak package body temperature (Tp) 260 °C

Time (tp)* within 5 °C of the specified classification temperature (Tc), see Figure 202 30 seconds*

Ramp-down rate (Tp to TL) 6 °C/second max. Time 25 °C to peak temperature 8 minutes max.

* The tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum. If, e.g. Tc is 260 °C and time tp is 30 seconds, this means for  suppliers: Min. peak temperature: 260 °C. Min. time above 255 °C: 30 seconds.  users: Max. peak temperature: 260 °C. Max. time above 255 °C: 30 seconds.

Supplier T ≥ T p C User Tp ≤ TC

TC -5°C Supplier tp User tp

Tp TC -5°C max. ramp up rate = 3°C/s tp max. ramp down rate = 6°C/s

TL t Tsmax Preheat area

Tsmin

ts T e m p r a t u

25 Time 25°C to peak Time

Figure 202: netX 90 Reflow classification profile

Term Description ACK ACKnowledde ADC Analog-to-Digital Converter AES Advanced Encryption Standard AHB Advanced High-performance Bus AHBL Advanced High-performance Bus Light APB Advanced Peripheral Bus APM Asynchronous Page Mode APP APPlication ARM Advanced RISC Machines Limited ASIC Application Specific Integrated Circuit BGA Ball Grid Array BiSS Bidirectional Serial Synchronous BOD Brown Out Detection BOM Bill Of Materials CAN Controller Area Network CAS Column Address Strobe CDT netX Studio C/C++ Development Tooling CLK Clock CNT Counter COM COMmunication CPU Central Processing Unit CRC Cyclic Redundancy Check(sum) CS Chip Select DC Direct Current DDR Double Data Rate DFP Dynamic Frame Packing DMA Direct Memory Access DMAC Direct Memory Access Controller DMUX DeMUltipleXer DPM Dual-Port Memory DQM Data Qualifier Mask DSP Digital Signal Processor D-TCM Data - Tightly Coupled Memory ECC Error Correcting Code ECC Elliptic Curve Cryptography EEPROM Electrically Erasable Programmable Read Only Memory EMC ElectroMagnetical Compatibility EMSA-PSS Encoding Method for Signature Appendix - Probabilistic Signature Scheme EnDat Encoder Data EOT End Of Transmission ExtBus Extension Bus FFWD fast-forwarding FIFO First In First Out netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Appendix 264/275

Term Description FIQ Frequently Asked Question FPU Floating Point Unit FSM Finite State Machine FSS Frame Slave Select FSU Fast startup FTDI Future Technology Devices International Ltd GPIO General Purpose Input Output HAL Hardware Abstraction Layer HIF Host InterFace High-z High-impedance IEC International Electronical Commission IEEE Institute of Electrical and Electronics Engineers I/F Interface IO or I/O Input Output or Input/Output IoT / IIoT Internet of Things / Industrial Internet of Things IP Intellectual Property IRQ Interrupt ReQuest ITCM Instruction - Tightly Coupled Memory I2C Inter-Integrated Circuit JTAG Joint Test Action Group LDO Low dropout regulator LED Light Emitting Diode LLI Linked List Items LSB Least Significant Bit LVDS Low Voltage Differential Signal MAC Media Access Controller MCU MicroController Unit MISO Master In Slave Out MLED Multi Light Emitting Diode MMC Multi Media Card MMIO Multiplex Matrix Input/Output MOSI Master Out Slave In MPU Memory Protection Unit MPWM Motion Pulse Width Modulation MUL MULtiplier MSB Most Significant Bit MUX MUltipleXer NAND-Flash Not + AND NER Error Message I/O, low active NOR-Flash Not + OR NVIC Nested Vectored Interrupt Controller NVRAM Non-Volatile Random Access Memory PCB Printed Circuit Board P/E Program/Erase PHY Physical Layer PIO Programmable Input/Output PLL Phase Lock Loop netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Appendix 265/275

Term Description POR Power-On Reset PWM Pulse-Width Modulation QDR Quadruple Data Rate QEI Quadrature Encoder Interface QSPI Quad Serial Peripheral Interface RAM Random Access Memory R/nW Bit “Read/not-Write” ROM Read Only Memory RTM Recovery Time Measurement R/W Used in register or bit descriptions: Bit (or register) can be read and written. RXD Receive Data S&H Sample and Hold circuit SAR ADC Successive Approximation Register Analog to Digital Converter SCL I2C signal: Serial Clock SDA I2C signal: Serial Data SDIO Serial Data In Out card SDRAM Synchronous Dynamic Random Access Memory SHA Secure Hash Algorithm SIMD Single Instruction Multiple Data SoC System on a Chip SPH Serial Clock PHase SPI Serial Peripheral Interface SPM Serial (Dual-)Port Memory SPO Serial Clock Polarity SQI Serial Quad I/O SQIROM Serial Quad I/O Read Only Memory SRAM Static Random-Access Memory SS Slave-Select SSI Synchronous Serial Interface SSL Secure Sockets Layer TC Threshold Capture TCM Tightly Coupled Memory TFTP Trivial File Transfer Protocol TI-OMAP Texas Instruments Open Multimedia Application Platform TLS Transport Layer Security TPIU Trace Port Interface Unit TSN Time-Sensitive Networking TXD Transmit Data UART Universal Asynchronous Receiver/Transmitter WDC WatchDog Counter WDG WatchDog xC flexible Communication (channel) XM XMAC (fleXible Media Access Controller) xPEC fleXible Protocol Execution Controller xPIC fleXible Peripheral Interface Controller Table 56: Terms, abbreviations, and definitions

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netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Appendix 269/275 9.3 Registered trademarks I2C is a registered trademark of NXP Semiconductors, formerly Philips Semiconductors. CANopen® is a registered trademark of CAN in AUTOMATION - International Users and Manufacturers Group e.V. (CiA), Nürnberg. CC-Link® is a registered trademark of Mitsubishi Electric Corporation, Tokyo, Japan. DeviceNet® and EtherNet/IP® are trademarks of ODVA (Open DeviceNet Vendor Association, Inc). EtherCAT® is a registered trademark and a patented technology of Beckhoff Automation GmbH, Verl, Germany, formerly Elektro Beckhoff GmbH. Modbus® is a registered trademark of Schneider Electric. Powerlink is a registered trademark of B&R, Bernecker + Rainer Industrie-Elektronik Ges.m.b.H, Eggelsberg, Austria Sercos interface® is a registered trademark of Sercos International e. V., Suessen, Germany. All other mentioned trademarks are property of their respective legal owners.

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Appendix 270/275 9.4 List of tables Table 1: List of revisions...... 5 Table 2: References to documents ...... 6 Table 3: Technical data ...... 11 Table 4: netX 90 signal description ...... 16 Table 5: DMA controllers data packing or unpacking depending on the programmed mode ...... 21 Table 6: Memory map of application side ...... 23 Table 7: Reset ...... 25 Table 8: Interrupt vectors ...... 31 Table 9: Watchdog counters and signals ...... 34 Table 10: SDRAM parameters ...... 38 Table 11: SDRAM memory size and organization ...... 38 Table 12: netX 90 SDRAM (Synchronous Dynamic Random Access Memory interface) ...... 39 Table 13: SDRAM timing requirement ...... 43 Table 14: Boot modes (RDY and RUN signal) ...... 62 Table 15: Pin configuration console modes ...... 63 Table 16: States of system LED (used from the ROM code)...... 64 Table 17: LED state definitions of system LED (used from the ROM code) ...... 64 Table 18: Multiplex matrix signals ...... 66 Table 19: Pin functions of parallel DPM ...... 71 Table 20: netX 90 DPM0+1_SPI signals and DPM0+1_SQI signals ...... 83 Table 21: netX 90 – SQI/SPI modes ...... 132 Table 22: netX 90 – SQI/SPI signal names listed according to mode ...... 133 Table 23: Data placement example of a 6-byte transfer ...... 144 Table 24: I/O timing parameters ...... 150 Table 25: I/O timing parameters ...... 163 Table 26: Combinations of GPIO_APP pins in "PWM with shadow register mode" ...... 177 Table 27: Combinations of GPIO pins in "PWM with shadow register mode" ...... 177 Table 28: I/O timing parameters ...... 181 Table 29: PIO ...... 182 Table 30: IO-Link Baud rates ...... 191 Table 31: Analog input channels ...... 193 Table 32: Motion PWM shared-with signals ...... 205 Table 33: Motion Encoder shared-with signals ...... 214 Table 34: Eletcrical specification ...... 219 Table 35: Absolute maximum ratings ...... 219 Table 36: Measured current consumption ...... 221 Table 37: Eletcrical specification ...... 222 Table 38: Absolute maximum ratings ...... 222 Table 39: General operating conditions...... 223 Table 40: Absolute maximum ratings ...... 224 Table 41: Electrical specification ...... 224 Table 42: Absolute maximum ratings ...... 224 Table 43: Electrical specification ...... 225 Table 44: Absolute maximum ratings ...... 225 Table 45: Flash memory block programming ...... 226 Table 46: Flash memory block characteristics ...... 226 Table 47: Electrical specification ...... 226 Table 48: Absolute maximum ratings ...... 226 Table 49: netX 90 – Signals (pin table sorted by signals) ...... 244 Table 50: netX 90 – Pin A1 … M12 (pin table sorted by pin number) ...... 250 Table 51: Pin overview netX 90: Colors ...... 252 Table 52: PAD type explanation netX 90...... 253 Table 53: Power-on description ...... 253 Table 54: Storage conditions ...... 259 Table 55: Floor life conditions ...... 259 Table 56: Terms, abbreviations, and definitions ...... 265

netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Appendix 271/275 9.5 List of figures Figure 1: Block diagram ...... 9 Figure 2: Simplified block diagram of the DMA controllers ...... 18 Figure 3: Simplified internal structure of the DMA controller ...... 20 Figure 4: netX 90 BOD structure ...... 24 Figure 5: Power supply scheme DC-DC...... 26 Figure 6: netX 90 oscillator ...... 27 Figure 7: Thermal diode ...... 27 Figure 8: Temperature error ...... 28 Figure 9: Timer function diagram ...... 32 Figure 10: System time ...... 33 Figure 11: Ongoing correction of time failure ...... 33 Figure 12: Internal structure of the watchdog logic ...... 34 Figure 13: Timing diagram of WDG_ACT...... 34 Figure 14: 16-bit SDRAM connection of netX 90 ...... 40 Figure 15: Read access from different SDRAM banks ...... 42 Figure 16: Read access from the same SDRAM banks ...... 42 Figure 17: SDRAM power-up and mode register initialization ...... 44 Figure 18: SDRAM auto refresh generation ...... 45 Figure 19: SDRAM self refresh mode entry and exit ...... 46 Figure 20: SDRAM write timing (SD_CKE is always high) ...... 46 Figure 21: SDRAM read timing (SD_CKE is always high)...... 47 Figure 22: Single read (left) and single write (right) access...... 51 Figure 23: Sequential read pre and post pause not disabled (compatible with netX 50, 100, 500, default) ...... 51 Figure 24: Sequential read pre and post pause disabled (recommended for memory devices) ...... 52 Figure 25: Sequential write ...... 52 Figure 26: Insertion of pre and post-pause at write and data direction change when 0 is configured ...... 52 Figure 27: Insertion of pre and post-pause at chip-select change if 0 is configured ...... 53 Figure 28: Pre and post-pause at chip-select or data direction change if 0 is not configured...... 53 Figure 29: APM read burst ...... 54 Figure 30: Read access with external wait state generation ...... 55 Figure 31: Read access with external wait state generation ...... 55 Figure 32: Read, pre and post-pauses enabled for sequential reads (write enable always high) ...... 57 Figure 33: Read, pre and post-pauses disabled for sequential reads (write enable always high) ...... 57 Figure 34: APM read burst, pre and post-pauses disabled between sequential reads ...... 57 Figure 35: Write (read enable always high) ...... 58 Figure 36: ROM code boot sequence ...... 61 Figure 37: Pin configuration operating modes ...... 62 Figure 38: Host interface block diagram ...... 67 Figure 39: Non-multiplexed mode read access and ready generation (SRAM mode example) ...... 75 Figure 40: Multiplexed mode read access and ready generation (SRAM mode example) ...... 75 Figure 41: Non-multiplexed mode write access ready generation (SRAM mode example) ...... 76 Figure 42: Multiplexed mode write access ready generation (SRAM mode example) ...... 76 Figure 43: Read data setup time and read address setup time (SRAM read) ...... 77 Figure 44: Hazards and spikes which will be suppressed when signal filtering is enabled ...... 79 Figure 45: IRQ signal driving modes ...... 81 Figure 46: SPI SPO=0 and SPH=0 transfer ...... 85 Figure 47: SPI SPO=0 and SPH=1 transfer ...... 85 Figure 48: SPI SPO=1 and SPH=0 transfer ...... 86 Figure 49: SPI SPO=1 and SPH=1 transfer ...... 86 Figure 50: Serial DPM protocol: straight stream, type 0 ...... 87 Figure 51: Serial mode 0 QSPI frame format example ...... 88 Figure 52: SQI Serial DPM protocol: straight stream, type 0 ...... 89 Figure 53: Handshake cell DWORD ...... 90 Figure 54: Handshake cell dataflow (16-bit) ...... 90 Figure 55: Handshake cell monitoring of intramhs ...... 92 Figure 56: Detailed timing of DPM SRAM mode read access DPM_RDn controlled ...... 94 Figure 57: Detailed timing of DPM SRAM mode read access DPM_CSn controlled...... 94 Figure 58: Detailed timing of DPM read burst access (DPM_A or DPM_DQM change without DPM_CSn or DPM_RDn toggling) ...... 95 Figure 59: Detailed timing of DPM SRAM mode write access when internal netX DPM side is idle (no insertion of wait cycles) ...... 96 Figure 60: Detailed timing of DPM SRAM mode write access when internal netX DPM side busy (insertion of wait cycles) ...... 97 Figure 61: Detailed timing of multiplexed SRAM mode read access ...... 99 Figure 62: Detailed timing of multiplexed SRAM mode read access with address phase overlapping into read-active phase ...... 100 netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Appendix 272/275 Figure 63: Detailed timing of multiplexed SRAM mode write access when internal netX DPM side is idle (no insertion of wait cycles) ...... 101 Figure 64: Detailed timing of multiplexed SRAM mode write access when internal netX DPM side busy (insertion of wait cycles) ...... 102 Figure 65: Detailed timing of multiplexed SRAM mode write access with address phase overlapping into write-active phase ...... 103 Figure 66: Detailed timing of an Intel-like byte enable controlled read access ...... 105 Figure 67: Detailed timing of an Intel-like chip-select controlled read access with read byte enables ...... 105 Figure 68: Detailed timing of an Intel-like read access not using read byte enables ...... 106 Figure 69: Detailed timing of an Intel-like write access with write byte enables ...... 107 Figure 70: Detailed timing of an Intel-like multiplexed mode read access ...... 108 Figure 71: Detailed timing of an Intel-like multiplexed mode read access with address phase overlapping with read-active phase ...... 109 Figure 72: Detailed timing of an Intel-like multiplexed mode read access without byte enables ...... 110 Figure 73: Detailed timing of an Intel-like multiplexed mode write access when internal netX DPM side busy (insertion of wait cycles) ...... 111 Figure 74: Detailed timing of a Motorola-like byte enable controlled read access ...... 113 Figure 75: Detailed timing of a Motorola-like chip-select controlled read access ...... 113 Figure 76: Detailed timing of a Motorola-like write access with write byte enables ...... 114 Figure 77: Detailed timing of a Motorola-like multiplexed mode read access ...... 115 Figure 78: Detailed timing of a Motorola-like multiplexed mode read access with address phase overlapping with read- active phase ...... 116 Figure 79: Detailed timing of an Intel-like multiplexed mode write access when internal netX DPM side busy (insertion of wait cycles)...... 117 Figure 80: DPM SPI slave timing SPO=0 and SPH=0 transfer (data valid on positive edge of serial clock) ...... 123 Figure 81: DPM SPI slave timing SPO=0 and SPH=1 transfer (data valid on negative edge of serial clock) ...... 124 Figure 82: DPM SPI slave timing SPO=1 and SPH=0 transfer (data valid on positive edge of serial clock) ...... 124 Figure 83: DPM SPI slave timing SPO=1 and SPH=1 transfer (data valid on negative edge of serial clock) ...... 124 Figure 84: SPI timing SPO=0 and SPH=0 transfer (data generation on falling edge, sampling on rising edge of SPI_CLK) ...... 126 Figure 85: SPI timing SPO=0 and SPH=1 transfer (data generation on rising edge, sampling on falling edge of SPI_CLK) ...... 126 Figure 86: SPI timing SPO=1 and SPH=0 transfer (data generation on rising edge, sampling on falling edge of SPI_CLK) ...... 126 Figure 87: SPI timing SPO=1 and SPH=1 transfer (data generation on falling edge, sampling on rising edge of SPI_CLK) ...... 127 Figure 88: SPI slave signal timing (SPO=0 and SPH=0) ...... 129 Figure 89: SPI slave signal timing (SPO=0 and SPH=1) ...... 129 Figure 90: SPI slave signal timing (SPO=1 and SPH=0) ...... 130 Figure 91: SPI slave signal timing (SPO=1 and SPH=1) ...... 130 Figure 92: Block diagram: Separate SQI peripheral mode and SQIROM/XiP mode ...... 134 Figure 93: Standard external SPI interconnection ...... 136 Figure 94: Extended external SPI interconnection with DMUX ...... 136 Figure 95: Quad SPI (SQI) and XiP/SQIROM interconnection ...... 137 Figure 96: SPI SPO=0 and SPH=0 transfer (mode 0) ...... 139 Figure 97: SPI SPO=0 and SPH=0 transfer (mode 0) without chip-select toggling ...... 139 Figure 98: SPI SPO=0 and SPH=1 transfer (mode 1) ...... 139 Figure 99: SPI SPO=1 and SPH=0 transfer (mode 2) ...... 140 Figure 100: SPI SPO=1 and SPH=0 transfer (mode 2) without chip-select toggling ...... 140 Figure 101: SPI SPO=1 and SPH=1 transfer (mode 3) ...... 140 Figure 102: SQI mode 0 and 3 transfer example ...... 141 Figure 103: Transfer bit order: MSB or LSB first ...... 143 Figure 104: Transfer byte order: Little or big endianness, MSB first ...... 143 Figure 105: Data on the wire for data placement example of a 6-byte transfer ...... 143 Figure 106: SQIROM header starting with command byte (bit addr_before_cmd not set) ...... 146 Figure 107: SQIROM header starting with address bytes (bit addr_before_cmd set) ...... 146 Figure 108: SQIROM data organization ...... 146 Figure 109: 32-bit CPU code execution related to data rate estimation (2 dummy cycles, 5 address cycles, 1 SCK min chip-select idle time) ...... 148 Figure 110: SPI timing SPO=0 and SPH=0 transfer (data sampling on positive edge, generation on negative edge of SQI_CLK) ...... 149 Figure 111: SPI timing SPO=0 and SPH=1 transfer (data sampling on negative edge, generation on positive edge of SQI_CLK) ...... 149 Figure 112: SPI timing SPO=1 and SPH=0 transfer (data sampling on negative edge, generation on positive edge of SQI_CLK) ...... 149 Figure 113: SPI timing SPO=1 and SPH=1 transfer (data sampling on positive edge, generation on negative edge of SQI_CLK) ...... 150 Figure 114: Block diagram of SPI module ...... 152 Figure 115: SPI SPO=0 and SPH=0 transfer (mode 0) ...... 153 netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Appendix 273/275 Figure 116: SPI SPO=0 and SPH=1 transfer (mode 1) ...... 154 Figure 117: SPI SPO=1 and SPH=0 transfer (mode 2) ...... 154 Figure 118: SPI SPO=1 and SPH=1 transfer (mode 3) ...... 154 Figure 119: Standard external SPI interconnection ...... 155 Figure 120: Extended external SPI interconnection with DMUX ...... 155 Figure 121: I2C module block diagram ...... 158 Figure 122: I2C signal conditions ...... 160 Figure 123: I2C 1-byte transfer ...... 160 Figure 124: I2C write transfer (master to slave) ...... 161 Figure 125: I2C read transfer (master from slave) ...... 161 Figure 126: I2C transfer with direction change ...... 161 Figure 127: I2C 10-bit addressing ...... 162 Figure 128: I2C initializing a read transfer from a 10-bit address slave ...... 162 Figure 129: Timing on I2C bus ...... 163 Figure 130: Block diagram (signals marked with [*] are valid for com-side Multi-LED module only) ...... 164 Figure 131: External connection examples ...... 165 Figure 132: Example of internal generation of the output pin ...... 166 Figure 133: GPIO block diagram ...... 169 Figure 134: Simple IO logic ...... 172 Figure 135: Capture continued at rising edge ...... 173 Figure 136: Capture once at rising edge ...... 173 Figure 137: Capture once at high level ...... 174 Figure 138: Counting rising edges of GPIO0 ...... 174 Figure 139: Active time measurement (e.g. GPIO0 is active in 5 of 13 clk cycles) ...... 175 Figure 140: Watchdog mode for GPIO0 (low level should not last longer than 50 ns here) ...... 175 Figure 141: Triangle (GPIO1/COUNTER1) versus sawtooth (GPIO0/COUNTER0) ...... 176 Figure 142: PWM with shadow register: GPIO1 used GPIO_TC register of GPIO2 ...... 177 Figure 143: DC-DC PWM ...... 178 Figure 144: Sequencer logic ...... 179 Figure 145: Example sequencer output (UART frame "0x69" in 8n1@33 MHz) ...... 179 Figure 146: Access of ARM and xPIC via separate CPU busses ...... 180 Figure 147: netX IRQ logic (exists once for each CPU address area) ...... 181 Figure 148: Block diagram ...... 183 Figure 149: Block diagram ...... 185 Figure 150: Block diagram of the UART ...... 188 Figure 151: IO-Link: Block diagram of a single port ...... 191 Figure 152: netX 90 with 8 IO-Link ports ...... 192 Figure 153: netX 90 IO-Link master interfacing ...... 192 Figure 154: ADC block diagram ...... 193 Figure 155: MPWM motion icons ...... 194 Figure 156: Motion PWM block diagram ...... 196 Figure 157: Sawtooth mode ...... 199 Figure 158: Inverse sawtooth mode ...... 199 Figure 159: Triangle mode ...... 199 Figure 160: Inverse triangle mode ...... 199 Figure 161: Compare channels ...... 200 Figure 162: Dead time generators ...... 201 Figure 163: Output sections ...... 202 Figure 164: Error condition input ...... 203 Figure 165: Incremental encoder disk ...... 207 Figure 166: Signals A, B, and N ...... 207 Figure 167: Pos. + neg. sequences of signals A + B ...... 207 Figure 168: Encoder module block diagram ...... 208 Figure 169: Noises in signal ...... 209 Figure 170: Digital filter at the encoder input signals ...... 209 Figure 171: Encoder module ...... 210 Figure 172: Encoder phase error ...... 210 Figure 173: The same “n = 1” by different frequencies ...... 211 Figure 174: Estimating average frequency within time T0 using method 3 ...... 212 Figure 175: Estimating average frequency within time T0 using method 4 ...... 212 Figure 176: Difference between method 3 and 4 ...... 212 Figure 177: Ta/Te mode of Motion Encoder unit ...... 213 Figure 178: Block diagram of the special real-time Ethernet features ...... 216 Figure 179: Current consumption measurement ...... 220 Figure 180: DC/DC converter with POR ...... 223 Figure 181: Power up and down ...... 224 Figure 182: MMIO level change ...... 228 Figure 183: MMIO output enable ...... 228 Figure 184: MMIO output disable ...... 228 netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Appendix 274/275 Figure 185: SPI timing SPO=0 and SPH=0 transfer (data generation on falling edge, sampling on rising edge of SPI_CLK) ...... 230 Figure 186: SPI timing SPO=0 and SPH=1 transfer (data generation on rising edge, sampling on falling edge of SPI_CLK) ...... 230 Figure 187: SPI timing SPO=1 and SPH=0 transfer (data generation on rising edge, sampling on falling edge of SPI_CLK) ...... 231 Figure 188: SPI timing SPO=1 and SPH=1 transfer (data generation on falling edge, sampling on rising edge of SPI_CLK) ...... 231 Figure 189: SPI master signal timing (SPO=0 and SPH=0) ...... 234 Figure 190: SPI master signal timing (SPO=0 and SPH=1) ...... 234 Figure 191: SPI master signal timing (SPO=1 and SPH=0) ...... 235 Figure 192: SPI master signal timing (SPO=1 and SPH=1) ...... 235 Figure 193: Timing on I2C bus ...... 237 Figure 194: UART ...... 238 Figure 195: Pin overview netX 90 ...... 251 Figure 196: Schematic view of netX 90 PAD types ...... 254 Figure 197: Packaging top, side, and bottom view ...... 255 Figure 198: Packaging dimensions ...... 256 Figure 199: netX 90 thermal resistance...... 257 Figure 200: netX 90 Moisture sensitivity levels ...... 258 Figure 201: netX 90 Reference conditions for drying ...... 260 Figure 202: netX 90 Reflow classification profile ...... 262

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Subsidiaries

China Japan Hilscher Systemautomation (Shanghai) Co. Ltd. Hilscher Japan KK 200010 Shanghai Tokyo, 160-0022 Phone: +86 (0) 21-6355-5161 Phone: +81 (0) 3-5362-0521 E-Mail: [email protected] E-Mail: [email protected] Support Support Phone: +86 (0) 21-6355-5161 Phone: +81 (0) 3-5362-0521 E-Mail: [email protected] E-Mail: [email protected]

France Korea Hilscher France S.a.r.l. Hilscher Korea Inc. 69500 Bron Seongnam, Gyeonggi, 463-400 Phone: +33 (0) 4 72 37 98 40 Phone: +82 (0) 31-789-3715 E-Mail: [email protected] E-Mail: [email protected] Support Phone: +33 (0) 4 72 37 98 40 Switzerland E-Mail: [email protected] Hilscher Swiss GmbH 4500 Solothurn India Phone: +41 (0) 32 623 6633 Hilscher India Pvt. Ltd. E-Mail: [email protected] Pune, Delhi, Mumbai Support Phone: +91 8888 750 777 Phone: +49 (0) 6190 9907-99 E-Mail: [email protected] E-Mail: [email protected]

Italy USA Hilscher Italia S.r.l. Hilscher North America, Inc. 20090 Vimodrone (MI) Lisle, IL 60532 Phone: +39 02 25007068 Phone: +1 630-505-5301 E-Mail: [email protected] E-Mail: [email protected] Support Support Phone: +39 02 25007068 Phone: +1 630-505-5301 E-Mail: [email protected] E-Mail: [email protected]