Technical data reference guide netX 90 Mass production Hilscher Gesellschaft für Systemautomation mbH www.hilscher.com DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public Introduction 2/275 Table of contents 1 Introduction ............................................................................................................................................. 5 1.1 About this document ...................................................................................................................... 5 1.2 List of revisions............................................................................................................................... 5 1.3 References to documents .............................................................................................................. 6 2 General description and features ......................................................................................................... 7 2.1 Block diagram................................................................................................................................. 9 2.2 Technical data netX 90 ................................................................................................................ 10 2.3 netX 90 signal description ............................................................................................................ 12 3 Core ....................................................................................................................................................... 17 3.1 CPU .............................................................................................................................................. 17 3.1.1 Cortex®-M4 CPU ............................................................................................................................ 17 3.1.2 xPIC CPU ........................................................................................................................................ 17 3.2 DMAC ........................................................................................................................................... 18 3.2.1 Overview ......................................................................................................................................... 18 3.2.2 Features .......................................................................................................................................... 19 3.2.3 Typical applications ......................................................................................................................... 19 3.2.4 Functional description...................................................................................................................... 20 3.2.5 Data transfer .................................................................................................................................... 21 3.2.6 DMA channel priority ....................................................................................................................... 22 3.2.7 DMA flow control ............................................................................................................................. 22 3.3 Crypto core ................................................................................................................................... 22 3.4 Memory map ................................................................................................................................ 23 3.5 Brown-Out Detector (BOD) .......................................................................................................... 24 3.6 Reset ............................................................................................................................................ 25 3.7 Power-on reset and DC/DC ......................................................................................................... 26 3.8 System clock (oscillator) .............................................................................................................. 27 3.9 Temperature sensor ..................................................................................................................... 27 3.10 Interrupt vectors ........................................................................................................................... 30 3.11 Timer ............................................................................................................................................ 32 3.11.1 CPU timer ........................................................................................................................................ 32 3.11.2 IEEE 1588 system time ................................................................................................................... 33 3.12 Watchdog ..................................................................................................................................... 34 3.12.1 Function ........................................................................................................................................... 34 3.12.2 WDG_ACT signal ............................................................................................................................ 34 3.13 Internal memory ........................................................................................................................... 35 3.13.1 Internal Flash ................................................................................................................................... 35 3.13.2 Internal RAM ................................................................................................................................... 35 3.14 External memory .......................................................................................................................... 36 3.14.1 Overview ......................................................................................................................................... 36 3.14.2 Features .......................................................................................................................................... 37 3.14.3 SDRAM interface ............................................................................................................................. 38 3.14.4 SRAM/Flash interface to memory interface controller ..................................................................... 50 4 Booting and SYS LED .......................................................................................................................... 61 4.1 Boot sequence and boot mode .................................................................................................... 61 4.1.1 Overview ......................................................................................................................................... 62 4.1.2 Standard boot mode ........................................................................................................................ 62 4.1.3 Console mode ................................................................................................................................. 63 4.1.4 Alternative boot mode...................................................................................................................... 63 4.2 System LED ................................................................................................................................. 64 5 Interfaces ............................................................................................................................................... 65 5.1 MMIO - Multiplex Matrix ............................................................................................................... 65 5.2 Host interface ............................................................................................................................... 67 5.2.1 Overview ......................................................................................................................................... 67 5.2.2 Block diagram .................................................................................................................................. 67 5.2.3 Features .......................................................................................................................................... 68 5.2.4 Dual-port memory interface structure .............................................................................................. 69 5.2.5 Parallel dual-port memory interface ................................................................................................. 70 5.2.6 Serial dual-port memory interface ................................................................................................... 83 5.2.7 Handshake registers........................................................................................................................ 90 5.2.8 Parallel dual-port memory timing ..................................................................................................... 93 netX 90 | Technical data reference guide DOC160609TRG05EN | Revision 5 | English | 2019-10 | Released | Public © Hilscher, 2017-2019 Introduction 3/275 5.2.9 Serial dual-port memory timing ...................................................................................................... 123 5.3 SQI/SPI .....................................................................................................................................