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Freescale Powerpc Architecture Primer, Rev Freescale PowerPC™ Architecture Primer POWRPCARCPRMRM Rev. 0.1, 6/2005 How to Reach Us: Home Page: www.freescale.com email: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) Information in this document is provided solely to enable system and software +49 89 92103 559 (German) implementers to use Freescale Semiconductor products. There are no express or +33 1 69 35 48 48 (French) implied copyright licenses granted hereunder to design or fabricate any integrated [email protected] circuits or integrated circuits based on the information in this document. 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Box 5405 unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor Denver, Colorado 80217 and its officers, employees, subsidiaries, affiliates, and distributors harmless against all (800) 441-2447 claims, costs, damages, and expenses, and reasonable attorney fees arising out of, 303-675-2140 directly or indirectly, any claim of personal injury or death associated with such Fax: 303-675-2150 LDCForFreescaleSemiconductor unintended or unauthorized use, even if such claim alleges that Freescale @hibbertgroup.com Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The PowerPC name is a trademark of IBM Corp. and is used under license. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005. All rights reserved. Document Number: POWRPCARCPRMRM Rev. 0.1, 6/2005 Contents Section Title Page Contents Chapter 1 Architectural Beginnings Divide, Conquer...........................................................................................................................................1 Extension and Expansion.............................................................................................................................2 Freescale’s PowerPC Processor Families ....................................................................................................3 Architecture and Microarchitecture.......................................................................................................3 A Common Microarchitectural Model ...................................................................................................4 A Family Portrait—Cores and Platforms ..............................................................................................7 e200 Cores and Platforms ................................................................................................................8 e300 Cores and Platform..................................................................................................................8 e500 Cores and Platform..................................................................................................................8 e600 Cores and Platforms ................................................................................................................9 Semicustom Processor Platforms.........................................................................................................10 Chapter 2 Architecture Definition The PowerPC Architecture as a RISC Architecture ..................................................................................11 Architectural Extensibility—AltiVec Technology...............................................................................12 Architectural Extensibility—Book E...................................................................................................13 Architectural Extensibility—The Freescale Book E Implementation Standards (EIS).......................14 PowerPC Architecture Overview...............................................................................................................15 A Common User Instruction Set Architecture......................................................................................15 Instruction Model.......................................................................................................................................17 Simplified Mnemonics..........................................................................................................................18 Instruction Set Overview......................................................................................................................18 Integer Instructions ........................................................................................................................19 Floating-Point Instructions ............................................................................................................19 Load and Store Instructions ...........................................................................................................21 Branch and Flow Control Instructions...........................................................................................21 Processor Control Instructions......................................................................................................23 Memory Synchronization Instructions ...........................................................................................23 Memory Control Instructions.........................................................................................................23 ISA Extensions—Auxiliary Processing Units (APUs)........................................................................24 AltiVec APU ..................................................................................................................................24 Integer Select APU ........................................................................................................................24 Signal Processing Engine (SPE) APU ...........................................................................................25 Freescale PowerPC Architecture Primer, Rev. 0.1 Freescale Semiconductor iii Contents Section Title Page Embedded Vector and Scalar Single-Precision Floating-Point APUs (SPFP APUs)....................25 Register Model...........................................................................................................................................25 Register Files .......................................................................................................................................29 Instruction-Accessible Registers..........................................................................................................30 Time Base Registers.............................................................................................................................31 MMU Control and Status Registers .....................................................................................................32 L1 Cache Registers ..............................................................................................................................34 Interrupt Registers ...............................................................................................................................35 Configuration Registers.......................................................................................................................37 Performance Monitor Registers (PMRs) .............................................................................................38 Debug Registers...................................................................................................................................39
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