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Mecanismos De Gestión De Escrituras En Sistemas Con Tecnologías De Memoria No Volátiles Write Management Mechanisms for Systems with Non-Volatile Memory Technologies

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Mecanismos De Gestión De Escrituras En Sistemas Con Tecnologías De Memoria No Volátiles Write Management Mechanisms for Systems with Non-Volatile Memory Technologies UNIVERSIDAD COMPLUTENSE DE MADRID FACULTAD DE INFORMÁTICA DEPARTAMENTO DE ARQUITECTURA DE COMPUTADORES Y AUTOMÁTICA TESIS DOCTORAL Mecanismos de gestión de escrituras en sistemas con tecnologías de memoria no volátiles Write management mechanisms for systems with non-volatile memory technologies MEMORIA PARA OPTAR AL GRADO DE DOCTOR PRESENTADA POR Roberto Alonso Rodríguez Rodríguez DIRECTORES Fernando Castro Rodríguez Daniel Ángel Chaver Martínez Madrid, 2017 © Roberto Alonso Rodríguez Rodríguez, 2016 Mecanismos de gestión de escrituras en sistemas con tecnologías de memoria no volátiles (Write management mechanisms for systems with non-volatile memory technologies) Roberto Alonso Rodríguez Rodríguez DACYA ♠ UCM UNIVERSIDAD COMPLUTENSE DE MADRID FACULTAD DE INFORMÁTICA DEPARTAMENTO DE ARQUITECTURA DE COMPUTADORES Y AUTOMÁTICA MECANISMOS DE GESTIÓN DE ESCRITURAS EN SISTEMAS CON TECNOLOGÍAS DE MEMORIA NO VOLÁTILES (WRITE MANAGEMENT MECHANISMS FOR SYSTEMS WITH NON-VOLATILE MEMORY TECHNOLOGIES) MEMORIA PARA OPTAR AL GRADO DE DOCTOR PRESENTADA POR Roberto Alonso Rodríguez Rodríguez Bajo la dirección de los doctores Fernando Castro Rodríguez Daniel Ángel Chaver Martínez Madrid 2016 Tesis doctoral presentada por el doctorando Roberto Alonso Rodríguez Rodríguez en el Departamento de Arquitectura de Computadores y Automática de la Universidad Complutense de Madrid para la obtención del título de Doctor en Ingeniería Infor­ mática. Terminada de escribir en Madrid el 31 de agosto de 2016. Título: Mecanismos de gestión de escrituras en sistemas con tecnologías de memoria no volátiles (Write management mechanisms for systems with non-volatile memory technologies) Doctorando: Roberto Alonso Rodríguez Rodríguez ([email protected]) Departamento de Arquitectura de Computadores y Automática, Universidad Complutense Facultad de Informática, 28040 Madrid, España Directores: Fernando Castro Rodríguez ([email protected]) Daniel Ángel Chaver Martínez ([email protected]) Esta tesis doctoral ha sido realizada dentro del grupo de investigación sobre Arqui­ tectura y Tecnología de Sistemas Informáticos de la UCM, como parte de las activi­ dades del proyecto de investigación: Arquitecturas y Tecnologías Emergentes, Eficien­ cia Energética Mediante Heterogeneidad (referencia TIN2012-32180). ISBN-13: 978-84-617-4671-2 Agradecimientos En unas horas estaré entregando la versión final de esta tesis en la que tanto esfuerzo e ilusión hemos puesto muchas personas. Los primeros que vienen a mi mente son Fernando y Dani, mis directores de tesis. Sus nombres aparecen al lado del mío en la portada y es ahí donde han estado durante estos años, a mi lado y poniendo toda su dedicación para que este trabajo fuese exitoso; gracias por darme siempre todo su apoyo sin el cual este trabajo no hubiera sido posible. En este largo viaje hemos tenido la suerte de contar con la inestimable ayuda de mis companeros del grupo ArTeCS: agradecerle a Luis Piñuel su consejo y guía en momentos cruciales y a Juan Carlos Sáez por toda su colaboración sin la cual no hubiera sido posible llegar a este punto. Gracias a Manuel Prieto y Francisco Tirado por estar siempre pendientes y ocuparse de que tuviéramos todo lo necesario para poder llevar a cabo nuestro trabajo. En octubre del 2014 llegaba a Zaragoza para realizar una colaboración con el grupo GAZ de la Universidad de Zaragoza. Agradecer a Pablo Ibáñez y Víctor Viñals por haberme acogido desde el primer momento y durante las dos estancias que realicé en su grupo; por su colaboración y por haberme dado la oportunidad de realizar el trabajo colaborativo con el que culmina esta tesis. Gracias a Michael Huang por permitirme realizar una estancia de investigación en la universidad de Rochester, la cual me permitió ampliar mi perspectiva de la investigación y gracias a los chicos de su laboratorio por haberme hecho sentir en casa. Me gustaría agradecer al profesor Narciso Martí Oliet, quien, como vicedecano de posgrado, día a día nos orienta en todos los trámites haciéndonos más ágiles con ellos. Agradecerles a mis padres Elisa y Roberto; su cariño, cuidado, comprensión y apoyo durante toda mi vida y en especial durante estos años en los que me han demostrado el significado de la palabra generosidad. Sin duda son aquellos que más han sufrido mi ausencia; gracias por esperarme siempre todos los días al otro lado de esa fría pantallita. Agradecimientos De manera especial quisiera agradecer a Laura, quien ha estado conmigo desde el inicio de esta aventura, quien me ha enseñado el significado del trabajo duro y con su ejemplo me ha hecho querer ser mejor cada día, quien con su cariño y apoyo me ha ayudado a seguir cuando no parececía que hubiera luz al final del túnel. También quiero agradecer a Paula, Pepe, Adolfo, Beatriz y Sandrita por haberme acogido y darme una familia en Madrid. Gracias a Rebe con quien la amistad ha transcendido el tiempo y el espacio y siempre ha estado más que dispuesta a ayudarme cuando he requerido de servicio técnico transcontinental. Agradecer a Víctor M. Alfaro, Enrique Coen, Andres Díaz y Jorge Romero por no haber dudado en firmar un cheque en blanco que me ha dado la oportunidad de poder llegar hasta aquí. Por último quiero agradecer a la Universidad de Costa Rica y al Ministerio de Ciencia y Tecnología de Costa Rica por el apoyo brindado para mi formación académica en el exterior. Contents Agradecimientos Contents i List of Figures v List of Tables ix Resumen 1 Abstract 5 1 Introduction 9 1.1 Memory hierarchy ........................... 9 1.2 Conventional memory technologies . 11 1.2.1 Dynamic Random-Access Memory (DRAM) . 11 1.2.2 Static Random-Access Memory (SRAM) . 12 1.2.3 Constraints of conventional memory technologies . 13 1.3 Emerging memory technologies .................... 16 1.3.1 Magnetic RAM (MRAM) and Spin-Transfer Torque RAM (STT-RAM) .......................... 16 1.3.2 Phase Change Memory (PCM) ................ 18 1.3.3 Other NVM technologies ................... 20 1.3.3.1 Flash memory .................... 20 1.3.3.2 Racetrack or Domain Wall Memory (DWM) . 20 1.3.3.3 Ferro-Electric RAM (FeRAM) . 21 1.3.3.4 Resistive RAM (ReRAM) .............. 21 1.4 Motivation and objectives ....................... 21 1.5 Outline ................................. 23 2 Related Work 25 2.1 Conventional cache replacement policies . 25 2.1.1 Least Recently Used (LRU) .................. 27 2.1.2 Not Recently Used (NRU) ................... 28 i ii Contents 2.1.3 Probabilistic escape LIFO (peLIFO) . 29 2.1.4 Static, Bimodal and Dynamic Re-Reference Interval Predic­ tion (SRRIP, BRRIP and DRRIP, respectively) . 29 2.1.5 Signature-based Hit Predictor (SHiP) . 35 2.1.6 Probabilistic Replacement Policy (PRP) . 35 2.2 Architecting PCM for main memory . 36 2.2.1 Write-aware cache replacement policies . 37 2.2.1.1 CLean-Preferred victim selection (CLP) . 37 2.2.1.2 Read-Write Aware (RWA) and Improved RWA (I­ RWA) ......................... 38 2.2.1.3 Adaptive and Combined Wear-out-Aware Replace­ ment algorithms (AC-WAR) . 39 2.2.1.4 Writeback-aware cache partitioning . 40 2.2.1.5 Least-Dirty-First (LDF) . 40 2.2.2 Other proposals ......................... 41 2.2.2.1 Eliminating redundant bit writes . 41 2.2.2.2 Flip-N-write ..................... 42 2.2.2.3 Wear leveling ..................... 42 2.2.2.4 Hybrid memory ................... 43 2.2.2.5 Error resilience .................... 45 2.2.2.6 SLC and MLC .................... 47 2.2.2.7 Data compression .................. 47 2.2.2.8 Quantifying wasted write energy in the memory hierarchy ....................... 48 2.3 Architecting STT-RAM for the last-level cache . 49 2.3.1 Reducing the amount of writes to an STT-RAM LLC . 50 2.3.2 Improving performance of an STT-RAM LLC . 52 3 LLC replacement policies for improving PCM endurance 55 3.1 Proposed policies ............................ 56 3.1.1 Rationale ............................ 56 3.1.2 Implementation ......................... 58 3.2 Experimental framework ........................ 69 3.2.1 General aspects ......................... 70 3.2.2 Endurance model ........................ 72 3.2.3 Memory endurance simulator ................. 74 Contents iii 3.2.4 Energy model .......................... 76 3.3 Evaluation ................................ 77 3.3.1 Write-aware policies in a single-core scenario . 77 3.3.1.1 Contribution of each proposed change . 78 3.3.1.2 Write filtering and endurance . 80 3.3.1.3 Performance ..................... 82 3.3.1.4 Memory energy consumption . 85 3.3.1.5 Putting it all together ................ 86 3.3.2 Write-aware policies in a multi-core scenario . 87 3.3.2.1 Multiprogrammed workloads . 87 3.3.2.1.1 Write filtering and endurance . 88 3.3.2.1.2 Performance ................ 89 3.3.2.1.3 Memory energy consumption . 92 3.3.2.2 Multithreaded applications . 92 3.3.2.2.1 Write filtering and endurance . 93 3.3.2.2.2 Performance ................ 96 3.3.2.2.3 Memory energy consumption . 97 3.3.2.3 Putting it all together ................ 98 3.3.3 Additional analysis ....................... 99 3.3.3.1 Comparison to an optimal policy . 99 3.3.3.2 Implementation overhead . 101 3.3.3.2.1 Algorithm complexity . 101 3.3.3.2.2 Extra storage ................ 102 3.3.3.3 Sensitivity to LLC size . 103 3.4 Conclusions ............................... 106 4 Reuse Detector for STT-RAM LLCs 107 4.1 Proposed design ............................ 108 4.1.1 Rationale ............................ 108 4.1.2 Baseline system ......................... 111 4.1.3 The Reuse Detector ...................... 111 4.1.3.1 Reuse Detector operation . 113 4.1.3.2 Example ....................... 115 4.1.3.3 Implementation details . 118 4.1.4 Reuse Detector vs DASCA .................. 119 4.2 Experimental framework ........................ 119 iv Contents 4.2.1 Energy model .......................... 121 4.3 Evaluation ................................ 123 4.3.1 Evaluation in a single-core scenario . 123 4.3.1.1 Write filtering .................... 124 4.3.1.2 Performance ..................... 125 4.3.1.3 Energy savings .................... 125 4.3.1.4 Discussion .....................
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