Design of Multi Standard Near Field Communication Outphasing Transmitter with Modulation Wave Shaping

Article Design of Multi Standard Near Field Communication Outphasing Transmitter with Modulation Wave Shaping

Žiga Korošak 1, Nejc Suhadolnik 1 and Anton Pleteršek 2,*

1 STMicroelectronics d.o.o., Tehnološki Park 21, 1000 Ljubljana, Slovenia; [email protected] (Ž.K.); [email protected] (N.S.) 2 Faculty of Electrical Engineering, University of Ljubljana, Tržaška Cesta 25, 1000 Ljubljana, Slovenia * Correspondence: [email protected]; Tel.: +386-41-961-342

Abstract: The aim of this work is to tackle the problem of modulation wave shaping in the field of near field communication (NFC) radio frequency identification (RFID). For this purpose, a high- efficiency transmitter circuit was developed to comply with the strict requirements of the newest EMVCo and NFC Forum specifications for pulse shapes. The proposed circuit uses an outphasing modulator that is based on a digital-to-time converter (DTC). The DTC based outphasing modulator supports amplitude shift keying (ASK) modulation, operates at four times the 13.56 MHz carrier frequency and is made fully differential in order to remove the parasitic phase modulation compo- nents. The accompanying transmitter logic includes lookup tables with programmable modulation pulse wave shapes. The modulator solution uses a 64-cell tapped current controlled fully differential delay locked loop (DLL), which produces a 360◦ delay at 54.24 MHz, and a glitch-free multiplexor to select the individual taps. The outphased output from the modulator is mixed to create an RF pulse width modulated (PWM) output, which drives the antenna. Additionally, this implementation is fully compatible with D-class amplifiers enabling high efficiency. A test circuit of the proposed differential multi-standard reader’s transmitter was simulated in 40 nm CMOS technology. Stricter Citation: Korošak, Ž.; Suhadolnik, pulse shape requirements were easily satisfied, while achieving an output linearity of 0.2 bits and N.; Pleteršek, A. Design of Multi maximum power consumption under 7.5 mW. Standard Near Field Communication Outphasing Transmitter with Keywords: RFID; EMVCO; NFC; outphasing; PWM; DLL; TX wave shaping Modulation Wave Shaping. Electronics 2021, 10, 188. https://doi.org/10.3390/electronics 10020188 1. Introduction

Received: 17 December 2020 Radio frequency identification (RFID) has gained prominence in recent years as one of Accepted: 11 January 2021 the dominant technologies in banking [1,2], access control [3], ticketing [4,5], tracking [6] Published: 15 January 2021 and in the Internet of things [7]. The technology can broadly be split into devices that operate in the following frequency bands: low frequency (LF), high frequency (HF) and Publisher’s Note: MDPI stays neutral ultra-high frequency (UHF). HF RFID devices that operate at 13.56 MHz are also called near with regard to jurisdictional claims in field communication (NFC) devices. These come in two categories. The first category is published maps and institutional affil- readers or proximity coupling devices (PCD), which are larger, more complex devices that iations. act as masters in the communication. They transmit a magnetic field that powers the tags or proximity inductively coupled cards (PICC), which are the second category of devices. They are usually simpler devices that can be entirely powered from the reader. They act as slaves in the communication and respond to reader’s commands by modulating reader’s Copyright: © 2021 by the authors. magnetic field. Licensee MDPI, Basel, Switzerland. Several standards exist in the field. In the HF frequency range, the most promi- This article is an open access article nent standards are ISO/IEC 14443 A/B, ISO/IEC 15693 and JIS: X6319-4/FeliCa [8–10]. distributed under the terms and A comparison between standards is shown in Table1. conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

Electronics 2021, 10, 188. https://doi.org/10.3390/electronics10020188 https://www.mdpi.com/journal/electronics Electronics 2021, 10, 188 2 of 17 Electronics 2021, 10, x FOR PEER REVIEW 2 of 17

Table 1. Standards comparison. ASK stands for amplitude shift keying, OOK stands for on–off keying, NRZ-L stands for Table 1. Standards comparison. ASK stands for amplitude shift keying, OOK stands for on–off keying, NRZ-L stands for non-return to zero level, BPSK stands for binary phase shift keying. non-return to zero level, BPSK stands for binary phase shift keying. Standard ISO/IEC 15693 JIS: X6319-4/FeliCa ISO/IEC 14443 A ISO/IEC 14443 B Standard ISO/IEC 15693 JIS: X6319-4/FeliCa ISO/IEC 14443 A ISO/IEC 14443 B CarrierCarrier frequency 13.56 13.56 MHz ± ± 7 kHzkHz 13.56 MHzMHz± ±50 50 ppm ppm 13.56 MHzMHz± ±7 7 kHz kHz SubcarrierSubcarrier frequency 423.75/484.28 423.75/484.28 kHzkHz Not usedused 847.5 847.5 kHz, kHz, 1.695 1.695 MHz,3.39 3.39 MHz, MHz, 6.78 6.78 MHz MHz 106106 kbps, kbps, 212 212 kbps, kbps, 424 424 kbps, kbps, 848 kbps, 848 kbps, 1.7 Mbps, 1.7 DataData Rate 6.67 6.67 kbps, kbps, 26.69 kbpskbps 212 212 kbps, 424424 kbps kbps Mbps,3.4 3.4 Mbps, Mbps, 6.8 Mbps 6.8 Mbps ASKASK Modulation Modulation indexindex 10%,10%, 100% 8–14% 8–14% 8–100% 8–14% 8–14% (PCD(PCD to PICC)PICC) DataData coding coding (PCD(PCD to to Modified Miller, PulsePulse position position codingcoding Manchester Modiﬁed Miller, NRZ-L NRZ-LNRZ-L PICC)PICC) NRZ-L ModulationModulation type (PICC(PICC OOKOOK OOKOOK OOK, BPSKBPSK BPSK BPSK toto PCD) Data Coding (PICC to Manchester, Data Coding (PICC to Manchester Manchester Manchester, NRZ-L PCD) Manchester Manchester NRZ-L NRZ-L PCD) NRZ-L

InIn addition to the standards there also exist specificationsspecifications released by organizations and industry industry consortia. consortia. The The main main organizations organizations are are EMVCo EMVCo [11], [11 which], which is an is organization an organiza- responsibletion responsible for payment for payment cards, cards, and NFC and NFCForum Forum [12], [which12], which is a technology is a technology consortium consor- workingtium working to further to further the use the of use HF ofRFID HF RFIDtechnology, technology, branded branded under under their own their name own nameNFC. BothNFC. organizations Both organizations release release their own their versions own versions of specifications, of specifications, which which include include previously previ- mentionedously mentioned standards standards but also but add also their add theirown fu ownnctionality, functionality, certification certification procedures procedures and requirements.and requirements. The recent recent version version of of EMVCo EMVCo specification specification Level Level 1 Specifications 1 Specifications of Payment of Payment Systems Sys- Contactlesstems Contactless Interface Interface Specification Specification Version Version 3.0 [13] 3.0 and [13 Contactless] and Contactless Terminal Terminal Level 1 LevelType Approval1 Type Approval Proximity Proximity Coupling Coupling Devices Devices (PCD) (PCD)Analogue Analogue Test Bench Test Bench and Test and TestCase Case Re- quirementsRequirements version version 3.0a 3.0a [14], [14 as], well as well as newer as newer versions versions of the of specification, the specification, introduce introduce more stringentmore stringent requirements requirements for modulation for modulation pulse pulseshapes. shapes. Similarly, Similarly, the recent the recent version version of NFC of ForumNFC Forum Analog Analog Technical Technical Specification Specification Version Version 2.1 [15] 2.1 [and15] andNFC NFC Forum Forum Test Test Cases Cases for Analogfor Analog Version Version 2.1 2.1[16] [ 16also] also specify specify stricter stricter requirements requirements for for pulse pulse shapes. shapes. Examples Examples of generalof general on–off on–off keying keying (OOK) (OOK) and and amplitude amplitude shift shift keying keying (ASK) (ASK) modulation modulation pulses pulses are displayed in Figure1. Each of the specifications has its own definition of the modulation displayed in Figure 1. Each of the specifications has its own definition of the modulation pulse wave shape. Overshoot, undershoot and ringing level are highlighted in the figure. pulse wave shape. Overshoot, undershoot and ringing level are highlighted in the figure. Modulation pulses in NFC are measured by the spy coil, which is present in the RF field Modulation pulses in NFC are measured by the spy coil, which is present in the RF field alongside the PCD and proximity inductively coupled cards (PICC) coils. The size and alongside the PCD and proximity inductively coupled cards (PICC) coils. The size and shape of the spy coil is specified by each of the specifications. shape of the spy coil is specified by each of the specifications.

Figure 1. Visualization of general purpose OOK and ASK modulation pulses. Overshoot, undershoot and ringing phe- Figure 1. Visualization of general purpose OOK and ASK modulation pulses. Overshoot, undershoot and ringing nomena are highlighted on both types of pulses. phenomena are highlighted on both types of pulses.

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Modulation pulse wave shapes created by the modulator are distorted by the trans- Electronics 2021, 10, 188mission path, which includes an electromagnetic compatibility filter (EMC), matching cir- 3 of 17 cuit, antenna coil and proximity coupled devices loading the antenna. Due to magnetic coupling between the PICC and PCD, the quality and resonance frequency of the antenna coil resonance circuit are affected by the antenna load. The shape of the pulses is thus changed with theModulation distance and pulse the wavenumber shapes of PICCs created present. by the The modulator most relevant are distorted require- by the transmis- ment affectingsion the path, reader’s which transmitter includes an is electromagnetic the overshoot compatibilityand undershoot filter requirement, (EMC), matching circuit, which is displayedantenna in coil Figure and 2. proximity The x axis coupled in the devicesfigure represents loading the the antenna. RF field Due riseto and magnetic fall coupling time. EMVCobetween specifies the this PICC requirement and PCD, to the be qualitytested with and three resonance reference frequency PICCs, of each the antennawith coil reso- two differentnance loads circuit (high arelinear affected load by(HLZ)—820 the antenna Ω load. and Thelow shapelinear ofload the (LLZ)—333 pulses is thus Ω changed) with and in five differentthe distance locations. and the Meanwhile, number of NFC PICCs Forum present. specifies The most three relevant of its own requirement reference affecting the PICC, all withreader’s 820 Ω transmitterload in 14 locations. is the overshoot Satisfying and the undershoot requirements requirement, with a modulator which is displayed in that does notFigure enable2. active The x wave axis in shaping the figure is extremely represents difficult. the RF field rise and fall time. EMVCo specifies This paperthis is requirement organized as to follows. be tested Section with three2 looks reference at existing PICCs, works each in the with field two and different loads attempts to expand(high linear them loadto comply (HLZ)—820 with exisΩ tingand new low linearand future load specifications. (LLZ)—333 Ω )Section and in 3 five different proposes a novellocations. solution Meanwhile, based on NFC a digital- Forumto-time specifies converter three of (DTC). its own Section reference 4 looks PICC, at all with 820 Ω simulation resultsload in for 14 the locations. proposed Satisfying solution theand requirementscompares them with to similar a modulator works. that Lastly, does not enable active wave shaping is extremely difficult. conclusions are presented in Section 5.

Modulation pulse overshoot and undershoot limit 0.450

0.400 EMVCo HLZ 0.350 EMVCo 0.300 LLZ NFC 0.250 Forum

0.200

0.150

0.100

0.050 as a fraction of modulation depth of modulation as a fraction

0.000

Maximum allowed overshoot and undershoot and undershoot overshoot allowed Maximum 0 0.2 0.4 0.6 0.8 1 1.2 Rise or fall time / ns

FigureFigure 2. 2. RequirementRequirement for for radio radio frequency frequency (RF) (RF) field ﬁeld ov overshootershoot in in relation relation to to rise rise or or fall time.

2. Existing TransmitterThis paper Solutions is organized for Near as Field follows. Devices Section 2 looks at existing works in the ﬁeld and In this section,attempts existing to expand works them presenting to comply transmitter with existing solutions new and for futurenear field speciﬁcations. devices Section3 are reviewed.proposes In recent a years, novel solutionnot many based works on have a digital-to-time been published converter in the field (DTC). of trans- Section4 looks at mitter solutionssimulation for NFC. results This was for thedue proposedto the simplicity solution of and modulation compares requirements them to similar prior works. Lastly, to the introductionconclusions of more are stringent presented requirements in Section5. in the last two years.

2.1. Multistandard2. Existing Polar Transmitter Transmitter with Solutions D-Class for Amplifier Near Field Devices The article AIn multi-standard this section, existing analog works front-end presenting circuit transmitterfor 13.56 MHz solutions RFID forreader near [17] ﬁeld devices are reviewed. In recent years, not many works have been published in the ﬁeld of transmitter presents a transmitter in polar architecture [18], which allows ASK modulation. The pre- solutions for NFC. This was due to the simplicity of modulation requirements prior to the sented transmitter consists of a dual p-stage D-class amplifier without a pre-driver. The introduction of more stringent requirements in the last two years.

2.1. Multistandard Polar Transmitter with D-Class Ampliﬁer The article A multi-standard analog front-end circuit for 13.56 MHz RFID reader [17] presents a transmitter in polar architecture [18], which allows ASK modulation. The pre- Electronics 2021, 10, 188 4 of 17 Electronics 2021, 10, x FOR PEER REVIEW 4 of 17

sented transmitter consists of a dual p-stage D-class ampliﬁer without a pre-driver. The dual dualp-stages p-stages can switchcan switch between between supply supply voltage voltage and a and regulated a regulated supply supply voltage, voltage, which which is used isto used create to 10%create ASK 10% modulation. ASK modulation. The regulator The re cangulator also becan switched also be switched off to create off 100%to create ASK 100%modulation. ASK modulation. The transmitter The transmitter has three inputhas thre signals,e input which signals, are which clock, dataare clock, and type data select. and typeThe select. data signal The data is used signal to switchis used between to switch modulated between modulated (data = 0) and(data non-modulated = 0) and non-mod- state ulated(data =state 1). The(data type = 1). select The type signal select is used signal to switch is used between to switch 100% between and 10% 100% ASK and modulation. 10% ASK modulation.When the type When select the signaltype select is high, signal the is circuit high, operatesthe circuit in operates 10% ASK in mode.10% ASK A simpliﬁed mode. A simplifiedcircuit diagram circuit ofdiagram a general of a dualgeneral p-stage dual p-stage polar transmitter, polar transmitter, which operateswhich operates similarly sim- to ilarlywhat to is what presented is presented in Reference in Reference [17], is shown[17], is inshown Figure in3 .Figure 3.

Figure 3. Simplified circuit diagram of a general dual p-stage polar transmitter. The Type sel signal Figurecontrols 3. Simplified the mode ofcircuit operation diagram and of can a general select betweendual p-stage ASK polar and OOKtransmitter. operation. The TheType Data sel signal signal controls the mode of operation and can select between ASK and OOK operation. The Data signal controls the modulation state and can switch between modulated and non-modulated states. controls the modulation state and can switch between modulated and non-modulated states. There are several drawbacks to the solution [17]. There is no non-overlap control circuitThere on theare D-classseveral drawbacks amplifier, causing to the solution cross conduction [17]. There [19 is], no which non-overlap decreases control efficiency cir- cuitof theon driver,the D-class causes amplifier, aging of causing the power cross transistors conduction and [19], limits which the scalabilitydecreases efficiency of the driver of theto higherdriver, outputcauses aging powers. of the The power solution transistor passess the and pulse-shape limits the scalability requirements of the of driver the older to higherstandards; output however, powers. reaching The solution compatibility passes with the thepulse-shape new specifications requirements would of be the extremely older standards;difficult. The however, pulse shape reaching is entirely compatibility dependent with on the transmissionnew specifications path, and would the solutionbe ex- tremelylacks any difficult. means The of actively pulse sh changingape is entirely the antenna dependent characteristic on the transmission or the shape path, of the and pulses. the solutionA possiblelacks any way means to expandof actively this changing work to complythe antenna with characteristic new standards or the is by shape adding of theadaptive pulses. antenna tuning [20]. This can be implemented in a way to ensure a constant magneticA possible field orway constant to expand matching this work impedance. to comply No research with new has standards been done is up by to adding date in adaptiveusing automatic antenna antennatuning [20]. tuning This to can control be im modulationplemented in wave a way shape. to ensure An alternative a constant way mag- to neticexpand field this or constant work is to matching replace theimpedance. simple regulator No research used has to make been ASKdone modulationup to date in with using RF automaticdigital-to-analog antenna converter. tuning to Thiscontrol way, modulati the modulatoron wave bandwidth shape. An could alternative be high way enough to ex- to pandshape this the work relatively is to replace slow modulation the simple pulses. regulator used to make ASK modulation with RF digital-to-analog converter. This way, the modulator bandwidth could be high enough to shape2.2. Multistandard the relatively Pulse slowWidth modulation Modulated pulses. (PWM) Transmitter Based on Delay Locked Loop (DLL) Architecture

The article Design of 13.56 MHz ASK transmitter for near ﬁeld communication using a DLL architecture [21] presents an NFC outphasing PWM [18] transmitter based on a DLL

Electronics 2021, 10, 188 5 of 17

structure. Outphasing is a method of modulation where two transmitted carrier signals’ phase relationship is changed in order to create amplitude and phase modulation. Let us assume, for the purpose of explanation, that we have two ideal cosine transmitters of which the phase can be modulated. Transmitted carrier is thus equal to:

1 v(t) = (cos(2π f + Φ (t)) + cos(2π f + Φ (t))) (1) 2 1 2 The outphasing angles can be split into a common part, where both transmitters are phase modulated in the same direction, and differential part, where transmitters are phase modulated in opposite directions.

Φ1(t) = ϕ(t) + ϑ(t) (2)

Φ2(t) = ϕ(t) − ϑ(t) (3) Inserting this into a previous equation and applying trigonometric relation for cos(a + b) we obtain:

v(t) = 1 (cos(2π f + ϕ(t) + ϑ(t)) + cos(2π f + ϕ(t) − ϑ(t))) 2 (4) = cos(ϑ(t)) ∗ cos(2π f + ϕ(t))

h π i ϑ(t) ∈ 0, , ϕ(t) ∈ [0, 2π] (5) 2 Thus, we obtained the amplitude component of modulation A(t) = cos(ϑ(t)) and phase component of modulation ϕ(t) by using just phase modulators. The same principle works for square signals as well, with higher harmonics being modulated as well. In the case where both carriers are modulated, differential outphasing is obtained, in which phase modulation and amplitude modulation can be separated. If only one of the carriers is modulated, while the other is left at constant phase, single ended outphasing is obtained. In this case both phase modulation and amplitude modulation happen at the same time and cannot be separated. Carriers can also be mixed prior to amplification. This creates RF PWM signals. The presented solution is multi standard and supports modulation indexes from 0% to 100%. It is composed of a load-controlled delay locked loop, which locks its output clock to its input clock. In this way a known phase delay is created. The loop has a phase-frequency detector, which compares its input and output phases to create an input signal for the charge pump. The charge pump moves charge to create a control voltage, which is filtered by a first order loop filter. Variable phase delay in the loop is achieved by using a 6-bit controllable offset current in the charge pump. The outphased clock, which is created by the DLL, is mixed with the reference clock in the control stage to create an RF PWM signal. The control stage also functions as a switch between the reference clock and RF PWM clock to create a modulated and non-modulated state. The solution also includes a power stage, which is a D-Class amplifier with a pre-driver. The power stage has 6-bit adjustable output power. A block of a generalized ASK RF PWM transmitter, similar to what is presented in [21], is shown in Figure4. Arbitrary clock phase generation can be implemented with a DLL, as presented in [21], but phase locked loop implementation is also viable. Both implementations can perform single ended or differential outphasing, the difference between which we tested in Figure5. The amplifier can be of any kind, but D-class and E-class amplifiers are generally used with this configuration. Electronics 2021, 10, x FOR PEER REVIEW 6 of 17

Figure 4. Block diagram of a generalized ASK RF- Pulse Width Modulated (PWM) transmitter.

The largest drawback of this solution is that its outphasing modulation is single ended, which creates parasitic phase modulation along with amplitude modulation [22]. Electronics 2021,, 10,, 188x FOR PEER REVIEWTransmitted phase during the modulated phase is thus dependent on the set ASK index.6 of 17 Additionally, when the transition happens between modulated and non-modulated state for 8–30% ASK, an abrupt change in phase also occurs, which the antenna circuit can translate into an increase of overshoot and undershoot of the envelope, which, in turn, can cause a failure to meet specifications. Figure 5 shows a comparison between an ASK pulse generated with single-ended outphasing (blue) and with differential outphasing (red) for the circuit in Figure 4. In the simulation, a generic single ended antenna with an EMC filter and matching circuit is used along with an ideal D-class amplifier with 0.5 Ω output resistance. The antenna is loaded by an NFC Forum reference listener 6 with a coupling factor of 0.2. Traces shown are from the spy coil and RF output (RFO) of the amplifier. From the envelope comparison it can be observed that single ended outphasing causes a larger undershoot and overshoot. The phase difference caused by the parasitic phase mod-

ulation can be seen in the zoomed-in view by observing the length of different periods at FigureFigure 4. 4. BlockBlock diagram diagram of of a a generalized generalized ASK ASK RF- Pulse Width Modulated (PWM) transmitter. the point where the pulse width transition occurs. The largest drawback of this solution is that its outphasing modulation is single ended, which creates parasitic phase modulation along with amplitude modulation [22]. Transmitted phase during the modulated phase is thus dependent on the set ASK index. Additionally, when the transition happens between modulated and non-modulated state for 8–30% ASK, an abrupt change in phase also occurs, which the antenna circuit can translate into an increase of overshoot and undershoot of the envelope, which, in turn, can cause a failure to meet specifications. Figure 5 shows a comparison between an ASK pulse generated with single-ended outphasing (blue) and with differential outphasing (red) for the circuit in Figure 4. In the simulation, a generic single ended antenna with an EMC filter and matching circuit is used along with an ideal D-class amplifier with 0.5 Ω output resistance. The antenna is loaded by an NFC Forum reference listener 6 with a coupling factor of 0.2. Traces shown are from the spy coil and RF output (RFO) of the amplifier. From the envelope comparison it can be observed that single ended outphasing causes a Figure 5. 5. ComparisonComparison of of RF RFlarger PWM PWM generatedundershoot generated by byandsingle single overshoot. ended ended and andThe differential differentialphase difference outphasing. outphasing. caused BlueBlue lines by linestherepresent parasitic represent signal phase signal gen- mod- eratedgenerated in single in single ended ended outphasing; outphasing;ulation red can redlines be lines seenrepres represent inent the signal zoomed-in signal generated generated view with withby differential observing differential outphasing. the outphasing. length of different periods at the point where the pulse width transition occurs. 3. NovelThe Solution largest drawback Based on ofDigital this solutionto Time Converter is that its outphasing modulation is single ended,Work which done creates in [23] parasitic was used phase as a modulationbasis for an outphasing along with amplitudetransmitter modulation based on a dig- [22]. ital-to-timeTransmitted converter phase during in our the work. modulated The benefit phase of is thusthis implementation dependent on the is setthat ASK it can index. be madeAdditionally, fully digital when and the can transition thus take happens full advantage between of modulated advanced andprocess non-modulated nodes. Outphas- state ingfor is 8–30% made ASK, fully andifferential abrupt change to remove in phase the parasitic also occurs, phase which modulation the antenna component circuit and can havetranslate only intoASK an modulation. increase of Additionally, overshoot and this undershoot implementation of the is envelope, fully compatible which, with in turn, D- classcan cause amplifiers, a failure enabli to meetng high specifications. efficiency. Figure5 shows a comparison between an ASK pulseThe generated solution with we propose single-ended for NFC outphasing outphasing (blue) transmitter and with differentialconsists of transmitter outphasing logic (red) withfor the a programmable circuit in Figure lookup4. In the table, simulation, where modu a genericlation single pulse ended wave antennashapes are with stored, an EMC and afilter modulator and matching that performs circuit ismodu usedlation along using with antheideal wave D-class shape amplifierdata fromwith the lookup 0.5 Ω output table. resistance. The antenna is loaded by an NFC Forum reference listener 6 with a coupling factor of 0.2. Traces shown are from the spy coil and RF output (RFO) of the amplifier. From the envelope comparison it can be observed that single ended outphasing causes

a larger undershoot and overshoot. The phase difference caused by the parasitic phase Figure 5. Comparison of RF modulationPWM generated can by be single seen inended the zoomed-inand differential view outphasing. by observing Blue the lines length represent of different signal gen- periods erated in single ended outphasing;at the pointred lines where repres theent pulse signal width generated transition with differential occurs. outphasing.

3.3. Novel Novel Solution Solution Based Based on on Digital Digital to to Time Time Converter WorkWork done inin [[23]23] waswas usedused as as a a basis basis for for an an outphasing outphasing transmitter transmitter based based on on a digital- a digital-to-timeto-time converter converter in our in work.our work. The benefitThe benefit of this of implementationthis implementation is that is it that can it be can made be madefully digitalfully digital and can and thus can takethus fulltake advantage full advantage of advanced of advanced process process nodes. nodes. Outphasing Outphas- is ingmade is made fully differentialfully differential to remove to remove the parasitic the parasitic phase phase modulation modulation component component and have and haveonly ASKonly ASK modulation. modulation. Additionally, Additionally, this implementation this implementation is fully is fully compatible compatible with with D-class D- classamplifiers, amplifiers, enabling enabli highng efficiency.high efficiency. TheThe solution solution we we propose propose for for NFC NFC outphasing outphasing transmitter consists of transmitter logic with a a programmable programmable lookup lookup table, table, where where modu modulationlation pulse pulse wave wave shapes shapes are stored, are stored, and aand modulator a modulator that performs that performs modu modulationlation usingusing the wave the waveshapeshape data from data the from lookup the lookup table.

Electronics 2021, 10, 188 7 of 17 ElectronicsElectronics 2021, 202110, x, 10FOR, x FOR PEER PEER REVIEW REVIEW 7 of 17 7 of 17

TheThetable. modulator, modulator, The modulator, operating operating operating at four attimes times four the timesthe carrier carrier the frequency, carrier frequency, frequency, is followed is followed is followed by a shiftby bya registershift a shift register ◦ basedbasedregister clock clock based divider divider clock with with divider a fixed with phase phase a fixed offset offset phase to to achieve offsetachieve to180° achieve180° phase phase 180offset offsetphase in a non-modu-in offset a non-modu- in a latedlatednon-modulated state. state. After After state. that,that, After outphasedoutphased that, outphased carrierscarriers ar carriersare econverted converted are converted to RFto RFPWM to PWM RF in PWM a indigital ina digital a digitalmixer mixer mixer composed of matched delay “AND” and “NOR” gates. Both gates have one of their composedcomposed of of matched matched delaydelay “AND” and and “NOR” “NOR” ga gates.tes. Both Both gates gates have have one ofone their of theirinputs inputs inputs negated. Lastly, this solution needs a D-class amplifier to operate, but this amplifier negated.negated. Lastly, Lastly, this this solutionsolution needsneeds a a D-class D-class amplifier amplifier to operate,to operate, but thisbut amplifierthis amplifier was was notwas included not included in this in work. this work.The block The diagram block diagram of the proposed of the proposed solution solutionis shown is in shown Figure in6. notFigure included6. in this work. The block diagram of the proposed solution is shown in Figure 6.

Figure 6. Block diagram of the proposed solution. Abbreviations Outph1/2 refer to outphased clock 1/2. Figure 6. Block diagram of the proposed solution. Abbreviations Outph1/2 refer to outphased clock 1/2. Figure 6. Block diagram ofThe the coreproposed of the so solutionlution. Abbreviations is DTC based Outph1/2 outphasing refer modulator to outphased that clockoperates 1/2. at four The core of the solution is DTC based outphasing modulator that operates at four times the carrier frequency and allows ASK modulation. Its block diagram is shown in times the carrier frequency and allows ASK modulation. Its block diagram is shown in FigureThe 7.core The of modulator the solution operation is DTC is basedbased on outp switchinghasing between modulator the tapsthat ofoperates the delay at four Figure7. The modulator operation is based on switching between the taps of the delay line timesline theto achieve carrier the frequency desired phase and onallows the output ASK. modulation.The current controlled Its block delay diagram line together is shown in to achieve the desired phase on the output. The current controlled delay line together with Figurewith the7. The charge modulator pump, phase operation detector is and based π loop on filterswitching constitutes between a delay the locked taps loop.of the delay the charge pump, phase detector and π loop ﬁlter constitutes a delay locked loop. line to achieve the desired phase on the output. The current controlled delay line together with the charge pump, phase detector and π loop filter constitutes a delay locked loop.

Figure 7. Block diagram ofof aa digital-to-timedigital-to-time converter converter (DTC) (DTC) based based outphasing outphasing modulator. modulator. Abbreviations Abbreviations Outph1/2 Outph1/2 refer refer to outphasedto outphased clock clock 1/2. 1/2. Abbreviation Abbreviation DFF DFF stands stands for for D-ﬂip-ﬂop. D-flip-flop.

3.1. Delay Locked Loop (DLL) Architecture 3.1. Delay Locked Loop (DLL) Architecture Figure 7. Block diagram of a digital-to-timeThe solution converter uses a(DTC) 64-cell base tappedd outphasing DLL, which modulator. produces Abbreviations 360° delay atOutph1/2 54.24 MHz. refer The solution uses a 64-cell tapped DLL, which produces 360◦ delay at 54.24 MHz. to outphased clock 1/2. AbbreviationWhen frequencyDFF stands is for divided D-flip-flop. down to 13.56 MHz this delay is divided as well to get 90°. When frequency is divided down to 13.56 MHz this delay is divided as well to get 90◦. Each cell of the delay line produces 280 ps of delay. Using a higher clock allows for smaller Each cell of the delay line produces 280 ps of delay. Using a higher clock allows for smaller 3.1.delay Delay line Locked size as Loop fewer (DLL) delay Architecture cells are needed and only slightly increases power consump- delay line size as fewer delay cells are needed and only slightly increases power consumption.tion.The A A totalsolution total of of 128 128uses noninverting noninverting a 64-cell delaytapped delay cells cellsDLL, would would which be required be produces required to achieve to360° achieve delaydifferential differential at 54.24 out- MHz. Whenputsoutputs frequencyof − of90~0°−90~0 and is◦ 0~90°anddivided 0~90 at 13.56 ◦downat 13.56MHz to MHzfrequency.13.56 frequency. MHz Total this Totaldelay delay delay of isthe ofdivided delay the delay line as would linewell would to thus get 90°. Eachbethus 180°,cell be of 180which the◦, whichdelay would wouldline not producesenable not enable locking 280 locking psof theof ofdelay. delay the delay lineUsing independent line a higher independent clock of input ofallows inputclock for clockduty smaller cycle. At four times the base frequency, full 360° lock can◦ be achieved with only 64 cells. delayduty line cycle. size Atas fourfewer times delay the cells base are frequency, needed and full 360only lockslightly can increases be achieved power with consump- only A further optimization can be made by using inverters instead of buffers as delay cells, tion.64 A cells. total A furtherof 128 noninverting optimization can delay be made cells bywould using be inverters required instead to achieve of buffers differential as delay out- further reducing their size by half. This has an effect where a 180° phase◦ difference is cre- putscells, of − further90~0° and reducing 0~90° their at 13.56 size byMHz half. frequency. This has an Total effect delay where of a 180the delayphase line difference would thus atedis created between between odd and odd even and cells, even which cells, whichhas to be has accounted to be accounted for with for multiplexer with multiplexer connec- be tions.180°, Thewhich total would number not of enable cells mustlocking remain of the even delay to ensureline independent an input clock of input duty clockcycle duty cycle. At four times the base frequency, full 360° lock can be achieved with only 64 cells. A further optimization can be made by using inverters instead of buffers as delay cells, further reducing their size by half. This has an effect where a 180° phase difference is created between odd and even cells, which has to be accounted for with multiplexer connections. The total number of cells must remain even to ensure an input clock duty cycle

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connections. The total number of cells must remain even to ensure an input clock duty cycleindependent independent lock. lock.With higher With higher frequency, frequency, the size the of size the of loop the loopfilter ﬁlteris reduced is reduced as well. as well.Differential Differential modulation modulation is achi iseved achieved by having by having separate separate multiplexers multiplexers but reusing but reusing the same the sametaps for taps both for outputs. both outputs. Output Output 1 moves 1 moves from from0 to 360° 0 to and 360◦ outputand output 2 moves 2 moves from from360 to 360 0°. toBecause 0◦. Because the delay the delaycells are cells inverting, are inverting, phases phases 0~180° 0~180 are ◦availableare available from from even even taps tapsand andphases phases 180~360° 180~360 are ◦availableare available from fromodd taps. odd Additional taps. Additional differential differential feedbacks feedbacks are added are addedbetween between cells to cellsreduce to reducemismatch mismatch of the de oflay the and delay duty and cycle duty between cycle betweeninverting inverting and non- andinverting noninverting taps. taps. ThereThere existexist severalseveral typestypes ofof delaydelay cells.cells. ForFor thisthis work,work, currentcurrent controlledcontrolled (Figure(Figure8 8a)a) andand loadload controlledcontrolled (Figure(Figure8 8b)b) delay delay cells cells were were considered. considered. In In a a current current controlled controlled delay delay cell,cell, currentcurrent ofof delay delay inverters inverters is is regulated regulated to to achieve achieve a desireda desired delay. delay. A serialA serial resistance resistance of aof load a load capacitor capacitor is regulated is regulated to ensureto ensure a correct a correct delay delay in load-controlledin load-controlled cells. cells.

Figure 8. (a) Current controlledFigure delay 8. ( acell.) Current (b) Load controlled controlled delay delay cell. cell. (b ()c) Load Circuit controlled diagram delay of a differential cell. (c) Circuit current diagram con- of trolled delay cell with feedback.a differential All bulk connections current controlled of transistors delay in cell depicted with feedback. circuits are All connected bulk connections to supply and of transistors ground in for PMOS and NMOS transistors,depicted respectively. circuits are Bar connected symbols to represent supply and supply ground voltage for PMOS Vdd, andwhich NMOS is equal transistors, to 2.4 V. respectively. Bar symbols represent supply voltage Vdd, which is equal to 2.4 V. Current controlled delay cells were found to have higher phase amplification and lowerCurrent mismatch controlled as well as delay much cells lower were power found consumption to have higher in the phase equivalent ampliﬁcation area as com- and lowerpared mismatchto load-controlled as well delay as much cells. lower The compromise power consumption for this is ina less the linear equivalent delay areacharac- as comparedteristic of the to load-controlled current controlled delay delay cells. cells. The This compromise drawback for ofthis current is a lesscontrolled linear delaydelay characteristiccells could be ofalleviated the current by adding controlled diodes delay in cells.parallel This to drawbackcontrol transistors of current at controlledthe cost of delaydecreased cells couldphase beamplification. alleviated by A adding comparison diodes of in delay parallel characteristic to control transistorsof the two atcells the made cost of decreased phase ampliﬁcation. A comparison of delay characteristic of the two cells from 2.5 V transistors in 40 nm CMOS is displayed in Figure 9. Red lines in Figure 9 rep- made from 2.5 V transistors in 40 nm CMOS is displayed in Figure9. Red lines in Figure9 resent a load-controlled delay cell, blue lines represent a current controlled delay cell. On represent a load-controlled delay cell, blue lines represent a current controlled delay cell. the x axis we have the PMOS control voltage, while the NMOS control voltage is generated

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On the x axis we have the PMOS control voltage, while the NMOS control voltage is fromgenerated the PMOS from thecontrol PMOS voltage control by voltage means by of means current of mirroring. current mirroring. The first The segment first segment in the figurein the represents figure represents the phase the change phase change of the delay of theed delayed clock at clock a given at a control given control voltage voltage or phase or amplificationphase amplification of the ofdelay the delaycell. The cell. second The second segment segment represents represents the actual the actual delay. delay. It can It canbe observedbe observed in Figure in Figure 9 that9 that the theusable usable control control voltage voltage range range of current of current controlled controlled delay delay cell iscell smaller is smaller (0.8~1.4 (0.8~1.4 V), but V), is but more is more centered centered around around halfhalf of the of thesupply supply voltage voltage (1.2 (1.2 V). V).A usefulA useful range range of load-controlled of load-controlled delay delay cell cellis higher is higher (0.95~1.8 (0.95~1.8 V) but V) butis more is more skewed skewed to- wardstowards higher higher voltages. voltages.

FigureFigure 9. A comparison of of delay cells. The The red red lines represent a lo load-controlledad-controlled delay delay cell, cell, blue blue lines lines represent represent a current controlledcontrolled delay cell.

CurrentCurrent controlled controlled delay delay cells cells in in differential differential configuration, configuration, as as shown shown in in Figure Figure 88c,c, werewere chosen chosen for for this this work. work. The The benefit benefit of of using using inverters inverters instead instead of of differential differential amplifier amplifier stagesstages to to create create differential differential delay delay cells cells is is a a ra railil to to rail rail operation operation independent independent of of the the control control voltage.voltage. Delay Delay cells cells are are current current controlled controlled on on both both sides sides to to ensure ensure symmetrical symmetrical rising and fallingfalling edges, edges, as as both both are are effectively effectively used. used. Di Differentialfferential feedback feedback inverters inverters are are sized sized to to have have one-fifthone-fifth to to one-third one-third of the current capability of the main delaydelay inverters.inverters. The delay delay line line ◦ isis connected connected in in such such a a way way that that the the 180° 180 delaydelayeded clock clock is is wrapped wrapped back back to to the the differential differential ◦ input,input, as as displayed displayed in in Figure Figure 10.10. This This enables enables the the delay delay line line to to have have 360° 360 ofof total total delay delay withwith inverting inverting delay delay cells cells while while keeping keeping a a proper proper delay delay between between inverted inverted and and noninverted noninverted outputs.outputs. The The area area of of the the delay delay line line is is thus thus r reducededuced by by half, half, but but a a nonlinearity nonlinearity is is introduced introduced atat the the point point where where it it wraps wraps back. back. This This can can be be seen seen at at code code 32 32 in in the the differential differential nonlinearity nonlinearity plotplot in in the Section Results4. section. To avoid To this avoid issue this the issue delay the delay line would line would either either have have to be to madebe made of ofnoninverting noninverting delay delay cells cells or or be be made made fully fully differential differential withwith invertinginverting delaydelay cells both of whichwhich would would double double the the area. area. The The PMOS PMOS control control voltage voltage is is generated generated by by a a charge charge pump pump andand is is filtered filtered by by the the loop loop filter filter as as shown shown in Figure 77.. NMOSNMOS controlcontrol voltagevoltage isis generatedgenerated by mirroring the PMOS control voltage. by mirroring the PMOS control voltage.

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FigureFigure 10. 10.Delay Delay line line architecture. architecture. The The number number of differentialof differential delay dela stagesy stages is 32,is 32, totaling totaling 64 64 delay delay inverters inverters and and 64 64 cross cross Figure 10. Delay line architecture. The number of differential delay stages is 32, totaling 64 delay inverters and 64 cross feedbackfeedback inverters. inverters. feedback inverters. ToTo lock lock the the DLL DLL a single-ended a single-ended charge charge pump pump is used,is used, adapted adapted from from the the differential differential To lock the DLL a single-ended charge pump is used, adapted from the differential chargecharge pump pump presented presented in in [24 [24].]. In In front front of of the the charge charge pump pump dynamic dynamic D-flip-flops D-flip-flops (DFF) (DFF) arechargeare used used pump as as phase phasepresented detectors, detectors, in [24]. as as shown In shown front in inof Figure Figurethe charge 11 11.. The The pump loop loop filterdynamic filter is is of ofD-flip-flops the the second second order,(DFF) order, whicharewhich used improves improvesas phase the detectors, the phase phase noise as noise shown characteristic characteristic in Figure of11. of the The the loop looploop [25 filter[25]] from fromis of high thehigh passsecond pass to order,to band band pass.whichpass. Filter improvesFilter in inπ topologyπ the topology phase was wasnoise found found characteristic to to be be most most appropriateof appropriatethe loop for[25] for the from the application. application.high pass The to The band first first capacitorpass.capacitor Filter on inon the π the topology charge charge pump waspump found output output to creates becreates most the theappropriate first first pole pole while for while the the theapplication. combination combination The of firstof the the resistorcapacitorresistor and onand secondthe second charge capacitor capacitor pump creates output creates an creates an additional additional the first pole. pole.pole The whileThe second second the combination pole pole is sizedis sized of to tothe be be muchresistormuch weaker weakerand second than than the capacitorthe first first pole, pole, creates to to keep keepan the additional the loop loop overdamped. overdamped. pole. The second pole is sized to be much weaker than the first pole, to keep the loop overdamped.

FigureFigure 11. 11.(a) ( Phasea) Phase detector detector block block diagram. diagram. (b) Dynamic(b) Dynamic flip flopflip circuitflop circuit diagram. diagram. Vdd isVdd equal is equal to 2.4 to V. All2.4 bulkV. All connections bulk connec- ofFigure transistorstions 11.of transistors (a) in Phase depicted detector in depicted circuits block arecircuits diagram. connected are connected(b) to Dynamic supply to and suflippply groundflop and circuit ground for PMOSdiagram. for andPMOS Vdd NMOS andis equal NMOS transistors, to 2.4 transistors, V. respectively. All bulk respectively. connections of transistors in depicted circuits are connected to supply and ground for PMOS and NMOS transistors, respectively. 3.2. Modulator Architecture 3.2.3.2. ModulatorModulator ArchitectureArchitecture Besides the DLL, the second major component of the modulator is its phase multi- plexingBesidesBesides system, thethe DLL, as displayed the second in major Figure compon component 7. This entswitching of of the the modulator modulatorsystem has is istwo its its phasesubsystems: phase multi- mul- a tiplexingplexingdeglitching system, system, system as as displayed displayedand an output in in Figure Figure switching 7.7. This This system. switching switching The systemoutput system systemhas has two two switches subsystems: subsystems: between a adeglitching deglitchingavailable phasessystem system createdand and an an outputby output the DLLswitching switching to pe rformsystem. system. the The The desired output phase system modulation. switches betweenbetween This sys- availableavailabletem consists phasesphases of created threecreated stages by by the the of DLL fourDLL to toto perform one perform multiplexers. the the desired desired The phase phase first modulation. stage modulation. has 16 This multiplexers This system sys- consists of three stages of four to one multiplexers. The first stage has 16 multiplexers and temand consists is common of three for stagesboth outputs. of four toThis one is multiplexers.an area optimization The first enabled stage has by 16 the multiplexers fact that both is common for both outputs. This is an area optimization enabled by the fact that both andoutputs is common are never for both connected outputs. to This the sameis an areafirst optimizationstage multiplexer enabled in differential by the fact thatamplitude both outputs are never connected to the same first stage multiplexer in differential amplitude outputsonly outphasing. are never connected The second to theand same third first stages stage of multiplexersmultiplexer in are differential separated amplitude for the two only outphasing. The second and third stages of multiplexers are separated for the two onlyoutputs, outphasing. adding The an additional second and 10 third multiplexers stages of to multiplexers the design. are separated for the two outputs, adding an additional 10 multiplexers to the design. outputs,The adding second an partadditional of the 10switching multiplexers system to theis the design. deglitching subsystem. This is re- The second part of the switching system is the deglitching subsystem. This is required quiredThe becausesecond partglitches of the on theswitching output systemof the modulator is the deglitching are not toleratedsubsystem. by theThis clock is re- di- because glitches on the output of the modulator are not tolerated by the clock divider. quiredvider. because Glitches glitches occur whenon the switching output of toth ea modulatordifferent phase are not clock tolerated when bythe the current clock clockdi- Glitches occur when switching to a different phase clock when the current clock and target vider.and targetGlitches clock occur are whenin different switching states, to as a showndifferent in phaseFigure clock 12. when the current clock clockand target are in clock different are in states, different as shown states, in as Figure shown 12 in. Figure 12.

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Figure 12. Comparison of theFigure switching 12. Comparison phase of a ofmultiplexer the switching clock phase when ofboth a multiplexer clocks are in clock the same when state both (dark clocks yellow are in the trace) and in a different statesame (blue state trace), (dark resulting yellow trace) in a g andlitch. in Red a different and green state traces (blue trace),are input resulting clocks, in between a glitch. which Red and the green switch happens. traces are input clocks, between which the switch happens.

TheThe time interval when when both both signals signals are are in inthe the same same state state (high (high or low) or low) decreases decreases with witha phase a phase difference difference between between the signals. the signals. This interval This interval reaches reaches zero when zero whenthe phase the phasediffer- differenceence becomes becomes 180°. 180 When◦. When a multi-stage a multi-stage mux mux is isused used for for output output switching switching this problemproblem becomesbecomes eveneven worse,worse, becausebecause notnot allall stagesstages ofof thethemux muxwill willswitch switch at atthe thesame same time. time. IfIf anyany ofof thethe transienttransient statesstates isis differentdifferent thanthan thethe finalfinal state,state, thisthis willwill bebe seenseen asas aa glitchglitch atat thethe output.output. Thus,Thus, switchingswitching cancan onlyonly happenhappen wherewhere nonenone ofof thethe transienttransient phasesphases willwill bebe inin aa differentdifferent state state than than the the current current state. state. Several Severa solutionsl solutions have have been been proposed proposed for for this this problem. prob- Referencelem. Reference [26] proposes [26] proposes a make-before-break a make-before- systembreak system implemented implemented by using by several using tapsseveral at thetaps same at the time same and time a 37.5% and dutya 37.5% cycle duty clock. cycle Their clock. solution Their allowssolution phase allows to switchphase forto switch up to 90for◦ perup to cycle 90° andper allowscycle and unwrapping allows unwrapping of phase. An of alternativephase. An solutionalternative to thissolution problem to this is toproblem use a dedicated is to use a adjustablededicated adjustable phase clock phas fore switching clock for switching the output. the This output. ensures This that ensures the switchthat the always switch happens always happens at the appropriate at the appropriate moment inmoment order notin order to cause not ato glitch. cause a glitch. InIn thisthis work, work, a a dedicated dedicated switching switching clock clock was was implemented implemented for eachfor each output output in conjunc- in con- tionjunction with with adaptive adaptive switching switching of inactive of inactive outputs outputs of second of second stage multiplexers. stage multiplexers. Such switch- Such ingswitching increases increases the size the of thesize timeof the window time wi tondow switch to the switch output the clock output without clock glitches.without Theglitches. switching The switching clock is implemented clock is implemented with an additional with an multiplexeradditional multiplexer in the DLL, whichin the DLL, only useswhich five only of theuses six five available of the six input available bits. The input most bits. significant The most bit significant is ignored bit because is ignored the overlapbecause ofthe phases overlap where of phases the output where can the beoutput switched can be without switched glitches without happens glitches twice happens per ◦ period.twice per This period. is made This by is using made the by same using clock the same phase clock to switch phase phases to switch 180 phasesapart. The180° phaseapart. ofThe the phase switching of the clock switching is selected clock dependingis selected ondepending the phase on of the the phase output of clockthe output in the clock next cycle.in the Anext comparator cycle. A comparator on the input on determinesthe input determines the direction the direction of change of from change the from current the cyclecurrent to thecycle next to cycle.the next A blockcycle. diagramA block ofdiag theram deglitching of the deglitching system is shownsystem inis Figureshown 13 in. ConnectionsFigure 13. Connections between the between tapped the DLL tapped and DL multiplexerL and multiplexer stages are stages not drawnare not todrawn avoid to unnecessaryavoid unnecessary clutter clutter in the figure.in the figure. Connections Conne betweenctions between these elements these elements are made are in made such in a waysuch that a way modulation that modulation setting 0setting creates 0 pulsescreates with pulses zero with duty zero ratio duty and ratio modulation and modulation setting 63setting creates 63 pulsescreates with pulses 50% with duty 50% ratio. duty ratio.

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FigureFigure 13. 13. BlockBlock diagram diagram of of the the output output and and deglitching deglitching systems. systems.

◦ TheThe implemented implemented system system allows allows outputs outputs to be to switched be switched without without glitches glitches for 70° for each, 70 everyeach, 54.24 every MHz 54.24 clock MHz cycle. clock The cycle. modulator The modulator input setting input is also setting changed is also with changed 54.24 MHz with 54.24 MHz by interpolating intermediate states. This has the benefit of increasing phase by interpolating intermediate states.◦ This has the benefit of increasing phase change to a theoreticalchange to alimit theoretical of 70° for limit each of 70outputfor eachand fo outputr every and clock for cycle every of clock 13.56 cycle MHz. of 13.56The actual MHz. The actual change allowed by interpolation is lower than the theoretical limit due to change allowed by interpolation is lower than the theoretical limit due to simplified◦ im- plementationsimplified implementation of interpolation. of interpolation.Actual available Actual phase available change phase is 45° change for every is 45 outputfor every and foroutput every and clock for cycle. every This clock is cycle. more Thisthan isenough more than for the enough intended for the usage, intended as the usage, intention as the is tointention transition is tointo transition full modulation into full modulationdepth gradually depth to gradually shape modulation to shape modulationpulses. pulses. 4. Results 4. Results The presented solution was simulated with a generic differential NFC controller antennaThe composedpresented solution of an antenna was simulated coil, resonance with a capacitors, generic differential matching capacitors,NFC controller and EMIan- tennafilter composed inductively of coupled an antenna to an coil, EMV—TEST resonance capacitors, PICC 2 to matching guarantee capacitors, the solution and meets EMI filterspecification inductively requirements. coupled to an Because EMV— theTEST modulator PICC 2 to has guarantee a much the higher solution bandwidth meets spec- and ificationresolution requirements. than the communication Because the modulato protocol datar has rate, a much the shapes higher of bandwidth the modulation and resolu- pulses tioncan than be actively the communication controlled. Furthermore, protocol data when rate, changing the shapes the of pulse the modulation width more pulses gradually can beat actively the output, controlled. aliasing Furthermore, into the transmission when changing band is reducedthe pulse due width to themore zero gradually order hold at theeffect output, in combination aliasing into with the a transmission square carrier band shape is [reduced22]. Power due consumption to the zero order of the hold presented effect insystem combination without with the D-class a square amplifier carrier inshape the worst-power[22]. Power consumption corner is below of 7.5themW, presented an amount sys- temwhich without is negligible the D-class compared amplifier to transmitter in the worst-power output power, corner which is below is over 7.5 1 mW, W for an most amount high whichend devices is negligible on the marketcompared today to [transmitter27–30]. Power output consumption power, which could is further over 1 be W drastically for most highreduced end bydevices using on low the voltage market transistors today [27–30] instead. Power of 2.5 consumption V transistors. could further be drastically reduced by using low voltage transistors instead of 2.5 V transistors. 4.1. Output Characteristic 4.1. OutputResults Characteristic in Figure 14 are obtained using an ideal D-class amplifier with 1 Ω output resistanceResults in in the Figure proposed 14 are solution, obtained simulated using an over ideal temperatures D-class amplifier from − with30 to 1 125 Ω output◦C and resistancesupply voltage in the variation proposed from solution 2.3 V, to simulated 2.5 V with over Monte temperatures Carlo local variations.from −30 to The 125 coupling °C and supplyfactor betweenvoltage variation the antenna from and 2.3 PICC V to was 2.5 0.20,V with which Monte represents Carlo local 10 mm variations. distance The between cou- plingthe PICC factor and between transmitter the antenna antenna. and Pulse PICC width was in0.20, the which simulation represents was swept 10 mm from distance input betweensetting 0the to PICC setting and 63. transmitter Setting 0 antenna. is missing Pulse from width the figurein the simulation because its was duty swept cycle from was input0 and setting could 0 not to setting be sampled. 63. Setting The 0 firstis miss seting of from lines the of thefigure graph because represents its duty differential cycle was 0nonlinearity and could not (DNL) be sampled. of the output The first duty set cycle. of lin Thees of offset the graph generated represents by the modulatordifferential is non- half linearitya bit, but (DNL) this is of negated the output by the duty mixer, cycle. which The swallows offset generated such short by pulses.the modulator The gain is error half isa

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bit, but this is negated by the mixer, which swallows such short pulses. The gain error is

Electronics 2021, 10, 188 one bit over the entire range of input codes, causing the highest code to be half a bit below13 of 17 nominal. This is visible in the DNL plot in Figure 14. Gain and offset errors are caused by the architecture, which was optimized for area and power consumption. The DNL plot shows a consistent nonlinearity in the middle of the range and at the edges. The middle nonlinearityone bit over is the up entire to 0.2 range bits in of size input and codes, is partially causing caused the highest by the code multiplexer to be half architecture a bit below wherenominal. the Thisfirst isstage visible of multiplexers in the DNL plotis common in Figure for 14 both. Gain outputs and offset and errorspartially are by caused folding by ofthe the architecture, delay line. whichEdge errors was optimized (left edge for is areanot shown and power because consumption. pulse is swallowed) The DNL plotare causedshows aby consistent changing nonlinearityof the delay inat thethe middleends of of the the delay range line. and Additional at the edges. dummy The middle delay stagesnonlinearity were implemented is up to 0.2 bits at inthe size edge, and but is partiallythey are causednot differential by the multiplexer and could architecturenot be per- fectlywhere matched the ﬁrst stageto delay of multiplexers stages in the is DLL. common The for amplitude both outputs of this and er partiallyror is under by folding 0.3 bits. of Boththe delay errors line. can Edge easily errors be accounted (left edge for is not in shownthe lookup because table pulse and isare swallowed) thus not a are problem. caused Totalby changing area of the of the transmitter delay at the is ~0.025 ends of mm the delay. We estimate line. Additional the area dummy would increase delay stages by about were 15%implemented without the at area the edge, optimizations but they arewhile not the differential power consumption and could not would be perfectly increase matched by 40% to delayThe stagessecond in set the of DLL. lines Theis the amplitude sampled of duty this cycle error isat underthe output 0.3 bits. of the Both modulator, errors can whereeasily good be accounted matching for between in the lookup simulation table runs and can are be thus seen. not The a problem. third set Total of lines area are of the the 2 sampledtransmitter amplitudes is ~0.025 mmof the. WeRF estimatefield envelope the area as would seen by increase the spy by coil. about The 15% sine without transfor- the mationarea optimizations characteristic while of differential the power outphasing consumption is also would clearly increase visible by in 40% this set of lines.

FigureFigure 14. Simulation 14. Simulation of output of output characteristic characteristic showing showing DNL, DNL, output output duty duty cycle cycle and andnormalized normalized antenna antenna envelope. envelope.

4.2. ISO14443The second A and set B ofModula linestion is the Pulse sampled Characteristic. duty cycle at the output of the modulator, whereISO14443 good matching A and B betweenmodulation simulation simulation runs re cansults be in seen. Figures The 15–17 third setare of obtained lines are in the a nominalsampled corner amplitudes with ge ofneric the RF differential field envelope 14 Ω asPCD seen antenna by the coupled spy coil. with The sineEMVCO transforma- Refer- encetion characteristicPICC 2. The load of differential on PICC is outphasing set to HLZ—820 is also clearlyΩ. Antenna visible coupling in this set factors of lines. used in the simulation are modeled for PICC distances 0–50 mm from the reader antenna as spec- 4.2. ISO14443 A and B Modulation Pulse Characteristic. ified by EMVCo. Only results for 0 mm distance are shown, as this antenna exhibits the most ISO14443challenging A andbehavior B modulation at this distance simulation. The resultspoint where in Figures the antenna15–17 are performs obtained the in worsta nominal depends corner on how with the generic antenna differential is configur 14edΩ (matchingPCD antenna circuit, coupled etc.) and with can EMVCO be dif- Reference PICC 2. The load on PICC is set to HLZ—820 Ω. Antenna coupling factors used ferent for different antennas, but this behavior cannot be avoided in general. Devices that in the simulation are modeled for PICC distances 0–50 mm from the reader antenna as do not address this issue can exhibit a dead zone in communication, which is undesirable. specified by EMVCo. Only results for 0 mm distance are shown, as this antenna exhibits the most challenging behavior at this distance. The point where the antenna performs the worst depends on how the antenna is configured (matching circuit, etc.) and can be different for different antennas, but this behavior cannot be avoided in general. Devices that do not address this issue can exhibit a dead zone in communication, which is undesirable.

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Electronics 2021, 10, x FOR PEER REVIEW 14 of 17

FigureFigure 15. 15. ISO14443ISO14443 type type A A 106 106 kbit/s kbit/s modulation modulation pulse pulse comparison comparison.. Yellow Yellow line line on on RF RF field field spy spy is is from from the the RF RF PWM PWM transmitter,Figuretransmitter, 15. ISO14443 red red line line is istype from from A the the106 simple simple kbit/s polarmodulation polar transmitter. transmitter. pulse Yellow Yellowcomparison and and purple purple. Yellow lines lines line are are on RF RFRF PWM PWM field transmispy transmitter is fromtter output outputthe RF clocks. clocks.PWM Redtransmitter,Red and and green green red traces traces line is in in from the the first firstthe simplesegment polar of th the transmitter.e figure figure are Yellow simple and transmittertran smitterpurple lines output are clocks. RF PWM transmitter output clocks. Red and green traces in the first segment of the figure are simple transmitter output clocks.

Figure 16. ISO14443 type B 106 kbit/s modulation pulse comparison. Yellow line on spy RF field is from the RF PWM transmitter,Figure 16. ISO14443ISO14443 red line is type type from B B the106 simple kbit/s polarmodulation modulation transmitter. pulse pulse comparison comparison.. Yellow Yellow line line on on spy spy RF RF fi fieldeld is is from from the the RF PWM transmitter,transmitter, red line is from the simple polarpolar transmitter.transmitter. In Figure 15 a comparison is made between a simple polar transmitter and the solution proposed in this work for an ISO14443 type A 106 kbits/s modulation pulse. The first set of lines in the figure are the RF outputs from the simple polar transmitter. The second set of lines are the RF outputs from the solution presented in this work. The third set of lines is a comparison between the RF field spies for this work (yellow line) and from the simple polar transmitter (red line). The two transmitters are transmitting with different phases for better visualization. The last set of lines is a comparison between normalized RF field spy envelopes. Colors are the same as before. From the figure we can observe that the simple polar transmitter does not comply with the overshoot requirement, but the proposed solution does without significant overshoot with the use of wave shaping. Furthermore, the transition into modulated state with proposed solution is much cleaner, reducing emissions outside the transmission band. Our wave shaping solution allows us to further adjust the shape of rising and falling edges in a programmable lookup table to suit different antennas and the requirements of different protocols and data rates. The same comparison as before is made for a ISO14443 type B 106 kbit/s pulse and is shown in Figure 16. Again, the simple polar transmitter does not reach the overshoot and undershoot requirement at the worst point required by the EMVCo specification, while our wave shaping solution satisfies the requirements without issue.

Figure 17. ISO14443 type A 848 kbit/s modulation pulse comparison. Yellow line on RF field spy is from the RF PWM transmitter,Figure 17. ISO14443 red line is type from A the 848 simple kbit/s polarmodulation transmitter. pulse comparison. Yellow line on RF field spy is from the RF PWM transmitter, red line is from the simple polar transmitter.

Electronics 2021, 10, x FOR PEER REVIEW 14 of 17

Figure 15. ISO14443 type A 106 kbit/s modulation pulse comparison. Yellow line on RF field spy is from the RF PWM transmitter, red line is from the simple polar transmitter. Yellow and purple lines are RF PWM transmitter output clocks. Red and green traces in the first segment of the figure are simple transmitter output clocks.

Electronics 2021, 10, 188 15 of 17 Figure 16. ISO14443 type B 106 kbit/s modulation pulse comparison. Yellow line on spy RF field is from the RF PWM transmitter, red line is from the simple polar transmitter.

FigureFigure 17. 17. ISO14443ISO14443 type type A A 848 848 kbit/s kbit/s modulation modulation pulse pulse comparison comparison.. Yellow Yellow line line on on RF RF field ﬁeld spy spy is is from from the the RF RF PWM PWM transmitter,transmitter, red red line line is is from from the the simple simple polar polar transmitter. transmitter.

4.3. ISO14443 Type A High Bitrate Modulation Pulse Characteristic

Figure 17 shows simulation results for ISO14443 type A 848 kbit/s obtained with the same setup as the previous figures. Simple polar transmitter is again unable to reach the overshoot requirement. Tests for modulation pulse shapes for bitrates higher than 106 kbit/s are not part of the current specification version; however, they may be added to future versions. The type B pulse shape requirements for bitrates higher than 106 kbit/s scale relatively linearly; however, for type A, the depth and length of modulation pulse changes with higher bitrates. This effect is the worst with type A 848 kbit/s modulation. The biggest problem lies in the fact that the rising and falling edges are often not separated by a constant amplitude part, like in type B. This situation arises when the PICC is far away and weakly coupled to the reader antenna, thus increasing the reader antenna Q and slowing the envelope. When this occurs, the length of the pulse that the RF field spy sees can become significantly different from the length that the modulator creates. This makes reaching the pulse length time requirement with a single wave shape setting at all the PICC locations specified by EMVCo and without changing the reader antenna circuit nigh impossible. One solution to this would be to measure the antenna load and adjust the wave shape to compensate. This solution was not implemented in this work, as the current version of specification only requires testing for type A and B at a bitrate of 106 kbit/s.

4.4. Comparison with Previous Works A comparison with previous works is shown in Table2. Added contribution of this work is modulation pulse wave shaping, which enables compliance with the newest speciﬁcations. Electronics 2021, 10, 188 16 of 17

Table 2. Comparison with previous works.

This Work [17][21] Architecture Outphasing Polar Outphasing Technology node 40 nm CMOS 180 nm CMOS 180 nm CMOS Current consumption 3 [email protected] V Not provided 3.2 mA Multi-standard Yes Yes Yes support Scalable power with Yes No Yes D-class ampliﬁers Adjustable ASK Yes No Yes modulation index Allows modulation Yes No No pulse wave shaping

5. Conclusions In this work, a novel outphasing transmitter for 13.56 MHz RFID readers and NFC controllers is presented. The system is based on a differential 6-bit DTC phase modulator implemented with 2.5 V transistors in a 40 nm CMOS process, which is configured to allow amplitude modulation and expands on the previous work [17,21] to comply with the new version of EMVCo and NFC Forum specifications. Modulation bandwidth of the system is much greater than what is required by the communication protocol, which allows it to not only perform the modulation but also control the rising and falling edge shape of the modulation pulses. Output linearity of 0.2 bits was achieved over process corners, temperature, and supply voltage variations. Power consumption of the system is under 7.5 mW in the worst corner, which is negligible compared to output power of most HF RFID readers. The presented system was simulated in conjunction with an ideal D-class amplifier to test modulation performance. EMVCo and NFC Forum modulation pulse wave shape specifications are easily satisfied. In the current specification release testing for higher bitrate modulation pulse wave shapes is not required, but we tested our solution for that as well; however, a single wave shape to satisfy the requirement in all PICC positions was not found. In future work adaptive wave shaping based on antenna load could be added, which would ease the satisfaction of possible new requirements.

Author Contributions: Conceptualization, Ž.K. and N.S.; methodology, Ž.K.; validation, Ž.K.; for- mal analysis, N.S.; investigation, Ž.K.; data curation, Ž.K.; writing—original draft preparation, Ž.K. and N.S.; writing—review and editing, Ž.K., N.S. and A.P.; visualization, Ž.K.; supervision, A.P.; project administration, A.P. All authors have read and agreed to the published version of the manuscript. Funding: This research received no external funding. Data Availability Statement: Data is contained within the article. Acknowledgments: The authors would like to thank staff members at STMicroelectronics d.o.o., Ljubljana, for helpful advice and support. We would additionally like to thank Tilen Svete for help with manuscript review and editing. Conﬂicts of Interest: The authors declare no conﬂict of interest.

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