Scaled Vertical and Lateral NEM Relays
Prof. H. S. Philip Wong, Daesung Lee, Soogine Chong, Xiaoying Shen, Simon Guan,
Stanford University
January 13, 2011
1 Acknowledgements
DARPA NEMS Team at Stanford : • Prof. Roger T. Howe, Prof. Subhasish Mitra • Chen Chen, W. Scott Lee, Roozbeh Parsa, Dr. J Provine, Kyeongran Yoo • SEMATECH (sidewall contact material selection)
Collaboration : IME (BEOL compatible process)
Funding : • DARPA/MTO NEMS Program • NSF, E3S • Stanford Nanofabrication Facility
2 Outline
Lateral NEM relay process: 3T and 4T relays
Scaled lateral NEM relay process
Vertical NEM relay process with graphene beam
3 FPGALaterally-actuated Configuration Using NEM Relays Relays
• Simplified fabrication process using fewer masks − Symmetrical structures, preserve symmetry after additional processing (e.g. sidewall coating done at a single step) • Wider device design space (e.g. varying gap size) • For conventional process flow, the gap and feature size is set by the lithographic resolution
Gate1 Beam to drain Drain1 gap: 50nm
Source Drain2 Gate2 10 m
Stanford polysilicon relays ( i line lithography, 500nm minimum Ru beam / e beam lithography feature size) [D.A. Czaplewski et al., JMM , 2009] 4 Scaled 3T Devices in Literature
Beam to drain gap: 20nm
Vpi =16V
[J.-O. Lee et al., IEDM , 2009] MOCVD TiN/PVD TiN beam, PVD TiN electrode
Beam to drain gap: 35nm
W ALD beam, Ti/Au electrode
[B.D. Davidson et al., MEMS , 2010] 5 Scaling of Lateral Electrostatic Actuators L l h⋅ w3 k ∝ l 3 w h⋅ L⋅V 2 F ∝ g e g 2
Fe = k ⋅ x h: height of device layer l 3 h⋅ w h⋅l ⋅V 2 w k ∝ F ∝ g l 3 e g 2
Beam aspect-ratio = h/w Scaling: ( w, g, l, L) (Sw, Sg, Sl, S L) Trench aspect-ratio = h/g Scaling of h is needed Pull-in voltage: S Resonant frequency: 1/S Active device area: S 2 Electrostatic, restoring force: S Van der Waals force: 1/S [important in gap < tens of nm] 6 Sidewall Coated Poly-Si Beams
1. Polysilicon patterning 2. Sidewall coated poly silicon beams Decouple beam material and contact material • LPCVD polysilicon beam: known mechanical properties • Conformal sidewall coating: several options Scaling implications: gap size reduces while beam thickness increases Simple 2-mask process 7 SEMs of Released NEM Relays
PVD Pt sidewall coated polysilicon beam
Sidewall Pt thickness=50nm
L=16µm 10µm
VD Pt coverage of drain pad
GND Sidewall roughness Beam and drain 2µm 2µm due to Pt sputter etch sidewall coverage et al R. Parsa, , Hilton Head 2010 Stanford i-line lithography (500nm minimum feature)8 Properties - Contact Resistance
Low R ON achieved via metal coating: RON =2k
3 1E-310 VDS =1V
1E-610 6 (A) VPI DS I 1E-910 9 VPO
1E-1210 12 0.00 5.00 10.00
VGS (V)
9 Properties - Reliability / Cycling
Relay is functional after 10 88 cycles
1.0E-510 5 VDS =0.5V 1.0E-6
1.0E-7 10 8 (A) 1.0E-8 (A) DS I 1.0E-9 DS V final I VPO final PI 1.0E-10 VPO initial VPI initial 1.0E-1110 11 1.0E-12 0.0 2.02 4.0 6.06 8.0 10.010 12.0 8 SEM after 10 cycles VGS (V)
10 TiN Perimeter Beam for Scaling
Isotropic Released etching of electrodes poly Si mold
Mask 2 Unreleased electrodes 2. Sidewall coated polysilicon beams Mask 3 3. Perimeter beams Ultimate scaling for low voltage actuation • Gap size reduction and beam thickness reduction Perimeter beams: stress gradient cancelled structures Additional mask for unreleased electrodes 11 D. Lee et al. , MEMS 2010 SEMs of Released NEM Relays MOCVD TiN perimeter beams
2µm 2µm
With released With unreleased electrodes electrodes
Sidewall TiN thickness=200nm
[D. Lee et al. , MEMS 2010]
Stanford i-line lithography (500nm minimum feature) 12 Vertical 4T Relays (UCB): Piston Poly-SiGe
Tungsten
OFF State:
|V gb | < V rl (release voltage)
ON State:
|V gb | > V pi (pull-in voltage)
[R. Nathanael et al., IEDM 2009 ] 13 Vertical 4T Relays (UCB): Piston
Pull-in voltage tuning by adjusting body bias Inverter implementation using Input voltage swing > Vpi − Vpo two 4T relays For scaling, minimize hysteresis Difficult to turn on only one window, Vpi at zero body bias, relay at a time: could cause and surface adhesion force unstable intermediate state (floating or short)
[R. Nathanael et al., IEDM 2009 ] 14 Vertical 4T Relays (UCB): Seesaw
Various digital logic functions
For scaling of Vdd, gaps and gate thickness need to be reduced
Seesaw relay structure: only one end is turned on at a time
[J. Jeon et al. , JMEMS letter, vol.19, no.4, Aug 2010] 15 Stanford 4T Lateral Relays
Conducting path
D1 D2 Conducting path, TiN G (in green) is electrically S1 S2 isolated from the gate with a sidewall insulating B1 B2 layer, HfO2 (in blue) B1 B2 D1 D2 Polysilicon mold (in red) S1 S2
B1 B2 G G
Extension of lateral 3-T relay process: (1) creating HfO2 sidewall, (2) selective etch of sidewall conducting layer Analogy with the seesaw relay structure
16 Finished Lateral 4T Relay
Source 1 Body 1
Gate Shared drain Selectively etched TiN Selectively etched TiN Body 2 Source 2
17 Electrical Data of Lateral 4T Relay
Is 2.00E-05
1.50E-05
1.00E-05
5.00E-06 Is_1 ID_1 0.00E+00
0 1 2 3 4 5 6 7 8 9 Is_2 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Id_2 -5.00E-06 V_gate Id -1.00E-05
-1.50E-05
-2.00E-05 Id= −−−Is Vpi=31V, Vpo=21.6V
Vb=0V, Vs=3V, Vd= 3V
Ib, Ig < 0.2pA (noise margin) 18 Outline
Lateral NEM relay process: 3T and 4T relays
Scaled lateral NEM relay process
Vertical NEM relay process with graphene beam
19 Sublithographic Poly-Si Mold Patterning (a) (b)
(a) Oxide hardmask (Mask1) + Nitride spacer formation Lithographic (b) Selective etching of oxide hardmask resolution Mask 2 in 6:1 BOE using PR mask (Mask 2) (d) (c) Spacer shape modification (Mask 3, Mask 3 Mask 4 (c) optional step) (d) PR mask to define regions for anchors (Mask 4, non-critical features)
Oxide hardmask Nitride spacer Photoresist mask Combined mask (top view) for transfer to polysilicon mold layer
[D. Lee et. al, Optical MEMS and Nanophotonics 2010 , Sapporo, Japan, Aug 2010] 20 High -aspect -ratio Scaled Lateral NEM Relay
W: lithographic resolution g, t: sublithographic gap and feature
Use of oxide spacer to enable high-aspect-ratio structures for reliable in-plane actuation
Post process: sidewall coating for reliable contact
Submitted to Transducers’11 21 Two Separated Cantilever Beams
-8 10
-10 TEOS 10 spacer Mask 3 ID1[A]
Mask 1 -12 10
VG1[V] (a) 2 m (b) 2 m -14 10 Mask 2 0 5 10 15
Drain 1 Drain 2 Vpi=12.8V, Vpo=11.8V, 14X reduction of Vpi (e) compared to conventional Gate 1 Gate 2 optical lithography Mask 4
(a), (b) before release (c), (d) after release (c) Beam 2 m (d) 1 m
Sublithographic gap and feature ~ 200nm
Stanford i-line lithography (500nm minimum feature) 22 In -plane Piston Actuator
6 TEOS spacer 10 Connector 8 10
10 10 ID1[A] Masking Poly Si 12 (a)3 m (b) 3 m 10
14 10 Drain 2 Drain 2 0 5 10 15 20 25 Gate 2 VG1[V]
Beam Vpi=21.8V, Vpo=19V, 15X reduction of Vpi compared to Drain 1 Gate 1 Drain 1 (c)3 m (d) 3 m conventional optical lithography Mask 4 Connector
Mask 1 Mask 2 (e) 23 Outline
Lateral NEM relay process: 3T and 4T relays
Scaled lateral NEM relay process
Vertical NEM relay process with graphene beam
24 Vertical Relays with Graphene Contact
Metal beams
S Metal electrodes G D Thin layer of CNT Insulating layer (e.g. HfO2) or graphene Variant 1
• Three-terminal vertical relays with graphene contact layer • Better cycling: easier to avoid stiction and contact degradation • Rely on transfer process of graphene layer on the process wafer • Developed a similar process in the past (shown in next slides)
Variant 2 Variant 3
25 Run 1: Graphene NEM Relay Process
Graphene layer LPCVD nitride Si substrate
1. Deposit 300nm LPCVD nitride followed by first nitride etch to 4. Transfer graphene on 6 inch wafer scale define step 1: 10, 20, 30, 50nm (multi layer) H2 H1
2. Second nitride etch to define step 2: 10nm, 20nm, 30nm, 50nm (H2=H1) 5. Pattern graphene by O2 ashing Strip PR in aceton CPD S D G Results: some weak stiction of the graphene to underlying electrodes
3. Electrode deposition (TiN) Revised run: use sacrificial layer and patterning before the transfer to avoid stiction 26 Micrographs after the Graphene Transfer
H1=H2=10nm, graphene=10nm H1=H2=20nm, graphene=20nm, after litho
H1=H2=30nm, graphene=30nm H1=H2=50nm, graphene=50nm
Some cracks of graphene film were observed: Occured during the transfer of graphene using UV tape 27 SEMs of Completed Devices
Graphene layer Graphene layer
Show the step 1 and step 2, TiN electrodes, and the patterned graphene H1=H2=20nm, graphene=20nm
28 Electrical Data
1.50E-08 VD=1V 1.50E-08 VD=2V IG 1.00E-08 1.00E-08 IG
5.00E-09 5.00E-09 ID ID 0.00E+00 VG 0.00E+00 VG 0 2 4 6 8 0 2 4 6 8 -5.00E-09 -5.00E-09
-1.00E-08 -1.00E-08 IB IB -1.50E-08 -1.50E-08
VD=3V Shift of contact from drain to gate 1.50E-08 1.50E-08 VD=4V
1.00E-08 IG 1.00E-08 ID IG
5.00E-09 ID 5.00E-09
0.00E+00 VG 0.00E+00 VG 0 2 4 6 8 0 1 2 3 4 5 6 7 8 -5.00E-09 -5.00E-09
-1.00E-08 -1.00E-08 IB IB -1.50E-08 -1.50E-08 Current compliance=10nA 2 terminal operation for low VD H1=H2=30nm, graphene=30nm Coupled 3 terminal operation for large VD 29 Works in Progress
Scaling studies of 4T relays
Combine 4T relay process with spacer process for scaling
Sidewall coating material studies (Pt, TiN, Ru)
Contact studies and modeling for reliable operations
Transfer process of graphene NEM relay
30