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CITCA Installation and Operating Information CITCA Installation and Operating Information Order Number: EK-CITCA-OM. 001 Digital Equipment Corporation August 1992 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. No responsibility is assumed for the use or reliability of software on equipment that is not supplied by Digital Equipment Corporation or its affiliated companies. Restricted Rights: Use, duplication, or disclosure by the U.S. Government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013. © Digital Equipment Corporation 1992. All Rights Reserved. DEC, DECstation, DECsystem, TURBOchannel, ULTRIX, and the Digital logo are trademarks of Digital Equipment Corporation. This document was prepared using VAX DOCUMENT, Version 2.0. Contents About This Manual ........................................... ix 1 Introduction 1.1 General Description ................................... 1–1 1.2 Physical Description ................................... 1–2 1.2.1 Components . ................................... 1–2 1.2.2 Logic Components ................................. 1–3 1.3 Features . ........................................... 1–4 1.4 Specifications ........................................ 1–5 2 Site Preparation and Installation 2.1 Site Preparation . ................................... 2–1 2.2 Module Setup ........................................ 2–2 2.2.1 Switchpack 1 . ................................... 2–4 2.2.2 Switchpack 2 . ................................... 2–7 2.2.3 Switchpack 3 . ................................... 2–8 2.2.4 CI Cable Routing .................................. 2–11 2.3 Installation ......................................... 2–12 2.3.1 Removing a CITCA ................................ 2–16 3 Verification and Acceptance 3.1 Verification Procedure ................................. 3–1 3.2 Troubleshooting . ................................... 3–5 3.3 Booting from CITCA .................................. 3–9 3.3.1 Boot Errors . ................................... 3–9 iii 4 Diagnostics 4.1 TCAST . ........................................... 4–1 4.1.1 TCAST Tests . ................................... 4–2 4.1.2 Running TCAST ................................... 4–2 4.1.3 Interpreting Error Information ....................... 4–3 4.2 PST............................................... 4–4 4.2.1 PST CITCA Subtests ............................... 4–4 4.2.2 Running the CITCA Subtest ......................... 4–5 4.2.3 Interpreting Error Information ....................... 4–5 4.3 CI Verification ....................................... 4–6 4.3.1 CI External Loopback Test ........................... 4–6 4.3.1.1 Connecting the CI Attenuator/Loopback Connectors . 4–6 4.3.1.2 Program Execution . ........................... 4–7 4.3.2 CI Node Configuration Test .......................... 4–9 4.4 FLASH_CITCA . ................................... 4–10 4.4.1 FLASH_CITCA Tests and Utilities . ................... 4–10 4.4.1.1 Test Description ................................ 4–11 4.4.1.2 Utility Description . ........................... 4–12 4.4.2 Loading FLASH_CITCA . ........................... 4–14 4.4.2.1 Booting the FLASH_CITCA Program Image .......... 4–14 4.4.2.2 Booting the System Console Program Image .......... 4–15 4.4.2.3 Overlaying the Existing ROM Objects ............... 4–16 4.4.3 Running FLASH_CITCA . ........................... 4–16 4.4.4 Selecting the TURBOchannel Slot Number .............. 4–18 4.4.5 Running Individual FLASH_CITCA Tests ............... 4–19 4.4.6 Exiting from FLASH_CITCA ......................... 4–19 4.4.7 Fault Isolation . ................................... 4–19 4.4.8 Updating the FLASH PROM ......................... 4–20 5 Functional Description 5.1 Logic Description . ................................... 5–1 5.2 TURBOchannel Transactions . ........................... 5–4 5.2.1 Sending a Packet to a CI Node ....................... 5–4 5.2.2 Receiving a Packet from a CI Node . ................... 5–6 iv A Registers A.1 Register Addressing ................................... A–1 A.2 TURBOchannel Registers . ........................... A–3 B Boot Errors B.1 What to Do .......................................... B–1 B.2 Error Codes ......................................... B–2 C Part Numbers Index Examples 3–1 Using the cnfg Command . ........................... 3–3 3–2 Boot n/l ......................................... 3–8 3–3 Using the cnfg n Command .......................... 3–8 4–1 Running the pdflt Subtest ........................... 4–5 4–2 CI External Loopback Test — Passed .................. 4–8 4–3 CI External Loopback Test — Failed ................... 4–8 4–4 CI Node Configuration Test .......................... 4–9 4–5 Loading FLASH_CITCA Program Image ................ 4–15 4–6 Loading the System Program Image ................... 4–16 4–7 Overlay ROM Objects . ........................... 4–16 4–8 Running FLASH_CITCA . ........................... 4–17 4–9 Selecting the TURBOchannel Slot . ................... 4–18 4–10 Running Test 3 . ................................... 4–19 4–11 FLASH_CITCA Error Report ......................... 4–19 4–12 Updating the FLASH PROM ......................... 4–20 A–1 Register Addressing Example ........................ A–1 B–1 Console Output of a Boot Failure . ................... B–2 v Figures 1–1 Simplified CITCA Connection ........................ 1–2 1–2 Hardware Components . ........................... 1–3 2–1 CITCA Module Switches and Connectors ................ 2–4 2–2 Cable Routing . ................................... 2–12 2–3 CPU Drawer — Rear View ........................... 2–14 2–4 Module Placement ................................. 2–15 2–5 Module Removal ................................... 2–17 3–1 Connecting the Attenuator/Loopback Cables . .......... 3–2 3–2 Connecting the CI Cables . ........................... 3–4 3–3 Installation Verification/Troubleshooting Flowchart (Part 1 of 2).............................................. 3–6 3–4 Installation Verification/Troubleshooting Flowchart (Part 2 of 2).............................................. 3–7 4–1 Location of CITCA Self-Test Passed LED ................ 4–3 4–2 Connecting the CI Attenuator/Loopback Connectors ....... 4–7 5–1 CITCA Simplified Block Diagram . ................... 5–2 5–2 CITCA Block Diagram . ........................... 5–2 A–1 TURBOchannel Device Register (TDEV) ................ A–3 A–2 TURBOchannel Bus Error Register (TBER) . .......... A–6 A–3 Port Scan Control Register (PSCR) . ................... A–8 A–4 Port Scan Data Register (PSDR) . ................... A–10 A–5 Port Diagnostic Control/Status Register (PDCSR) ......... A–11 A–6 Channel/Adapter Status Register (CASR) ............... A–13 A–7 Channel/Adapter Failing Address Register (CAFAR) ....... A–15 A–8 Adapter Serial Number Register (ASNR) ................ A–16 A–9 Adapter Block Base Register (ABBR) ................... A–17 A–10 Channel Command Queue 2 Insertion Register (CCQ2IR) . A–18 A–11 Channel Command Queue 1 Insertion Register (CCQ1IR) . A–19 A–12 Channel Command Queue 0 Insertion Register (CCQ0IR) . A–20 A–13 Adapter Datagram Free Queue Insertion Register (ADFQIR) ........................................ A–21 A–14 Adapter Message Free Queue Insertion Register (AMFQIR) ....................................... A–22 A–15 Channel/Adapter Status Release Control Register (CASRCR) ....................................... A–23 A–16 Channel Enable Control Register (CECR) ............... A–23 vi A–17 Port Initialize Control Register (CICR) ................. A–24 A–18 Adapter Maintenance/Sanity Timer Control Register (AMTCR) ........................................ A–24 A–19 Adapter Maintenance/Sanity Timer Expiration Control Register (AMTECR) ................................ A–25 A–20 Adapter Interrupt Holdoff Timer Control Register (AITCR) ......................................... A–25 A–21 Adapter Maintenance Control/Status Register (AMCSR) . A–26 Tables 1 Related Documents ................................ x 1–1 CITCA Hardware Components ........................ 1–2 1–2 Environmental Specifications ......................... 1–5 1–3 Electrical Specifications . ........................... 1–5 2–1 Summary of Switch Settings ......................... 2–3 2–2 Switchpack 1 - Switch 1 . ........................... 2–4 2–3 Switchpack 1 - Switch 2 . ........................... 2–5 2–4 Switchpack 1 - Switches 3 through 10 and Switchpack 2 - Switches 3 through 10 . ........................... 2–6 2–5 Switchpack 2 - Switch 1 . ........................... 2–7 2–6 Switchpack 2 - Switch 2 . ........................... 2–7 2–7 Switchpack 3 - Switches 1 through 3, Quiet Slot Time Configuration Switches . ........................... 2–8 2–8 Switchpack 3 - Switches 4 through 6 ................... 2–9 2–9 Switchpack 3 - Switches 7 through 10 .................. 2–10 3–1 PDFLT Codes . ................................... 3–5 4–1 TCAST Pass/Fail Information ........................ 4–2 4–2 PDFLT Codes . ................................... 4–4 4–3 FLASH_CITCA Event Flags ......................... 4–13 A–1 CITCA Register List ............................... A–2 A–2 TDEV Bit Description . ........................... A–4 A–4 TBER Bit Description . ........................... A–6 A–5 PCSR Bit Description
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