DOCSLIB.ORG

ECE606: Solid State Devices Lecture 17 Schottky Diode

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
ECE606: Solid State Devices Lecture 17 Schottky Diode ECE606: Solid State Devices Lecture 17 Schottky Diode Gerhard Klimeck [email protected] Klimeck – ECE606 Fall 2012 – notes adopted from Alam 1 Presentation Outline 1) Importance of metal-semiconductor junctions 2) Equilibrium band-diagrams 3) DC Thermionic current (simple derivation) 4) Intermediate Summary 5) DC Thermionic current (detailed derivation) 6) AC small signal and large-signal response 7) Additional information 8) Conclusions Reference : Semiconductor Device Fundamentals, Chapter 14, p. 477 Klimeck – ECE606 Fall 2012 – notes adopted from Alam 2 Metal-semiconductor Diode Symbols M N ND Metal Wire N Klimeck – ECE606 Fall 2012 – notes adopted from Alam 3 Applications of M-S Diode …. STM (scanning tunneling microscope) Detectors on semiconductor CNT (carbon nanotube) www.fz-juelich.de/ibn/index.php?index=674 Original Bipolar Transistors Originally, Gelena (PbS), Si as semiconductor and Phospor Bronze for metal (cat ’s whisker) Klimeck – ECE606 Fall 2012 – notes adopted from Alam 4 Presentation Outline 1) Importance of metal-semiconductor junctions 2) Equilibrium band-diagrams 3) DC Thermionic current (simple derivation) 4) Intermediate Summary 5) DC Thermionic current (detailed derivation) 6) AC small signal and large-signal response 7) Additional information 8) Conclusions Klimeck – ECE606 Fall 2012 – notes adopted from Alam 5 Topic Map Equilibrium DC Small Large Circuits signal Signal Diode Schottky BJT/HBT MOS Klimeck – ECE606 Fall 2012 – notes adopted from Alam 6 Drawing Band Diagram in Equilibrium… ∇•= −++ − − D qpnN( D N A ) Equilibrium ∂n 1 = ∇•J −r + g ∂t q N N N =µ E + ∇ J Nqn N qD N n DC dn/dt=0 Small signal dn/dt ~ jωtn ∂p 1 =− ∇•J −r + g Transient --- full sol. ∂t q P P P =µ E − ∇ J Pqp P qD P p Klimeck – ECE606 Fall 2012 – notes adopted from Alam 7 Band-Diagram 1. E F flat in equilibrium 2. E C/E V in Metal 3. Vacuum level in Metal N D 4. Ec/Ev in semiconductor 5. Vacuum level in semiconductor 6. Connect vacuum levels Vacuum level Φ 7. duplicate the connections M χ down to Ec/Ev EC EF Since N A is large, xp is negligible .. EV = NxAp Nx Dn Charge(metal) = charge(semiconductor) Klimeck – ECE606 Fall 2012 – notes adopted from Alam 8 Built-in Potential: bc @Infinity neglect qV bi Φ M χ Φ B ∆ ∆ + χ + = Φ =(Φ−χ ) − ∆ ≡ Φ − ∆ qV bi M qV bi M B N non- =Φ − k T ln D B B degenerate NC Klimeck – ECE606 Fall 2012 – notes adopted from Alam 9 Analytical Solution (Simple Approach ) Depletion Approximation E ρ qN D integrate Actual Xn x x Xn Q qN x E =D = − D n max ε ε QD = Area negligible Ks0 K s 0 QM =-QD NDXn integrate φ φB q Φ =qV E max bi C x Xn EV E x φ = − max n x max Xn 2 Notice how we neglect xp here, is Klimeck – ECE606 Fall 2012 – notes adopted from Alam there a proof? 10 Complete Analytical Solution + qN x E ()0 = D n ε Charg ks 0 e − qN M xp + x E ()0 = ? n ε - ks 0 Position x = p ⇒ ND xn NM xp E-field − + Position E(0) x E ( 0 ) x qV =n + p bi 2 2 Potentia 2 l qN x 2 qN x =D n + M p ε ε 2ks0 2 k s 0 Position Klimeck – ECE606 Fall 2012 – notes adopted from Alam 11 Depletion Regions ND xp xn ε ε = 2ks 0 NM 2 k s 0 1 NDxn N M xp x =V → V n ()+ bi bi qNNNDMD qN D ∞ 2 2 NM qN x qN M xp qV =D n + 2k ε N bi 2k ε 2 k ε x =s0 D V → 0 s 0s 0 p ()+ bi q NMN M N D This is why we can neglect xp Klimeck – ECE606 Fall 2012 – notes adopted from Alam 12 Presentation Outline 1) Importance of metal-semiconductor junctions 2) Equilibrium band-diagrams 3) DC Thermionic current (simple derivation) 4) Intermediate Summary 5) DC Thermionic current (detailed derivation) 6) AC small signal and large-signal response 7) Additional information 8) Conclusions Klimeck – ECE606 Fall 2012 – notes adopted from Alam 13 Topic Map Equilibrium DC Small Large Circuits signal Signal Diode Schottky BJT/HBT MOS Klimeck – ECE606 Fall 2012 – notes adopted from Alam 14 Band Diagram with Applied Bias… ∇•= −++ − − D qpnN( D N A ) Band diagram … ∂n 1 = ∇•J −r + g This works for doping-modulated ∂t q N N N Semiconductors. J =qnµ E + qD ∇ n N N N Does not work for heterostructures ∂p 1 (when the conduction band is not =− ∇•J −r + g ∂t q P P P continuous) =µ E − ∇ J Pqp P qD P p Metal-Semiconductor is a HS Need theory of thermionic Klimeck – ECE606 Fall 2012 – notes adopted from Alam emission 15 Depletion Regions with Bias ND xp xn 2kε N 2 k ε 1 x=s0 M V → s 0 () VV − n ()+ bi bi A qNNNDMD qN D Forward bias: x decrease 2kε N n x=s0 D V → 0 Reverse bias: x increase p ()+ bi n q NM N M N D Klimeck – ECE606 Fall 2012 – notes adopted from Alam 16 Band-diagram with Bias Forward Bias qV bi -V EC-EF VA qV bi EC-EF Reverse Bias VA EC-EF Klimeck – ECE606 Fall 2012 – notes adopted from Alam 17 I-V Characteristics N-type Forward Bias VA Metal Ec I Semi. EF EF M ESF 1,2,3 EV 4 – generation current I 5 – impact ionization Reverse Bias 6,7 EF M 4 1 – diffusion control 5 Ec 2 – ambipolar EF 3 – resistance drop ESF 6 – defects – trap assist 7 – Esaki EV Klimeck – ECE606 Fall 2012 – notes adopted from Alam 18 Current Flow Concept Barrier Barrier smaller Partition problem in The same! M<=S increased M=>S current qV -V 2 currents bi A E -E Φ C F unchanged! B M=>S S<=M VA Forward Bias qV Φ bi B Barrier EC-EF The same! Barrier bigger M=>S current M<=S decreased Φ unchanged! B q(V bi +V A) VA In Equilibrium: M=>S current EC-EF and Independent Reverse Bias are equal of bias! Klimeck – ECE606 Fall 2012 – notes adopted from Alam 19 Left Boundary Condition We use thermionic emission q(V bi -VA) because: EC 1. EC is not continuous here V 2. There’s no minority carriers! A J( V ===0) 0 J (0) − J (0) T A m→s s→ m (detailed balance) = ⇒ Jm→ s (0) J s→ m (0) J (V ) =J( V ) − J( V ) T A m→ s A s→ m A M=>S current = − independent of bias Jm→s (0) J s→ m(V A ) = − JVTA() J sm→ (0) JV smA → () Klimeck – ECE606 Fall 2012 – notes adopted from Alam 20 Semiconductor to Metal Flux V n −q bi = −s kT υ = J s→ m (0) q e th Jm→ s (0) J → (0) = m s 2 V− V Φ −q bi A q B n n − s kT m kT J→ ( V ) = − q e υ J → (V ) = − q e υ s m A th m s A 2 th M 2 n υ − qV bi qV A Only the ones = −s th kT × kT Only half of above the q e e them goes to 2 barrier goes to qVA the right the right = kT J s→ m (0) e qVA q(Vbi -VA) = kT Jm→ s (0) e VA EC-EF Φ n υ − qB qV A = − qm th M ekT e kT 2 −q Φ Φ qV qn υ mB A =− =m th M kT kT − JT J s→m(0)J s → m ( V A ) e e 1 Klimeck – ECE606 Fall 2012 – notes adopted from Alam 2 21 Diffusion vs. Thermionic Emission ∆n Fn Fp Check that both gives the same result for a diode… Thermionic Emission theory is a more general approach, can be used for device so small that no scattering F n occur (can’t use diffusion!). Fp Klimeck – ECE606 Fall 2012 – notes adopted from Alam 22 Intermediate Summary Schottky barrier diode is a majority carrier device of great historical importance. There are similarities and differences with p-n junction diode: for electrostatics, it behaves like a one-sided diode, but current, the drift-diffusion approach requires modification. The trap-assisted current, avalanche breakdown, Zener tunneling all could be calculated in a manner very similar to junction diode. Klimeck – ECE606 Fall 2012 – notes adopted from Alam 23 Presentation Outline 1) Importance of metal-semiconductor junctions 2) Equilibrium band-diagrams 3) DC Thermionic current (simple derivation) 4) Intermediate Summary 5) DC Thermionic current (detailed derivation) 6) AC small signal and large-signal response 7) Additional information 8) Conclusions Klimeck – ECE606 Fall 2012 – notes adopted from Alam 24 Energy Resolved Thermionic Flux 1 Energy < m*υ 2 Occupation 2 min ~ DOS (non-denegerate) will be bounced back −υ ∞ ∞ min Ω −() − β J= − qdk dkedk E E F υ s→m ∫ ∫ ∫ π 3 xy z x −∞ −∞ −∞ 4 Only movement in the υ x direction will contribute min to the current flux q(Vbi -VA) VA EC-EF x Klimeck – ECE606 Fall 2012 – notes adopted from Alam 25 Thermionic Flux from Semi to Metal .. E ∞ ∞ −υ min E Ω −()− β C E E F E J= − q dk dk dk e υ F sm→ ∫ ∫ ∫ π 3 xyz x −∞ −∞ −∞ 4 1 1 1 E− E =()EE− + ()EE−= mmm*2υ + *2 υ+ *2 υ + () EE − F CCF 2 xyz 2 2 C F ∞ ∞ −υ ** * (mυ 2+ mυ 2+ m υ 2 ) min υ υ υ − x y z β −()− β Ω dm( x) dm( y) dm( z ) = qe Ec E F e 2 υ ∫ ∫ ∫ π 3 x −∞ −∞ −∞ 4 ℏ ℏ ℏ 3m *υ 2 υ 2 υ 2 * ∞−y β ∞ − m* z β −υ − m* x β qΩ() m min −()E − E β 2 2 2 J= ec F ededυ υ de υ υ s→ m π 3ℏ 3 ∫y ∫ z ∫ x x 4 −∞ −∞ −∞ Klimeck – ECE606 Fall 2012 – notes adopted from Alam 26 Thermionic Current … 2q υ =()V − V min m* bi A 3m *υ 2 υ2 υ2 * ∞−y β ∞ − m* z β −υ − m* x β qΩ() m min −()E− E β 2 2 2 J= ec F ededυ υ de υυ s→ m π 3 3 ∫y ∫ z ∫ x x 4 ℏ −∞− ∞ −∞ 1 − − β π π e q(Vbi V A ) 2 * 2 π ()− − β β β 4 qm k 2 EF E C qV bi qVAq V A J→ = Te eAe = s m h3 0 β =−=qVA − JJT sm→ J ms → Ae0 ( 1) Klimeck – ECE606 Fall 2012 – notes adopted from Alam 27 Some insight of the Thermionic Current … Compare to the current of p-n diodes… β =−=qVA − JJT sm→ J ms → Ae0 ( 1) Schottky diode 2 2 D n Dp n β =−n i +i qV A − JT q () e 1 p-n diode Wp N A Wn N D Both of them depends exponentially on V A, however current of p-n diodes depends more on temperature (since ni depends strongly on Eg), where the Schottky diode doesn’t have that dependence.
Load more

Recommended publications
  • Extremely High-Gain Source-Gated Transistors
    Extremely high-gain source-gated transistors Jiawei Zhanga,1, Joshua Wilsona,1, Gregory Autonb, Yiming Wangc, Mingsheng Xuc, Qian Xinc, and Aimin Songa,c,1,2 aSchool of Electrical and Electronic Engineering, University of Manchester, Manchester M13 9PL, United Kingdom; bNational Graphene Institute, University of Manchester, Manchester M13 9PL, United Kingdom; and cState Key Laboratory of Crystal Materials, Centre of Nanoelectronics and School of Microelectronics, Shandong University, Jinan 250100, People’s Republic of China Edited by Alexis T. Bell, University of California, Berkeley, CA, and approved January 29, 2019 (received for review December 6, 2018) Despite being a fundamental electronic component for over 70 turn-on voltage (19, 20). This susceptibility to negative bias illu- years, it is still possible to develop different transistor designs, mination temperature stress (NBITS) is one of the main factors including the addition of a diode-like Schottky source electrode delaying the wide-scale adoption of IGZO in the display industry. to thin-film transistors. The discovery of a dependence of the Another major problem is that TFTs require precise lithography source barrier height on the semiconductor thickness and deriva- to enable large-area uniformity, and difficulties with registration tion of an analytical theory allow us to propose a design rule to between different TFT layers are likely to be compounded by the achieve extremely high voltage gain, one of the most important use of flexible substrates. One major advantage of the SGT is that figures of merit for a transistor. Using an oxide semiconductor, an it does not require such precise registration, because the current intrinsic gain of 29,000 was obtained, which is orders of magni- is controlled by the dimensions of the source contact rather than tude higher than a conventional Si transistor.
    [Show full text]
  • The Pennsylvania State University the Graduate School THE
    The Pennsylvania State University The Graduate School THE EFFECTS OF INTERFACE AND SURFACE CHARGE ON TWO DIMENSIONAL TRANSITORS FOR NEUROMORPHIC, RADIATION, AND DOPING APPLICATIONS A Dissertation in Electrical Engineering by Andrew J. Arnold © 2020 Andrew J. Arnold Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy August 2020 The dissertation of Andrew J. Arnold was reviewed and approved by the following: Thomas Jackson Professor of Electrical Engineering Co-Chair of Committee Saptarshi Das Assistant Professor of Engineering Science and Mechanics Dissertation Advisor Co-Chair of Committee Swaroop Ghosh Assistant Professor of Electrical Engineering Rongming Chu Associate Professor of Electrical Engineering Sukwon Choi Assistant Professor of Mechanical Engineering Kultegin Aydin Professor of Electrical Engineering Head of the Department of Electrical Engineering ii Abstract The scaling of silicon field effect transistors (FETs) has progressed exponentially following Moore’s law, and is nearing fundamental limitations related to the materials and physics of the devices. Alternative materials are required to overcome these limitations leading to increasing interest in two dimensional (2D) materials, and transition metal dichalcogenides (TMDs) in particular, due to their atomically thin nature which provides an advantage in scalability. Numerous investigations within the literature have explored various applications of these materials and assessed their viability as a replacement for silicon FETs. This dissertation focuses on several applications of 2D FETs as well as an exploration into one of the most promising methods to improve their performance. Neuromorphic computing is an alternative method to standard computing architectures that operates similarly to a biological nervous system. These systems are composed of neurons and operate based on pulses called action potentials.
    [Show full text]
  • Lecture 3: Diodes and Transistors
    2.996/6.971 Biomedical Devices Design Laboratory Lecture 3: Diodes and Transistors Instructor: Hong Ma Sept. 17, 2007 Diode Behavior • Forward bias – Exponential behavior • Reverse bias I – Breakdown – Controlled breakdown Æ Zeners VZ = Zener knee voltage Compressed -VZ scale 0V 0.7 V V ⎛⎞V Breakdown V IV()= I et − 1 S ⎜⎟ ⎝⎠ kT V = t Q Types of Diode • Silicon diode (0.7V turn-on) • Schottky diode (0.3V turn-on) • LED (Light-Emitting Diode) (0.7-5V) • Photodiode • Zener • Transient Voltage Suppressor Silicon Diode • 0.7V turn-on • Important specs: – Maximum forward current – Reverse leakage current – Reverse breakdown voltage • Typical parts: Part # IF, max IR VR, max Cost 1N914 200mA 25nA at 20V 100 ~$0.007 1N4001 1A 5µA at 50V 50V ~$0.02 Schottky Diode • Metal-semiconductor junction • ~0.3V turn-on • Often used in power applications • Fast switching – no reverse recovery time • Limitation: reverse leakage current is higher – New SiC Schottky diodes have lower reverse leakage Reverse Recovery Time Test Jig Reverse Recovery Test Results • Device tested: 2N4004 diode Light Emitting Diode (LED) • Turn-on voltage from 0.7V to 5V • ~5 years ago: blue and white LEDs • Recently: high power LEDs for lighting • Need to limit current LEDs in Parallel V R ⎛⎞ Vt IV()= IS ⎜⎟ e − 1 VS = 3.3V ⎜⎟ ⎝⎠ •IS is strongly dependent on temp. • Resistance decreases R R R with increasing V = 3.3V S temperature • “Power Hogging” Photodiode • Photons generate electron-hole pairs • Apply reverse bias voltage to increase sensitivity • Key specifications: – Sensitivity
    [Show full text]
  • Comparing Trench and Planar Schottky Rectifiers
    Whitepaper Comparing Trench and Planar Schottky Rectifiers Trench technology delivers lower Qrr, reduced switching losses and wider SOA By Dr.-Ing. Reza Behtash, Applications Marketing Manager, Nexperia The Schottky diode - named after its inventor, the German physicist Walter Hans Schottky - consists essentially of a metal-semiconductor interface. Because of its low forward voltage drop and high switching speed, the Schottky diode is widely used in a variety of applications, such as a boost diode in power conversion circuits. The electrical performance of a Schottky diode is, of course, subject to physical trade-offs, primarily between the forward voltage drop, the leakage current and the reverse blocking voltage. The Trench Schottky diode is a development on the original Schottky diode, providing greater capabilities than its planar counterpart. In this paper the structure and the benefits of Trench Schottky rectifiers are discussed. Schottky operation Trench technology The ideal rectifier would have a low forward voltage drop, Given this explanation, one might ask how the major a high reverse blocking voltage, zero leakage current and advantage of Schottky rectifiers - namely, a low voltage a low parasitic capacitance, facilitating a high switching drop across the metal semiconductor interface - is preserved, speed. When considering the forward voltage drop, despite the demand for a low leakage current and a high there are two main elements: the voltage drop across the reverse blocking voltage? Here, Trench rectifiers prove very junction - PN junction in case of PN rectifiers and metal- useful. The concept behind the Trench Schottky rectifier semiconductor junction in case of Schottky rectifiers; and is termed ‘RESURF’ (reduced surface field).
    [Show full text]
  • Electrical Properties of Silicon Nanowires Schottky Barriers Prepared by MACE at Different Etching Time
    Electrical Properties of Silicon Nanowires Schottky Barriers Prepared by MACE at Different Etching Time Ahlem Rouis ( [email protected] ) Universite de Monastir Faculte des Sciences de Monastir https://orcid.org/0000-0002-9480-061X Neila Hizem Universite de Monastir Faculte des Sciences de Monastir Mohamed Hassen Institut Supérieur des Sciences Appliquées et de Technologie de Sousse: Institut Superieur des Sciences Appliquees et de Technologie de Sousse Adel kalboussi Universite de Monastir Faculte des Sciences de Monastir Original Research Keywords: Electrical Properties of Silicon, Etching Time, symmetrical current-voltage, capacitance-voltage Posted Date: February 11th, 2021 DOI: https://doi.org/10.21203/rs.3.rs-185736/v1 License: This work is licensed under a Creative Commons Attribution 4.0 International License. Read Full License Electrical properties of silicon nanowires Schottky barriers prepared by MACE at different etching time Ahlem Rouis 1, *, Neila Hizem1, Mohamed Hassen2, and Adel kalboussi1. 1Laboratory of Microelectronics and Instrumentation (LR13ES12), Faculty of Science of Monastir, Avenue of Environment, University of Monastir, 5019 Monastir, Tunisia. 2Higher Institute of Applied Sciences and Technology of Sousse, Taffala City (Ibn Khaldoun), 4003 Sousse, Tunisia. * Address correspondence to E-mail: [email protected] ABSTRACT This article focused on the electrical characterization of silicon nanowires Schottky barriers following structural analysis of nanowires grown on p-type silicon by Metal (Ag) Assisted Chemical Etching (MACE) method distinguished by their different etching time (5min, 10min, 25min). The SiNWs are well aligned and distributed almost uniformly over the surface of a silicon wafer. In order to enable electrical measurement on the silicon nanowires device, Schottky barriers were performed by depositing Al on the vertically aligned SiNWs arrays.
    [Show full text]
  • Schottky Diode Replacement by Transistors: Simulation and Measured Results
    SCHOTTKY DIODE REPLACEMENT BY TRANSISTORS: SIMULATION AND MEASURED RESULTS Martin Pospisilik Department of Computer and Communication Systems Faculty of Applied Informatics Tomas Bata University in Zlin 760 05, Zlin, Czech Republic E-mail: [email protected] KEYWORDS MOTIVATION Model, SPICE, MOSFET, Electronic Diode, Voltage The expansion of metal oxide field effect transistors has Drop, Power Dissipation led to efforts to substitute conventional diodes by electronic circuit that behave in the same way as the ABSTRACT diodes, but show considerably lower power dissipation The software support for simulation of electrical circuits as the voltage drop over the transistor can be eliminated has been developed for more than sixty years. Currently, to very low levels. In Fig. 1 there is a block diagram of a the standard tools for simulation of analogous circuits backup power source for the devices that use Power are the simulators based on the open source package over Ethernet technology. This solution, that has been Simulation Program with Integrated Circuit Emphasis developed at Tomas Bata University in Zlin, enables generally known as SPICE (Biolek 2003). There are immediate switching from the main supply to the backup many different applications that provide graphical one together with gentle charging of the accumulator, interface and extended functionalities on the basis of unlike the conventional on-line uninterruptable power SPICE or, at least, using SPICE models of electronic sources do (Pospisilik and Neumann 2013). devices. The author of this paper performed a simulation of a circuit that acts as an electronic diode in Multisim and provides a comparison of the simulation results with the results obtained from measurements on the real circuit.
    [Show full text]
  • A Vertical Silicon-Graphene-Germanium Transistor
    ARTICLE https://doi.org/10.1038/s41467-019-12814-1 OPEN A vertical silicon-graphene-germanium transistor Chi Liu1,3, Wei Ma 1,2,3, Maolin Chen1,2, Wencai Ren 1,2 & Dongming Sun 1,2* Graphene-base transistors have been proposed for high-frequency applications because of the negligible base transit time induced by the atomic thickness of graphene. However, generally used tunnel emitters suffer from high emitter potential-barrier-height which limits the tran- sistor performance towards terahertz operation. To overcome this issue, a graphene-base heterojunction transistor has been proposed theoretically where the graphene base is 1234567890():,; sandwiched by silicon layers. Here we demonstrate a vertical silicon-graphene-germanium transistor where a Schottky emitter constructed by single-crystal silicon and single-layer graphene is achieved. Such Schottky emitter shows a current of 692 A cm−2 and a capacitance of 41 nF cm−2, and thus the alpha cut-off frequency of the transistor is expected to increase from about 1 MHz by using the previous tunnel emitters to above 1 GHz by using the current Schottky emitter. With further engineering, the semiconductor-graphene- semiconductor transistor is expected to be one of the most promising devices for ultra-high frequency operation. 1 Shenyang National Laboratory for Materials Science, Institute of Metal Research, Chinese Academy of Sciences, 72 Wenhua Road, Shenyang 110016, China. 2 School of Materials Science and Engineering, University of Science and Technology of China, 72 Wenhua Road, Shenyang 110016, China. 3These authors contributed equally: Chi Liu, Wei Ma. *email: [email protected] NATURE COMMUNICATIONS | (2019) 10:4873 | https://doi.org/10.1038/s41467-019-12814-1 | www.nature.com/naturecommunications 1 ARTICLE NATURE COMMUNICATIONS | https://doi.org/10.1038/s41467-019-12814-1 n 1947, the first transistor, named a bipolar junction transistor electron microscope (SEM) image in Fig.
    [Show full text]
  • Basics of Transistors and Circuits Dr
    BASICS OF TRANSISTORS AND CIRCUITS DR. HEATHER QUINN, LANL TEXTBOOK For these slides I am using many figures from the second edition of the Principles of CMOS VLSI Design by Weste and Esharaghain, and the fourth edition of CMOS VLSI Design: A Circuit and Systems Perspective INTRODUCTION There are two ways to view radiation effects in electronics: Start from the material science and work upward to transistors to circuits Start from computer circuits and work downward to transistors and then to material science There are advantages and disadvantages to both TOP/BOTTOM VS. BOTTOM/TOP Top/Bottom Bottom/Top Pros: Pros: Understanding of how the entire circuit Deep understanding of the mechanism works (sort of) Deep understanding the potential of the Understanding of the effect of electrical, effect, able to determine whether new temporal, and logical masking, which can be effects are possible used to limit the effects to the ones that cause noticeable effect Cons: Cons: Lack of understanding about electrical, temporal, and logical masking Hard to scale down to the material science Hard to scale up Might not understand the mechanism WHICH WAY TO GO? Likely depends on your background I’m a computer architect that learned radiation effects OJT, so I feel more comfortable personally going top down Some of my team is better versed in radiation effects are learning the circuit part OJT Either way, it is almost impossible to do both well, unless you would like to earn two PhDs, so working in teams is always best At the end of
    [Show full text]
  • Design and Fabrication of Schottky Diode with Standard CMOS Process3
    第 26 卷 第 2 期 半 导 体 学 报 Vol. 26 No. 2 2005 年 2 月 CHINESEJOURNAL OF SEMICONDUCTORS Feb. ,2005 Design and Fabrication of Schottky Diode with Standard CMOS Process 3 Li Qiang , Wang J unyu, Han Yifeng, and Min Hao ( State Key L aboratory of A S IC &System , Fudan U niversity , S hanghai 200433 , China) Abstract : Design and fabrication of Schottky barrier diodes (SBD) with a commercial standard 0135μm CMOS process are described. In order to reduce the series resistor of Schottky contact ,interdigitating the fingers of schottky diode layout is adopted. The I2V , C2V ,and S parameter are measured. The parameters of realized SBD such as the saturation current , breakdown voltage ,and the Schottky barrier height are given. The SPICE simulation model of the realized SBDs is given. Key words : CMOS; Schottky diode; integration EEACC : 2560H; 2570D CLC number : TN311 + 17 Document code : A Article ID : 025324177 (2005) 0220238205 sured results[5 ,6 ] . In this paper we describe the way to 1 Introduction design and layout a Schottky diode in a low cost com2 mercial standard CMOS process without any process Schottky diodes have advantages such as fast modification. The measured results and SPICE simu2 switching speed and low forward voltage drop. Due to lation model are offered. these excellent high frequency performance ,they have been widely used in power detection and microwave 2 Design and layout of Schottky diode network circuit [1 ] . Schottky diodes are often fabricat2 ed by depositing metals on n2type or p2type semicon2 This design was performed through MPW(multi ductor materials such as GaAs and SiC[2～4 ] .
    [Show full text]
  • Schottky Barrier Height Dependence on the Metal Work Function for P-Type Si Schottky Diodes
    Schottky Barrier Height Dependence on the Metal Work Function for p-type Si Schottky Diodes G¨uven C¸ ankayaa and Nazım Uc¸arb a Gaziosmanpas¸a University, Faculty of Sciences and Arts, Physics Department, Tokat, Turkey b S¨uleyman Demirel University, Faculty of Sciences and Arts, Physics Department, Isparta, Turkey Reprint requests to Prof. N. U.; E-mail: [email protected] Z. Naturforsch. 59a, 795 – 798 (2004); received July 5, 2004 We investigated Schottky barrier diodes of 9 metals (Mn, Cd, Al, Bi, Pb, Sn, Sb, Fe, and Ni) hav- ing different metal work functions to p-type Si using current-voltage characteristics. Most Schottky contacts show good characteristics with an ideality factor range from 1.057 to 1.831. Based on our measurements for p-type Si, the barrier heights and metal work functions show a linear relationship of current-voltage characteristics at room temperature with a slope (S = φb/φm) of 0.162, even though the Fermi level is partially pinned. From this linear dependency, the density of interface states was determined to be about 4.5 · 1013 1/eV per cm2, and the average pinning position of the Fermi level as 0.661 eV below the conduction band. Key words: Schottky Diodes; Barrier Height; Series Resistance; Work Function; Miedema Electronegativity. 1. Introduction ear dependence should exist between the φb and the φm. Corresponding to this, SB heights of various el- The investigation of rectifying metal-semiconductor emental metals, including Au, Ti, Pt, Ni, Cr, have contacts (Schottky diodes) is of current interest for been reported [14 – 16].
    [Show full text]
  • Ni Silicide Schottky Barrier Tunnel FET for Low Power Device Applications
    Tokyo Institute of Technology Master’s Thesis – March 2011 Ni Silicide Schottky barrier tunnel FET for Low power device applications (低消費電力動作に向けたニッケルシリサイドバリアトンネルFET） Yan Wu Department of Electronics and Applied Physics Interdisciplinary Graduate School of Science and Engineering MASTER OF SCIENCE IN PHYSICAL ENGINEERING 09M53470 Supervisor: Professor Akira Nishiyama and Hiroshi Iwai Abstract To solve this problem that the supply voltage and the threshold voltage should be scaled but induction of the leakage would increase current at the zero gate voltage. The Subthreshold slope (SS) cannot be scaled down below 60mV/decade at Room temperature in principle and this fact hinders the applied voltage scaling. The tunnel FET is one of the promising candidates to decreases SS. Schottky barrier Tunneling FET (SBTT), which uses schottky tunnel junction, has many advantages to ordinary PN junction Tunnel FETs: low parasitic resistance, better short channel effect immunity and high controllability of output characteristics by the silicide material selection. The tunnel FET with NiSi/Si schottky barrier at the source/channel interface was fabricated and the characteristics were analyzed in terms of the drive current mechanism at low and high voltage. For that purpose, temperature dependence measurements of the transistor characteristics were mainly performed. Contents Abstract I Introduction I.1 Background of This Study I.2 Ultimate CMOS downsizing I.3 subthreshold leakage increasing I.4 tunneling FET I.5 Objective of this study II Metal-Semiconductor
    [Show full text]
  • Si7748dp N-Channel 30 V (D-S) MOSFET with Schottky Diode
    Si7748DP www.vishay.com Vishay Siliconix N-Channel 30 V (D-S) MOSFET with Schottky Diode FEATURES PRODUCT SUMMARY •SkyFETTM monolithic TrenchFET® power V (V) R (Ω)I (A) a Q (TYP.) DS DS(on) D g MOSFET and Schottky diode 0.0048 at VGS = 10 V 50 30 27.8 nC • 100 % R and UIS tested 0.0066 at VGS = 4.5 V 50 g • Material categorization: For definitions of compliance please see ® PowerPAK SO-8 Single www.vishay.com/doc?99912 D D 8 D APPLICATIONS 7 D D 6 5 • Notebook - Vcore low-side 6.15 mm 1 2 S Schottky Diode 3 S G 1 5.15 mm 4 S G Top View Bottom View N-Channel MOSFET Ordering Information: Si7748DP-T1-GE3 (lead (Pb)-free and halogen-free) S ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V 30 DS V Gate-Source Voltage VGS ± 20 a TC = 25 °C 50 a TC = 70 °C 50 Continuous Drain Current (TJ = 150 °C) ID b, c TA = 25 °C 23.5 T = 70 °C 18.6 b, c A A Pulsed Drain Current (t = 100 μs) IDM 150 a TC = 25 °C 50 Continuous Source-Drain Diode Current IS b, c TA = 25 °C 4.3 Single Pulse Avalanche Current I 30 L = 0.1 mH AS Single Pulse Avalanche Energy EAS 45 mJ TC = 25 °C 56 TC = 70 °C 31 Maximum Power Dissipation PD b, c W TA = 25 °C 4.8 b, c TA = 70 °C 3 Operating Junction and Storage Temperature Range T , T -55 to 150 J stg °C Soldering Recommendations (Peak Temperature) d, e 260 THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYPICAL MAXIMUM UNIT Maximum Junction-to-Ambient b, f t ≤ 10 s R 21 26 thJA °C/W Maximum Junction-to-Case (Drain) Steady State RthJC 1.7 2.2 Notes a.
    [Show full text]