DOCSLIB.ORG

A Binary Instrumentation Tool for the Blackfin Processor

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
A Binary Instrumentation Tool for the Blackfin Processor A Binary Instrumentation Tool for the Blackfin Processor Enqiang Sun David Kaeli Department of Electrical and Computer Department of Electrical and Computer Engineering Engineering Northeastern University Northeastern University Boston, MA, U.S.A Boston, MA, U.S.A [email protected] [email protected] ABSTRACT tems. Software developers have used them to gather pro- While a large number of program profiling and instrumenta- gram information and identify critical sections of code. Hard- tion tools have been developed to support hardware and soft- ware designers use them to facilitate their evaluation of fu- ware analysis on general purpose systems, there is a general ture designs. Instrumentation tools can be divided into two lack of sophisticated tools available for embedded architec- categories, based on when instrumentation is applied. In- tures. Embedded systems are sensitive to performance bot- strumentation applied at run-time is called dynamic instru- tlenecks, memory leaks, and software inefficiencies. There is mentation; instrumentation applied at compile time or link a growing need to develop more sophisticated profiling and time is called static instrumentation. instrumentation tools in this rapidly growing design space. Instrumentation techniques in the embedded domain are rel- In this paper we describe, DSPInst, a binary instrumenta- atively immature, though due to the increased sophistication tion tool for the Analog Device’s Blackfin family of Digital of recent embedded systems, the need for more powerful Signal Processors (DSPs). DSPInst provides for fine-grained tools is growing. It is critical for embedded system design- control over the execution of programs. Instrumentation ers to be able to properly debug hardware and software is- tool users are able to gain transparent access to the pro- sues. The need for improved instrumentation frameworks cessor and memory state at instruction boundaries, without for digital signal processing systems continues to grow [18, perturbing the architected program state. DSPInst provides 11]. a platform for building a wide range of customized analy- sis tools at an instruction level granularity. To demonstrate In this paper we describe DSPInst, a binary instrumenta- the utility of this toolset, we provide an example analysis tion tool targeting Analog Devices’ Blackfin family of DSPs. and optimization tool that performs dynamic voltage and DSPInst provides an infrastructure wherein embedded sys- frequency scaling to balance performance and power. tem developers can design a wide range of customized anal- ysis tools that operate at an instruction granularity. In Categories and Subject Descriptors DSPInst we have adopted a static instrumentation approach, and modified the binary executables of the applications be- D.3.4 [Programming languages]: Code generation, Opti- fore run-time. mization The remainder of the paper is organized as follows. Sec- General Terms tion 2 introduces the Blackfin DSP architecture used in our Languages, Management, Measurement, Performance work. Section 3 presents an survey of related instrumenta- tion tools. Section 4 presents the design details of DSPInst. Keywords In section 5, we illustrate the usage of DSPInst by present- DSPInst, Binary instrumentation, Embedded architectures, ing an example utility. Section 6 concludes the paper and Dynamic voltage and frequency scaling discusses future directions. 1. INTRODUCTION 2. ANALOGDEVICESBLACKFINDSPAR- Instrumentation tools have been shown to be extremely use- CHITECTURE ful in analyzing program behavior on general purpose sys- The infrastructure discussed in this paper targets the Analog Devices Blackfin family of DSPs. The specific DSP used in our example application is the ADSP-BF548. We start by Permission to make digital or hard copies of all or part of this work for providing a brief overview of the Blackfin family and its core personal or classroom use is granted without fee provided that copies are architecture. More detailed information is available in the not made or distributed for profit or commercial advantage and that copies Analog Devices Programmers Reference Manual [4, 1, 5, 2]. bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific The Blackfin DSP is a Micro Signal Architecture (MSA) permission and/or a fee. WBIA ’09, Dec 12, New York City, NY based architecture developed jointly by Analog Devices and Copyright(c) 2009 ACM 978-1-60558-793-6/12/09...$10.00. Intel Corporation. The architecture combines a dual 16- bit Multiply Accumulate (MAC) signal processing engine, Tools that operate on a binary format can be further di- flexible 32-bit Single Instruction Multiple Data (SIMD) ca- vided into two categories based on when instrumentation is pabilities, an orthogonal RISC-like instruction set and mul- applied. Probably the most commonly used static binary timedia features into a single instruction set architecture. instrumentation toolset ever developed was ATOM, which Combining DSP and microcontrol in a single instruction set targeted the Digital Alpha processor [21]. Other commonly enables the Blackfin to perform equally well in either signal used instrumentation toolsets include EEL [14], Etch [17] processing or control intensive applications. and Morph [24]. Some of the Blackfin Instruction Set Architecture (ISA) fea- The second class of binary instrumentation tools we consider tures include: are dynamic instrumentation. A number of high quality dy- namic instrumentation tools have been developed in recent years, and include Dyninst [7], Kerninst [22], Detours [12] • two 16-bit multipliers, two 40-bit accumulators, two and Vulcan [10]. These tools dynamically modify the origi- 40-bit arithmetic logic units (ALUs), four 8-bit video nal code in memory during execution in order to insert in- ALUs and a 40-bit shifter, strumentation trampolines (i.e., a mechanism that jumps be- • two Data Address Generator (DAG) units, tweeen the instrumented code and analysis code, and back again). Most of these dynamic instrumentation systems do • 16-bit instructions (which represent the most frequently not address instrumentation transparency, preserving the ar- used instructions), chitected state of the processor. Other dynamic instrumen- tation systems use caches and dynamic compilation of the bi- • complex DSP instructions are encoded into 32-bit op- nary, and include Valgrind [16], Strata [20], DynamoRIO [6], codes as multifunction instructions, Diota [15] and Pin [13]. Most of these tools target general • support limited multi-issue capabilities in a Very Long purpose architectures. Instruction Word (VLIW) fashion, where a 32-bit in- struction can be issued in parallel with two 16-bit in- Instrumentation tools targeting embedded systems need to structions, and satisfy a different set of requirements [11]. Some of these constraints include power efficiency and lack of operating • a fixed point processor, offering 8, 16, 32-bit signed or system support. Many of these issues force us to take a unsigned traditional data types, as well as 16 or 32-bit minimalists approach to instrumentation (i.e., less is more). signed fractional data types. The DELI [9] developed by Hewlett-Packard and ST Micro- electronics provides utilities to manipulate VLIW instruc- tions on the LX/ST210 embedded processor. DSPTune [18] The Blackfin processor supports a modified Harvard archi- is a toolset similar to DSPInst targeting the Analog Devices tecture in combination with a hierarchical memory struc- SHARC architecture. However, DSPTune can only instru- ture, which is organized into two levels. The L1 memory ment C or assembly code, which limits its usefulness when can be accessed at the core clock frequency in a single clock source is not available. cycle. The L2 memory is slightly slower, but still faster than external memory. The L1 memory can be configured DSPInst utilizes static instrumentation. The main contri- as cache and/or SRAM, giving Blackfin the flexibility to sat- butions of DSPInst are: isfy a range of application requirements [19]. The Blackfin Processor was designed to be a low-power pro- • This is the first tool-building system targeting the Black- cessor, and is equipped with a Dynamic Power Manage- fin DSP processors. Analysis tools to perform code ment Controller (DPMC). The DPMC works together with profiling or code modification can be built easily. the Phase Locked Loop (PLL) circuitry, allowing the user to scale both frequency and voltage, to arrive at the best • DSPInst allows for selective instrumentation; the user power/performance frequency/voltage operating point for can specify on instruction boundaries when to turn the target application. profiling or code modifications on/off. The Blackfin Processor has a built-in performance monitor • unit (PMU) that monitors internal resources unintrusively. DSPInst instruments object code, versus source or as- The PMU covers a wide range of events, including pipeline sembly. DSPInst decouples the user from having to and memory stalls, and includes penalties associated with provide source code of the application to be instru- these events. Developers can use the PMU to count proces- mented. sor events during program execution. This kind of profiling can be utilized to better understand performance bottle- necks and opportunities for voltage/frequency scaling. The The basic philosophy of DSPInst is to replace instructions PMU provides a more efficient debugging utility as opposed in the
Load more

Recommended publications
  • Dynamic Optimization of IA-32 Applications Under Dynamorio by Timothy Garnett
    Dynamic Optimization of IA-32 Applications Under DynamoRIO by Timothy Garnett Submitted to the Department of Electrical Engineering and Computer Science in Partial Fulfillment of the Requirements for the Degree of Master of Engineering in Computer Science Abstract The ability of compilers to optimize programs statically is diminishing. The advent and increased use of shared libraries, dynamic class loading, and runtime binding means that the compiler has, even with difficult to accurately obtain profiling data, less and less knowledge of the runtime state of the program. Dynamic optimization systems attempt to fill this gap by providing the ability to optimize the application at runtime when more of the system's state is known and very accurate profiling data can be obtained. This thesis presents two uses of the DynamoRIO runtime introspection and modification system to optimize applications at runtime. The first is a series of optimizations for interpreters running under DynamoRIO's logical program counter extension. The optimizations include extensions to DynamoRIO to allow the interpreter writer add a few annotations to the source code of his interpreter that enable large amounts of optimization. For interpreters instrumented as such, improvements in performance of 20 to 60 percent were obtained. The second use is a proof of concept for accelerating the performance of IA-32 applications running on the Itanium processor by dynamically translating hot trace paths into Itanium IA-64 assembly through DynamoRIO while allowing the less frequently executed potions of the application to run in Itanium's native IA-32 hardware emulation. This transformation yields speedups of almost 50 percent on small loop intensive benchmarks.
    [Show full text]
  • Corecommander for Microprocessors and Microcontrollers
    CORECOMMANDER FOR MICROPROCESSORS AND MICROCONTROLLERS Factsheet Direct access to memory and peripheral devices (I/O) for testing, debugging and in-system programming • Direct access to memory and peripheral (I/O) devices of a micro- processor through its (JTAG) debug interface • Read data from, write data to memory and peripherals without software programming • At-speed execution of read and write cycles • Testing and debugging of the connectivity of processor memory and peripherals with at-speed bus cycles without software programming • Easy programming of processor flash memory without software programming Corecommander provides high-level functions to write data to and read data from microprocessor memory Order information CoreComm Micro (core) and I/O addresses without software programming. (core) = ARM 7, ARM 9, ARM 11, Cortex-A, Cortex-R, CoreCommander functions are applied via the JTAG Cortex-M, Blackfin, PXA2xx, PXA3xx, IXP4xx, PowerPC- interface. MPC500 family, PowerPC-MPC5500 family, PowerPC- MPC5600 family, C28x, XC166, Tricore, PIC32 Applications CoreCommander is used in design debug, manufactu- ring test and (field) service for many different applica- [1] if the uProcessor also contains a boundary-scan register then teh tests and in-system tions such as: programming operations can also be done using the boundary-scan register instead of the CoreCommander. Whether in that case the CoreCommander or the boundary-scan register is used depends on preference or performance. • Diagnosing “dead-kernel” boards; no embedded code is required to perform memory reads and Background writes. A uP performs read and write operations on its bus to ac- cess memory and I/O locations. The read and write cycles • Determining the right settings for the peripheral normally result when the uP executes a program that is controller (DDR controller, flash memory controller, stored in memory.
    [Show full text]
  • PDF 19308 Kb ADSP-Bf50x Blackfin ® Processor Hardware Reference
    ADSP-BF50x Blackfin® Processor Hardware Reference Revision 1.2, February 2013 Part Number 82-100101-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information © 2013 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu- ment may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by impli- cation or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, Blackfin, CrossCore, EngineerZone, EZ-KIT Lite, and VisualDSP++ are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. CONTENTS PREFACE Purpose of This Manual .................................................................. li Intended Audience .......................................................................... li Manual Contents ........................................................................... lii What’s New in This Manual ........................................................... lv Technical Support .........................................................................
    [Show full text]
  • Dynamic Binary Translation & Instrumentation
    Dynamic Binary Translation & Instrumentation Pin Building Customized Program Analysis Tools with Dynamic Instrumentation CK Luk, Robert Cohn, Robert Muth, Harish Patil, Artur Klauser, Geoff Lowney, Steven Wallace, Kim Hazelwood Intel Vijay Janapa Reddi University of Colorado http://rogue.colorado.edu/Pin PLDI’05 2 Instrumentation • Insert extra code into programs to collect information about execution • Program analysis: • Code coverage, call-graph generation, memory-leak detection • Architectural study: • Processor simulation, fault injection • Existing binary-level instrumentation systems: • Static: • ATOM, EEL, Etch, Morph • Dynamic: • Dyninst, Vulcan, DTrace, Valgrind, Strata, DynamoRIO C Pin is a new dynamic binary instrumentation system PLDI’05 3 A Pintool for Tracing Memory Writes #include <iostream> #include "pin.H" executed immediately before a FILE* trace; write is executed • Same source code works on the 4 architectures VOID RecordMemWrite(VOID* ip, VOID* addr, UINT32 size) { fprintf(trace,=> “%p: Pin Wtakes %p %dcare\n”, of ip, different addr, size); addressing modes } • No need to manually save/restore application state VOID Instruction(INS ins, VOID *v) { if (INS_IsMemoryWrite(ins))=> Pin does it for you automatically and efficiently INS_InsertCall(ins, IPOINT_BEFORE, AFUNPTR(RecordMemWrite), IARG_INST_PTR, IARG_MEMORYWRITE_EA, IARG_MEMORYWRITE_SIZE, IARG_END); } int main(int argc, char * argv[]) { executed when an instruction is PIN_Init(argc, argv); dynamically compiled trace = fopen(“atrace.out”, “w”); INS_AddInstrumentFunction(Instruction,
    [Show full text]
  • Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation
    Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation Chi-Keung Luk Robert Cohn Robert Muth Harish Patil Artur Klauser Geoff Lowney Steven Wallace Vijay Janapa Reddi Kim Hazelwood Intel Corporation ¡ University of Colorado ¢¤£¦¥¨§ © £ ¦£ "! #%$&'( £)&(¦*+©-,.+/01$©-!2 ©-,2¦3 45£) 67©2, £¦!2 "0 Abstract 1. Introduction Robust and powerful software instrumentation tools are essential As software complexity increases, instrumentation—a technique for program analysis tasks such as profiling, performance evalu- for inserting extra code into an application to observe its behavior— ation, and bug detection. To meet this need, we have developed is becoming more important. Instrumentation can be performed at a new instrumentation system called Pin. Our goals are to pro- various stages: in the source code, at compile time, post link time, vide easy-to-use, portable, transparent, and efficient instrumenta- or at run time. Pin is a software system that performs run-time tion. Instrumentation tools (called Pintools) are written in C/C++ binary instrumentation of Linux applications. using Pin’s rich API. Pin follows the model of ATOM, allowing the The goal of Pin is to provide an instrumentation platform for tool writer to analyze an application at the instruction level with- building a wide variety of program analysis tools for multiple archi- out the need for detailed knowledge of the underlying instruction tectures. As a result, the design emphasizes ease-of-use, portabil- set. The API is designed to be architecture independent whenever ity, transparency, efficiency, and robustness. This paper describes possible, making Pintools source compatible across different archi- the design of Pin and shows how it provides these features.
    [Show full text]
  • Introduction to Uclinux
    Introduction to uClinux V M Introduction to uClinux Michael Opdenacker Free Electrons http://free-electrons.com Created with OpenOffice.org 2.x Thanks to Nicolas Rougier (Copyright 2003, http://webloria.loria.fr/~rougier/) for the Tux image Introduction to uClinux © Copyright 2004-2007, Free Electrons Creative Commons Attribution-ShareAlike 2.5 license http://free-electrons.com Nov 20, 2007 1 Rights to copy Attribution ± ShareAlike 2.5 © Copyright 2004-2007 You are free Free Electrons to copy, distribute, display, and perform the work [email protected] to make derivative works to make commercial use of the work Document sources, updates and translations: Under the following conditions http://free-electrons.com/articles/uclinux Attribution. You must give the original author credit. Corrections, suggestions, contributions and Share Alike. If you alter, transform, or build upon this work, you may distribute the resulting work only under a license translations are welcome! identical to this one. For any reuse or distribution, you must make clear to others the license terms of this work. Any of these conditions can be waived if you get permission from the copyright holder. Your fair use and other rights are in no way affected by the above. License text: http://creativecommons.org/licenses/by-sa/2.5/legalcode Introduction to uClinux © Copyright 2004-2007, Free Electrons Creative Commons Attribution-ShareAlike 2.5 license http://free-electrons.com Nov 20, 2007 2 Best viewed with... This document is best viewed with a recent PDF reader or with OpenOffice.org itself! Take advantage of internal or external hyperlinks. So, don't hesitate to click on them! Find pages quickly thanks to automatic search.
    [Show full text]
  • Cross-Compiling Linux Kernels on X86 64: a Tutorial on How to Get Started
    Cross-compiling Linux Kernels on x86_64: A tutorial on How to Get Started Shuah Khan Senior Linux Kernel Developer – Open Source Group Samsung Research America (Silicon Valley) [email protected] Agenda ● Cross-compile value proposition ● Preparing the system for cross-compiler installation ● Cross-compiler installation steps ● Demo – install arm and arm64 ● Compiling on architectures ● Demo – compile arm and arm64 ● Automating cross-compile testing ● Upstream cross-compile testing activity ● References and Package repositories ● Q&A Cross-compile value proposition ● 30+ architectures supported (several sub-archs) ● Native compile testing requires wide range of test systems – not practical ● Ability to cross-compile non-natively on an widely available architecture helps detect compile errors ● Coupled with emulation environments (e.g: qemu) testing on non-native architectures becomes easier ● Setting up cross-compile environment is the first and necessary step arch/ alpha frv arc microblaze h8300 s390 um arm mips hexagon score x86_64 arm64 mn10300 unicore32 ia64 sh xtensa avr32 openrisc x86 m32r sparc blackfin parisc m68k tile c6x powerpc metag cris Cross-compiler packages ● Ubuntu arm packages (12.10 or later) – gcc-arm-linux-gnueabi – gcc-arm-linux-gnueabihf ● Ubuntu arm64 packages (13.04 or later) – use arm64 repo for older Ubuntu releases. – gcc-4.7-aarch64-linux-gnu ● Ubuntu keeps adding support for compilers. Search Ubuntu repository for packages. Cross-compiler packages ● Embedded Debian Project is a good resource for alpha, mips,
    [Show full text]
  • ADSP-Bf60x Blackfin Embedded Processor Data Sheet, Revision
    Blackfin Dual Core Embedded Processor ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 FEATURES MEMORY Dual-core symmetric high-performance Blackfin processor, Each core contains 148K bytes of L1 SRAM memory (proces- up to 500 MHz per core sor core-accessible) with multi-parity bit protection Each core contains two 16-bit MACs, two 40-bit ALUs, and a Up to 256K bytes of L2 SRAM memory with ECC protection 40-bit barrel shifter Dynamic memory controller provides 16-bit interface to a RISC-like register and instruction model for ease of single bank of DDR2 or LPDDR DRAM devices programming and compiler-friendly support Static memory controller with asynchronous memory inter- Advanced debug, trace, and performance monitoring face that supports 8-bit and 16-bit memories Pipelined Vision Processor provides hardware to process sig- 4 Memory-to-memory DMA streams, 2 of which feature CRC nal and image algorithms used for pre- and co-processing protection of video frames in ADAS or other video processing Flexible booting options from flash, SD EMMC and SPI mem- applications ories and from SPI, link port and UART hosts Accepts a range of supply voltages for I/O operation. See Memory management unit provides memory protection Operating Conditions on Page 52 Off-chip voltage regulator interface 349-ball BGA package (19 mm × 19 mm), RoHS compliant SYSTEM CONTROL BLOCKS PERIPHERALS EMULATOR PLL & POWER FAULT EVENT DUAL TEST & CONTROL MANAGEMENT MANAGEMENT CONTROL WATCHDOG 2× TWI 8× TIMER 1× COUNTER L2 MEMORY 2× PWM CORE 0 CORE 1 32K BYTE ROM B B 3× SPORT 256K BYTE 148K BYTE 148K BYTE 1× ACM PARITY BIT PROTECTED PARITY BIT PROTECTED ECC- L1 SRAM L1 SRAM PROTECTED INSTRUCTION/DATA INSTRUCTION/DATA SRAM 2× UART 112 GP I/O EMMC/RSI DMA SYSTEM 1× CAN 2× EMAC EXTERNAL WITH BUS 2× IEEE 1588 INTERFACES 2× SPI PIPELINED DYNAMIC STATIC CRC VISION PROCESSOR 4× LINK PORT MEMORY MEMORY CONTROLLER CONTROLLER VIDEO SUBSYSTEM HARDWARE 3× PPI FUNCTIONS PIXEL COMPOSITOR LPDDR 16 FLASH 16 USB 2.0 HS OTG DDR2 SRAM Figure 1.
    [Show full text]
  • Getting Started with Blackfin Processors, Revision 6.0, September 2010
    Getting Started With Blackfin® Processors Revision 6.0, September 2010 Part Number 82-000850-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information ©2010 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices. Printed in the USA. Disclaimer Analog Devices reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or oth- erwise under the patent rights of Analog Devices. Trademark and Service Mark Notice The Analog Devices logo, Blackfin, the Blackfin logo, CROSSCORE, EZ-Extender, EZ-KIT Lite, and VisualDSP++ are registered trademarks of Analog Devices. EZ-Board is a trademark of Analog Devices. All other brand and product names are trademarks or service marks of their respective owners. CONTENTS PREFACE Purpose of This Manual .................................................................. xi Intended Audience ......................................................................... xii Manual Contents ........................................................................... xii What’s New in This Manual ........................................................... xii Technical or Customer Support ....................................................
    [Show full text]
  • An Infrastructure for Adaptive Dynamic Optimization
    An Infrastructure for Adaptive Dynamic Optimization Derek Bruening, Timothy Garnett, and Saman Amarasinghe Laboratory for Computer Science Massachusetts Institute of Technology Cambridge, MA 02139 fiye,timothyg,[email protected] Abstract ing profile information improves the predictions but still falls short for programs whose behavior changes dynami- Dynamic optimization is emerging as a promising ap- cally. Additionally, many software vendors are hesitant to proach to overcome many of the obstacles of traditional ship binaries that are compiled with high levels of static op- static compilation. But while there are a number of com- timization because they are hard to debug. piler infrastructures for developing static optimizations, Shifting optimizations to runtime solves these problems. there are very few for developing dynamic optimizations. Dynamic optimization allows the user to improve the per- We present a framework for implementing dynamic analy- formance of binaries without relying on how they were ses and optimizations. We provide an interface for build- compiled. Furthermore, several types of optimizations are ing external modules, or clients, for the DynamoRIO dy- best suited to a dynamic optimization framework. These in- namic code modification system. This interface abstracts clude adaptive, architecture-specific, and inter-module opti- away many low-level details of the DynamoRIO runtime mizations. system while exposing a simple and powerful, yet efficient Adaptive optimizations require instant responses to and lightweight, API. This is achieved by restricting opti- changes in program behavior. When performed statically, a mization units to linear streams of code and using adaptive single profiling run is taken to be representative of the pro- levels of detail for representing instructions.
    [Show full text]
  • Using Dynamic Binary Instrumentation for Security(And How You May Get
    King’s Research Portal Document Version Peer reviewed version Link to publication record in King's Research Portal Citation for published version (APA): Cono D'Elia, D., Coppa, E., Palmaro, F., & Cavallaro, L. (Accepted/In press). SoK: Using Dynamic Binary Instrumentation for Security (And How You May Get Caught Red Handed). In ACM Asia Conference on Information, Computer and Communications Security (ASIACCS 2019) Citing this paper Please note that where the full-text provided on King's Research Portal is the Author Accepted Manuscript or Post-Print version this may differ from the final Published version. If citing, it is advised that you check and use the publisher's definitive version for pagination, volume/issue, and date of publication details. And where the final published version is provided on the Research Portal, if citing you are again advised to check the publisher's website for any subsequent corrections. General rights Copyright and moral rights for the publications made accessible in the Research Portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognize and abide by the legal requirements associated with these rights. •Users may download and print one copy of any publication from the Research Portal for the purpose of private study or research. •You may not further distribute the material or use it for any profit-making activity or commercial gain •You may freely distribute the URL identifying the publication in the Research Portal Take down policy If you believe that this document breaches copyright please contact [email protected] providing details, and we will remove access to the work immediately and investigate your claim.
    [Show full text]
  • Jamaicavm Provides Hard Realtime Guarantees for Most Common Realtime Operating Systems Are Sup- All Primitive Java Operations
    ��������� Java-Technology for Critical Embedded Systems ��������� �������� ���������� ����������� ������� ���������� ������� ������� ���������� ����������� ���������� ������ ��������� Java-Tools for developers of critical software applications. Key Technologies Interoperability Hard realtime execution Ported to standard RTOSes The JamaicaVM provides hard realtime guarantees for Most common realtime operating systems are sup- all primitive Java operations. This enables all of Java’s ported by JamaicaVM, ports for VxWorks, QNX, Linux- features to be used for your hard realtime tasks. Fea- variants, RTEMS, etc. exist. The supported architectures tures essential to object-oriented software develop- include SH4, PPC, x86, ARM, XScale, ERC32, and many ment like dynamic allocation of objects, inheritance, more. To support your specific system, we can provide and dynamic binding become available to the real- you with the required porting service. time developer. ROMable code Realtime Garbage Collection Class files and the Jamaica Virtual Machine may be The JamaicaVM provides the only Java implementa- linked into a standalone binary for execution out of tion with an efficient hard realtime garbage collector. ROM. A filesystem in not necessary for running Java It operates in small increments of only a few machine code. instructions and guarantees to recycle all garbage memory, to avoid memory fragmentation, and to Library and JNI Native Code bound the execution time for allocations. Existing library code or low level performance critical code for hardware access can be embedded into Fast & Small your realtime application using the Java Native Inter- A highly optimizing static compiler ensures best runtime face. performance. A profiling tool gathers information for providing the best trade-off between runtime perfor- mance and code size. Jamaica Toolset Sophisticated automatic class file compaction, dead- � � � � � � � � � � code elimination and profile-guided partial compila- tion techniques reduce the code footprint to the bare ���������� minimum.
    [Show full text]