Architectural Frameworks for Automated Design and Optimization of Hardware Accelerators
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Development of Systemc Modules from HDL for System-On-Chip Applications
University of Tennessee, Knoxville TRACE: Tennessee Research and Creative Exchange Masters Theses Graduate School 8-2004 Development of SystemC Modules from HDL for System-on-Chip Applications Siddhartha Devalapalli University of Tennessee - Knoxville Follow this and additional works at: https://trace.tennessee.edu/utk_gradthes Part of the Electrical and Computer Engineering Commons Recommended Citation Devalapalli, Siddhartha, "Development of SystemC Modules from HDL for System-on-Chip Applications. " Master's Thesis, University of Tennessee, 2004. https://trace.tennessee.edu/utk_gradthes/2119 This Thesis is brought to you for free and open access by the Graduate School at TRACE: Tennessee Research and Creative Exchange. It has been accepted for inclusion in Masters Theses by an authorized administrator of TRACE: Tennessee Research and Creative Exchange. For more information, please contact [email protected]. To the Graduate Council: I am submitting herewith a thesis written by Siddhartha Devalapalli entitled "Development of SystemC Modules from HDL for System-on-Chip Applications." I have examined the final electronic copy of this thesis for form and content and recommend that it be accepted in partial fulfillment of the equirr ements for the degree of Master of Science, with a major in Electrical Engineering. Dr. Donald W. Bouldin, Major Professor We have read this thesis and recommend its acceptance: Dr. Gregory D. Peterson, Dr. Chandra Tan Accepted for the Council: Carolyn R. Hodges Vice Provost and Dean of the Graduate School (Original signatures are on file with official studentecor r ds.) To the Graduate Council: I am submitting herewith a thesis written by Siddhartha Devalapalli entitled "Development of SystemC Modules from HDL for System-on-Chip Applications". -
A Fedora Electronic Lab Presentation
Chitlesh GOORAH Design & Verification Club Bristol 2010 FUDConBrussels 2007 - [email protected] [ Free Electronic Lab ] (formerly Fedora Electronic Lab) An opensource Design and Simulation platform for Micro-Electronics A one-stop linux distribution for hardware design Marketing means for opensource EDA developers (Networking) From SPEC, Model, Frontend Design, Backend, Development boards to embedded software. FUDConBrussels 2007 - [email protected] Electronic Designers Problems Approx. 6 month design development cycle Tackling Design Complexity Lower Power, Lower Cost and Smaller Space Semiconductor Industry's neck squeezed in 2008 Management (digital/analog) IP Portfolio FUDConBrussels 2007 - [email protected] FUDConBrussels 2007 - [email protected] A basic Design Flow FUDConBrussels 2007 - [email protected] TIP: Use verilator to lint your verilog files. Most of the Veripool tools are available under FEL. They are in sync with Wilson Snyder's releases. FUDConBrussels 2007 - [email protected] FUDConBrussels 2007 - [email protected] GTKWaveGTKWave Don'tDon't forgetforget itsits TCLTCL backendbackend WidelyWidely usedused togethertogether withwith SystemCSystemC FUDConBrussels 2007 - [email protected] Tools Standard Cell libraries FUDConBrussels 2007 - [email protected] BackendBackend designdesign Open Circuit Design, Electric FUDConBrussels 2007 - [email protected], Toped gEDA/gafgEDA/gaf Well known and famous. A very good example of opensource -
Simulator for the RV32-Versat Architecture
Simulator for the RV32-Versat Architecture João César Martins Moutoso Ratinho Thesis to obtain the Master of Science Degree in Electrical and Computer Engineering Supervisor(s): Prof. José João Henriques Teixeira de Sousa Examination Committee Chairperson: Prof. Francisco André Corrêa Alegria Supervisor: Prof. José João Henriques Teixeira de Sousa Member of the Committee: Prof. Marcelino Bicho dos Santos November 2019 ii Declaration I declare that this document is an original work of my own authorship and that it fulfills all the require- ments of the Code of Conduct and Good Practices of the Universidade de Lisboa. iii iv Acknowledgments I want to thank my supervisor, Professor Jose´ Teixeira de Sousa, for the opportunity to develop this work and for his guidance and support during that process. His help was fundamental to overcome the multiple obstacles that I faced during this work. I also want to acknowledge Professor Horacio´ Neto for providing a simple Convolutional Neural Net- work application, used as a basis for the application developed for the RV32-Versat architecture. A special acknowledgement goes to my friends, for their continuous support, and Valter,´ that is developing a multi-layer architecture for RV32-Versat. When everything seemed to be doomed he always had a miraculous solution. Finally, I want to express my sincere gratitude to my family for giving me all the support and encour- agement that I needed throughout my years of study and through the process of researching and writing this thesis. They are also part of this work. Thank you. v vi Resumo Esta tese apresenta um novo ambiente de simulac¸ao˜ para a arquitectura RV32-Versat baseado na ferramenta de simulac¸ao˜ Verilator. -
Chapter 1. Origins of Mac OS X
1 Chapter 1. Origins of Mac OS X "Most ideas come from previous ideas." Alan Curtis Kay The Mac OS X operating system represents a rather successful coming together of paradigms, ideologies, and technologies that have often resisted each other in the past. A good example is the cordial relationship that exists between the command-line and graphical interfaces in Mac OS X. The system is a result of the trials and tribulations of Apple and NeXT, as well as their user and developer communities. Mac OS X exemplifies how a capable system can result from the direct or indirect efforts of corporations, academic and research communities, the Open Source and Free Software movements, and, of course, individuals. Apple has been around since 1976, and many accounts of its history have been told. If the story of Apple as a company is fascinating, so is the technical history of Apple's operating systems. In this chapter,[1] we will trace the history of Mac OS X, discussing several technologies whose confluence eventually led to the modern-day Apple operating system. [1] This book's accompanying web site (www.osxbook.com) provides a more detailed technical history of all of Apple's operating systems. 1 2 2 1 1.1. Apple's Quest for the[2] Operating System [2] Whereas the word "the" is used here to designate prominence and desirability, it is an interesting coincidence that "THE" was the name of a multiprogramming system described by Edsger W. Dijkstra in a 1968 paper. It was March 1988. The Macintosh had been around for four years. -
High Speed Data Link
High Speed Data Link Vladimir Stojanovic liheng zhu Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2017-72 http://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-72.html May 12, 2017 Copyright © 2017, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. University of California, Berkeley College of Engineering MASTER OF ENGINEERING - SPRING 2017 Electrical Engineering and Computer Science Physical Electronics and Integrated Circuits Project High Speed Data Link Liheng Zhu This Masters Project Paper fulfills the Master of Engineering degree requirement. Approved by: 1. Capstone Project Advisor: Signature: __________________________ Date ____________ Print Name/Department: Vladimir Stojanovic, EECS Department 2. Faculty Committee Member #2: Signature: __________________________ Date ____________ Print Name/Department: Elad Alon, EECS Department Capstone Report Project High Speed Data Link Liheng Zhu A report submitted in partial fulfillment of the University of California, Berkeley requirements of the degree of Master of Engineering in Electrical Engineering and Computer Science March 2017 1 Introduction For our project, High-Speed Data Link, we are trying to implement a serial communication link that can operate at ~25Gb/s through a noisy channel. We decided to build a parameterized library to allow individual user to set up his/her own parameters according to the project specifications and requirements. -
FPGA-Accelerated Evaluation and Verification of RTL Designs
FPGA-Accelerated Evaluation and Verification of RTL Designs Donggyu Kim Electrical Engineering and Computer Sciences University of California at Berkeley Technical Report No. UCB/EECS-2019-57 http://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-57.html May 17, 2019 Copyright © 2019, by the author(s). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. FPGA-Accelerated Evaluation and Verification of RTL Designs by Donggyu Kim A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science in the Graduate Division of the University of California, Berkeley Committee in charge: Professor Krste Asanovi´c,Chair Adjunct Assistant Professor Jonathan Bachrach Professor Rhonda Righter Spring 2019 FPGA-Accelerated Evaluation and Verification of RTL Designs Copyright c 2019 by Donggyu Kim 1 Abstract FPGA-Accelerated Evaluation and Verification of RTL Designs by Donggyu Kim Doctor of Philosophy in Computer Science University of California, Berkeley Professor Krste Asanovi´c,Chair This thesis presents fast and accurate RTL simulation methodologies for performance, power, and energy evaluation as well as verification and debugging using FPGAs in the hardware/software co-design flow. Cycle-level microarchitectural software simulation is the bottleneck of the hard- ware/software co-design cycle due to its slow speed and the difficulty of simulator validation. -
Static Analysis to Improve RTL Verification
Static Analysis to Improve RTL Verification Akash Agrawal Thesis submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements for the degree of Master of Science in Computer Engineering Michael Hsiao, Chair Haibo Zeng A. Lynn Abbott February 16, 2017 Blacksburg, Virginia Keywords: Static Analysis, ATPG, RTL, Reachability Analysis Copyright 2017, Akash Agrawal Static Analysis to Improve RTL Verification Akash Agrawal ABSTRACT Integrated circuits have traveled a long way from being a general purpose microprocessor to an application specific circuit. It has become an integral part of the modern era of technology that we live in. As the applications and their complexities are increasing rapidly every day, so are the sizes of these circuits. With the increase in the design size, the associated testing effort to verify these designs is also increased. The goal of this thesis is to leverage some of the static analysis techniques to reduce the effort of testing and verification at the register transfer level. Studying a design at register transfer level gives exposure to the relational information for the design which is inaccessible at the structural level. In this thesis, we present a way to generate a Data Dependency Graph and a Control Flow Graph out of a register transfer level description of a circuit description. Next, the generated graphs are used to perform relation mining to improve the test generation process in terms of speed, branch coverage and number of test vectors generated. The generated control flow graph gives valuable information about the flow of information through the circuit design. -
THE FUTURE of HOME NETWORKING the Impact of Wi-Fi, Remote UI and Open Source Stacks on Service Provider Network Architecture
THE FUTURE OF HOME NETWORKING The Impact of Wi-Fi, Remote UI and Open Source Stacks on Service Provider Network Architecture Business Integration with Clarity The Future of Home Networking | pureIntegration Table of Contents 1 Introduction ................................................................................................. 2 2 Proposed Evolutions .................................................................................... 3 Authentication and WebUI .............................................................................................................. 5 Self-Healing/Diagnostic ................................................................................................................... 6 Security and Content Protection ..................................................................................................... 6 3 Gateway design impact ................................................................................ 7 4 CPE and IoT devices design impact ............................................................... 8 5 Proposed development and integration approach ....................................... 9 Phase 1: Interconnection tests with RDK-B or OpenWrt on Raspberry PI ...................................... 9 Phase 2: Authentication & Remote Management development on Raspberry PI .......................... 9 Phase 3: Port on Production Gateway ............................................................................................ 9 Phase 4: End to End Integration ................................................................................................... -
Performed the Most Often. in FPGA Design Flow, Functional and Gate
performed the most often. In FPGA design flow, functional and gate-level timing simulation is typically performed when designers suspect that there might be a mismatch between RTL and functional or gate-level timing simulation results, which can lead to an incorrect design. The mismatch can be caused for several reasons discussed in more detail in Tip #59. Note that the nomenclature of simulation types is not consistent. The same name, for instance “gate-level simulation”, can have slightly different meaning in simulation flows of different FPGA vendors. The situation is even more confusing in ASIC simulation flows, which have many more different simulation types, such as transistor-level, and dynamic simulation. The following figure shows simulation types designers can perform during Xilinx FPGA synthesis and physical implementation process. Figure 1: Simulation types Xilinx FPGA designers can perform simulation after each level of design transformation from the original RTL to the bitstream. The following example is a 12-bit OR gate implemented in Verilog. module sim_types(input [11:0] user_in, output user_out); assign user_out = |user_in; endmodule XST post-synthesis simulation model is implemented using LUT6 and LUT2 primitives, which are parts of Xilinx UNISIMS RTL simulation library. wire out, out1_14; LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFE )) out1 ( .I0(user_in[3]), .I1(user_in[2]), .I2(user_in[5]), .I3(user_in[4]), .I4(user_in[7]), .I5(user_in[6]), .O(out)); LUT6 #( .INIT ( 64'hFFFFFFFFFFFFFFFE )) out2 ( .I0(user_in[9]), .I1(user_in[8]), .I2(user_in[11]), .I3(user_in[10]), .I4(user_in[1]), .I5(user_in[0]), .O(out1_14)); LUT2 #( .INIT ( 4'hE )) out3 ( .I0(out), .I1(out1_14), .O(user_out) ); Post-synthesis simulation model can be generated using the following command: $ netgen -w -ofmt verilog -sim sim.ngc post_synthesis.v Post-translate simulation model is implemented using X_LUT6 and X_LUT2 primitives, which are parts of Xilinx SIMPRIMS simulation library. -
RTL Design and Implementation of a Framebuffer for a RISC-V Processor
Universitat Politècnica de Catalunya (UPC) BarcelonaTech Facultat d’Informàtica de Barcelona (FIB) RTL design and implementation of a framebuffer for a RISC-V processor Educational Cooperative Agreement with Barcelona Supercomputing Centre (BSC) Computer Engineering Degree Final Project Author: Narcís Rodas Quiroga Supervisor: Miquel Moretó (Computer Architecture Department DAC) Co-supervisor: Guillem Cabo Specialization: Computer Engineering Date of oral defense: 28th of October 2020 Abstract The RISC-V instruction set architecture (ISA) and the foundation that supports it continue to grow rapidly as an open-source alternative for hardware designs. Despite open-source software already being established as an important part of all the software solutions, open-source hardware has only recently begun to expand. Before that, the market was entirely made of proprietary ISAs (mostly from the US) that controlled it. This Final Degree Thesis shows the design, implementation and testing of a VGA (Video Graphics Array) framebuffer for the RISC-V processor being developed in the DRAC project by the Barcelona Supercomputing Centre. This document explains the various steps taken along the way and the reasoning behind the decisions that were taken. Keywords: RISC-V, VGA, RTL, Verilog, Framebuffer, AXI. Resumen El conjunto de instrucciones o ISA (del inglés instruction set architecture) RISC-V y la fundación que lo respalda siguen creciendo rápidamente como una alternativa open-source para los diseños hardware. Aunque el software open-source ya representa una parte importante de todas las soluciones software, el hardware open-source todavía está empezando a expandirse. Antes de esto, el mercado estaba compuesto íntegramente de ISAs propietarias (la gran mayoría provenientes de los E.E. -
Pymtl: a Unified Framework for Vertically Integrated Computer
Appears in the Proceedings of the 47th Int’l Symp. on Microarchitecture (MICRO-47), December 2014 PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research Derek Lockhart, Gary Zibrat, and Christopher Batten School of Electrical and Computer Engineering, Cornell University, Ithaca, NY {dml257,gdz4,cbatten}@cornell.edu Abstract—Technology trends prompting architects to con- tures, it has general value as a methodology for more tradi- sider greater heterogeneity and hardware specialization have tional architecture research as well. exposed an increasing need for vertically integrated research Unfortunately, attempts to implement an MTL methodol- methodologies that can effectively assess performance, area, and energy metrics of future architectures. However, constructing ogy using existing publicly-available research tools reveals such a methodology with existing tools is a significant challenge numerous practical challenges we call the computer architec- due to the unique languages, design patterns, and tools used ture research methodology gap. This gap is manifested as in functional-level (FL), cycle-level (CL), and register-transfer- the distinct languages, design patterns, and tools commonly level (RTL) modeling. We introduce a new framework called used by functional level (FL), cycle level (CL), and register- PyMTL that aims to close this computer architecture research methodology gap by providing a unified design environment transfer level (RTL) modeling. We believe the computer ar- for FL, CL, and RTL modeling. PyMTL leverages the Python chitecture research methodology gap exposes a critical need programming language to create a highly productive domain- for a new vertically integrated framework to facilitate rapid specific embedded language for concurrent-structural modeling design-space exploration and hardware implementation. -
Capability Directory 3
AUTOMOTIVE CONSULTANCIES DEVELOPMENT TOOL SUPPLIERS POWERTRAIN CONSULTANCIES CAPABILITY TEST & CERTIFICATION FACILITIES TIER 1 - SYSTEM DEVELOPERS & DIRECTORY INTEGRATORS TIER 2 - COMPONENT DEVELOPERS & SUPPLIERS VEHICLE COMPONENT SUPPLIERS 2018/19 UK based Companies offering Automotive Electronics services and solutions. AESIN Capability Directory 3 As Chairman of AESIN I am delighted to announce the second revision of this valuable Automotive Capability Directory which provides a rich resource of UK based Companies offering Automotive Electronics services and solutions. As part of our work at AESIN to help enable rapid innovation in Automotive Electronic Systems, it is vital that we reach out to companies and organisations across the UK and engage with our core Industry led Workstream activities (Connectivity (V2X), More Electric powertrain, ADAS & AV, Security, Software and Research). As the AESIN Community is growing and seeking technology solutions this Directory has both a searchable on-line and printed version to be distributed at AESIN2018 Annual Conference 2nd October. I would like to thank all those involved at AESIN and TECHWORKS for the work in preparing this new revision of the publication and also to those providing the engaging Editorial supplements. I would encourage you make full use of the directory to help locate and connect with new potential suppliers and look forward to seeing this valuable resource grow year on year as we expand the AESIN Community to include Research and Academic Institutions . Alan Banks AESIN