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Ina21x Voltage Output
Product Order Technical Tools & Support & Folder Now Documents Software Community INA210, INA211, INA212, INA213, INA214, INA215 SBOS437J –MAY 2008–REVISED FEBRUARY 2017 INA21x Voltage Output, Low- or High-Side Measurement, Bidirectional, Zero-Drift Series, Current-Shunt Monitors 1 Features 3 Description The INA21x are voltage-output, current-shunt 1• Wide Common-Mode Range: –0.3 V to 26 V monitors (also called current-sense amplifiers) that • Offset Voltage: ±35 μV (Maximum, INA210) are commonly used for overcurrent protection, (Enables Shunt Drops of 10-mV Full-Scale) precision-current measurement for system • Accuracy: optimization, or in closed-loop feedback circuits. This – Gain Error (Maximum Over Temperature): series of devices can sense drops across shunts at common-mode voltages from –0.3 V to 26 V, – ±0.5% (Version C) independent of the supply voltage. Six fixed gains are – ±1% (Versions A and B) available: 50 V/V, 75 V/V, 100 V/V, 200 V/V, 500 V/V, – 0.5-µV/°C Offset Drift (Maximum) or 1000 V/V. The low offset of the zero-drift architecture enables current sensing with maximum – 10-ppm/°C Gain Drift (Maximum) drops across the shunt as low as 10-mV full-scale. • Choice of Gains: These devices operate from a single 2.7-V to 26-V – INA210: 200 V/V power supply, drawing a maximum of 100 µA of – INA211: 500 V/V supply current. All versions are specified over the – INA212: 1000 V/V extended operating temperature range (–40°C to +125°C), and offered in SC70 and UQFN – INA213: 50 V/V packages. -
Performance Characteristics of IC Packages 4
Performance Characteristics of IC Packages 4 4.1 IC Package Electrical Characteristics As microprocessor speeds have increased and power supply voltages have decreased, the function of the microprocessor package has transitioned from that of a mechanical interconnect which provides protection for the die from the outside environment to that of an electrical interconnect that affects microprocessor performance and which must be properly understood in an electrical context. Inherent in understanding the electrical performance effects of the package is the need for electrical characterization of the package. The package is a complex electrical environment and the characterization of this environment is a multi-faceted task that consists of models constructed from both theoretical calculations and experimental measurements. In simple terms, a package electrical model translates the physical properties of a package into electrical characteristics that are usually combined into a circuit representation. The typical electrical circuit characteristics that are reported are DC resistance (R), inductance (L), capacitance (C), and characteristic impedance (Z_o) of various structures in the package. A package model consists of two parts, both of which are necessary for fully understanding the electrical performance effects of the package environment on Intel’s microprocessors. The first is an I/O lead model that describes the signal path from the die to the board. Depending upon the complexity of the model required for simulation purposes, the I/O lead model can take the form of a simple lumped circuit model, a distributed lumped circuit model, a single-conductor transmission-line model, or a multiple-conductor transmission-line model. While lumped models can adequately model simple effects, such as DC resistive voltage drop, more sophisticated models like the multiple-conductor transmission-line model include effects such as time delay and crosstalk. -
FC-PBGA, Flip Chip Plastic Ball Grid Array
TM Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. Table of Contents Slide 1. FC-PBGA Package Configurations 3 2. Printed Circuit Board Design for FC-PBGA 11 3. Surface Mount Assembly 16 4. Component Level Qualification 29 5. Board-Level Reliability 31 6. Thermal Performance 38 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a TM 2 Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc. TM FC-PBGA Package Configurations Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. -
Manufacturing and Reliability Challenges with QFN
Manufacturing and Reliability Challenges With QFN Dr. Craig Hillman and Cheryl Tulkoff DfR Solutions SMTA DC Chapter Ashburn, VA February 25, 2009 QFN as a ‘Next Generation’ Technology What is ‘Next Generation’ Technology? Materials or designs currently being used, but not widely adopted (especially among hi-rel manufacturers) Carbon nanotubes are not ‘Next Generation’ Not used in electronic applications Ball grid array is not ‘Next Generation’ Widely adopted © 2004 - 2007 2 Introduction (cont.) Why is knowing about ‘Next Generation’ Technologies important? These are the technologies that you or your supply chain will use to improve your product Cheaper, Faster, Stronger, ‘Environmentally-Friendly’, etc. And sooner then you think! © 2004 - 2007 3 Reliability and Next Gen Technologies One of the most common drivers for failure is inappropriate adoption of new technologies The path from consumer (high volume, short lifetime) to high rel is not always clear Obtaining relevant information can be difficult Information is often segmented Focus on opportunity, not risks Can be especially true for component packaging BGA, flip chip, QFN © 2004 - 2007 4 Component Packaging Most of us have little influence over component packaging Most devices offer only one or two packaging styles Why should you care? Poor understanding of component qualification procedures Who tests what and why? © 2004 - 2007 5 Component Testing Reliability testing performed by component manufacturers is driven by JEDEC JESD22 series (A & B) Focus is -
Land Grid Array (LGA) Package Rework
Freescale Semiconductor Document Number: AN3241 Application Note Rev. 1.0, 10/2009 Land Grid Array (LGA) Package Rework 1 Introduction Contents 1 Introduction . 1 This application note describes rework considerations 2 What is LGA? . 3 for the Land Grid Array (LGA) style package. 3 LGA Rework . 5 4 Package Removal . 6 Freescale has introduced radio frequency (RF) modules 5 LGA Reliability . 14 such as the MC1320x and MC1321x in LGA packages as 6 References . 14 an alternative package to ball grid array (BGA). The LGA packages reduce the amounts of lead in finished products and are Reduction of Hazardous Substances (RoHS) compliant, optimized for improved radio-frequency (RF) performance for wireless applications, and/or reduce the overall height of the package by eliminating the stand-off height associated with BGA balls. For assistance with any questions about the information contained in this note or for more details about the MC1320x and MC1321x devices, visit www.freescale.com/802154. or contact the appropriate product applications team. © Freescale Semiconductor, Inc., 2009. All rights reserved. Introduction 1.1 Acronyms and Abbreviations BGA Ball Grid Array BT Bismaleimide Triazine CBGA Ceramic Ball Grid Array CTE Coefficient of Thermal Expansion EU European Union ESD Electrostatic Discharge HCTE High Coefficient of Thermal Expansion HDI High Density Interconnect LGA Land Grid Array LTCC Low Temperature Co-fired Ceramic MSLn Moisture Sensitivity Level n NSMD Non-Solder Mask Defined OSP Organic Solderability Protectant PCB Printed Circuit Board RF Radio Frequency RoHS Reduction of Hazardous Substances SMD Solder Mask Defined SMT Surface Mount Technology Land Grid Array (LGA) Package Rework Application Note, Rev. -
Recommendations for Board Assembly of Infineon Ball Grid Array Packages
Recommendations for Board Assembly of Infineon Ball Grid Array Packages Additional Information Please read the Important Notice and Warnings at the end of this document Revision 4.0 www.infineon.com page 1 of 18 2020-11-09 Recommendations for Board Assembly of Infineon Ball Grid Array Packages Table of Contents Table of Contents Table of Contents ........................................................................................................................... 2 Acronyms and Abbreveations ........................................................................................................... 3 1 Package Description ............................................................................................................... 4 1.1 BGA Package Type ................................................................................................................................... 4 1.3 Package Features and General Handling Guidelines ............................................................................. 5 2 Printed Circuit Board .............................................................................................................. 7 2.1 Routing .................................................................................................................................................... 7 2.2 Pad Design ............................................................................................................................................... 7 3 PCB Assembly ....................................................................................................................... -
INTEGRATED CIRCUITS Introduction
INTEGRATED CIRCUITS Introduction Integrated circuits (ICs) are a keystone of modern electronics. They are the heart and brains of most circuits. They are the ubiquitous little black “chips” you find on just about every circuit board. Unless you’re some kind of crazy, analog electronics wizard, you’re likely to have at least one IC in every electronics project you build, so it’s important to understand them, inside and out. Integrated circuits are the little black “chips”, found all over embedded electronics. An IC is a collection of electronic components – resistors, transistors, capacitors, etc. – all stuffed into a tiny chip, and connected together to achieve a common goal. They come in all sorts of flavors: single-circuit logic gates, op amps, 555 timers, voltage regulators, motor controllers, microcontrollers, microprocessors, FPGAs…the list just goes on-and-on IC Packages The package is what encapsulates the integrated circuit die and splays it out into a device we can more easily connect to. Each outer connection on the die is connected via a tiny piece of gold wire to a pad or pin on the package. Pins are the silver, extruding terminals on an IC, which go on to connect to other parts of a circuit. These are of utmost importance to us, because they’re what will go on to connect to the rest of the components and wires in a circuit. There are many different types of packages, each of which has unique dimensions, mounting-types, and/or pin- counts. Polarity Marking and Pin Numbering All ICs are polarized, and every pin is unique in terms of both location and function. -
Package Outline Diagram Page Layout Used in This Data Book
Package Outline Diagram Page Layout Used in This Data Book Header: Shows form and number of pins FINE PITCH BALL GRID ARRAY PACKAGE 176 PIN PLASTIC BGA-176P-M03 Package code 176-pin plastic FBGA Lead pitch 0.50 mm Package width × 8.00 × 8.00 mm package length Characteristics Lead shape Soldering ball Sealing method Plastic mold Mounting height 1.13 mm MAX BGA Illustration Weight 0.12g (BGA-176P-M03) PLASTIC Ta b : S h ow s fo r m 176-pin plastic FBGA (BGA-176P-M03) +0.20 8.00±0.10(.315±.004)SQ 0.93 Ð0.10 176-¯0.30±0.10 Mounting height 0.05(.002) M +.008 (176-¯.012±.004) .037 Ð.004 0.50(.020) TYP 15 Package outline 14 13 12 diagram 11 10 0.08(.003) 9 7.00(.276) 8 REF INDEX 7 6 5 4 3 2 1 DEFGHJKLMNPR ABC INDEX AREA 0.25±0.10 Stand off (.010±.004) Dimensions in mm (inches). C 2000 FUJITSU LIMITED B176003S-1c-1 1 Introduction to Packages 1.1 Overview...................................................................................................... 3 1.2 Package Lineup .......................................................................................... 4 1.3 Package Forms 1.3.1 Lead insertion types .......................................................................... 6 1.3.2 Surface mounted types...................................................................... 6 1.4 Package Structures 1.4.1 Structure diagrams ............................................................................ 8 1.4.2 Sample Assembly Process.............................................................. 11 1.4.3 Structural materials ......................................................................... 13 1.4.4 Lead-Free Packages........................................................................ 15 1.5 How Package Dimensions Are Indicated 1.5.1 SOP dimensions.............................................................................. 16 1.6 Package Codes 1.6.1 Fujitsu Code Labeling...................................................................... 18 1.7 Marking 1.7.1 Standard marking ........................................................................... -
EE Concierge Style Guide PCB Layout and Component Creation
EE Concierge Style Guide PCB Layout and Component Creation For more information or component creation services visit EEConcierge.com Version 1.2 For more information or component creation services visit EEConcierge.com Table of Contents Introduction Checklist: What a perfect part looks like Style Guide: Pins Number of Pins Pin Numbers Pin Names Pin Types Style Guide: Attributes Step by Step Walkthrough Style Guide: Symbols Step by Step Walkthrough Headers Pin Organization Style Guide: Footprints General Tips Component Origin Layers Top Component Top Package Outline Top Solder Mask Top Paste Mask Top Copper Top Courtyard Top Silkscreen Top Keepout Bottom Layers Mechanical Details, Rulers, Notes, Design Rules Hole Layer Hole Sizing Plated Through Holes TO-92 and Other Parts With Overlapping Holes/Pads Non Plated Through Holes (NPTH) Axial Components DIP Components Thermal Pads BGAs Additional Guidelines Common Mistakes Made Missing refdes (both symbol and footprint) For more information or component creation services visit EEConcierge.com Holes not big enough (exact size of the hole) The datasheet is for a different part No part number on IC schematic No keepouts (this came up with antennas) Ground or power pins on the top or bottom of a symbol No pin one marker (footprint) Footprints not centered Missing mechanical details or holes on the wrong layers Wrong number of pins Bad pin names Missing overbars or # or n in the pin name Marking pin one improperly Specific Guidelines for Axial Components Specific Guidelines for Radial Components -
PDF Package Information
This version: Apr. 2001 Previous version: Jun. 1997 PACKAGE INFORMATION 1. PACKAGE CLASSIFICATIONS This document is Chapter 1 of the package information document consisting of 8 chapters in total. PACKAGE INFORMATION 1. PACKAGE CLASSIFICATIONS 1. PACKAGE CLASSIFICATIONS 1.1 Packaging Trends In recent years, marked advances have been made in the electronics field. One such advance has been the progression from vacuum tubes to transistors and finally, to ICs. ICs themselves have been more highly integrated into LSIs, VLSIs, and now, ULSIs. With increased functions and pin counts, IC packages have had to change significantly in the last few years in order to keep-up with the advancement in semiconductor development. Functions required for conventional IC packages are as follows: 1) To protect IC chips from the external environment 2) To facilitate the packaging and handling of IC chips 3) To dissipate heat generated by IC chips 4) To protect the electrical characteristics of the IC Standard dual-in-line packages (DIP), which fulfill these basic requirements, have enjoyed wide usage in the electronics industry for a number of years. With increasing integration and higher speed ICs, and with the miniaturization of electronic equipment, newer packages have been requested by the industry which incorporate the functions listed below: 1) Multi-pin I/O 2) Ultra-miniature packages 3) Packages suited to high density ICs 4) Improved heat resistance for use with reflow soldering techniques 5) High throughput speed 6) Improved heat dissipation 7) Lower cost per pin In response to these requests, OKI has developed a diversified family of packages to meet the myriad requirements of today’s burgeoning electronics industry. -
Quad Flat No-Lead (QFN) Evauation Test
National Aeronautics and Space Administration Quad Flat No-Lead (QFN) Evaluation Testing Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California Jet Propulsion Laboratory California Institute of Technology Pasadena, California 6/17 National Aeronautics and Space Administration Quad Flat No-Lead (QFN) Evaluation Testing NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Success Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory Pasadena, California NASA WBS: 724297.40.43 JPL Project Number: 104593 Task Number: 40.49.02.35 Jet Propulsion Laboratory 4800 Oak Grove Drive Pasadena, CA 91109 http://nepp.nasa.gov 6/17 This research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, and was sponsored by the National Aeronautics and Space Administration Electronic Parts and Packaging (NEPP) Program. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise, does not constitute or imply its endorsement by the United States Government or the Jet Propulsion Laboratory, California Institute of Technology. Copyright 2017. California Institute of Technology. Government sponsorship acknowledged. Acknowledgments The author would like to acknowledge many people from industry and the Jet Propulsion Laboratory (JPL) who were critical to the progress of this activity including the Rochester Institute of Technology (RIT). The author extends his appreciation to program managers of the National Aeronautics and Space -
AN1902: Assembly Guidelines for QFN and SON Packages
AN1902 Assembly guidelines for QFN (quad flat no-lead) and SON (small outline no-lead) packages Rev. 9 — 28 April 2021 Application note Document information Information Content Keywords QFN, SON, PCB, Assembly, Soldering Abstract This document provides guidelines for the handling and board mounting of QFN and SON packages including recommendations for printed-circuit board (PCB) design, soldering, and rework. NXP Semiconductors AN1902 Assembly guidelines for QFN (quad flat no-lead) and SON (small outline no-lead) packages Revision history Rev Date Description v.9 20210428 Updated description in Section 7.1 and Section 7.2 v.8 20180206 Rewrote to combine Freescale AN1902 and NXP AN10365 application notes into a single document. AN1902 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Application note Rev. 9 — 28 April 2021 2 / 50 NXP Semiconductors AN1902 Assembly guidelines for QFN (quad flat no-lead) and SON (small outline no-lead) packages 1 Introduction This application note provides guidelines for the handling and board mounting of NXP's QFN and SON packages including recommendations for printed-circuit board (PCB) design, board mounting, and rework. Generic information of package properties such as moisture sensitivity level (MSL) rating, board level reliability, mechanical and thermal resistance data are also provided. Semiconductor components are electrical (ESD) and mechanical sensitive devices. Proper precautions for handling, packing and processing are described. 2 Scope This application note contains generic information about various QFN and SON packages assembled at NXP and NXP's assembly and test vendors. Refer to Section 9 "Downloading package information from NXP website" of this application note for step by step instructions for retrieving package information.