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Architecture Overview Handbook, V1.1, Feb. 2006 C166S V2 16-Bit Synthesizable Microcontroller Microcontrollers Never stop thinking. Edition 2006-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2006. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Architecture Overview Handbook, V1.1, Feb. 2006 C166S V2 16-Bit Synthesizable Microcontroller Microcontrollers Never stop thinking. C166S V2 Architecture Overview Handbook Revision History: 2006-02 V1.1 Previous Version: none Page Subjects (major changes since last revision) Reissue. Updated Instruction Set Summary C166® is a registered trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] C166S V2 16-Bit Synthesizable Microcontroller 1Preface . 4 1.1 Overview . 5 1.2 Technical Summary . 6 1.3 Target Applications . 7 2 System Components . 8 3 Central Processing Unit (CPU) . 12 3.1 Overview . 12 3.2 CPU Special Function Registers (SFRs) . 14 3.3 Instruction Fetch Unit (IFU) & Program Flow Control . 15 3.4 Code Addressing via Code Segment & Instruction Pointers . 16 3.5 General Purpose Registers (GPR) . 17 3.6 Context Switch . 19 3.7 System Stack . 19 3.8 Data & DSP Addressing . 20 4 Data Processing . 21 4.1 Data Types . 21 4.2 Constants . 22 4.3 16-bit Add/Subtract, Barrel Shifter & Logic Unit . 23 4.4 Bit Manipulation Unit . 23 4.5 Multiply & Divide Unit . 24 4.6 Program Status Word (PSW) . 25 4.7 Parallel Data Processing . 25 5 Memory Organization . 27 5.1 SFR Notes . 27 6 Instruction Pipeline . 28 6.1 Injected Instructions . 30 7 Interrupt & Exception Handling . 31 7.1 Peripheral Event Controller (PEC) . 32 7.2 Priority, Arbitration & Structure . 33 8 External Bus Controller (EBC) . 34 9 Instruction Set Summary . 35 9.1 Instruction Mnemonics . 35 9.2 Instruction Opcodes . 49 Architecture Overview Handbook 3 V1.1, 2006-02 C166S V2 16-Bit Synthesizable Microcontroller Preface 1 Preface This document has been produced for engineering managers and hardware/software engineers, to provide an overview of the C166S V2 architecture. The C166S is the synthesizable version of the 16-bit C166 microcontroller family from Infineon, one of the world’s most successful 16-bit architectures. It is designed to meet the high performance requirements of real-time embedded control applications. 16-bit microcontrollers remain a strong force in the microprocessor market, providing a compact, cost-competitive, high-performance alternative to the 32-bit architecture world. Further information and documentation on the C166 product line (including the complete C166S V2 User’s Manual), can be found on the Internet at: http://www.infineon.com/xc166-family Alternatively, contact your nearest Infineon Sales office to request more information. Architecture Overview Handbook 4 V1.1, 2006-02 C166S V2 16-Bit Synthesizable Microcontroller Preface 1.1 Overview C166S V2 is the latest member of the C166 generation of microcontroller cores, combining high performance with enhanced modular architecture. With its impressive DSP performance and advanced interrupt handling features, the C166S V2 architecture has been developed to provide a simple and straightforward migration from existing C16x based applications. The C166S V2 inherits the successful hardware and software system architecture concepts established in the C16x 16-bit microcontroller families, while C166 code compatibility enables re-use of existing code to dramatically reduce the time-to-market for new product development. The C166S V2 core is strategically placed for contemporary and emerging markets dealing with performance-hungry, real-time applications. Features include: • High CPU performance - Single clock cycle execution doubles the performance at the same CPU frequency (relative to the performance of the C166). • Built-in advanced MAC (Multiply & Accumulate) unit dramatically increases DSP performance. • High Internal Program Memory bandwidth and use of the Instruction Fetch Pipeline to significantly improve program flow regularity and optimize fetches into the Execution Pipeline. • Sophisticated Data Memory structure and multiple high-speed data buses, providing transparent data access (0 cycles) and broad bandwidth for efficient DSP processing. • Advanced exceptions handling block with multi-stage arbitration capability, to yield dramatic interrupt performance with extremely small latency. • Upgraded PEC (Peripheral Event Controller) supporting efficient and flexible DMA (Direct Memory Access) features to support a broad range of fast peripherals. • Highly modular architecture and flexible bus structure to provide effective methods of integrating application-specific peripherals to produce customer-oriented derivatives. Architecture Overview Handbook 5 V1.1, 2006-02 C166S V2 16-Bit Synthesizable Microcontroller Preface 1.2 Technical Summary Technical features of the C166S V2 architecture include: • 7 stage Instruction Pipeline: – 2-stage Instruction Fetch Pipeline with FIFO (First In First Out) for instruction prefetching – 5-stage Execution Pipeline – Pipeline forwarding that controls data dependencies in hardware • 16 Mbytes total linear address space for code and data (von Neumann architecture) • Multiple, high bandwidth internal busses for data and instructions • Enhanced memory map with extended I/O areas • C16x family compatible on-chip Special Function Register (SFR) area • Fast instruction execution – Most instructions executed in one CPU clock cycle – Fast multiplication (16-bit × 16-bit) in one CPU clock cycle – MAC (Multiply & Accumulate) instructions executed in one CPU clock cycle – Fast background execution of division (32-bit/16-bit) in 21 CPU clock cycles – Zero cycle jump execution • Enhanced boolean bit manipulation facilities • Additional instructions to support HLL (High Level Language) and operating systems • Register-based design with multiple variable register banks – Two additional fast register banks • General Purpose Register (GPR) architecture – 16 GPRs for byte operands – 16 GPRs for integer operands • Overlapping 8-bit and 16-bit registers • Opcode fully upward compatible with C166 family • Variable stack with automatic stack overflow/underflow detection • High performance branch, call and loop processing • “Fast interrupt” and “Fast context switch” features • Peripheral bus (PDBUS+) with bit protection • Flexible PMU (Program Memory Unit) and DMU (Data Management Unit) with cache capabilities Architecture Overview Handbook 6 V1.1, 2006-02 C166S V2 16-Bit Synthesizable Microcontroller Preface 1.3 Target Applications The C166 architecture is firmly established in a diverse range of real-time embedded control applications. Optimization of the architecture for high instruction throughput and minimum response time to external stimuli (such as interrupts), has resulted in the core being employed in a wide variety of different application areas. These include: Automotive Telecom / Datacom • Engine Management • Communications Boards (LAN) • Transmission Control • Modems • ABS / ASK • PBX • Active Suspension • Mobile Communications Industrial Control EDP • Robotics • Hard Disk Drives • PLCs • Tape Drives • Servo-Drives • Printers • Motor-Control • Scanners • Power-Inverters • Digital Copiers • Machine-Tool Control (CNC) • FAX Machines Consumer • DVD / CD-Rom • TV / Monitor • VCR / Satellite Receiver • Set Top Box • Games • Video Surveillance Architecture Overview Handbook 7 V1.1, 2006-02 C166S V2 16-Bit Synthesizable Microcontroller System Components 2 System Components C166S V2 System C166S V2 Core Data 16 Memory up to Program Program 24 Kbytes 64 64 Memory Memory Up to 3 Kbytes SRAM C166S V2 CPU up to Unit DPRAM 4 Mbytes (PMU) Data Management Break Injection Trace Unit Interface Interface Interface (DMU) Interrupt Controller WDT PLL & SCU CGU Peripheral Event Controller (PEC) OSC High Speed System Bus 16 PDBUS+ 16 OCDS EBC . JTAG Config. Block 1 2
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