DOCSLIB.ORG

C166sv2 Architecture Overview Handbook

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
C166sv2 Architecture Overview Handbook Architecture Overview Handbook, V1.1, Feb. 2006 C166S V2 16-Bit Synthesizable Microcontroller Microcontrollers Never stop thinking. Edition 2006-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2006. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Architecture Overview Handbook, V1.1, Feb. 2006 C166S V2 16-Bit Synthesizable Microcontroller Microcontrollers Never stop thinking. C166S V2 Architecture Overview Handbook Revision History: 2006-02 V1.1 Previous Version: none Page Subjects (major changes since last revision) Reissue. Updated Instruction Set Summary C166® is a registered trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] C166S V2 16-Bit Synthesizable Microcontroller 1Preface . 4 1.1 Overview . 5 1.2 Technical Summary . 6 1.3 Target Applications . 7 2 System Components . 8 3 Central Processing Unit (CPU) . 12 3.1 Overview . 12 3.2 CPU Special Function Registers (SFRs) . 14 3.3 Instruction Fetch Unit (IFU) & Program Flow Control . 15 3.4 Code Addressing via Code Segment & Instruction Pointers . 16 3.5 General Purpose Registers (GPR) . 17 3.6 Context Switch . 19 3.7 System Stack . 19 3.8 Data & DSP Addressing . 20 4 Data Processing . 21 4.1 Data Types . 21 4.2 Constants . 22 4.3 16-bit Add/Subtract, Barrel Shifter & Logic Unit . 23 4.4 Bit Manipulation Unit . 23 4.5 Multiply & Divide Unit . 24 4.6 Program Status Word (PSW) . 25 4.7 Parallel Data Processing . 25 5 Memory Organization . 27 5.1 SFR Notes . 27 6 Instruction Pipeline . 28 6.1 Injected Instructions . 30 7 Interrupt & Exception Handling . 31 7.1 Peripheral Event Controller (PEC) . 32 7.2 Priority, Arbitration & Structure . 33 8 External Bus Controller (EBC) . 34 9 Instruction Set Summary . 35 9.1 Instruction Mnemonics . 35 9.2 Instruction Opcodes . 49 Architecture Overview Handbook 3 V1.1, 2006-02 C166S V2 16-Bit Synthesizable Microcontroller Preface 1 Preface This document has been produced for engineering managers and hardware/software engineers, to provide an overview of the C166S V2 architecture. The C166S is the synthesizable version of the 16-bit C166 microcontroller family from Infineon, one of the world’s most successful 16-bit architectures. It is designed to meet the high performance requirements of real-time embedded control applications. 16-bit microcontrollers remain a strong force in the microprocessor market, providing a compact, cost-competitive, high-performance alternative to the 32-bit architecture world. Further information and documentation on the C166 product line (including the complete C166S V2 User’s Manual), can be found on the Internet at: http://www.infineon.com/xc166-family Alternatively, contact your nearest Infineon Sales office to request more information. Architecture Overview Handbook 4 V1.1, 2006-02 C166S V2 16-Bit Synthesizable Microcontroller Preface 1.1 Overview C166S V2 is the latest member of the C166 generation of microcontroller cores, combining high performance with enhanced modular architecture. With its impressive DSP performance and advanced interrupt handling features, the C166S V2 architecture has been developed to provide a simple and straightforward migration from existing C16x based applications. The C166S V2 inherits the successful hardware and software system architecture concepts established in the C16x 16-bit microcontroller families, while C166 code compatibility enables re-use of existing code to dramatically reduce the time-to-market for new product development. The C166S V2 core is strategically placed for contemporary and emerging markets dealing with performance-hungry, real-time applications. Features include: • High CPU performance - Single clock cycle execution doubles the performance at the same CPU frequency (relative to the performance of the C166). • Built-in advanced MAC (Multiply & Accumulate) unit dramatically increases DSP performance. • High Internal Program Memory bandwidth and use of the Instruction Fetch Pipeline to significantly improve program flow regularity and optimize fetches into the Execution Pipeline. • Sophisticated Data Memory structure and multiple high-speed data buses, providing transparent data access (0 cycles) and broad bandwidth for efficient DSP processing. • Advanced exceptions handling block with multi-stage arbitration capability, to yield dramatic interrupt performance with extremely small latency. • Upgraded PEC (Peripheral Event Controller) supporting efficient and flexible DMA (Direct Memory Access) features to support a broad range of fast peripherals. • Highly modular architecture and flexible bus structure to provide effective methods of integrating application-specific peripherals to produce customer-oriented derivatives. Architecture Overview Handbook 5 V1.1, 2006-02 C166S V2 16-Bit Synthesizable Microcontroller Preface 1.2 Technical Summary Technical features of the C166S V2 architecture include: • 7 stage Instruction Pipeline: – 2-stage Instruction Fetch Pipeline with FIFO (First In First Out) for instruction prefetching – 5-stage Execution Pipeline – Pipeline forwarding that controls data dependencies in hardware • 16 Mbytes total linear address space for code and data (von Neumann architecture) • Multiple, high bandwidth internal busses for data and instructions • Enhanced memory map with extended I/O areas • C16x family compatible on-chip Special Function Register (SFR) area • Fast instruction execution – Most instructions executed in one CPU clock cycle – Fast multiplication (16-bit × 16-bit) in one CPU clock cycle – MAC (Multiply & Accumulate) instructions executed in one CPU clock cycle – Fast background execution of division (32-bit/16-bit) in 21 CPU clock cycles – Zero cycle jump execution • Enhanced boolean bit manipulation facilities • Additional instructions to support HLL (High Level Language) and operating systems • Register-based design with multiple variable register banks – Two additional fast register banks • General Purpose Register (GPR) architecture – 16 GPRs for byte operands – 16 GPRs for integer operands • Overlapping 8-bit and 16-bit registers • Opcode fully upward compatible with C166 family • Variable stack with automatic stack overflow/underflow detection • High performance branch, call and loop processing • “Fast interrupt” and “Fast context switch” features • Peripheral bus (PDBUS+) with bit protection • Flexible PMU (Program Memory Unit) and DMU (Data Management Unit) with cache capabilities Architecture Overview Handbook 6 V1.1, 2006-02 C166S V2 16-Bit Synthesizable Microcontroller Preface 1.3 Target Applications The C166 architecture is firmly established in a diverse range of real-time embedded control applications. Optimization of the architecture for high instruction throughput and minimum response time to external stimuli (such as interrupts), has resulted in the core being employed in a wide variety of different application areas. These include: Automotive Telecom / Datacom • Engine Management • Communications Boards (LAN) • Transmission Control • Modems • ABS / ASK • PBX • Active Suspension • Mobile Communications Industrial Control EDP • Robotics • Hard Disk Drives • PLCs • Tape Drives • Servo-Drives • Printers • Motor-Control • Scanners • Power-Inverters • Digital Copiers • Machine-Tool Control (CNC) • FAX Machines Consumer • DVD / CD-Rom • TV / Monitor • VCR / Satellite Receiver • Set Top Box • Games • Video Surveillance Architecture Overview Handbook 7 V1.1, 2006-02 C166S V2 16-Bit Synthesizable Microcontroller System Components 2 System Components C166S V2 System C166S V2 Core Data 16 Memory up to Program Program 24 Kbytes 64 64 Memory Memory Up to 3 Kbytes SRAM C166S V2 CPU up to Unit DPRAM 4 Mbytes (PMU) Data Management Break Injection Trace Unit Interface Interface Interface (DMU) Interrupt Controller WDT PLL & SCU CGU Peripheral Event Controller (PEC) OSC High Speed System Bus 16 PDBUS+ 16 OCDS EBC . JTAG Config. Block 1 2
Load more

Recommended publications
  • AMD Athlon™ Processor X86 Code Optimization Guide
    AMD AthlonTM Processor x86 Code Optimization Guide © 2000 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other applica- tion in which the failure of AMD’s product could create a situation where per- sonal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD logo, AMD Athlon, K6, 3DNow!, and combinations thereof, AMD-751, K86, and Super7 are trademarks, and AMD-K6 is a registered trademark of Advanced Micro Devices, Inc. Microsoft, Windows, and Windows NT are registered trademarks of Microsoft Corporation.
    [Show full text]
  • Benchmark Evaluations of Modern Multi Processor Vlsi Ds Pm Ps
    1220 Session 1220 Benchmark Evaluations of Modern Multi-Processor VLSI DSPµPs Aaron L. Robinson and Fred O. Simons, Jr. High-Performance Computing and Simulation (HCS) Research Laboratory Electrical Engineering Department Florida A&M University and Florida State University Tallahassee, FL 32316-2175 Abstract - The authors continue their tradition of presenting technical reviews and performance comparisons of the newest multi-processor VLSI DSPµPs with the intention of providing concise focused analyses designed to help established or aspiring DSP analysts evaluate the applicability of new DSP technology to their specific applications. As in the past, the Analog Devices SHARCTM and Texas Instruments TMS320C80 families of DSPµPs will be the focus of our presentation because these manufacturers continue to push the envelop of new DSPµPs (Digital Signal Processing microProcessors) development. However, in addition to the standard performance analyses and benchmark evaluations, the authors will present a new image-processing bench marking technique designed specifically for evaluating new DSPµP image processing capabilities. 1. Introduction The combination of constantly evolving DSP algorithm development and continually advancing DSPuP hardware have formed the basis for an exponential growth in DSP applications. The increased market demand for these applications and their required hardware has resulted in the production of DSPuPs with very powerful components capable of performing a wide range of complicated operations. Due to the complicated architectures of these new processors, it would be time consuming for even the experienced DSP analysts to review and evaluate these new DSPuPs. Furthermore, the inexperienced DSP analysts would find it even more time consuming, and possibly very difficult to appreciate the significance and opportunities for these new components.
    [Show full text]
  • (12) Patent Application Publication (10) Pub. No.: US 2011/0231717 A1 HUR Et Al
    US 20110231717A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2011/0231717 A1 HUR et al. (43) Pub. Date: Sep. 22, 2011 (54) SEMICONDUCTOR MEMORY DEVICE Publication Classification (76) Inventors: Hwang HUR, Kyoungki-do (KR): ( 51) Int. Cl. Chang-Ho Do, Kyoungki-do (KR): C. % CR Jae-Bum Ko, Kyoungki-do (KR); ( .01) Jin-Il Chung, Kyoungki-do (KR) (21) Appl. N 13A149,683 (52) U.S. Cl. ................................. 714/718; 714/E11.145 ppl. No.: 9 (22)22) FileFiled: Mavay 31,51, 2011 (57) ABSTRACT Related U.S. Application Data Semiconductor memory device includes a cell array includ (62) Division of application No. 12/154,870, filed on May ing a plurality of unit cells; and a test circuit configured to 28, 2008, now Pat. No. 7,979,758. perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a (30) Foreign Application Priority Data write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a Feb. 29, 2008 (KR) ............................. 2008-OO18761 wafer-level. O 2 FAD MoDE PE, FRS PWD PADX8 GENERATOR EAELER PEC 3. PD) PWDC CRECKCCES CKCKB RASCASECSCE SISTE CLOCKBUFFER CEE e EST CLK BSI RASCASECSCKE WREFB ESTE s ACTF 32 P 8:W 4. 38t.A 3. se. A(2) FIRST REFRESH AKE13A2) REFIREFA CONTROR ROWANC RSBSAApp.12BS ARS BA255612.ESE E L - ww.i. 33 EE 3. PE PWDA RAE7(3) ECS issi: OLREFB SECOND LAK:2) BSDT DATABUFFERG08 EABLER REFIREFA SECON REFRESH BSE Y ADDRC CONTROLLER BST YEADDK)) PWS Testaposs WKB811-12 BAADDICBAAD BSYBRST (88.11:12) "Of BST CLK 380 3.
    [Show full text]
  • Computer Architecture Out-Of-Order Execution
    Computer Architecture Out-of-order Execution By Yoav Etsion With acknowledgement to Dan Tsafrir, Avi Mendelson, Lihu Rappoport, and Adi Yoaz 1 Computer Architecture 2013– Out-of-Order Execution The need for speed: Superscalar • Remember our goal: minimize CPU Time CPU Time = duration of clock cycle × CPI × IC • So far we have learned that in order to Minimize clock cycle ⇒ add more pipe stages Minimize CPI ⇒ utilize pipeline Minimize IC ⇒ change/improve the architecture • Why not make the pipeline deeper and deeper? Beyond some point, adding more pipe stages doesn’t help, because Control/data hazards increase, and become costlier • (Recall that in a pipelined CPU, CPI=1 only w/o hazards) • So what can we do next? Reduce the CPI by utilizing ILP (instruction level parallelism) We will need to duplicate HW for this purpose… 2 Computer Architecture 2013– Out-of-Order Execution A simple superscalar CPU • Duplicates the pipeline to accommodate ILP (IPC > 1) ILP=instruction-level parallelism • Note that duplicating HW in just one pipe stage doesn’t help e.g., when having 2 ALUs, the bottleneck moves to other stages IF ID EXE MEM WB • Conclusion: Getting IPC > 1 requires to fetch/decode/exe/retire >1 instruction per clock: IF ID EXE MEM WB 3 Computer Architecture 2013– Out-of-Order Execution Example: Pentium Processor • Pentium fetches & decodes 2 instructions per cycle • Before register file read, decide on pairing Can the two instructions be executed in parallel? (yes/no) u-pipe IF ID v-pipe • Pairing decision is based… On data
    [Show full text]
  • Coverstory by Robert Cravotta, Technical Editor
    coverstory By Robert Cravotta, Technical Editor u WELCOME to the 31st annual EDN Microprocessor/Microcontroller Di- rectory. The number of companies and devices the directory lists continues to grow and change. The size of this year’s table of devices has grown more than NEW PROCESSOR OFFERINGS 25% from last year’s. Also, despite the fact that a number of companies have disappeared from the list, the number of companies participating in this year’s CONTINUE TO INCLUDE directory has still grown by 10%. So what? Should this growth and change in the companies and devices the directory lists mean anything to you? TARGETED, INTEGRATED One thing to note is that this year’s directory has experienced more compa- ny and product-line changes than the previous few years. One significant type PERIPHERAL SETS THAT SPAN of change is that more companies are publicly offering software-programma- ble processors. To clarify this fact, not every company that sells processor prod- ALL ARCHITECTURE SIZES. ucts decides to participate in the directory. One reason for not participating is that the companies are selling their processors only to specific customers and are not yet publicly offering those products. Some of the new companies par- ticipating in this year’s directory have recently begun making their processors available to the engineering public. Another type of change occurs when a company acquires another company or another company’s product line. Some of the acquired product lines are no longer available in their current form, such as the MediaQ processors that Nvidia acquired or the Triscend products that Arm acquired.
    [Show full text]
  • Thread Scheduling in Multi-Core Operating Systems Redha Gouicem
    Thread Scheduling in Multi-core Operating Systems Redha Gouicem To cite this version: Redha Gouicem. Thread Scheduling in Multi-core Operating Systems. Computer Science [cs]. Sor- bonne Université, 2020. English. tel-02977242 HAL Id: tel-02977242 https://hal.archives-ouvertes.fr/tel-02977242 Submitted on 24 Oct 2020 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Ph.D thesis in Computer Science Thread Scheduling in Multi-core Operating Systems How to Understand, Improve and Fix your Scheduler Redha GOUICEM Sorbonne Université Laboratoire d’Informatique de Paris 6 Inria Whisper Team PH.D.DEFENSE: 23 October 2020, Paris, France JURYMEMBERS: Mr. Pascal Felber, Full Professor, Université de Neuchâtel Reviewer Mr. Vivien Quéma, Full Professor, Grenoble INP (ENSIMAG) Reviewer Mr. Rachid Guerraoui, Full Professor, École Polytechnique Fédérale de Lausanne Examiner Ms. Karine Heydemann, Associate Professor, Sorbonne Université Examiner Mr. Etienne Rivière, Full Professor, University of Louvain Examiner Mr. Gilles Muller, Senior Research Scientist, Inria Advisor Mr. Julien Sopena, Associate Professor, Sorbonne Université Advisor ABSTRACT In this thesis, we address the problem of schedulers for multi-core architectures from several perspectives: design (simplicity and correct- ness), performance improvement and the development of application- specific schedulers.
    [Show full text]
  • Errata Sheet NG For
    16/32-Bit Architecture XC27x5X Derivatives 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family / Base Line Errata Sheet V1.5 2013-02 Microcontrollers Edition 2013-02 Published by Infineon Technologies AG 81726 Munich, Germany © 2013 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
    [Show full text]
  • Reconfigurable Accelerators in the World of General-Purpose Computing
    Reconfigurable Accelerators in the World of General-Purpose Computing Dissertation A thesis submitted to the Faculty of Electrical Engineering, Computer Science and Mathematics of Paderborn University in partial fulfillment of the requirements for the degree of Dr. rer. nat. by Tobias Kenter Paderborn, Germany August 26, 2016 Acknowledgments First and foremost, I would like to thank Prof. Dr. Christian Plessl for the advice and support during my research. As particularly helpful, I perceived his ability to communicate suggestions depending on the situation, either through open questions that give room to explore and learn, or through concrete recommendations that help to achieve results more directly. Special thanks go also to Prof. Dr. Marco Platzner for his advice and support. I profited especially from his experience and ability to systematically identify the essence of challenges and solutions. Furthermore, I would like to thank: • Prof. Dr. João M. P. Cardoso, for serving as external reviewer for my dissertation. • Prof. Dr. Friedhelm Meyer auf der Heide and Dr. Matthias Fischer for serving on my oral examination committee. • All colleagues with whom I had the pleasure to work at the PC2 and the Computer Engineering Group, researchers, technical and administrative staff. In a variation to one of our coffee kitchen puns, I’d like to state that research without colleagues is possible, but pointless. However, I’m not sure about the first part. • My long-time office mates Lars Schäfers and Alexander Boschmann for particularly extensive discussions on our research and far beyond. • Gavin Vaz, Heinrich Riebler and Achim Lösch for intensive and productive collabo- ration on joint research interests.
    [Show full text]
  • Dsp56156 Overview
    Freescale Semiconductor, Inc... MOTOROLA 1 - DSP56156 OVERVIEW Freescale Semiconductor,Inc. F o r M o r G e o I SECTION 1 n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , Freescale Semiconductor, Inc. SECTION CONTENTS 1.1 INTRODUCTION . 1-3 1.2 DSP56100 CORE BLOCK DIAGRAM DESCRIPTION . 1-5 1.3 MEMORY ORGANIZATION. 1-12 1.4 EXTERNAL BUS, I/O, AND ON-CHIP PERIPHERALS. 1-12 1.5 OnCE . 1-18 1.6 PROGRAMMING MODEL . 1-18 1.7 INSTRUCTION SET SUMMARY . 1-26 . c n I , r o t c u d n o c i m e S e l a c s e e r F 1 - 2 DSP56156 OVERVIEW MOTOROLA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. INTRODUCTION 1.1 INTRODUCTION This manual is intended to be used with the DSP56100 Family Manual (see Figure 1-1). The DSP56100 Family Manual provides a description of the components of the DSP56100 CORE56100 CORE processor (see Figure 1-2) which is common to all DSP56100 family processors (except for the DSP56116) and includes a detailed descrip- tion of the basic DSP56100 CORE instruction set. The DSP56156 User’s Manual and DSP56166 User’s Manual (see Figure 1-1) provide a brief overview of the core processor and detailed descriptions of the memory and peripherals that are chip specific.
    [Show full text]
  • The Insider's Guide to Planning 166 Family Designs
    Issue B Frequency (MHz) Frequency Rx2 (Ohm) Rx2 CX1 (pF) CX1 CX2 (pF) CX2 CL (pF) CL C0typ (pF) C0typ R1typ (Ohm) R1typ R1max (Ohm) R1max R1max (TK) (Ohm) R1max Pw (uW) Pw Rqmax (Ohm) Rqmax Safety Factor (SF) Factor Safety 40 0 12 15 13 7 10 50 60 420 300 2.11 32 0 12 15 11 5 15 50 60 520 390 3.07 24 180 15 22 12 5 15 50 60 510 390 3.24 20 390 8.2 39 10 4 20 60 80 375 560 3.57 18 390 12 39 14 4 20 60 80 335 540 4.08 16 390 12 47 13 4 20 60 80 353 580 4.24 12 390 15 47 13 4 30 70 90 312 1000 6.50 10 390 15 47 14 3 30 80 100 216 1200 8.14 8 390 15 47 15 3 35 80 100 372 1800 12.50 6 390 15 47 14 3 35 80 140 100 2200 10.66 5 390 22 47 18 3 35 80 140 110 2700 14.17 4 390 22 47 16 4 20 80 150 46 3300 14.08 166 Decoupling capacitor on reverse of board CB Vcc Vss XTAL1 XTAL2 RX CX1 CX2 = Connections to Crystal ground layer { time_for_60_degreesThe = CC15 - time_las Insiders Guide To CC0 = CC15 + (Injector_Firing _Angle time_last_60 = CC15 ; } CC15 Interrupt, cylinder 0 Injector Firing Angle 0 0 Injector 3 6 Opening Time Planning 166 5 7 1 CC0 Interrupt, 11 cylinder 0 injector { CC0 += Inje CC3 Interrupt, 10 8 cylinder 3 injector 4 2 Family Designs jector_Pulse_Width ; } Injector 0 Opening Time 9 3 Injector Firing Angle 3 CC15 Interrupt, cylinder 3 { time_for_60_degrees = CC15 - time_last_6 CC3 = CC15 + (Injector_Firing _Angle * t time_last_60 = CC15 ; } VAREF Analog Voltage Varef input Reference Internal capacitance Resistance Analog Voltage ~ Reference GND Optional Over-Voltage Protection Resistor AN0 Rap Signal Source Internal A/D Convertor Resistance Sample & Hold Capacitor A/D Convertor Analog Signal ~ Voltage Source VAGND 167 GND 166 Designers Guide - Page 1 This guide contains basic information that is useful when doing your first 166 family design.
    [Show full text]
  • Study, Design and Implementation of an Application Specific Instruction Set Processor for a Specific DSP Task
    Study, Design and Implementation of an Application Specific Instruction Set Processor for a Specific DSP Task Master thesis in Electronics Systems at Linköping Institute of Technology by VIVEK PACKIARAJ LiTH-ISY-EX--09/4089--SE Linköping 2008 Study, Design and Implementation of an Application Specific Instruction Set Processor for a Specific DSP Task Master thesis in Electronics Systems at Linköping Institute of Technology by VIVEK PACKIARAJ LiTH-ISY-EX--09/4089--SE Linköping 2008 Supervisor: Kent Palmkvist ISY, Linköping Universitet. Examinator: Kent Palmkvist ISY, Linköping Universitet. Linköping, 4th November, 2008 Presentation Date Department and Division 04 – November - 2008 Department of Electrical Engineering Publishing Date (Electronic version) Electronics Systems Language Type of Publication ISBN (Licentiate thesis) X English Licentiate thesis ISRN LiTH-ISY-EX—09/4089—SE Other (specify below) Degree thesis Thesis C-level X Thesis D-level Title of series (Licentiate thesis) Report Number of Pages Other (specify below) 78 Series number/ISSN (Licentiate thesis) URL, Electronic Version http://www.ep.liu.se Publication Title Study, Design and Implementation of an Application Specific Instruction Set processor for Specific DSP Task Author Vivek Packiaraj Abstract There is a lot of literature already available describing well-structured approach for embedded design and implementation of Application Specific Integrated Processor (ASIP) micro processor core. This concept features hardware structured approach for implementation of processor core from minimal instruction set, encoding standards, hardware mapping, and micro architecture design, coding conventions, RTL,verification and burning into a FPGA. The goal is to design an ASIP processor core (Micro architecture design and RTL) which can perform DSP task, e.g., FIR.
    [Show full text]
  • Characterizing X86 Processors for Industry-Standard Servers: AMD Opteron and Intel Xeon Technology Brief
    Characterizing x86 processors for industry-standard servers: AMD Opteron and Intel Xeon Technology brief Abstract.............................................................................................................................................. 3 Acronyms in text.................................................................................................................................. 3 Introduction......................................................................................................................................... 4 Micro-architectural similarities ............................................................................................................... 5 32-bit operations.............................................................................................................................. 5 64-bit operations.............................................................................................................................. 6 Instruction set and registers............................................................................................................ 6 Operating modes ......................................................................................................................... 7 Memory addressability.................................................................................................................. 8 Micro-architectural differences............................................................................................................... 8
    [Show full text]