Synthesis Techniques for Semi-Custom Dynamically Reconfigurable Superscalar Processors
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Synthesis Techniques for Semi-Custom Dynamically Reconfigurable Superscalar Processors BY Jorge Ortiz Submitted to the graduate degree program in Electrical Engineering and the Graduate Faculty of the University of Kansas in partial fulfillment of the requirements for the degree of Doctor of Philosophy Thesis Committee: Dr. Perry Alexander: Chairperson Dr. David Andrews: Co-Chair Dr. Arvin Agah Dr. Swapan Chakrabarti Dr. James Sterbenz Dr. Kirk McClure Date Defended 2009 Jorge Ortiz The Dissertation Committee for Jorge Ortiz certifies that this is the approved version of the following dissertation: Synthesis Techniques for Semi-Custom Dynamically Reconfigurable Superscalar Processors Committee: Dr. Perry Alexander: Chairperson Dr. David Andrews: Co-Chair Dr. Arvin Agah Dr. Swapan Chakrabarti Dr. James Sterbenz Dr. Kirk McClure Date Approved ii Abstract The accelerated adoption of reconfigurable computing foreshadows a com- putational paradigm shift, aimed at fulfilling the need of customizable yet high-performance flexible hardware. Reconfigurable computing fulfills this need by allowing the physical resources of a chip to be adapted to the com- putational requirements of a specific program, thus achieving higher levels of computing performance. This dissertation evaluates the area requirements for reconfigurable processing, an important yet often disregarded assessment for partial reconfiguration. Common reconfigurable computing approaches today attempt to create cus- tom circuitry in static co-processor accelerators. We instead focused on a new approach that synthesized semi-custom general-purpose processor cores. Each superscalar processor core's execution units can be customized for a particular application, yet the processor retains its standard microproces- sor interface. We analyzed the area consumption for these computational components by studying the synthesis requirements of different processor configurations. This area/performance assessment aids designers when con- straining processing elements in a fixed-size area slot, a requirement for modern partial reconfiguration approaches. Our results provide a more de- terministic evaluation of performance density, hence making the area cost analysis less ambiguous when optimizing dynamic systems for coarse-grained parallelism. The results obtained showed that even though performance density decreases with processor complexity, the additional area still provides a positive contri- bution to the aggregate parallel processing performance. This evaluation of parallel execution density contributes to ongoing efforts in the field of recon- figurable computing by providing a baseline for area/performance trade-offs for partial reconfiguration and multi-processor systems. iii I dedicate this dissertation to the three most important women in my life. To my mother, who shaped me into the man I am today. To my sister, for encouraging me to touch the sky. To my fianc´ee,for sharing her life with me. iv Acknowledgments I would like to thank my committee members for helping me decide on an area of focus for my education through their coursework. A special thanks to Dr. David Andrews, my advisor, for initiating me into research, and allowing me enough freedom to choose a project of my liking. I wish to also thank my labmates for their insights and feedback for the implementation of this project, especially Jason, whose clever solutions saved me weeks of work. v Contents Acceptance Page ii List of Figures x List of Tables xii 1 Introduction 1 1.1 Background . .1 1.2 Reconfigurable Computing . .2 1.3 General-purpose specialized processor . .3 1.4 Processor characteristics . .4 1.5 Processor evaluation . .4 1.6 Toward dynamic run-time reconfiguration . .5 1.7 Dissertation Organization . .5 2 Objectives 6 2.1 Create a configurable superscalar processor . .6 2.2 Processor's synthesis onto reconfigurable fabric . .7 2.3 Monitoring resource use under different configurations . .8 2.4 Evaluating resource use and area expenditure . .8 2.5 Constraining area for slotted synthesis . .9 2.6 Thesis Statement . .9 2.7 Contributions . .9 vi 3 Related Work 11 3.1 Introduction . 11 3.2 ASIC technologies . 12 3.3 Reconfigurable computing background . 13 3.4 Types of reconfigurable computing . 15 3.4.1 Reconfigurable architectures . 15 3.4.1.1 Granularity . 15 3.4.1.2 Structure . 15 3.4.1.3 Reconfigurability . 18 3.4.2 Soft-core processors . 18 3.5 Current State of soft-core processors . 20 3.5.1 Xilinx - MicroBlaze . 21 3.5.2 Altera - Nios II . 22 3.5.3 Lattice - LatticeMico32 . 22 3.5.4 Other soft-core processors . 23 3.6 Instruction-level parallelism . 23 3.7 Hephaestus' approach . 25 3.8 Summary . 28 4 Implementation Methodology 29 4.1 Structure and configuration variables . 29 4.1.1 Rationale . 31 4.1.2 Advantages . 32 4.1.3 Disadvantages . 32 4.2 Instrumentation . 34 4.2.1 Platform Selection . 34 4.2.2 Programming language . 35 4.2.3 Simulation tools . 35 4.2.4 Synthesis tools . 35 4.3 Model implementation . 36 4.3.1 Design Overview . 36 4.3.2 Components . 39 4.3.2.1 Program Counter . 39 4.3.2.2 Instruction Memory . 41 vii 4.3.2.3 Jump Decoder . 43 4.3.2.4 Register Rename . 43 4.3.2.5 Execution Unit Demultiplexer . 48 4.3.2.6 Instruction Dispatch . 49 4.3.2.7 Register File/Future File . 50 4.3.2.8 Reservation Station Manager . 53 4.3.2.9 Execution Unit Manager . 54 4.3.2.10 Common Data Bus . 56 4.3.2.11 ReOrder Buffer . 57 4.3.3 Interconnect . 59 4.3.3.1 Pipeline Control . 59 4.3.3.2 Design Hierarchy . 61 4.3.4 Protocols . 62 4.4 Processor assessment . 62 4.4.1 Instruction set architecture . 63 4.4.2 Software execution . 64 4.4.3 Simulation and debugging . 66 4.4.4 Synthesis . 69 4.4.5 Reconfigurability . 72 4.4.6 Limitations . 72 4.4.7 Complexity . 73 4.5 Summary . 74 5 Evaluation 75 5.1 Area use . 76 5.1.1 Synthesized area . 76 5.1.2 Area constraints . 76 5.1.3 FPGA resources . 83 5.1.4 Area cost metrics . 84 5.2 Performance gains . 86 5.2.1 Clock frequency limitations . 86 5.2.1.1 Register Rename delay . 86 5.2.1.2 Instruction Dispatch delay . 87 5.2.2 Performance metrics . 88 viii 5.3 Performance/area evaluation . 90 5.3.1 Instruction-execution density . 90 5.3.2 Bit execution density . 91 5.3.3 Maximum instruction execution . 91 5.4 Summary . 92 6 Results and Discussion 94 6.1 Performance . 95 6.1.1 Clock frequencies . 95 6.1.2 Logic and routing delays . 96 6.1.3 Instruction Execution Rate . 98 6.1.4 Processor configuration performance . 101 6.2 Area . 104 6.2.1 Costs of Parallelism . 104 6.2.2 Total area . 105 6.2.3 Area Constraints . 109 6.2.4 Area Use Reduction . 110 6.2.5 Synthesis time . 112 6.3 Performance/Area trade offs . 113 6.3.1 Maximum execution rate . 113 6.3.2 Instruction execution rate density . 116 6.3.3 Bit execution density . 118 6.3.4 Secondary Independent Variables . 119 6.4 Summary . 122 7 Conclusions 124 7.1 Limitations and Future Work . 126 7.2 Concluding Remarks . 127 References 128 ix List of Figures 3.1 ASIC vs FPGA Market . 13 3.2 FPGA Dollar Consumption . 14 3.3 Regular Reconfigurable Architectures . 16 3.4 Morphware Terminology . 17 3.5 Microprocessor Use in FPGAs . ..