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Reliability Analysis for AI/ML Hardware

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Reliability Analysis for AI/ML Hardware Special Session: Reliability Analysis for AI/ML Hardware Shamik Kundu1, Kanad Basu1, Mehdi Sadi2, Twisha Titirsha3, Shihao Song3, Anup Das3, Ujjwal Guin2 1Electrical & Computer Engineering, University of Texas at Dallas (fshamik.kundu,[email protected]) 2Electrical & Computer Engineering, Auburn University (fmehdi.sadi, [email protected]) 3Electrical & Computer Engineering, Drexel University (ftt624, s3695, [email protected]) Abstract—Artificial intelligence (AI) and Machine Learning DNN Accelerator Inference (ML) are becoming pervasive in today’s applications, such as autonomous vehicles, healthcare, aerospace, cybersecurity, and DIMM many critical applications. Ensuring the reliability and robustness Input Faulty of the underlying AI/ML hardware becomes our paramount Memory Subsytem importance. In this paper, we explore and evaluate the relia- Output MAC MAC MAC bility of different AI/ML hardware. The first section outlines 1,1 1,2 1,N Label: SPEED the reliability issues in a commercial systolic array-based ML MAC MAC MAC Non-faulty 2,1 2,2 2,N accelerator in the presence of faults engendering from device- Broadcast Output level non-idealities in the DRAM. Next, we quantified the impact Label: STOP of circuit-level faults in the MSB and LSB logic cones of the Accumulate MAC MAC MAC Multiply and Accumulate (MAC) block of the AI accelerator N,1 N,2 N,N on the AI/ML accuracy. Finally, we present two key reliability issues – circuit aging and endurance in emerging neuromorphic Figure 1: Fault manifestation in DRAM leading to misclassi- hardware platforms and present our system-level approach to fication in a mission-critical DNN accelerator. mitigate them. Index Terms—Machine learning, deep learning accelerator, To execute an inference network at the edge, considerable neuromorphic computing, reliability amount of on-chip memory is required to store millions of trained network parameters, input activations and intermediate feature maps. For this purpose, energy restricted DNN accel- I. IMPACT ON DRAM FAULTS ON DNN ACCELERATORS erators utilize Dynamic Random Access Memory (DRAM) as their primary memory subsystem, owing to its low ac- Deep Neural Networks (DNNs), with their ever increasing cess latency and high density architecture. However, due to computing power are gaining momentum over classical ma- various non-idealities associated with the access transistor, chine learning and computer vision algorithms. As a result, the charge stored in the DRAM cells leak away over time, DNNs are being extensively deployed across real-time data engendering bit-level faults throughout the memory. In order driven applications on resource constrained Internet-of-Things to alleviate this, a DRAM is periodically replenished using (IoT) edge devices. Conventional CPU architectures tend to an implicit background refresh operation, which contributes lose out on implementing the computational complexity of to a significant amount of DRAM energy overhead as well state-of-the-art DNNs, which propelled the development of as performance bottleneck in the DNN accelerator. Existing cost and energy efficient application-specific neural network research to alleviate this high refresh rate of DRAMs have accelerators. Both industry and academia responded to this focused on utilizing sub-optimal refresh rates; at the expense emerging community of DNN accelerators by developing sev- of bit-flip faults that are highly dependent on temperature and eral purpose-built inference hardware [1]–[3]. Google’s Tensor variable retention times of each cell in the structure. Such Processing Unit (TPU) is one such accelerator that achieves faults manifested in the structure adversely impact the classifi- 15–30× higher performance and 30–80× higher performance- cation of the network, as demonstrated in Figure 1. Since DNN per-watt over traditional CPUs and GPUs [1]. These custom accelerators are often deployed in high-assurance environ- built DNN accelerators find their application in the domains ments, e.g., self driving vehicles for enhancing the autonomous of computer vision, multimedia processing, graph analytics, driving dynamics, smart sensors in aerial surveillance vehicles and search. With this widespread proliferation of DNNs, like drones, analyzing the impact of these DRAM faults is researchers have focused on performance optimization and highly imperative to avoid catastrophic circumstances. energy-efficiency of such hardware architectures. Even though DNNs are presumed to be resilient against errors by virtue of A. DRAM Basics their inherent fault tolerant capabilities, the threshold of such resiliency can be easily inflicted with bit-level hardware faults, DRAM is the primary choice for main memory in most leading to graceless degradation in classification accuracy of computing platforms ranging from large scale data centers the DNN [4]. to miniature edge devices, due to its high density, longevity, and low cost. The basic element of the 2D-DRAM array is and therefore, skip certain computations during the inference, a DRAM bitcell, which consists of a single capacitor and based on the bitmap encoding of the tensors. In these sparse an access transistor. Depending on the charge in the DRAM accelerators, DRAM reliability is extremely critical, which can cell capacitor, a binary data value is identified as 1 when the lead to subverting the accuracy of the DNN accelerator. capacitor is fully charged, or 0 when it is in a discharged With the extensive deployment of DNN accelerators in a state. However, DRAM capacitor loses charge over time due wide gamut of applications, researchers have analyzed the to various factors predominantly related to the non-ideality impact of faults in various inference hardware. To explore of the access transistor like sub-threshold leakage and gate- the correlation between bit error rate and model accuracy, induced drain leakage. As a result of this, faults in the form permanent faults are injected in the memory elements of a of bit flips start to manifest in the data bits after a certain customized DNN accelerator [17]. The impact of single bit time interval (known as retention time). Therefore, the charge soft errors in the memory on the network performance is needs to be refreshed periodically to preserve the integrity explored in [18], which further proposed a bit-flip resilience of the data. The leakiest cell in the entire DRAM array optimization method for DNN accelerators. Memory faults determines the worst-case retention time, which is usually are induced in the Autonomous Driving System (ADS) of a 64ms in case of commercial DRAM modules. Even though vehicle and the corresponding resilience of different modules high refresh rates are imperative to maintain correctness, they are examined [19]. The susceptibility of the architecture under also adversely impact on the overall energy efficiency and single event upsets on the datapath of an accelerator is performance. Energy efficiency declines due to the periodic analyzed on multiple Convolutional Neural Network (CNN) activation of individual rows as well as the increase in energy models [20]. The safety critical bits in a machine learning consumption due to a longer execution time. system were identified by inducing soft errors in the network Existing research to alleviate the high refresh rate of datapath and evaluating them on eight DNN models across six DRAMs have focused on utilizing sub-optimal refresh rates, datasets [21]. A formal analysis on the impact of faults in the approximating the device performance. One of the earliest datapath of an accelerator has been illustrated using Discrete- work in this domain, Flikker, partitions the application data Time Markov Chain (DTMC) formalism [22]. The intense into critical and non-critical parts, injecting errors in the non- performance penalty in a systolic array-based DNN accelerator critical portion at higher refresh intervals [5]. Sparkk, a DRAM has been demonstrated by inducing manufacturing defects in approximation framework refreshes the most significant bits at the datapath of the accelerator [4], [23], [24]. However, fault a higher refresh rate than the least significant ones [6]. Other characterization of DNN accelerators due to device-level non- DRAM approximation schemes have also been proposed, that idealities in the DRAM cells has not been well explored. reduces DRAM energy consumption at lower refresh rates C. Fault Characterization to Estimate Network Performance [7]–[9]. A quality configurable approximate DRAM has been proposed, that utilizes the concept of critical and non-critical In order to analyze the impact of DRAM faults on the data partitioning to allocate data in multiple quality bins, performance of the DNN accelerator, we implement Multilayer considering the property of variable retention times exhibited Perceptron (MLP) on two different datasets —MNIST and by DRAM cells [10]. However, the impact of the errors on Fashion-MNIST. The detailed network configuration of the high assurance DNN accelerators has not been well explored MLP is provided in Table I. We consider Google’s Tensor at high DRAM refresh intervals, which drives us to analyze Processing Unit as the baseline DNN accelerator, having 8GB the reliability of such high assurance architectures. of dual-channel DDR3 DRAM as the main memory subsys- tem. The trained weights from each network are extracted and B. DNN Accelerator and Its Reliability quantized to 8 bits to be stored in the DRAM, similar to In recent years, DNNs have acquired a meteoric
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