Audio Frequency to Voltage Converter

Erick Rodriguez Hannah Savoldy

May 14, 2020

Abstract This project focuses on producing an output that is proportional to an input audio frequency. To find the highest amplitude frequency in a signal, a series of bandpass filters is used, one of which yields a pure sinusoid of the desired frequency. By comparing the rectified positive, no-offset voltage for each signal, the highest-amplitude signal is isolated via comparator stages which compare and select the highest-amplitude wave of the previous stages. After obtaining the desired theoretically pure sinusoid, it is converted to a DC voltage proportional to its frequency using a differentiator, recti- fiers, and a voltage division circuit. This is then converted into a pulse width modu- lated (PWM) signal using a 555 timer and comparator. The final circuit has bandpass filters corresponding to the notes in one octave, successfully filtering the signal, selecting the dominant frequency, and producing a PWM signal with a proportional duty cycle.

1 Introduction

This circuit takes in an audio frequency with the range of one octave, outputting a PWM that could be used to drive motors at different speeds. A novelty application would be in playing different notes to make wheels spin or a lever to move faster as the note climbs. As motors are able to be implemented in a vast range of applications, so can this circuit. The project can be divided into two separate halves. The ﬁrst half chooses the largest amplitude frequency in an audio signal. The second half takes in the sinusoidal signal of the ﬁrst and converts it into a PWM signal.

1 2 Block Diagram

Figure 1: Overview of System

An audio signal registered via a microphone is split into multiple narrow frequency bands via bandpass ﬁlters tuned across one octave at the range of 261.63Hz - 523.25Hz. These bands undergo 4 stages of magnitude comparisons until the highest amplitude signal is selected. The signal is then split, with one of them differentiated and both rectiﬁed before being divided to produce a voltage proportional to the frequency. This voltage is then compared with a sawtooth wave generated by a 555 timer to create the PWM output.

2 3 Implementation

3.1 Voltage Selector (Hannah Savoldy)

3.1.1 Overview

Figure 2: The entire voltage selector schematic with the input (microphone output) entering on the left and the pure sinusoid exiting on the right.

Calculating an output voltage that is proportional to an input frequency requires a signal with only one frequency. Therefore, before performing calculations on the input signal, a pure sinusoid must ﬁrst be extracted. A microphone output will contain multiple frequencies in the form of noise and note harmonics. The frequency that will control the voltage output should be that of the largest amplitude component.

3 Figure 3: Side-by-side of an unﬁltered microphone output containing noise and harmonics (left) and the ﬁltered signal containing only the highest amplitude component (right)

In music, this is typically the fundamental frequency of a note. To obtain this, a hardware approximation of a Fourier transform must be implemented. The input signal is split into frequency bands by a series of 13 bandpass ﬁlters, where the center frequency of each corresponds to a note in an octave ranging from a C4 (261.63Hz) to a C5 (523.25Hz).

Figure 4: The array of bandpass ﬁlters that the input signal goes through- each ﬁlter rep- resented with the note corresponding to its center frequency.

The output of each ﬁlter is then rectiﬁed and, in pairs of two, passed into a comparator. If the output is high, one transistor will turn on and allow the higher of the two signals to pass through. If the output is low, it will turn on the other transistor after passing through a not gate, allowing the other signal to continue.

4 Figure 5: The building block of bandpass ﬁlter output comparisons

The ﬁnal output will be the highest amplitude ﬁlter output, once all signals have been compared. This is a theoretically pure sinusoid.

An intuitive understanding of this process can be attained through a comparison with a bracket system typically used in sports.

Figure 6: A bracket representation of the voltage comparisons

Each “competition” between ﬁlter outputs results in a “winner.” Then winners are compared with winners until a ﬁnal, highest amplitude sinusoid results.

3.1.2 Building the Filters

Because the frequencies to be ﬁltered are so close in magnitude, with the lowest difference being 15.55Hz, the choice of bandpass ﬁlter should have as narrow a roll-off as possible. The natural choice was a narrow-band Sallen-Key topology.

5 Figure 7: The bandpass ﬁlter used in this circuit

Further choices could be made to make the band as narrow as possible. While maintaining a capacitor value of 220nF for both C1 and C2, increasing R1 and R2 and decreasing R3 decreases the bandwidth. However, making these changes worsens the transient of the ﬁlter output.

Figure 8: The input (green) and output (blue) of a ﬁlter with a very low bandwidth and a long transient (Q = 11).

After some optimizations, a Q value of about 17 was chosen, creating an acceptable balance between low bandwidth and short transient.

6 Figure 9: The final result of the tuned filter (Q = 17) with green input and pink output. (Note that this figure was captured after many more modifications to the circuit, so the slight distortion is not a result of changing the filter)

3.1.3 Choosing a Transistor

The ﬁrst thought was to use pnp and npn transistors to switch on the appropriate signal for negative and positive comparator output voltages, respectively. This would avoid the use of an extra component, a not gate, for every comparison block. However, several nonidealities exist with this approach. Because bipolar transistors are current-controlled, the voltage-based comparator output meant to switch on the base created issues. For example, without a resistor in series with each transistor, they yielded no output. Including a resistor made the transistors function as expected, but it created undesirable power losses that were difﬁcult to make up, due to the unpredictability of the input.

Trying to use MOSFETs instead was the next step. The issue with MOSFETs is that, al- though they are voltage-controlled which would result in more predictable behavior, they have an internal diode, so to pass an AC signal, they need an offset: positive for the n-type and negative for the p-type. This could be accomplished through a simple diode clamper circuit.

Figure 10: The implemented diode clamper circuit. The capacitor and resistor values were chosen so that the time constant would be appropriate for the range of frequencies. The offset could be used to adjust for the 0.7V drop across the diode.

The diode clamping step only needs to be performed once: at the output of every ﬁlter.

7 This offset is then removed before the ﬁnal output through an in-series capacitor.

In practice, different MOSFET models yield sometimes dramatically different results. For example, the output of the MOSFET initially appeared extremely distorted.

Figure 11: The input (red) vs output (green) of the ﬁrst MOSFET model tried, with notice- able distortion on the output

This issue was resolved with another model: the Si7336ADP, probably due to a slew rate limitation. The ﬁnal problem came from the use of both n-type and p-type MOSFETs, which must have different characteristics. Despite best attempts to match them, in a circuit whose goal is to compare amplitudes, using different transistor models for different branches made little sense. In the end, the original design idea involving all the same model MOSFETs and not gates prevailed.

3.1.4 Final Debugging

After the basic building block of the voltage comparison was complete, new challenges arose from putting them all together. Despite the buffer placed before the filters, the large load on the circuit, which involved capacitors in series with each other, required more buffer stages. This was implemented by placing unity-gain operational amplifiers between comparison stages. Unfortunately, this drastically increased the runtime of the simulation, so testing the entire, perfected system was infeasible. However, the somewhat functional schematic with no between-stage buffers, and the final one-stage building block design, are both testable, so the circuit as a whole can be confidently presumed to function.

8 Figure 12: A close shot of the ﬁnal, perfected voltage comparison design with unity gain op amp buffers between stages

3.1.5 Testing

Because the perfected overall design is too slow to effectively test, an analysis can be done on just one voltage comparison between two filters. The filters chosen for testing corre- spond to a C4 (261.63Hz) and a C#4 (277.18Hz) because these are the two closest center frequencies among all the filters.

Figure 13: The setup for testing a single voltage comparison block

The input to the circuit is a .wav sound ﬁle, in which a keyboard alternates between the two notes: a C4 and a C#4.

9 Figure 14: The input used to test the circuit- an audio wave representing a keyboard switching between the center frequencies of both ﬁlters

A general idea of the circuit’s success can be gathered by examining the comparator output relative to each note change. A note change in the audio ﬁle is observed as a sudden increase in amplitude: in the clip shown in ﬁgure 14, there are three note changes.

Figure 15: The output of the comparator (red) relative to the audio ﬁle (green), with changes in comparator output mirroring changes in audio frequency

In figure 15, the comparator output switches approximately 50ms after the note changes, with the exception of the middle note change. The messiness in comparator shift for this instance is most likely due to noise, indicating that the system would benefit from hysteresis. To ensure that the comparator switching accurately corresponds to a different bandpass filter output, a closer examination can be done by comparing the final output to the output of each filter.

10 Figure 16: A zoomed in view of the audio clip representing a C4. The final output (blue) and C filter output (green) match as the higher amplitude wave while the C# filter output (red) is lower and does not get selected

Figure 17: A zoomed in view of the audio clip representing a C#4. The final output (blue) and C# filter output (red) match as the higher amplitude wave while the C filter output (green) is lower and does not get selected

As a ﬁnal check of the overall system, the input microphone signal that is comprised of the fundamental frequency, noise, and harmonics can be compared to the output.

Figure 18: A zoomed in view of the raw audio clip containing a series of sinusoids (green) and the output of the ﬁrst stage (pink)

Figure 18 shows that the messy input wave is ﬁltered and selected to result in a phase- shifted pure sinusoid of the dominant frequency. This output signal now contains only

11 one frequency, so it is ready for the calculations required to convert it into a voltage in the following circuit stage.

3.1.6 Improvements

Only creating the circuit in simulation removed certain pressures: mainly the necessity to optimize for cost. The circuit implemented above was created with no concern for part prices, so the physical implementation of it may be more expensive than is necessary. Fur- ther analyses need to be done to create an effective and reasonably priced solution.

In the circuit itself, implementing hysteresis in the comparator switching would make the system more resilient to input noise, which most microphone output will likely be fraught with. This would involve an operational ampliﬁer receiving the output of the comparator and using a reference voltage to provide an output for the transistors. Doing this would account for slight ﬂuctuations in compared amplitudes when the input frequency shifts, creating a more stable comparator output.

As a ﬁnal note, this circuit only accounts for one octave of range in semitone intervals. By adding more ﬁlters, the circuit could handle more notes and be more robust to different uses.

3.2 Frequency to Voltage Converter (Erick Rodriguez)

3.2.1 Overview

Figure 19: The full frequency to voltage schematic. The input is the voltage selector’s sinusoidal output, and outputs a frequency-dependent PWM signal.

12 With the sinusoid of interest isolated by the voltage selector, it then needs to be converted into a frequency-dependent signal capable of driving devices. It must, however, remain independent of the amplitude of the incoming signal. To accomplish this, the signal is split, and one path is differentiated. This produces two signals, the original Vin, and new signal Vdt. For some amplitude A and frequency of interest ω, the voltage signals are

Vin = Asin(ωt) and Vdt = Aτωcos(ωt). The two signals are then rectiﬁed, since the device will need DC input in order to operate. At this stage each signal is now Vin,dc = kA and

Vdt,dc = kAτω where k is a constant taken on by the signals due to the rectiﬁcation. The last step before conversion to a PWM is then to divide the voltages to obtain Vout = cω with a constant c gained during conversion that is not affected by the input’s frequency. While this derivation is theoretically straightforward, actual implementation proved to be less so.

3.2.2 Differentiation and Rectiﬁcation

In order to obtain the derivative of the signal, an op-amp differentiator ampliﬁer is used.

Figure 20: Op-Amp Differentiator Ampliﬁer and Inverter.

While the traditional differentiator has only an input capacitor and feedback resistor, this operation proved too idealistic and did not generate the desired waveforms. An input resistor and feedback capacitor were added to the op-amp in order to improve the amplifier. An inverter was then added to restore the polarity that was flipped by the differentiator as well as to amplify the signal as its magnitude was reduced. The specific value of amplification (8.6x) was obtained experimental as it was found that adjusting this amplification impacted the delta of final output voltages at different frequencies.

13 (a) Half-Wave Rectiﬁer (b) Rectiﬁer Output Plot

Figure 22: The larger signal in (b) is the rectiﬁed differentiated signal’s, while the smaller is the original input’s.

Figure 21: This ﬁgure shows the input signal and resulting output of the differentiator and inverter. The large green signal is the input, while the small red signal is the differentiator output that is inverted and ampliﬁed to the blue signal. At minimum operating frequency of 200 Hz the differentiated signal is at its smallest and is lower than the input signal’s.

The nonidealities that lead to the complications in the circuit exist primarily in the rectifier. For this circuit a half-wave recifier was used. This generates an output waveform far from the ideal constant DC, instead giving a positive half wave-form. An improvement for future implementation would be to use an RC filtered full-bridge rectifier or more ideal DC-converter such as an IC component.

3.2.3 Analog Division

The division of two input voltages was performed via multiple stages of analog computa- tion using op-amps. The ﬁrst stage is to obtain the natural log of the input. Obtaining this allows us to perform mathematical division by then subtracting the two signals in the next

14 stage. After subtraction the signal is then exponentiated to remove the logarithm, leaving a signal proportion to the division of the two inputs.

Figure 23: Op-Amp Logarithmic Ampliﬁer.

The first stage of the divider is the logarithmic amplifier, implemented as shown above. A Schottky diode BAT54AHM was used due to its low forward current and lower voltage drop. Resistance is kept low as higher resistances led to too small a difference between the final output voltages at different frequencies.

Figure 24: Both paths’ rectiﬁed inputs and resultant outputs are shown.

An issue to notice is that due to the nonideal nature of the reciﬁed inputs, the logarth- mic result only occurs when the waveforms are non-zero. The differentiator shifted the phase of the input, causing it to not align with the original signal. This exacerbates the nonidealities of the output of the subsequent step, the subtractor.

15 Figure 25: Op=Amp Subtractor Ampliﬁer.

The subtractor ampliﬁer’s gain is set to 1.2, a value experimentally determined with the ﬁnal output results. It was seen that a gain of 1 led to too small a range for the voltage, within 1 volt across the operational frequency range of 260 - 520 Hz.

Figure 26: Op-Amp Subtractor Ampliﬁer Plot.

As seen in the plot, the two logarithmic input’s difference in phase resulted in a periodic waveform that nonetheless contains calculation in the overlap between the two inputs.

Figure 27: Exponential Ampliﬁer Stage.

16 The final stage in the analog divider is to remove the logarithmic aspect of the signal using an exponential amplifier. Due to the inverting aspect of the amplifier, it is followed by an inverter that also allows for a gain to boost the magnitude of the signal. The diode and resistance utilized in the exponential amplifier is kept identical to the previous logarithmic amplifiers in order to effectively reverse their performed calculations. Due to the nonidealities of the rectified waveform, a filter is added to the end in order to allow for a cleaner output that is closer in approximation to DC.

Figure 28: Exponential Ampliﬁer stage’s input and resultant ﬁltered output.

3.2.4 Frequency to Voltage Test

The resulting circuit was tested using sinusoidal inputs with frequencies ranging from 260Hz to 520Hz, which is the range of the octave that the voltage selector is designed to operate under.

17 Figure 29: Plot showing circuit’s output for different input signals from 260 to 520 Hz. Signal frequency input increments by 52 Hz for each line.

It can be seen that the circuit has a start-up delay that increases as the frequency increases. The scale of this delay (around 10µs) is small enough to be considered acceptable due the circuits usage in DC applications operating on practical timescales larger than fractions of a second.

3.2.5 Sawtooth wave and Comparator

In order to generate a PWM signal that could be used to drive a device at differing levels of power, the frequency to voltage circuit’s output is input into a comparator with a sawtooth wave generated by a 555 timer. The 555 timer’s conﬁguration is shown below. To note is that V cc is lower than the previously used 15V. If physically implemented the circuit, the voltage can be dropped before entering the 555 such as with a voltage divider.

18 Figure 30: 555 timer setup.

The output is from the capacitor rather than the Output pin in order to produce the sawtooth wave. The frequency of the wave can be expressed by the formula f = (Vcc − 4.7)/(RCV pp) where R is the resistor connected to the PNP transistor’s emitter, C is the capicator creating the sawtooth, and 4.7 is the 1N750 zener diode’s breakdown voltage. The 555 timer conﬁguration used generates a sawtooth wave frequency of around 1kHz. The primary characteristic of importance in the sawtooth is that its V pp be somewhat larger of the voltage range of the frequency to voltage converter’s. This is so that the subsequent PWM will have larger duty cycles as the frequency is increased, and keeping it closer to the range allows the duty cycle to span a larger range of percentages.

Figure 31: Sawtooth overlaid with the voltage outputs at different frequencies

3.2.6 PWM Output

With the sawtooth generator and frequency dependent voltage circuit in place, a comparator is then used to create the PWM signal. A diode follows so that the output wave ﬂattens at 0V rather than the negative supply rail.

19 Figure 32: Final stage of the circuit using a AD549 comparator and diode

The resultant output is a PWM signal whose duty cycle increases with frequency of the original input.

Figure 33: Final stage of the circuit using a AD549 comparator and diode

The different color waves in Figure 33 are of the output for signals ranging from 260 - 520 Hz, with 52 Hz in between.

4 Conclusion

Being entirely virtual, the circuit avoids the issues faced in physical implementation. Costs and efficiency of parts are of no issue, and variations in quality control of parts are not faced. Simulation was made more accurate by utilizing specific parts numbers on compo- nents, but those are still the idealized versions of the parts. The voltage selecting stage of the circuit successfully filters a microphone output signal and selects the highest amplitude component within a one-octave range. The current design could be improved by having more bandpass filters to increase the range over which is operates. Also, successful operation of the circuit depends somewhat on the magnitude of the input signal, so if the input is too large or small, the output will not respond as expected. This could be corrected with an input voltage-normalization. Given an input in the expected frequency and amplitude range, the circuit accomplishes its intended goal.

20 For the second half of the circuit, the mathematics behind the analog division were straightforward, but the non-ideality of the rectification lead to issues in accurately applying the division. The diode and RC filter following the analog divider generated an approximately DC output signal, while subsequent tweaking of the resistances used in the op-amp config- urations created more proportional spacing between the voltages at different frequencies. A further piece of the project that was not implemented was for the PWM output to lead to a buck converter that would create a higher current DC waveform to power more basic devices. As it stands, the PWM signal is still appropriate for motor control. A model of a device that would receive the output from the buck converter was also proposed but not implemented as it would have followed the buck converter. The omission of the buck converter changed the anticipated final output of the circuit from driving appliances at different speed or brightness to motor control, but still falls within the expectation of operation at a frequency-dependent intensity.

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