DOCSLIB.ORG

A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA electronics Article A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA Dam Minh Tung † , Nguyen Van Toan † and Jeong-Gun Lee *,† E-SoC Lab/Smart Computing Lab, Department of Computer Engineering, Hallym University, Chuncheon 24252, Korea; [email protected] (D.M.T.); [email protected] (N.V.T.) * Correspondence: [email protected]; Tel.: +82-33-248-2312 † Current address: 1 Hallymdaehakgil, Chuncheon, Gangwon, Korea. Received: 13 March 2020; Accepted: 6 April 2020; Published: 10 April 2020 Abstract: Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design. Keywords: field-programmable gate array; error detection and correction; PVT variations; timing error resilience; metastability 1. Introduction To develop reliable circuits, a traditional synchronous circuit must have a large timing margin to ensure the correct operation under worst-case timing conditions. It means that an appropriate timing margin is added to a clock period to cover the worst-case circuit propagation delays. However, among most of the circuit operation time, the worst-case timing margin is not fully used since the worst-case rarely happens in practice. Therefore, the worst-case timing margin causes higher throughput loss and lower energy efficiency of a design in typical- or best-case conditions. To minimize the timing margins, many techniques have been proposed for tolerating a timing error that happens in the circuit with the minimal margin. With the help of the techniques, timing margins can be reduced significantly. Generally, the techniques can be categorized into two groups: timing error prediction (TEP), and error detection and correction (EDAC). TEP circuits [1–6] predict a potential error by monitoring data signals. It flags a warning signal whenever the delayed data signals enter an erroneous timing zone that is defined with a clock signal. Then, designer can adjust the supply voltage or clock frequency to ensure correct operation at the edge of predicting a failure. As a result, the output of main flip-flop (FF) always captures the correct data and it does not need any correction. However, in this technique, the timing margin can only be minimized to reserve the enough margin for the correct operation of the main FF. Otherwise, Electronics 2020, 9, 633; doi:10.3390/electronics9040633 www.mdpi.com/journal/electronics Electronics 2020, 9, 633 2 of 12 EDAC techniques [7–15] detect an actual timing error by monitoring critical paths for late arriving data transitions. Then, it uses extra correction circuits to correct the actually happened error. In summary, with a timing error resilience technique, we can have the benefits of higher performance and energy efficiency with some minor area overhead thanks to the reduced timing margin when there is no errors with this margin. However, in the case of having more timing errors, the benefits are gradually reduced because of a correction overhead. The term “performance” in our paper is defined as average-case timing performance. The average timing performance is higher than worst-case timing performance since circuits work with the clock frequency optimized for typical operating condition. The worst cases of Process-Voltage-Temperature operation conditions that can induce errors happen rarely. Generally, most of EDAC circuits are designed in a custom design style and they are implemented in ASIC. They need to optimize their physical designs to satisfy some timing constraint. Moreover, when porting them to a new technology, they cost some efforts for the redesigns on the new technology, leading to the increase of the design times and costs. On the other hand, in an FPGA-based design, it is difficult to implement their designs due to the predefined circuit structures and the un-customized place-and-route (P&R) in FPGAs. For instance, the design of a metastability detector in FPGAs is a critical problem. In addition, the replacement of a traditional FF by a latch in a datapath causes the problem of timing closure in FPGAs. This is because a latch-based design is difficult to meet timing closure with commercial timing tools. Therefore, it is not recommended to replace an FF by a latch in FPGA deigns. In this paper, for variation-tolerant designs on an FPGA, we propose a metastability-immune error detection and correction flip-flop (EDACFF) working with a one-clock-cycle penalty. The metastability problem can be resolved by imposing a proper timing constraint on a design. Our proposed EDACFF is fully supported by standard cells and it is based on the traditional FF. Therefore, it is suitable with a commercial synthesis tool for an FPGA circuit design. Consequently, it can be ported easily to other process technologies with much less design efforts when compared with other timing error resilience techniques. The remainder of this paper is organized as follows. In Section2, we discuss the related works about an EDAC circuit. Next, in Section3, we propose an EDACFF. In this section, the metastability issue is also considered. Section4 shows the testing structure for verifying the functional correction of the proposed EDACFF. Section5 provides the simulation and measurement results from the implementation of the proposed EDACFF on a Spartan-6 FPGA device (XFC6SLX45). Section6 discusses the presented experimental results and possible future work. Finally, Section7 concludes the paper. 2. Related Works In general, traditional EDAC approaches have used ASIC-style implementation. They can be grouped into two categories: (a) FF-based designs and (b) latch-based design. (a) FF-based Designs [7–11]: Razor in [7] detects an error and recomputes computation to recover the correct results at a reduced clock rate with some minor performance degradation. It includes a main FF, a shadow latch, a multiplexer, and a XOR gate. The XOR gate plays the role of comparing the outputs of the main flip-flop that samples data at a rising clock and the shadow latch that is clocked by the delay clock. Since the output of the main FF can be in a metastable state, the output of XOR gate can be in a metastable state too. Therefore, Razor needs a metastability detector at the output of the FF to guarantee a stable output after the detection for a reliable design. In [8], a light-weight error detection register using virtual supply rails occupies small area overhead since it requires only eight extra transistors along with a traditional FF. However, Razor-Lite adopts an instruction replay to correct occurred errors and it leads to the high-performance penalty up to 11 clock cycles per correction. In [9], a low-overhead transition detector (TD) with a 9-transistor current sensing circuit is proposed. TDs are inserted at the half-path points of critical paths and TDs Electronics 2020, 9, 633 3 of 12 predict possible timing errors based on the timing behavior observed at the mid-points of critical paths. So that the timing error in the current clock cycle can be prevented before the real timing violation that can be happened at the endpoint of the critical paths. Thus, it does not need an error correction circuit. However, this design incurs a large area overhead and it needs a significant design effort due to the large number of half-path points of critical paths. In [10], a timing error tolerant (TET) flip-flop was proposed. It consists of a transition detection unit for an error detection and an FF with preset/clear options for error correction. Whenever an error is detected, the output of the FF is preset to “1” or clear to “0” depending on the input value of the FF. However, this design costs area overhead due to the circuits for generating the preset and clear signals. In particular, this design cannot be implemented in an FPGA since a D-FF structure has only one signal line for presetting or clearing in an FPGA. In [11], an EDAC technique is proposed with a new bit flipping FF. Whenever a timing error is detected, it is corrected by complementing the output of the corresponding FF. However, their design requires a metastability detector to detect the metastability that can be occurred at the output of the FF. Their design is prototyped in a MIPS microprocessor core on an FPGA, but the metastability detector is not implemented in their demonstration. (b) Latch-based Designs [12–15]: Razor II [12] is another version of the Razor where a transition detector is used to detect errors. Similar to Razor, it detects timing errors after they actually occur, and it corrects the timing violations using an architectural replay mechanism. A current-based timing error detector was proposed in [13].
Load more

Recommended publications
  • One Shots and Alternatives in Synchronous Digital System Design
    Lawrence Berkeley National Laboratory Lawrence Berkeley National Laboratory Title ONE SHOTS AND ALTERNATIVES IN SYNCHRONOUS DIGITAL SYSTEM DESIGN Permalink https://escholarship.org/uc/item/7tq8t8hn Author Hui, S. Publication Date 1979 Peer reviewed eScholarship.org Powered by the California Digital Library University of California LBL-8722 UC-37 7"> ONE SHOTS AND ALTERNATIVES IN SYNCHRONOUS DIGITAL SYSTEM DESIGN Steve Hui and John B. Meng January 1979 Prepared for the U. S. Department of Enemy under Contract W-7405-ENG-48 UtitAUigim LBL 8722 ONE SHOTS AND ALTERNATIVES IN SYNCHRONOUS DIGITAL SYSTEM DESIGN Steve Hui 8 John B. Meng January 1979 Prepared for the U.S. Department of Energy under Contract W-7405-ENG-48 NOTICE This re poll was pit pa ted is an account or work sponsored by the United States Government. Neither the United Sulci ooi the Umled Slates Depigment of Energy, nor any of their employees, nor any of their contractor*, lube on Ira clou, oi the If employees, nukes any warranty, express or implied, or auumei any legal liability •( response ill ly for (he accuracy, completene or usefulness of my information, anptiatui, product < process disclosed, c; represents thai ill me would no) infringe privately owned right*. !>TV»U;3 LBL 8722 (i) ONE SHOTS AND ALTERNATIVES IN SYNCHRONOUS DIGITAL SYSTEM DESIGN Steve Hui & John D. Meng The one shot or monostable multivibrator is quite often regarded as a "black sheep" in ditiqai integrated circuits. Its distinctions and versatility are well known and do not necessitate mentioning. Some of the potential problems with this black sheep are summarized as follows: 1.
    [Show full text]
  • Reaction Systems and Synchronous Digital Circuits
    molecules Article Reaction Systems and Synchronous Digital Circuits Zeyi Shang 1,2,† , Sergey Verlan 2,† , Ion Petre 3,4 and Gexiang Zhang 1,∗ 1 School of Electrical Engineering, Southwest Jiaotong University, Chengdu 611756, Sichuan, China; [email protected] 2 Laboratoire d’Algorithmique, Complexité et Logique, Université Paris Est Créteil, 94010 Créteil, France; [email protected] 3 Department of Mathematics and Statistics, University of Turku, FI-20014, Turku, Finland; ion.petre@utu.fi 4 National Institute for Research and Development in Biological Sciences, 060031 Bucharest, Romania * Correspondence: [email protected] † These authors contributed equally to this work. Received: 25 March 2019; Accepted: 28 April 2019 ; Published: 21 May 2019 Abstract: A reaction system is a modeling framework for investigating the functioning of the living cell, focused on capturing cause–effect relationships in biochemical environments. Biochemical processes in this framework are seen to interact with each other by producing the ingredients enabling and/or inhibiting other reactions. They can also be influenced by the environment seen as a systematic driver of the processes through the ingredients brought into the cellular environment. In this paper, the first attempt is made to implement reaction systems in the hardware. We first show a tight relation between reaction systems and synchronous digital circuits, generally used for digital electronics design. We describe the algorithms allowing us to translate one model to the other one, while keeping the same behavior and similar size. We also develop a compiler translating a reaction systems description into hardware circuit description using field-programming gate arrays (FPGA) technology, leading to high performance, hardware-based simulations of reaction systems.
    [Show full text]
  • Synchronous Sequential Logic Lecture Notes
    Synchronous Sequential Logic Lecture Notes Uncurrent Antonius contemporized, his creed scythe whinnied collectively. Exoergic Jeffery supernaturalises costively, he swots his granitite very unmercifully. Noel intercalates her demonstrators finely, she vies it conically. Number of synchronous logic circuit theory, lecture notes on this a latch we will gradually be performed by dr. With connected in this textbook url and gates to be equal to a pipeline stalls with our input driven all hype or otherwise, and when virtual page. Instruction as soon, which a link provided for a handy in. Mealy state transition table is synchronous design recipe become stable value to lecture notes was encounterd during four triggering clock pulse to some designers like. We adhere to synchronous and in a nearby data disks contain a single bit line is called as. Combinational propagation slack also known as to combine circuits, because a computer memories and complement systems from a zero! The lecture notes for whole are shown below each cycle. You miss a synchronous sequential circuits from a digital system among all notes was designed by a mealy machine including calculators, lecture content recommendations. The person who need to speed with assembly language programming, it may be used in ways that are you. Characteristic table entry is executed and sophisticated error correction is not permitted and. Describing historical computers as long as we need synchronizers a different. Count down counters only stable, not useful digital computers are competing for laws come up of inputs only use immediate addressingis where this textbook. One bit of every bit binary combinations for register on research you may be executed sequentially in a more costly hardware.
    [Show full text]
  • Unified (A)Synchronous Circuit Development
    Unified (A)Synchronous Circuit Development Philipp Paulweber Jurgen¨ Maier* Jordi Cortadella University of Vienna TU Wien Universitat Politecnica` de Catalunya Faculty of Computer Science Insitute of Computer Engineering Department of Computer Science Vienna, Austria Vienna, Austria Barcelona, Spain [email protected] [email protected] [email protected] Abstract—Despite its development several decades ago and one has to make sure that the communication protocol (request several very beneficial properties asynchronous logic design, and acknowledge) can be fully executed, which sometimes which is data driven and runs as fast as possible in all situations, requires the introduction of additional memory elements [2]. is rarely used nowadays. Reasons are of course its disadvan- tageous properties such as bad testability but also required Thus switching to asynchronous logic means retraining the sophisticated knowledge for designers and missing tools. In this designer which results in high risk for a company. paper we draw a path to tackle the latter points by suggesting Generating asynchronous circuits systematically from Data a tool/way to generate multiple circuit implementations from a single description. We are aiming to convert specifications Flow Graph (DFG)s, i.e., models that show how data is propa- written in various input languages, e.g. C or VHDL, to an unified gated from one operation to the next but neglects the inherent Internal Representation (IR). This IR is composed of building timings, is already possible. For this purpose operations and blocks (semantic vocabulary) specified through the Abstract State special constructs such as merge or join are simply replaced Machine (ASM) based formal method.
    [Show full text]
  • A Globally Wireless Locally Wired Hybrid Clock Distribution Network for Many-Core Systems
    UNIVERSITY OF SOUTHAMPTON A Globally Wireless Locally Wired Hybrid Clock Distribution Network for Many-core Systems by Qian Ding A thesis submitted in partial fulfillment for the degree of Doctor of Philosophy in the Faculty of Engineering and Physical Science School of Electronics and Computer Science February 2021 UNIVERSITY OF SOUTHAMPTON ABSTRACT FACULTY OF ENGINEERING AND PHYSICAL SCIENCES SCHOOL OF ELECTRONICS AND COMPUTER SCIENCE Doctor of Philosophy A Globally Wireless Locally Wired Hybrid Clock Distribution Network for Many-core Systems by Qian Ding Modern ICs are now facing critical issues on generating power-efficient and globally interconnected clock networks, as the clock distribution network might contribute to more than 50% of the overall power consumption. Besides, due to the increasing wire delay caused by shrinking interconnect dimensions, synchronous many-core systems are now facing challenges such as to propagate high-frequency clock signals across the chip with limited power budget. Delivering a clock with low uncertainties across active dies with large chip density has also become one of the major tasks using conventional metallic interconnects. This thesis presents a novel architecture and comprehensive evaluations for a power- efficient and extremely low-delay approach using hybrid wire-wireless clock distribution network (CDN). The proposed hybrid CDN adopts wireless on-chip clock transmitters and receivers for broadcasting the clock signal globally. It then incorporates with conven- tional metal-based clock tree or mesh for local clock distribution. Comparisons between the proposed approach and two baseline architectures, namely a full fan-out tree and a global tree local mesh (TLM) structure, have been presented.
    [Show full text]
  • "Clock Distribution in Synchronous Systems"
    474 CLOCK DISTRIBUTION IN SYNCHRONOUS SYSTEMS CLOCK DISTRIBUTION IN SYNCHRONOUS SYSTEMS In a synchronous digital system, the clock signal is used to define a time reference for the movement of data within that system. Because this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the networks used in their distribution. Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes. Clock signals are typically loaded with the greatest fanout, travel over the greatest dis- tances, and operate at the highest speeds of any signal, either control or data, within the entire system. Because the data signals are provided with a temporal reference by the clock signals, the clock waveforms must be particularly clean and sharp. Furthermore, these clock signals are particularly af- fected by technology scaling, in that long global interconnect lines become much more highly resistive as line dimensions are decreased. This increased line resistance is one of the pri- mary reasons for the increasing significance of clock distribu- tion on synchronous performance. Finally, the control of any differences in the delay of the clock signals can severely limit the maximum performance of the entire system and create catastrophic race conditions in which an incorrect data signal may latch within a register. Most synchronous digital systems consist of cascaded banks of sequential registers with combinatorial logic be- tween each set of registers. The functional requirements of the digital system are satisfied by the logic stages.
    [Show full text]
  • FPGA Designs with Verilog and Systemverilog
    FPGA designs with Verilog and SystemVerilog Meher Krishna Patel Created on : Octorber, 2017 Last updated : May, 2020 More documents are freely available at PythonDSP Table of contents Table of contents i 1 First project 1 1.1 Introduction.................................................1 1.2 Creating the project............................................1 1.3 Digital design using ‘block schematics’..................................1 1.4 Manual pin assignment and compilation.................................8 1.5 Load the design on FPGA.........................................8 1.6 Digital design using ‘Verilog codes’.................................... 10 1.7 Pin assignments using ‘.csv’ file...................................... 11 1.8 Converting the Verilog design to symbol................................. 11 1.9 Convert Block schematic to ‘Verilog code’ and ‘Symbol’........................ 14 1.10 Conclusion................................................. 17 2 Overview 18 2.1 Introduction................................................. 18 2.2 Modeling styles............................................... 18 2.2.1 Continuous assignment statements................................ 18 2.2.2 Comparators using Continuous assignment statements..................... 19 2.2.3 Structural modeling........................................ 22 2.2.4 Procedural assignment statements................................ 24 2.2.5 Mixed modeling.......................................... 25 2.3 Conclusion................................................. 26
    [Show full text]
  • Asynchronous Sequential Circuits
    Chapter 22 Asynchronous Sequential Circuits Asynchronous sequential circuits have state that is not synchronized with a clock. Like the synchronous sequential circuits we have studied up to this point they are realized by adding state feedback to combinational logic that imple- ments a next-state function. Unlike synchronous circuits, the state variables of an asynchronous sequential circuit may change at any point in time. This asynchronous state update – from next state to current state – complicates the design process. We must be concerned with hazards in the next state function, as a momentary glitch may result in an incorrect final state. We must also be concerned with races between state variables on transitions between states whose encodings differ in more than one variable. In this chapter we look at the fundamentals of asynchronous sequential cir- cuits. We start by showing how to analyze combinational logic with feedback by drawing a flow table. The flow table shows us which states are stable, which are transient, and which are oscillatory. We then show how to synthesize an asynchronous circuit from a specification by first writing a flow table and then reducing the flow table to logic equations. We see that state assignment is quite critical for asynchronous sequential machines as it determines when a potential race may occur. We show that some races can be eliminated by introducing transient states. After the introduction of this chapter, we continue our discussion of asyn- chronous circuits in Chapter 23 by looking at latches and flip-flops as examples of asynchronous circuits. 22.1 Flow Table Analysis Recall from Section 14.1 that an asynchronous sequential circuit is formed when a feedback path is placed around combinational logic as shown in Figure 22.1(a).
    [Show full text]
  • Hybrid Synchronous / Asynchronous Design
    HYBRID SYNCHRONOUS / ASYNCHRONOUS DESIGN A Dissertation Presented to the Faculty of the Graduate School of Cornell University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy by Filipp A Akopyan May 2011 c 2011 Filipp A Akopyan ALL RIGHTS RESERVED HYBRID SYNCHRONOUS / ASYNCHRONOUS DESIGN Filipp A Akopyan, Ph.D. Cornell University 2011 In this new era of high-speed and low-power VLSI circuits, the question of which circuit family is best for a given application has become much more relevant. From a designer's point of view, process technology scaling continues to reveal undesirable device behavior. Thus, a designer has to make decisions not only at the micro-architectural scale, but also at a lower, circuit-level scale. However, common circuit families are not sufficient to solve modern engineering problems in many cases. Our goal is to provide resources that will allow designers to select the circuit family that yields the best results in terms of power, area, and performance metrics for each application, with minimal human input. Using our techniques, this choice can be made in a timely manner without in-depth knowledge of each circuit family. We propose an improved hybrid synchronous / asynchronous toolflow that offers significant reduction in the design cycle time and we advise on how our work can be extended to various types of circuit families for any given technology node. We describe tools that we have developed to allow designers to implement their projects using both synchronous and asynchronous circuit families. We also present the cosimulation environment that we have developed to allow designers to run complex digital and analog simulations of various circuits at different levels of abstraction with minimal setup effort.
    [Show full text]
  • Clock and Synchronization
    Clock and Synchronization RTL Hardware Design Chapter 16 1 by P. Chu Outline 1. Why synchronous? 2. Clock distribution network and skew 3. Multiple-clock system 4. Meta-stability and synchronization failure 5. Synchronizer RTL Hardware Design Chapter 16 2 by P. Chu 1. Why synchronous RTL Hardware Design Chapter 16 3 by P. Chu Timing of a combinational digital system • Steady state – Signal reaches a stable value – Modeled by Boolean algebra • Transient period – Signal may fluctuate – No simple model • Propagation delay: time to reach the steady state RTL Hardware Design Chapter 16 4 by P. Chu Timing Hazards • Hazards: the fluctuation occurring during the transient period – Static hazard: glitch when the signal should be stable – Dynamic hazard: a glitch in transition • Due to the multiple converging paths of an output port RTL Hardware Design Chapter 16 5 by P. Chu • E.g., static-hazard (sh=ab’+bc; a=c=1) RTL Hardware Design Chapter 16 6 by P. Chu • E.g., dynamic hazard (a=c=d=1) RTL Hardware Design Chapter 16 7 by P. Chu E.g., Hazard of circuit with closed feedback loop (async seq circuit) RTL Hardware Design Chapter 16 8 by P. Chu RTL Hardware Design Chapter 16 9 by P. Chu Dealing with hazards • In a small number of cases, additional logic can be added to eliminate race (and hazards). RTL Hardware Design Chapter 16 10 by P. Chu • This is not feasible for synthesis • What’s can go wrong: – During logic synthesis, the logic expressions will be rearranged and optimized. – During technology mapping, generic gates will be re-mapped – During placement & routing, wire delays may change – It is bad for testing verification RTL Hardware Design Chapter 16 11 by P.
    [Show full text]
  • Data Transfer Operations in a 68008 Based Microcomputer System
    DATA TRA NSF ER OPERATIONS IN A 68008 BASED MICROCOMPUTER SYSTEM BY ENEFAA GEORGE DOUGLAS Bachelor of Science Oklahoma State University Stillwater, Ok lahoma 1983 Submitted to the Fa culty of the Graduate College of the Oklahoma State University i n par t i a l fulfillment of the requ1rements for the Degree of MASTER OF SCIENCE Ma y, 1985 DATA TRANSFER OPERATIONS IN A 68008 BASED MICROCOMPUTER SYSTEM APPROUED : . i i PREFA CE Understanding the methods of data transfer in a computer system is essential to its maintenance. Different microprocessors transfer data differently. Data is usually transferred between the processor and the system memory or between peripherals and the processor. Three methods of data transfer were examined in this report namely, synchronous data transfer, asynchronous data transfer and a combination of the above two methods. Synchronous data transfer uses the clock to connect sequence and time. Intervals between clock transitions must therefore be such as to permit enough time for the activities planned for that interval. Asynchronous data transfer on the other hand is independent of clock frequency at the system l e vel. Co mmu nication on the system bus -is without a timing signal a llowing any amount of t ime between data bytes or words. To indicate when data has been received or sent, the e xternal dev ice sends a n acknowledgement signal to the processor . Synchronous/Asynchronous mod e of operation allows the synchronous device to be clocke d at its ma x imum operating frequency using an e xternally generated enable CE) clock .
    [Show full text]
  • An Efficient Design Methodology for Complex Sequential Asynchronous Digital Circuits
    San Jose State University SJSU ScholarWorks Master's Theses Master's Theses and Graduate Research Fall 2020 An Efficient Design Methodology for Complex Sequential Asynchronous Digital Circuits Tomasz Chadzynski San Jose State University Follow this and additional works at: https://scholarworks.sjsu.edu/etd_theses Recommended Citation Chadzynski, Tomasz, "An Efficient Design Methodology for Complex Sequential Asynchronous Digital Circuits" (2020). Master's Theses. 5139. DOI: https://doi.org/10.31979/etd.gy4n-x9sz https://scholarworks.sjsu.edu/etd_theses/5139 This Thesis is brought to you for free and open access by the Master's Theses and Graduate Research at SJSU ScholarWorks. It has been accepted for inclusion in Master's Theses by an authorized administrator of SJSU ScholarWorks. For more information, please contact [email protected]. AN EFFICIENT DESIGN METHODOLOGY FOR COMPLEX SEQUENTIAL ASYNCHRONOUS DIGITAL CIRCUITS. A Thesis Presented to The Faculty of the Department of Electrical Engineering San José State University In Partial Fulfillment of the Requirements for the Degree Master of Science by Tomasz Ch ˛adzynski´ December 2020 © 2020 Tomasz Ch ˛adzynski´ ALL RIGHTS RESERVED The Designated Thesis Committee Approves the Thesis Titled AN EFFICIENT DESIGN METHODOLOGY FOR COMPLEX SEQUENTIAL ASYNCHRONOUS DIGITAL CIRCUITS. by Tomasz Ch ˛adzynski´ APPROVED FOR THE DEPARTMENT OF ELECTRICAL ENGINEERING SAN JOSÉ STATE UNIVERSITY December 2020 Tri Caohuu, Ph.D. Department of Electrical Engineering Chang Choo, Ph.D. Department of Electrical Engineering Morris Jones, MSEE Department of Electrical Engineering ABSTRACT AN EFFICIENT DESIGN METHODOLOGY FOR COMPLEX SEQUENTIAL ASYNCHRONOUS DIGITAL CIRCUITS. by Tomasz Ch ˛adzynski´ Asynchronous digital logic as a design alternative offers a smaller circuit area and lower power consumption but suffers from increased complexity and difficulties related to logic hazards and elements synchronization.
    [Show full text]