Architectural Specification

May 1980

© INTEL CORPORATION, 1980. AFN-01488A-01 Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any enors which may appear in this document nor does it make a commitment to update the information contained herein. Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, duplication or disclosure is subject to restrictions stated in Intel's software license, or as defined in ASPR 7-104.9 (a) (9). Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. No part of this document may be copies or reproduced in any form or by any means without the prior wr:itten consent of Intel Corporation. The following are trademarks of Intel Corporation and may only be used to identify Intel products: i Intellec Multimodule ICE iSBC PROMPT ICS Library Manager Promware im MCS RMX Insite Megachassis UPI Intel Micromap J,lScope . Intelevision and the combinations of ICE, iCS, iSBC, MCS or RMX and a numerical suffix. Additional copies of this or other Intel literature may be obtained from: Literature Department Intel Corporation 3065 Bowers Avenue Santa Clara, CA 95051 f·INTEL CORPORATION. 1980 8051 Architectural Specification and Functional Description

8031/8051/8751 SINGLE-COMPONENT 8-BIT MICROCOMPUTER • 803t - Control Oriented CPU With RAM and I/O

• 8051 - An 8031 With Factory Mask- Programmable ROM

• 8751 - An 8031 With User Programmable/Erasable EPROM

• 4K x 8 ROM/EPROM • External Memory Expandable to 128K • 128 x 8 RAM • MCS-48™ Architecture Enhanced with: • Four 8-Bit Ports, 32 I/O Lines • Non-Paged Jumps • Two 16-Bit Timer/Event Counters • Direct Addressing • High-Performance Full-Duplex Serial • Four 8-Register Banks Channel • Stack Depth Up to 128-Bytes • Boolean Processor • Multiply, Divide, Subtract, Compare • Compatible with MCS-80™/MCS-85TM • Most Instructions Execute in 111S Peripherals • 411s Multiply and Divide

The Intel® 8031/8051/8751 is a stand-alone, high-performance single-chip computer fabricated with Intel's highly-reliable +5 Volt, depletion-load, N-Channel, silicon-gate HMOS technology and packaged in a 40-pin DIP. It provides the hardware features, architectural enhancements and new instructions that are necessary to make it a powerful and cost effective controller for applications requiring up to 64K bytes of program memory and / or up to 64K bytes of data storage. The 8051/8751 contains a non-volatile 4K x 8 read only program memory; a volatile 128 x 8 read/write data memory; 32 I/O lines; two 16-bit timer/counters; a five-source, two-priority-Ievel, nested interrupt structure; a serial I/O port for either multi-processor communications, I/O expansion, or full duplex UART; and on-chip oscillator and clock circuits. The 8031 is identical, except that it lacks the program memory. For systems that require extra capability, the 8051 can be expanded using standard TTL compatible memories and the byte oriented MCS-80 and MCS-85 peripherals. The 8051 microcomputer, like its 8048 predecessor, is efficient both as a controller and as an arithmetic processor. The 8051 has extensive facilities for binary and BCD arithmetic and excels in bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions execute in Ills, 40% in 2f1s and mUltiply and divide require only 411S. Among the many instructions added to the standard 8048 instruction set are multiply, divide, subtract and compare.

AST/VPD FREQUENCY REFERENCE COUNTERS P1.0 vee -1 P1,1 PO.o r ,...----'---'---, P1.2 PO.1 I TWO 16-BIT I P1.3 PO.2 ADDRESS 128 BYTES TIMER/EVENT AND DATA MEMORY COUNTERS P1.4 PO.3 }-.OATA BUS I I P1.5 PO.4 P1.6 PO.S I I P1.7 PO.S PSEN I I RST/VPO PO.7 EAtVDO RXD P3.0 ALE/PROG I I TXO P3.1 ALEIPROG INTO P3.2 PSEN I I }-, PROGRAMMABLE P2.7 uin P3.3 64K-SYTE 8US SERIAL PORT I • FULL DUPLEX I TO P3.4 P2.S • EXPANSION CONTROL UART • SYNCHRONOUS T1 P3.5 P2.5 TXO ..... I I .m_ {{ INTERRUPTS SHIFTER \VA P3.6 P2." INTO ...... I RD P3.7 P2.3 INT'...... : I TO-' g ADDRESS L- XTAL2 P2.2 BUS n...... Q. XTAL1 P2.1 }~"'. WA~ INTERRUPTS CONTROL PARALLEL PORTS. SERIAL SERIAL VSS P2.D AD"- ADDRESS/DATA BUS, IN OUT AND 110 PINS Figure 1. Pin Figure 2. Logic Symbol Figure 3. Block Diagram Configuration

Intel Corporation Assumes No Responsibility for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit Patent licenses Are Implied. © INTEL CORPORATION. 1980. AFN-01488A-02 8051 Single-Chip Contents

Microcomputer CHAPTER 1 INTRODUCTION ...... - ...... 1 Architectural Specification 1.0 Abstract...... 1 1.1 Intel's Complete Line of Single-Chip and Microcomputers ...... 1 1.2 Enhancing the 8048 Architecture for Functional Description the 80's ...... 1

CHAPTER 2 ARCHITECTURAL OVERVIEW AND FUNCTIONAL DESCRIPTION ...... 2 2.0 The 8051 Family ...... 2 2.1 Macro-view of the 8051 Architecture ...... 2 2.1: 1 8051 CPU Architecture ...... 2 2.1.2 On-Chip Peripheral Functions...... 3 2.1.2.1 Interrupt System ...... 3 2.1.2.2 I/O Facilities...... 4 2.1.2.2.1 Open Drain I/O Pins. . .. 4 2.1.2.2.2 Quasi-Bidirectional I/O Pins ...... 4 2.1.2.2.3 Microprocessor Bus .. .. 5 2.1.2.3 Timer/Event Counters ...... 6 2.1.2.4 Serial Communications...... 7 2.2 CPU Hardware...... 9 2.2.1 Instruction Decoder...... 9 2.2.2' Program Counter ...... 9 2.2.3 Internal Data Memory ...... 9 2.2.3.1 Internal Data RAM ...... 9 2.2.3.2 Register Banks .•...... 9 2.2.3.3 Special Function Registers ... 9 2.2.3.4 A Register...... 9 2.2.3.5 B Register...... 9 2.2.3.6 PSW Register...... 9 2.2.3.7 Stack Pointer ...... 9 2.2.3.8 Data Pointer ...... 11 2.2.4 Arithmetic Section ...... 11 2.2.5 Program Control Section ...... 11 2.2.6 Oscillator and Timing Circuitry ...... 11 2.2.7 Boolean Processor ...... 11 2.3 Memory Organization ...... 11 2.4 Operand Addressing ...... 12 2.5 Data Manipulation ...... " ...... 14 2.5.1 Data Transfer Operations ...... 14 2.5.2 logic Operations ...... 15 2.5.3 Arithmetic Operations ...... 16 2.6 Control Transfer ...... 17 2.7 I nstruction Set ...... 18 2.7.1 What the Instruction Set Is ...... 18 2.7.2 Organization of the Instruction Set ". 18 2.7.3 Operand Addressing Modes and Associated Operations ...... 21 2.8 Interrupt System ...... 22 2.8.1 External Interrupts ...... 24 2.8.1.1 Transition-Activated Interrupts ...... 24 2.8.1.2 level-Activated Interrupts .... 24 ©Intel Corporation 1980. All rights reserved. 2.9 Ports and I/O Pins ...... 24

AFN-Q1488A·03 CHAPTER 2 ARCHITECTURAL OVERVIEW AND FUNCTIONAL DESCRIPTION (Continued)

2.10 Accessing External Memory ...... 25 2.10.1 Operation of Ports ...... 26 2.10.2 Bus Cycle Timing ...... 26 2.11 TimerlCounter ...... 28 2.11.1 TIC Mode Selection ...... 28 2.11.2 Configuring the TIC Input ...... 28 2.11.3 TIC Operation ...... 29 2.11.4 Reading and Reloading the TIC .... 29 2.12 Serial Channel ...... 29 2.12.1 Serial Port Control Register and Serial Data Registers ...... '.... 31 2.12.2 Operating Modes ...... 31 2.12.2.1 Operating Mode O •....•••. 31 2.12.2.2 Operating Modes 1 through 3 ...... 32 2.12.3 The Serial Frame ...... 32 2.12.4 Transmission Rate Generation ..... 32 2.12.5 UART Message Error Conditions ... 33 2.13 External Interface ...... 33 2.13.1 Processor Reset and Initialization ...... 33 2.13.2 Power Down Operation of Internal RAM ...... 33 2.14 EPROM Programming ...... 34 2.15 The 8051 as an Evolution of the 8048 ...... 34 2.16 Development System and Software Support ...... 34 2.17 8051 Pin Description ...... 35 Table 2.1 Instruction Set Summary ...... 37

AFN-01488A-04 8051 Architectural Specification and Functional Description

1.0 ABSTRACT Now, thanks to the density of HMOS, technology has once again permitted the birth of a microcomputer with The 8031, 8051, and 8751 are the latest additions to Inters performance to leap into new product areas. The 8051 line of single-chip microcomputers. The CPU architec achieves a lOX function/speed improvement over the ture and on-chip peripheral functions of the 8051 are 8048 by packing 60,000 transistors onto a die 230 mils described in this document. A user familiar with the square. MCS-48 family should be able to evaluate and design-in the 8051 using the information included herein. The 8051 family addresses the high-end of the single-chip A detailed description of the hardware required to computer market. It is the highest performance micfo expand the 8051 with more program memory, data computer family in the world and out-performs all micro memory, I/O, specialized peripherals and into multi processors and microcomputers in control oriented processor configurations is described in the 8051 Family applications. It offers an upward compatible growth path User's Manual. for 8048 users with ten times the power of the 8048 as shown in Table 1.1. 1.1 INTEL'S COMPLETE LINE OF SINGLE-CHIP MICROCOMPUTERS • 4X Program Memory (4k Bytes) In 1976 Intel introduced the 8748 microcomputer. This • 2X Data Memory (128 Bytes) marked the first time in history that technology permitted • 2X Register Banks (4 vs. 2) a complete 8-bit computer to be fabricated on a single • 2X Timers (Two 16-bit Timers) silicon die. This single chip can control a limitless variety • New Full-Duplex Serial I/O Port of products ranging from appliances to automobiles to • More I/O Pins (32 vs. 27) computer terminals. • Enhanced MCS-48 Architecture • 21/2 X To 10X Execution Speed Since 1976 Intel has offered products for the full range of • 1.4X Die Size single-chip microcomputer applications by pushing the 8048's architecture in several directions. The 8049 ran nearly twice as fast as the 8748/8048 while doubling the Table 1.1: 8051 Functions/Speed/Cost Relative amount of on-chip program memory and data memory. to 8048 Applications requiring solely external program memory were satisfied with the 8035 and 8039. Cost sensitive and 1.2 ENHANCING THE 8048 ARCHITEC less I/O intensive applications incorporated the 8021 TURE FOR THE 80's which executed a subset of the 8048's instruction set at a The goal of the 8051 is to extend the architecture of the slower speed. Finally, the 8022 integrated an 8-bit A/D industry standard 8048 single-chip microcomputer into converter onto the 8021 die to allow the chip to interface the 80's. This meant increasing the power of the 8048's directly to a world in which most signals are analog. CPU as well as increasing the power, variety and quantity Figure I. I positions these products on a performance of on-chip CPU peripherals. versus die-size curve. The 8048's CPU architecture is ideal for control-oriented 10 applications demanding a low-cost microcomputer because 8051• 9 of its hardware simplicity and resulting silicon efficiency. A simpleALU is used in virtually all operations: arith 8 metic, logic, data moves, bit testing and I/O. Since all 7 data is moved through the ALU this also simplifies the iu il 6 internal data path. The 8048's simple addressing methods c of Register-, Register-Indirect- and Immediate-Address ~ 5 o... ing minimize hardware. The conditional branch logic ...ffi 4 simply concatenates an immediate value to the upper 3 bits of the program counter to economize on silicon, but 2 results in page boundaries. The simplicity of the table 8022. 8048 • look-up circuitry also results in page boundaries. The 8021. user flags and test pins provided for monitoring program 0~------*X----~~1~.5~X------~2~X------.~2.5X and external status in an efficient manner are limited to DIE SIZE -Based on execution speed, memory size and peripheral functions. two of each. This architecture, and the choice of instruc tion encodings that it permits, results In 1,024 byte Figure 1.1. Performance Versus Cost programs of unsurpassed byte efficiency. AFN-01488A-05 1 8051 Architectural Specification and Functional Description

The silicon economic architecture of the 8048 causes ment, prototyping, low-volume production and applica some inconvenience to the programmer but the relatively tions requiring field updates; the 8051 for low-cost, short programs (one or two kilobytes) keep frustration high-volume production and the 8031 for applications levels in check. The 8051 challenge was to maintain soft desiring the flexibility of external Program Memory ware and feature compatibility with the 8048 while which can be easily modified and updated in the field. providing a more powerful microcomputer that is easier to program and use. This allows a designer currently 2.1 MACRO-VIEW OF THE 8051 ARCHI using the 8048 to easily upgrade to the 8051 while pro TECTURE tecting his investment in algorithm development and the knowledge he gained by designing with the 8048. On a single die the 8051 microcomputer combines CPU; non-volatile 4K x 8 read-only program memory; volatile 128 x 8 read/write data memory; 32 I/O lines; two 16-bit Some of the achievements of the 8051 were to extend the timer / event counters; a five-source, two-priority-Ievel, maximum program memory address space to 64K-bytes, nested interrupt structure; serial I/O port for either multi extending on-chip peripheral functions (counters, serial processor communications, I/O expansion, or full duplex ports and parallel ports) to satisfy emerging single-chip UART; and on-chip oscillator and clock circuits. This applications, and enhancing a paged architecture to section will provide an overview of the 8051 by providing make it suitable for the relocatable and re-entrant code a high-level description of its major elements: the CPU generated by modern programming techniques. Op codes architecture and the on-chip functions peripheral to the were reassigned to add new high-power operations and to permit new addressing modes which make the old CPU. The generic term "8051" is also used to refer collec operations more orthogonal. During this process special tively to the 8031, 8051, and 8751. care was taken to provide optimum byte efficiency and maximum execution speed. The 8051 is typically 20% more code efficient than the 8049 for programs longer 2.1.1 8051 CPU Architecture than 2048 bytes. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41 % The 8051 CPU manipulates operands in four memory two-byte and 15% three-byte instructions. With a 12 spaces. These are the 64K-byte Program Memory, 64K byte External Data Memory, 384-byte Internal Data M Hz crystal, 58% of the instructions execute in ltis, 40% Memory and 16-bit Program Counter spaces. The Inter in 2;,Is and multiply and divide require 'only 4tis. nal Data Memory address space is further divided into the 256-byte Internal Data RAM and 128-byte Special 2.0 THE 8051 FAMILY Function Register (SFR) address spaces shown in Figure 2.1. Four Register Banks (each with eight registers), 128 The 8051 is a stand-alone high-performance single-chip addressable bits, and the stack reside in the Internal Data computer intended for use in sophisticated real-time RAM. The stack depth is limited only by the available applications such as instrumentation, industrial control Internal Data RAM and its location is determined by the and intelligent computer peripherals. It provides the 8-bit Stack Pointer. All registers except the Program hardware features, architectural enhancements and new Counter and the four 8-Register Banks reside in the instructions that make it a powerful and cost effective Special Function Register address space. These memory controller for applications requiring up to 64K-bytes of mapped registers include arithmetic registers, pointers, program memory and/ or up to 64K-bytes of data storage. I/O ports, and registers for the interrupt system, timers A Block Diagram is shown in Figure 3. and serial channel. 128 bit locations in the SFR address space are addressable as bits. The 8051 contains 128 bytes The 8031 is a control-oriented CPU without on-chip of Internal Data RAM and 20 SFRs. program memory. It can address 64K-bytes of external Program Memory in addition to 64K-bytes of External The 8051 provides a non-paged Program Memory Data Memory. For systems requiring extra capability, address space to accommodate relocatable code. Con each member of the 8051 family can be expanded using ditional branches are performed relative to the Program standard memories and the byte oriented MCS-80 and Counter. The register-indirect jump permits branching MCS-85 peripherals. The 8051 is an 8031 with the lower relative to a 16-bit base register with an offset provided by 4K-bytes of Program Memory filled with on-chip mask an 8-bit index register. Sixteen-bit jumps and calls permit programmable ROM while the 8751 has 4K-bytes ofUV branching to any location in the contiguous 64K Program light-erasable/ electrically-programmable ROM. Memory address space.

The three pin-compatible versions of this component The 8051 has five methods for addressing source oper reduce development problems to a minimum and provide ands: Register, Direct, Register-Indirect, Immediate, and maximum flexibility. The 8751 is well suited for develop- Base-Register- plus Index-Register- Indirect Addressing.

AFN-01488A-06 2 8051 Architectural Speciffcation ancrFunctionaJ Descrlpfion

64K 64K t EXTERNAl-

OYERl-APPED SPACE

4095 ------INTERNAl-I -"Lr-----A255 I I 25S , 0 1~1.. I 128 ,I I, , , , , , , , J 'l PROGRAM- PROGRAM INTERNAl SPECIAL EXTERNAL COUNTER MEMORY DATA RAM FUNCTION DATA REGISTERS MEMORY INTERNAL DATA- MEMORY

Figure 2.1. 8051 Family Memory Organization

The first three methods can be used for addressing single-byte, 4S two-byte and 17 three-byte instructions. destination operands. Most instructions have a "desti When using a 12 MHz oscillator, 64 instructions execute nation,source" field that specifies the data type, address in IlJs and 4S instructions execute in 4ls. The remaining ing methods and operands involved. For operations instructions (multiply and divide) require only ~s. The other than moves, the destination operand is also a source number of bytes in each instruction and the number of operand. oscillator periods required for execution are listed in the appended 80S I Instruction Set Summary. Registers in the four 8-Register Banks can be accessed through Register, Direct, or Register-Indirect Ad dressing; the 128 bytes of Internal Data RAM through 2.1.2 On-Chip Peripheral Functions Direct or Register-Indirect Addressing; and the Special Thus far only the CPU and memory spaces of the 80S 1 Function Registers through Direct Addressing. External have been described. In addition to the CPU and Data Memory is accessed through Register-Indirect memories, an interrupt system, extensive I/O facilities, Addressing. Look-Up-Tables resident in Program and several peripheral functions are integrated on-chipto Memory can be accessed through Base-Register- plus relieve the CPU of repetitious, complicated or time Index-Register- Indirect Addressing. critical tasks and to permit stringent real-time control of external system interfaces. The extensive 110 facilities The 80S 1 is classified as an 8-bit machine since the include the 110 pins, parallel 110 ports, bidirectional internal ROM, RAM, Special Function Registers, address/data bus and the serial port for I/O expansion. Arithmeticl Logic Unit and external data bus are each 8- The CPU peripheral functions integrated on-chip are the bits wide. The 80S 1 performs operations on bit, nibble, two 16-bit counters and the serial port. All of these work byte and double-byte data types. together to greatly boost system performance.

The 80S1 has extensive facilities for byte transfer, logic, and integer arithmetic operations. It excels at bit handling 2.1.2.1 INTERRUPT SYSTEM since data transfer, logic and conditional branch External events and the real~time-driven on-chip operations· can be performed directly on Boolean peripherals require service by the CPU asynchronous to variables. the execution of any particular section of code. To tie the asynchronous activities of these functions to normal The 80S I's instruction set is an enhancement of the program execution, a sophisticated multiple-source, two~ instruction set familiar to MCS-48 users. It is enhanced to priority-level, nested interrupt system is provided. In allow expansion of on-chip· CPU peripherals and to terrupt response latency ranges from 3IJs to 7IJs when optimize byte efficiency and execution speed. Op codes using a 12 MHz crystal. were reassigned to add new high-power operations and to permit new addressing modes which make the old The 80S I acknowledges interrupt requests from five operations more orthogonal. Efficient use of program sources: Two from external sour.res via the INTO and memory results from an instruction set consisting of 49 INTI pins, one from each of the two internal counters and AFN-Ol488A-D7 3 8051 Architectural Specification and Functional Description

one from the serial I/O port. Each interrupt vectors to a the 8051 as long as the pin is configured as an input. The separate location in Program Memory for its service configuration of the ports is shown on the 8051 Family program. Each of the five sources can be assigned to either Logic Symbol of Figure 2. of two priority levels and can be independently enabled and disabled. Additionally all enabled sources can be 2.1.2.2.1 Open Drain 1/0 Pins globally disabled or enabled. Each external interrupt is programmable as either level- or transition-activated and Each pin of Port 0 can be configured as an open drain is active-low to allow the "wire or-ing" of several interrupt output or as a high impedance input. Resetting the sources .to the input pin. The interrupt system is shown microcomputer programs each pin as an input by writing diagrammatically in Figure 2.2. a one (I) to the pin. Ifa zero (0) is later written to the pin it becomes configured as an output and will continuously sink current. Re-writing the pin to a one (I) will place its 2.1.2.2 1/0 FACILITIES output driver in a high-impedance state and configure the The 8051 has instructions that treat its 32 I/O lines as 32 pin as an input. Each I/O pin of Port 0 can sink two TTL individually addressable bits and as four parallel 8-bit loads. ports addressable as Ports 0, 1,2 and 3. Ports 0,2 and 3 can also assume other functions. Port 0 provides the 2.1.2.2.2 Quasi-Bidirectional 1/0 Pins multiplexed low-order address and data bus used, for expanding the 8051 with standard memories and Ports 1,2 and 3 are quasi-bidirectional buffers. Resetting peripherals. Port 2 provides the high-order address bus the microcomputer programs each pin as an input by when expanding the 8051 with external Program Memory writing a one (l) to the pin. If a zero (0) is later written to or more than 256 bytes of External Data Memory. The the pin it becomes configured as an output and will pins of Port 3 can be configured individually to provide continuously sink current. Any pin that is configured as external interrupt request inputs, counter inputs, the an output will be reconfigured as an input when a one (I) serial port's receiver input and transmitter output, and to is written to the pin. Simultaneous to this reconfiguration generate the control signals used for reading and writing the output driver of the quasi-bidirectional port will External Data Memory. The generation or use of an source current for two oscillator periods. Since current is alternate function on a Port 3 pin is done automatically by sourced only when a bit previously written to a zero (0) is

POLLING HARDWARE

INPUT LEVEL AND INTERRUPT INTERRUPT REQUEST INTERRUPT ENABLE PRIORITY FLAG REGISTERS: REGISTER: REGISTER: SOURCE GLOBAL HIGH PRIORITY ENABLE ENABLE INTERRUPT REQUEST eXTERNAL ..AI'" ------INTO ...... INTRQST0 V INTERNAL ...... AI"'" 1----- TIMER 0 SOURCE VECTOR I.D. EXTERNAL I"'" => tNT1 ...... INT RQST 1 -

INTERNAL I'" TIMER 1 INTERNAL~ ,.. SERIAL r:. LOW PRIORITY PORT R - INTERRUPT r--REQUEST

• FIVE INTERRUPT SOURCES • EACH INTERRUPT CAN BE INDIVIDUALLY ENABLED/DISABLED V • ENABLED INTERRUPTS CAN BE GLOBALLY ENABLED/DISABLED • EACH INTERRUPT CAN BE ASSIGNED TO EITHER OF TWO PRIORITY LEVELS ----- • EACH INTERRUPT VECTORS TO A SEPARATE LOCATION IN PROGRAM MEMORY SOURCE VECTOR • INTERRUPT NESTING TO TWO LEVELS I.D. • EXTERNAL INTERRUPT REQUESTS CAN BE PROGRAMMED TO BE LEVEL- OR ~ TRANSITION-ACTIVATED

Figure 2.2. 8051 Interrupt System

AFN-01488A-08 4 8051 Architectural Specification and Functional Description

updated to a one (1), a pin programmed as an input will The ALE signal is provided for strobing the address into not source current into the TTL gate that is driving it if the an external latch. The program store enable (PSEN) pin is later written with another one (1). Since the quasi signal is provided for enabling an external memory device bidirectional output driver sources current for only two to Port 0 during a read from the Program Memory oscillator periods, an internal pullup resistor of ap address space. When the MOVX instruction is executed proximately 20K- to 4OK-ohms is provided to hold the Port 3 automatically generates the read (RD) signal for external driver's loading at a TTL high level. Ports 1, 2 enabling an External Data Memory device to Port 0 or and 3 can sink/ source one TTL load. generates the write (WR) signal for strobing the external memory device with the data emitted by Port O. Port 0 2.1.2.2.3 Microprocessor Bus emits the address and data to the external memory A microprocessor bus is provided to permit the 80S 1 to through a push/ pull driver that can sink/ source two TTL solve a wide range of problems and to allow the upward loads. At the end of the read/write bus cycle Port 0 is growth of user products. This multiplexed address and automatically reprogrammed to its high impedance state data bus provides an interface compatible with standard and Port 2 is returned to the state it had prior to the bus memories, MCS-80 peripherals and the MCS-8S cycle. The 80S 1 generates the address, data and control memories that include on-chip programmable I/O ports signals needed by memory and I/O devices in a manner and timing functions. These are summarized in the 80S 1 that minimize the requirements placed on external Microcomputer Expansion Components chart of Figure program and data memories. At 12 MHz, the Program 2.3. Memory cycle time is SOOns and the access times required When accessing external memory the high-order address from stable address and PSEN are approximately 320ns is emitted on Port 2 and the low-order address on Port O. and lSOns respectively. The External Data Memory cycle

Category 1.0. Description Comments

I/O Expander 8 Line I/O Expander (Shift Register) Low Cost I/O Expander Standard EPROMs 2758 I K x 8 450 ns Light Erasable User programmable and erasable. 2716-1 2K x 8 350 ns Light Erasable 2732 4K x 8 450 ns Light Erasable 2732A 4K x 8 250 ns Light Erasable Standard RAMs 2114A IK x 4 100 ns RAM Data memory can be easily expanded 2148 lK x 4 70 ns RAM using standard NMOS RAMs. 2142-2 I K x 4 200 ns RAM

Multiplexed Address/ 8185A I K x 8 300 ns RAM Da.ta RAMs C'" c '"0 Standard I/O 8212 8-Bit Ii 0 Port . Serves as Address Latch or I/O port. eQ, 8282 8-Bit I/O Port 0 8283 8-Bit I/O Port U on 8255A Programmable Peripheral Interface Three 8-bit porgrammable I/O ports. QO Q 8251 A Programmable Communications Serial Communcations Receiver/ QO Interface Transmitter. ell• U ~ Standard Peripherals 8205 I of 8 Binary Decoder MCS-80 and MCS-85 peripheral devices 8286 Bi-directional Bus Driver are compatible with the 8051· allowing ;§'" ; 8287 Bi-directional Bus Driver (Inverting) easy addition of specialized interfaces. eQ, 8253A Programmable Interval Timer Future MCS-80/85 devices will also be 0 8279 Programmable Keyboard/ Display compatible. U Interface (128 Keys) 8291 GPIB Talker/Listener 8292 GPIB Controller Universal Peripheral 8041 A ROM Program Memory User programmable to perform custom Interfaces 8741A EPROM Program Memory I/O and control functions. Memories with 8155-2 256 x 8 330 ns RAM on-chip I/O and 8355-2 2K x 8 300 ns ROM Peripheral 8755-2 2K x 8 300 ns EPROM Functions.

Figure 2.3. 8051 Microcomputer Expansion Components AFN-Q1488A-09 5 8051 Architectural Specification and Functional Description

time is IllS and the access times required from stable CRYSTAL address and from read (RD) or write (WR) command are OSCILLATOR approximately 600ns and 250ns respectively.

2.1.2.3 TIMER/EVENT COUNTERS OVERFLOW The 8051 contains two 16-bit counters for measuring time EXTERNAL-.$ ~_--I~ (INTERRUPT SOURCE REQUEST) intervals, measuring pulse widths, counting events and FLAG 0 • 8048 TIMER/COUNTER generating precise, periodic interrupt requests. Each can • 16-BIT TIMER/COUNTER be programmed independently to operate similar to an • 8-BIT AUTO-RELOAD TIMER/COUNTER 8048 8-bit timer with divide by 32 prescaler or 8-bit CRYSTAL counter with divide by 32 prescaler (Mode 0), as a 16-bit time-interval or event counter (Mode I), or as an 8-bit time-interval or event counter with automatic reload °ii~O,.R __~~~~~ __~ OVERFLOW upon overflow (Mode 2). EXTSOEURRNCALE -. 1---4t----I~ (INTERRUPT REQUEST) FLAG 1 Additionally, counter 0 can be programmed to a mode • 8048 TIMER/COUNTER • 16-BIT TIMER/COUNTER that divides it into one 8-bit time-interval or event • 8-BIT AUTO-RELOAD TIMER/COUNTER PULSE TO counter and one 8-bit time-interval counter (Mode 3). SERIAL PORT

When counter 0 is in Mode 3, counter I can be Figure 2.4.A. Timer/Event Counter programmed to any of the three aforementioned modes, Modes 0, 1, and 2 although it cannot set an interrupt request flag or generate an interrupt. This mode is useful because counter I's over CRYSTAL CRYSTAL flow can be used to pulse the serial port's transmission-rate OSCilLATOR OSCILLATOR generator. Along with their multiple operating modes and 16-bit precision, the counters can also handle very high OVERFLOW input frequencies. These range from 0.1 MHzto 1.0 MHz (INTERRUPT EXTERNAL ___$ REQUEST) (for 1.2 MHz to 12 MHz crystal) when programmed for FLAG 1 SOURCE an input that is a division by 12 of the oscillator frequency OVERFLOW L--____--I~ (INTERRUPT and from 0 Hz to an upper limit of 50 KHz to 0.5 MHz REQUEST) (for 1.2 MHz to 12 MHz crystal) when programmed for • 8-BIT TIMER/COUNTER • 8-BIT TIMER FLAG 0 external inputs. Both· internal and external inputs can be CRYSTAL OSCilLATOR gated to the counter by a second external source for directly measuring pulse widths. The counters are started and stopped under software $ control. Each counter sets its interrupt request flag when EX;5~:~~'" it overflows from all ones to aU zeros (or auto-reload value). The operating modes and input sources are • 8048 TIMER/COUNTER • 16-BIT TIMER/COUNTER PULSE TO summarized in Figures 2.4A and 2.4B. The effects of the • 8-BIT AUTO-RELOAD TIMER/COUNTER SERIAL PORT configuration flags and the status flags are shown in Figures 2.5A and 2.5B. Figure 2.4.8. Timer/Event Counter Mode 3

INTERRUPT COUNTER/TIMER RUN REQUEST GATE

COUNTER 0 INTO --~=-~l:'~>-"t"--r-\--J====j~:J MODE 0: 8-BIT TIMER WITH PRESCALER/8-BIT COUNTER WITH PRESCAlER TO------~ >----f MODE 1: 16-BIT TIMER/COUNTER MODE 2: 8-BIT AUTO-RELOAD TIMER/COUNTER MODE 3: 8-BIT TIMER/COUNTER (TlO)

XTAl1

Figure 2.S.A. Timer/Counter 0 Control and Status Flag Circuitry AFN-01488A-l0 6 8051 Architectural Specification and Functional Description

INTERRUPT COUNTERI REQUEST GATE TIMER TIMERI RUN COUNTER • OIN ~ MODE 3 G J- )-

PULSE TO SERIAL Hn PORT COUNTER 1

MODE 0: 8-BIT TIMER WITH PRESCALERI 8-BIT COUNTER WITH PRESCALER- MODE 1: 16-BIT TIMER/COUNTER MODE 2: 8-BIT AUTO-RELOAD TIC MODE 3: PREVENTS INCREMENTING OF TIC 1 J >- r-r- --1"'" ~ INT1 ~r~ :=fJ- T1 -r- - - COUNTER 0 XTAL1 +12 1 ~"' - ~ 8-8ITTIMER ~ (THO)

Figure 2.5.8. Timer/Counter 1 Control and Status Flag Circuitry

• 100r11 Bit Frame r ------:;:R:;:;S;.-TT-;;-----l • Baud Rate Generetlon I INTERRUPT from Oscillator or Timer 1 I I-___-:- __ ~~~~SMIT • Address Frame Recognition I ~-~-----~

I SCON I (SERIAL CONTROL) I CONTROL" I TIMING CIRCUITRY

g:~~~~t.,.OR - ....1..... -:-16 TIMER 1 OVERFLOW RECEIVER ~~ L ______RECEIVE DATA

Figure 2.6. Serial Port~UART Modes 1, 2, and 3

2.1.2.4 SERIAL COMMUNICATIONS The 8051 has a serial I/O port that is useful for serially service the serial link. A block diagram of the serial port is linking peripheral devices as well as multiple805ls shown in Figure 2.6. Methods for linking U ART (univer through standard asynchronous protocols with full sal asynchronous receiver / transmitter) devices are shown duplex operatiori. The serial port also has a synchronous in Figure 2.7 and a method for I/O expansion is shown in mode for expansion of I/O lines using CMOS and TTL Figure 2.8. shift registers. This hardware serial communications interface saves ROM code and permits a much higher The full-duplex serial I/O port provides asynchronous transmission rate than could be achieved through o modes to facilitate communications with standard U ART software. In response to a serial port interrupt request the devices, such as printers and CRT terminals, or com CPU has only to read/write the serial port's buffer to munications with other 8051s in multi-processor systems. AFN-01488A-11 7 8051 Architectural Specification and Functional Description

I .~ ~

I TXD RXD TXD RXD TXD RXD RXD TXD TXD RXD TXD RXD TXD r----- RXD RXD TXD PORT PIN ~. CTS 8051 8051 8051 8051 8051 8051 8051 8251

A. MULTI-80S1 INTERCONNECT-HALF DUPLEX B. MULTI-80S1 INTERCONNECT-FULL DUPLEX C. 8051-8251 INTERFACE

Figure 2.7. UART Interfacing Schemes

The receiver is double buffered to eliminate the overrun that would occur if the CPU failed to respond to the receiver's interrupt before the beginning of the next 8051 frame. Double buffering of the transmitter is not needed since the 8051 can generally maintain the serial link at its DATA CLOCK maximum rate without it. A minor degradation in PORT PIN transmission rate can occur in rare events such as when the servicing of the transmitter has to wait for a lengthy A.1I0INPUT interrupt service program to complete. In asynchronous EXPANSION modes, false start-bit rejection is provided on received frames. For noise rejection a best two-out-of-three vote is 8051 taken on three samples near the center of each received bit. DATA OS CLOCK EN PORT PIN When interfacing with standard UART devices the serial channel can be programmed to a mode (Mode 1) that B. 110 OUTPUT transmits/ receives a ten-bit frame or programmed to a EXPANSION mode (Mode 2 or 3) that transmits/receives an eleven-bit frame as shown in Figure 2 ..9. The frame consists of a start Figure 2.8. I/O Expansion Technique bit, eight or nine data bits and a stop bit. In Modes 1 and 3, the transmission-rate timing circuitry receives a pulse MODE ~~~------~--~--~---'I~ from counter I each time the counter overflows. The TTY , be START 7-BIT DATA PARITY' input to counter 1 can an external source or a division 2 STOP by 12 of the oscillator frequency. The auto-reload mode of the counter provides communication rates of 122 to

31,250 bits per second (including start and stop bits) for a TYPICAL START 7·BIT DATA MARK STOP 12 MHz crystal. In Mode 2 the communication rate is a CRT division by 64 of the oscillator frequency yielding a transmission rate of 187,500 bits per second (including START 8-BIT DATA PARITY STOP start and stop bits) for a 12 MHz crystal.

Distributed processing offers a faster, more powerful 2&3 MULTI START a-BIT DATA system than can be provided by a single CPU processor. PROCESSOR ~~~:I STOP COMMUNICA This results from a hierarchy of interconnected TIONS processors, each with its own memories and 1/ O. In 2&3 multiprocessing, a host 8051 microcomputer controls a START 9-BIT DATA STOP multiplicity of 8051 s configured to operate simultaneous lyon separate portions of the program, each controlling a 1/0 a·BITS j..DATA o EXPANSION portion of the overall process. The interconnected 8051 s ....------' __ ClK reduce the load on the host processor and result in a low cost system of data transmission. This form of distributed Figure 2.9. Typical Frame Formats AFN-01488A-12 8 8051 Architectural Specification and Functional Description

processing is especially effective in systems where controls 2.2.3 Internal Data Memory in a complex process are required at physically separated The 8051 contains a I 28-byte Internal Data RAM (which locations. includes registers R7-RO in e'ach of four Banks), and In Modes 2 and 3 the automatic wake-up of slave twenty memory-mapped Special Functional Registers. processors through interrupt driven address-frame recognition is provided to facilitate interprocessor com 2.2.3.1 INTERNAL DATA RAM munications. The protocol for interprocessor com The Internal Data RAM provides a convenient 128-byte munications is shown in Figure 2.10. scratch pad memory.

1. Slaves -Configure serial port to interrupt CPU if the 2.2.3.2 REGISTER BANKS received ninth data bit is a one (I). There are four 8-Register Banks within the Internal Data 2. Master-Transmit frame containing address in first 8 RAM, each containing registers R7-RO. data bits and set ninth data bit (i.e., ninth data bit designates address frame). 2.2.3.3 SPECIAL FUNCTION REGISTERS 3. Slaves - Serial port interrupts CPU when address frame is received. Interrupt service program The Special Function Registers include arithmetic registers compares received address to its address. (A , B, PSW), pointers (SP, DPH, DPL) and registers The slave which has been addressed recon that provide an interface between the CPU and the figures its serial port to interrupt the CPU on all subsequent transmissions. on-chip peripheral functions. 4. Master-Transmit control frames and data frames (these will be accepted only by the previously 2.2.3.4 A REGISTER addressed slave.) The A register is the accumulator register. ACC is the location of the accumulator in the Internal Data Memory. Figure 2.10. Protocol for Multi-Processor Communications 2.2.3.5 B REGISTER In synchronous mode (Mode 0) the high-speed serial port The B register is dedicated during multiply and divide and provides an efficient, low-cost method of expanding I/O serves as both a source and a destination. During all other lines using standard TTL and CMOS shift registers. The operations the B register is simply another location of serial channel provides a clock output for synchronizing the Internal Data Memory. . the shifting of bits to/from an external register. The data rate is a.division by 12 of the oscillator frequency and is 2.2.3.6 PSW REGISTER I M bits p(:r second at 12 MHz. The carry (CY), auxialiary carry (AC), user flag 0 (FO), register bank select I (RS I), register bank select 0 (RSO), 2.2 CPU HARDWARE overflow (OV) and parity (P) flags reside in the Program Status Word (PSW) Register. These flags are bit This section describes the hardware architecture of the memory-mapped within the byte-memory-mapped PSW. 8051's CPU in detaiL The interrupt system and on-chip The PSW flags record processor status information and functions peripheral to the CPU are described in control the operation of the processor. subsequent sections. A detailed 8051 Functional Block The CY, AC, and OV flags generally reflect the status of Diagram is displayed in Figure 2. II. the latest arithmetic operation. The P flag always reflects the parity of the A register. The carry flag is also a 2.2.1 Instruction Decoder Boolean accumulator for bit operations. Specific details Each program instruction is decoded by the instruction are provided in the "Flag Register Settings" section of decoder. This unit generates the internal signals that 2.7.2. control the functions of each unit within the CPU sec FO is a general purpose flag which is pushed onto the tion. These signals control the sources and destination stack as part of a PSW save. of data, as well as the function of the Arithmetic/Logic The two Register Bank select bits (RS I 'and RSO) deter Unit (ALU). mine which of the four 8-Register Banks is selected.

2.2.2 Program Counter 2.2.3.7 STACK POINTER The I6-bit Program Counter (PC) controls the sequence in The 8-bit Stack Pointer (SP) contains the address at which the instructions stored in program memory are which the last byte was pushed onto the stack. This is executed. It is manipulated with the Control Transfer also the address of the next byte that will be popped. SP instructions listed in section 2.7.2. is updatable under software control.

AFN·01488A-13 9 - ~-~,-~------=----c---: 8051 Architectural Specification and Functional Description

· t1: r-- ~~~U i'.r ri PARITY, I I/t-- I I ~ a: w CY I AC I FO I RS11RSOI OV I Ip Q lr - I~ 0 A U w Q B ROTATE CONTROLP '" a: w IPC w '"a: INTERRUP Q Q - 0 Q IEC CONTROL r- u <:( w a: Q w SBUF ~ ... SERIAL '"w '" PORT I--- '"a: -V aw SCON Q Q 4K ·8 a: <:( TH1 NONE (8031) z >- 0 a: ROM (8051V i= TL1 0 EPROM (87511 U :I z w :l... THO :I ... TIMER :I <:( CONTROL f4 <:( U TLO a: w Cl Q. 0 TMOD a: '" Q. TCON

DPH I'\, DPL V SP ~ '\.7 ~ a: PROGRAM CONTROL w Q 128·8 --- V 0 RAM PCH Uw Q f------PCL REGISTER BANK 3 w'" :) '"a: f------Q REGISTER BANK 2

~ f------CONTROL :I REGISTER BANK 1 <:( f------PLA a: REGISTER BANK 0 CONTROL DRIVERS DRIVERS ENGINE INSTRUCTION VL ~~ i DECODER Iv ~~ I ~"r '" ~ /~ '" '';. • ~ osc & l}, ~ ,/, 7- TIMING ~L J~ rr CIRCUITRY q I I I I I 1 r 1 t + x X E A P ~R V V T T A L S S C S A A / E E D D D T C S PORT PORT2 0 PORT 1 3 PORTO L L V / N / 1 2 D P V D R P o D G

Figure 2.11. 8051 Family Functional Block Diagram

AFN-01488A-14 10 8051 Architectural Specification and Functional Description

2.2.3.8 DATA POINTER On any addressable bit, the Boolean processor can per The 16-bit Data Pointer (DPTR) register is the concatina form the bit operations of set, clear, complement, tion of registers DPH (data pointer's high-order byte) and jump-if-set, jump-if-not-set, j~mp-if-set-then-clear and DPL (data pointer's low-order byte). The DPTR is used in move to/from carry. Between any addressable bit (or its Register-Indire91 Addressing to move Program Memory complement) and the carry flag it can perform the bit constants, to move External Data Memory variables, and operation of logical and or logical or with the result to branch over the 64K Program Memory address space. returned to the carry flag. The bit-manipulation instructions provide optimum code 2.2.4 Arithmetic Section and speed efficiency in "bit-banging" applications such as the control of the 8051's on-chip peripherals. The Boolean The arithmetic section of the processor performs many processor also provides a straightforward means of con data manipulation functions and is comprised of the verting logic equations (like those used in random Arithmetic/Logic Unit (ALU), A register, B register and logic design) directly into software. Complex combina PSW register. torial-logic functions can be resolved without extensive The AL U accepts 8-bit data words from one or two data movement, byte masking and test-and-branch trees. sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arith 2.3 MEMORY ORGANIZATION metic operations of add, subtract, multiply, divide, incre ment, decrement, BCD-decimal-add-adjust and compare In the 8051 family the memory is organized ever three address spaces and the program counter. The memory and .the logic operations of and, or, exclusive-or, spaces shown in Figure 2.1 are the: complement and rotate [right, left, or nibble swap (left four)]. • 16-bit Program Counter • 64K-byte Program Memory address space 2.2.5 'Program Control Section • 64K-byte External Data Memory address space The program control section controls the sequence in • 384-byte Internal Data Memory address space which the instructions stored in program memory are executed. The conditional branch logic enables conditions The 16-bit Program Counter register provides the 8051 internal and external to the processor to cause a change with its 64K addressing capabilities. The Program Counter in the sequence of program execution. allows the user to execute calls and branches to any loca tion within the Program Memory space. There are no 2.2.6 Oscillator and Timing Circuitry instructions that permit program execution to move from the Program Memory space to any of the data memory Timing generation for the 8051 is completely self spaces. contained, except for the frequency reference which can be a crystal or external clock source. The on-board In the 8051 and 8751 the lower 4K of the 64K Program oscillator is a parallel anti-resonant circuit with a Memory address space is filled by internal ROM and frequency range of 1.2 to 12 MHz. The XTAL2 pin is the EPROM, respectively. By trying the EA pin high, the output of a high-gain amplifier, while XT AL I is its input. processor can be forced to fetch from the internal A crystal connected between XT AL I and XT AL2 ROM/EPROM for Program Memory addresses 0 provides the feedback and phase shift required for through 4K. Bus expansion for accessing Program oscillation. The t.2 to 12 MHz range is also accomodated Memory beyond 4K is automatic since external in when an external TTL compatible clock is applied to struction fetches occur automatically when the Program XT AL 1 as the frequency source. Counter increases above 4095. If the EA pin is tied low all Program Memory fetches are from external memory. 2.2.7 Boolean Processor The execution speed of the 8051 is an same regardless of whether fetches are from internal or external Program Although the Boolean processor is an integral part of the Memory. If all program storage is on-chip, byte location 8051's architecture, it may be considered an independent 4095 should be left vacant to prevent an undesired bit processor since it has its own instruction set, its own prefetch from external Program Memory address 4096. accumulator (the carry flag), and its own bit-addressable Certain locations in Program Memory are reserved for RAM and I/O. specific programs. Locations 0000 through 0002 are The bit-manipulation instructions allow the Direct reserved for the initialization program. Following reset, Addressing of 128 bits within the Internal Data RA M the CPU always begins execution at location 0000. and 128 bits within the Special Function Registers. The Locations 0003 through 0042 are reserved for the five Special Function Registers with an address evenly interrupt-request service programs. Each resource that divisable by eighqpO, TCON, PI, SCON, P2, IEC, P3, can request an interrupt requires that its service program IPC, PSW, A. and B) contain Direct Addressable bits. be stored at its reserved location. AFN-01488A-15 11 8051 Architectural Specification and Functional Description

The 64K-byte External Data Memory address space.is Register accessible through Direct Addressing can be automatically accessed when the MOVX instruction is pushed I popped. executed. The Special Function Register address space is 128 to 255. Functionally the Internal Data Memory is the most flex All registers except the Program Counter and the four ible of the address spaces. The Internal Data Memory 8-Register Banks reside here. Memory mapping the space is subdivided into a 256-byte Internal Data RAM Special Function Registers allows them to be accessed as address space and a 128-byte Special Function Register"' easily as internal RAM. As such, they can be operated on address space as shown in Figure 2. 12. by most instructions. In addition, 128 bit locations within SPECIAL the Special Function Register address space can be FUNCTION INTERNAL DATA RAM REGISTERS accessed using Direct Addressing. These bits reside in the ( A ,,------A--, Special Function Register byte locations divisible by

255 255 248 F8H eight. The twenty Special Function Registers are listed 255 FOH in Figure 2. 13. Their mapping in the Special Function E8H EOH Register address space is shown in Figure 2.14. D8H DOH C8H ADDRESS- ARITHMETIC REGISTERS: ABLE COH BITS IN ACCumulator*, B register*, B8H SFRs Program Status Word* BOH (128 BITS) A8H POINTERS: AOH Stack Pointer, Data Pointer (high & low) 98H PARALLEL I/O PORTS: 90H 88H Port 3*, Port 2*, Port 1*, Port 0* 128 135 128 80H INTERRUPT SYSTEM: 128 -~127 Interrupt Priority Control*, Interrupt Enable Control* ADORE 55- 48 TIMERS: ABLE - 127 120 BITS IN Timer MODe, Timer CONtrol*, Timer 1 RAM (high low), Timer 0 (high low) (128 BIT S) 32 7 0 & & R7 BANK 3 SERIAL 1/0 PORT: 24 RO Serial CONtrol*, Serial data BUFfer - R7 BANK 2 16 RD REGISTE RS -< *Bits in these registers are bit addressable R7 BANK 1 8 RO R7 Figure 2.13. Special Function Registers BANKO 0 RO ~ Performing a read from a location of the Internal Data INTERNAL SPECIAL FUNCTION DATA RAM REGISTERS Memory where neither a byte of Internal Data RAM (i.e. RAM addresses 128-255) nor a Special Function Register Figure 2.12. Internal Data Memory exists will access data of indeterminable value. Address Space Architecturally, each-memory space is a linear sequence The Internal Data RAM address space is 0 to 255. Four of 8-bit wide bytes. By Intel convention the storage of 8-Register Banks occupy locations 0 through 31. The multi-byte address and data operands in program and stack can be located anywhere in the Internal Data RAM data memories is least significant byte at the low-order address space. In addition, 128 bit locations of the on-chip address and the most significant byte at the high-order RAM are accessible through Direct Addressing. These address. Within byte X, the most significant bit is repre bits reside in Internal Data RAM at byte locations 32 sented by X.7 while the least significant bit is X.O. Any through 47. Currently locations 0 through 127 of the deviation from these conventions will be explicitly stated Internal Data RAM address space are filled with on-chip in the text. RAM. Locations 128 through 255 may be filled on later products without affecting existing software. 2.4 OPERAND ADDRESSING The stack depth is limited only by the available Internal There are five methods of addressing source operands. Data RAM, thanks to an 8-bit reloadable Stack Pointer. They are Register Addressing, Direct Addressing, The stack is used for storing the Program Counter during Register-Indirect Addressing, Immediate Addressing,and subroutine calls and may be used for passing parameters. Base-Register- plus Index-Register- Indirect Addressing. Any byte of Internal Data RAM or Special Function The first three of these methods can also be used to AFN-01488A-16 12 8051 Architectural Specification and Functional Description

SYMBOLIC BYTE • Register Addressing ADDRESS BIT ADDRESS ADDRESS A. R7-RO ~( \~ -- A, B, C (bit), AB (two bytes), 2481 B (FOH) DPTR (double byte) • Direct Addressing ACC A ~I: (EOH) Lower 128 bytes of Internal Data RAM 231 224 208 'F (DOH) Special Function Registers psw I I 128 bits in subset of Internal Data RAM 215 208 184 IPC 1 I (B8H) address space 184 P3 191 128 bits in subset of Special Function I 1176 (BOH) Register address space 176 168 IEC 183 I (ASH) • Register-Indirect Addressing 1 168 P2 175 Internal Data RAM [@R1, @RO, @SP I (AOH) 160 I160 SFR's 167 CONTAINING (PUSH and POP only)) SBUF (99H) DIRECT Least Significant Nibbles in Internal I 153 ADDRESSABLE SCON 1152 (98H) BITS Data RAM (@R1, @RO) P1 159 152 144 I I (9OH) External Data Memory (@R1, @RO, 151 144 @DPTR) TH1 141 (8DH) THO 140 (8CH) • Immediate Addressing Tl1 139 (8BH) -- Program Memory (tn-code constant) TlO 138 (BAH) TMOD 137 (89H) • Base - Register- plus Index-Register- Indirect TCON 136 (88H) Addressing Program Memory (@ DPTR+A, :~ ~143136 ~: :::: @PC+A) SP 129 (81H) PO 128 (SOH) Figure 2.15. Operand Addressing Methods 135 128 (R 7-RO) of the selected Register Bank (RB). One of the Figure 2.14. Mapping Of Special Function Registers four 8-Register Banks is selected by a two-bit field in the PSW. The registers may also be accessed through Direct address a destination operand. Since operations in the Addressing and Register-Indirect Addressing since the 8051 require 0 (NOP only), I, 2, 3 or 4 operands, these four Register Banks are mapped into the lowest 32 bytes five addressing methods are used in combinations to of Internal Data RAM as shown in Figure 2.16. Other provide the .8051 with its 21 addressing modes. Iflternal Data Memory locations that are addressed as registers are A, B, C, AB and DPTR. Most instructions have a "destination, source'" field that specifies the data type, addressing methods and operands Direct Addressing provides the only means of accessing involved. For operations other than moves, the destina the memory-mapped byte-wide Special Function Registers tion operand is also a source operand. For example, in and memory mapped bits within the Special Function Registers and Internal Data RAM. Direct Addressing of "subtract-with-borrow A,#5" the A register receives the bytes may also be used to access the lower 128 bytes result of the value in register A minus 5, minus C. of Internal Data RAM. Direct Addressing of bits gains access to a 128 bit subset of the Internal Data RAM and Most operations involve operands that are located in 128 bit subset of the Special Function Registers as shown Internal Data Memory. The selection of the Program in Figures 2. 12, 2. 14 and 2. 16. Memory space or External Data Memory space for a second operand is determined by the operation mnemonic Register-Indirect Addressing using the content of R I or unless it is an immediate operand. The subset of the RO in the selected Register Bank, or using the content of Internal Data Memory being addressed is determined by the Stack Pointer (PUSH and POP only), addresses the the addressing method and address value. For example, Internal Data RAM. Register-Indirect Addressing is also the Special Function Registers can be accessed only used for accessing the External Data Memory. In this thorugh Direct Addressing with an address of 128-255. A case, either R 1 or RO in the selected Register Bank may.be summary of the operand addressing methods is shown in used for accessing locations within a 256-byte block. The Figure 2.15. The following paragraphs describe the five block number can be preselected by the contents of a addressing methods. port. The 16-bit Data Pointer may be used for accessing any location within the full 64K external address space. Register Addressing permits access to the eight registers Immediate Addressing allows constants which are part AFN'01488A-17 13 8051 Architectural Specification and Functional Description

of the instruction to be accessed from the Program as two locations in Internal Data Memory (DPH & Memory. DPL). The Program Counter is always manipulated as a Base-Register- plus Index-Register- Indirect Addressing single double-byte register. simplifies accessing look-up-tables (LUT) resident in While the 8051 has extensive facilities for byte logic Program Memory. A byte may be accessed from a LUT operations as well as byte binary and two-digit BCD via an indirect move from a location whose address is the arithmetic, it excels in its bit handling capabilities. 128 sum of a base register (the DPTR or PC) and the index· bits in the Special Function Registers and 128 software register (A). flags in the Internal Data RAM are all supported orthogonally by the logic operations of and, or, set, clear,

INTERNAL SPECIAL and complement; the conditional branch operations of DATA RAMI FUNCTION jump-if-bit-set, jump-if-bit-not-set, and jump-if-bit-set STACK REGISTERS then-clear-bit; and the transfer operation of move bit. ~~ Performing conditional branch, logical, and transfer op 255 255 248 F8H 248 FOH erations directly on Boolean variables is a breakthrough 240 E8H for microcomputers, since this makes the 8051 both a 232 EOH 224 byte processor and a Boolean processor. D8H 216 DOH 208 C8H 2.5.1 Data Transfer Operations 200 DIRECT COH 192 ADDRESS- Look-up-tables resident in Program Memory can be B8H ING 164 accessed by indirect moves. A byte constant can be 176 BOH (BITS) 168 ASH transferred to the A register (Le. accumulator) from the 160 AOH Program Memory location whose address is the sum of a 152 98H 144 90H base register (the PC or DPTR) and the index register 136 88H (A). This provides a convenient means for programming 128 135 128 80H ..,.....:::.- translation algorithms such as ASCII to seven segment conversions. The Program Memory move operations are shown diagrammatically in Figure 2. 17. ~ DIRECT 127 120 ADDRESSING (BITS) 7 0 REGISTER .E. A R7 BANK 3 24 RO R7 BANK2 REGISTER .!! RO ADDRESSING , R7 BANK 1 8 RO R7 BASE-REGISTER- PLUS BANKO BASE-REGISTER- PLUS 0 RO INDEX-REGISTER-INDIRECT INDEX-REGISTER-INDIRECT '- @PC+A @OPTR+A ~ (PROG MEM 0-64K) (PROG MEM 0-64K) "~--~y ) DIRECT ADDRESSING STACK-POINTER REGISTER-INDIRECT AND REGISTER-INDIRECT ADDRESSING Figure 2.17 Program Memory Move Operations Figure 2.16. Addressing Operands In A byte location within a 256-byte block of External Data Internal Data Memory Memory can be accessed using R I or RO in Register 2.5 DATA MANIPULATION Indirect Addressing. Any location within the full 64K The 8051 microcomputer is efficient both as an arith External Data Memory address space can be accessed metic processor and as a controller. In addition to the through Register-Indirect Addressing using a 16-bit bas .. capabilities of its 8048 predecessor, the 8051 was enhanced register (i.e. the Data Pointer). These moves are shown with improved data transfer, logic manipulation, arith in Figure 2.18. metic processing, and real-time control capabilities. The 8051 performs operations on bit, nibble (4-bit), byte The byte in-code-constant (immediate) moves and byte (8-bit) and double-byte (l6-bit) data types. It is classified variable moves within the 8051 are highly orthogonal as as an 8-bit machine since the internal ROM, RAM, detailed in Figure 2. 19. When one considers that the Special Function Registers, Arithmetic/ Logic Unit (ALU) accumulator and the registers in the Register Banks can and the external data bus are each 8-bits wide. The be Direct Addressed, the two-operand data transfer double-byte data type is used only by the Data Pointer operations allow a byte to be moved between any two of and the Program Counter. The Data Pointer can be the RB registers, Internal Data, RAM, accumulator and manipulated as a single double-byte register (DPTR) or Special Function Registers. Also, immediate operands

AFN-01488A-18 14 8051 Architectural Specification and Functional Description

Figure 2.20. Internal Data Memory Exchange can be moved to any of these locations. Of particular Operations interest is the Direct Address to Direct Address move which permits the value in a port to be moved to the 2.5.2 Logic Operations Internal Data RAM without using any RB registers or the accumulator. The Data Pointer register can be loaded The 8051 permits the logic operations of and, or, and with a double-byte immediate value. Also, the 8051's exlusive-or to be performed on the A register by a second Boolean Processor can move any Direct Addressed bit to operand which can be immediate value, a register in the or from the carry flag. selected Register Bank, a Register-Indirect Addressed byte of Internal Data RAM ora Direct Addressed byte of The A register can be exchanged with a register in the Internal Data RAM or Special Function Register. In selected Register Bank, with a Register-Indirect Addressed addition, these logic operations can be performed on a byte in the Internal Data RAM or with a Direct Addressed Direct Addressed byte of the Internal Data RAM or byte in the Internal Data RAM or Special Function Reg Special Function Register using the A register as the ister. The least significant nibble of the A registt;r can also second operand. Also, use of Immediate Addressing with be exchanged with the least significant nibble of a Register Direct Addressing permits these logic operations to set, Indirect Addressed byte in the Internal Data RAM. The clear or complement any bit anywhere in the Internal exchange operation is shown in Figure 2.20 Data RAM or Special Function Registers without

DIRECT IMMEDIATE Data # data

Figure 2.19. Internal Data Memory Move Operations AFN-01488A-19 15 affecting the PSW,RB registers or accumulator. When one takes into account that registers R 7-RO and the REGISTER • Set(SETB) C accumulator can be Direct Addressed, the two-operand • Clear (ClR) (SETB, logic operations allow the destination (first operand) to • Complement (CPL) ClR,CPL) • Jump-It-BII-Set-Then-Clear-BII (JBC) be a byte in the Internal Data RAM, a Special Function Register, RB registers (R 7-RO) or the accumulator while Figure 2.23. Internal Data Memory Logic Operations the choice of the second operand can be any of the (Bit-Specific) aforementioned or an immediate value. The 8051 can also perform a logical or, or a logical and, between the add, increment, decrement, compare-to-zero, decrement Boolean accumulator (i.e. the carry flag) and any bit, or and-compare-to-zero, and decimal-add-adjust, the 8051 its complement, that can be accessed through Direct implemented subtract-with-borrow, compare, mUltiply Addressing. The and, or, and exclusive-or logic opera and divide. tions are summarized in Figure 2.21. Only unsigned binary integar arithmetic is performed in the ArithmetiC/Logic Unit. In the two-operand opera • And (ANL) tions of add, add-with-carry and subtract-with-borrow, .Or(ORL) • Exclusive-or (XRL) the A register is the first operand and receives the result of the operatjon. The second operand can be an immediate byte, a register in the selected Register Bank, a Register Indirect Addressed byte or a Direct Addressed byte. These instructions affect the overflow, carry, auxiliary carry and parity flags in the Program Status Word (PSW). The carry flag facilitates nonsigned integer and multi-precision addition and subtraction and multi precision rotation. Handling two's-complement-integer (signed) addition and subtraction can easily be accomo dated with software's monitoring ofthe PSWs overflow flag. The auxiliary-carry flag simplifies BCD arithmetic.

IMMEDtATE An operation that has an arithmetic aspect similar to a # data subtract is the compare-and-j~mp-if-not-equal opera tion. This operation perforros a conditional branch if a Figure 2.21. Internal Data Memory Logic Operations register in the selected Register Bank, or an Indirect Addressed byte of Internal Data RAM, does not equal an In addition to the logic operations that are performed on immediate value; or if the A register does not equal a byte Internal Data Memory as shown in Figure 2.21, there are in the Direct Addressable Internal Data RAM, or a also logic operations that are performed specifically on Special Function Register. While the destination operand the A register. These are summarized in Figure 2.22. is not updated and neither source operand is affected by the compare operation, the carry flag is. A summary of the two-operand add/subtract operations is shown in • Clear REGISTER • Complement Figure 2.24. • Rotate-Laft A • Rotate-Laft-Through-Carry • Rotate-Right • Rotate-Rlght-Through-Carry • Add • Swep-NlbbI.. (Rotate Left Four) • Add-With-Carry • Subtract-With·Borrow • Compare-And-Jump-II·Not·Equal ( ••••) Figure 2.22. Internal Data Memory Logic Operations DIRECT (Register A Specific) Data In addition to the and andor bit logicals shown in Figure " ", , 2.21, there are logicals that can operate exclusively on a ,/ Direct Addressed bit. These operations are listed in ,/ '" ,/ ,/ Figure 2.23. The carry flag is also addressed as a register ,/ and can be set, cleared or complemented with one-byte '" instructions. REGISTER REGISTER·INDIRECT R7·RO @Rl,@RO

2.5.3 Arithmetic Operations Figure 2:24. Internal Data Memory Arithmetic Along with the existing 8048 arithmetic operations of Operations AFN·01488A·20 16 8051 Architectural Specification and Functional Description

There are three arithmetic operations that operate exclusively on the A· register. These are the decimal ::': r REGISTERT REGISTER 1 adjust for BCD addition and the two test conditions A I B shown in Figure 2.25. The decimal-adjust operation converts the result from a binary addition of two two-digit Figure 2.27. Internal Data Memory Arithmetic BCD values to yield the correct two-digit BCD result. Operations (Register A with During this operation the auxiliary-carry flag helps effect B Specific) the proper adjustment. Conditional branches may be taken based on the value in the A register being zero or modate relocatable code. The advantage of a non-paged not zero. memory is that a minor change to a program tha( causes a shift of the code's position in memory will not cause page boundary readjustments to be necessary. This also • Declmal-Add-Adjust [:EJ • Jump-lf-A-ls.Zero REG~TER makes relocation possible. Relocation is desirable since it • Jump-I'·A-Is-Nol·Zero permits several programmers to write relocatable modules in various assembly and high-level languages which can Figure 2.25. Internal Data Memory Arithmetic later be linked together to form the machine object code. Operations (Register A Specific) Sixteen-bit jumps and calls are provided to allow branch The 805 I simplifies the implementation of software ing to any location in the contiguous 64K Program counters since the increment and decrement operations Memory address space and preempt the need for Program can be performed on the A register, a register in the Memory bank switching. Eleven-bit jumps and calls are selected Register Bank, an Indirect Addressed byte in the also provided to maintain compatibility with the 8048 Internal Data RAM or a byte in the Direct Addressed and to provide an efficient jump within a 2K program Internal Data RAM or Special Function Register. The module. Unlike the 8048, the 8051's call operations do 16-bit Data Pointer can be incremented. For efficient not push the Program Status Word (PSW) to the stack loop control the decrement-and-jump-if-not-zero opera along with the Program Counter, since many subroutines tion is provided. This operation can test a register in the written for the 8051 do not affect the PSW. Hence the selected Register Bank, any Special Function Register or 8051 return operations pop only the Program Counter. The any byte of Internal Data RAM accessible through Direct 8051 's branch, call and return operations are shown dia Addressing and force a branch if it is not zero. The incre grammatically in Figures 2.28 , 2.29 and 2.3f> respectively. ment I decrement operations are summarized in Figure 2.26.

REGplSCTER ,.j 1"'"4e-_-I-(~_--I~I_MM_E_D_'A_:r_E_ /16 _ Addr16 • Increment (INC) • Decremeilt (DEC) • Decremenl-And.Jump-tf-Nol-Zero (DJNZ)

DIRECT REGISTER 11 Dala . DPTR (INC, DEC, DJNZ) (INC) Figure 2.28. Unconditional Branch Operations REGISTER A (INC, DEC)

Figure 2.26. Internal Data Memory Arithmetic ·SP is pre-incremented. Operations The mUltiply operation multiplies the one-byte A register by the one-byte B register and returns a double-byte result (MSB in B, LSB in A). The divide operation divides the . 11 one-byte A register by the one-byte B register and returns a byte quotient to the A register and a byte remainder to the B register. These are shown in Figure 2.27. *SP is pre .. incremented. 2.6 CONTROL TRANSFER The 805 I has a non-paged Program Memory to accom- Figure 2.29. Call Operations AFN-Ol488A-21 17 8051 Architectural Specification and Functional Description

machine codes that the computer recognizes, so much as REG~~TER 141---I/'-16---t1... REGIST:~~~DIRECT I it depends upon the structure of the symbolic language that is used to describe the machine codes. 'SP Is post-dec:remented. The 8051 assembly language needs only forty-two mne Figure 2.30. Return Operation monics to specify the 8051 's thirty-three functions. A function may have several mnemonics (e.g., MOV, The 805 I also provides a method for performing condi MOVX, MOVq since the function mnemonic specifies tional and unconditional branching relative to the starting when the Program Memory or External Data Memory address of the next instruction (PC - 128 to PC + 127). The is used in conjunction with the Internal Data Memory. bit test operations allow a conditional branch to be taken When the function mnemonics are combined with unique on the condition of a Direct Addressed bit being set or address combinations specified in the "destination, source" not set.· The accumulator test operations allow a field, III instructions are possible. The "destination, conditional branch based on the accumulator being zero source" field specifies the data type and the combination or non-zero. Also provided are compare-and-jump-if of addressing methods to be used to address the destina not-equal and decrement-and-compare-to-zero. These are tion and source operands. A summary of the 8051 shown in Figure 2.31. instruction set is provided in Table 2-1.

• Short Jump • Jump-If-A-Zero The syntax of most 805 I assembly language instructions • Jump-If-Blt-Sel • Jump-If-A-Not-Zero • Jump-If-Blt-Not-Set • Dec:remenl-And-Jump-If-Nol-Zero consists of a function mnemonic followed by a "destina • Jump-If-Bil-Set-Then-Clear-Sit • Compare-And-Jump-ll-Not-Equal tion, source" operand field. Thus "MOV @RO, Data" may be interpreted as "The content of the Internal Data Memory location addressed by the content of Register 0 receives the content of the Internal Data Memory loca tion addressed by Data." In two operand instructions, the destination address also serves as the address of the first source. As an example of this, "ANL Data, #5" may be interpreted as "The content of the Internal Data Memory location addressed by Data receives the result of the operation when the content of the memory location Figure 2.31. Unconditional Short Branch and specified by Data is and-ed with the immediate 5." Conditional Branch Operations The 8051 's instruction set is an enhancement of the instruction set familiar to MCS-48 users. It is enhanced The register-indirect jump in the 8051 permits branching to allow expansion of on-chip CPU peripherals and to relative to a base register (DPTR) with an offset provided optimize byte efficiency and execution speed. Efficient by the non-signed integer value in the index register (A). use of program memory results from an instruction set This accommodates N-way branching. The indirect jump consisting of 49 single-byte, 45 two-byte and 17 three is shown in Figure 2.32. byte instructions. Most arithmetic, logical and branching operations can be performed using an instruction that appends either a short address or a long address. For example, Register Addressing allows a two byte equiva lent of the three byte Direct Addressing instructions. Also, short branches are more code efficient than long branches. 64 instructions execute in twelve oscillator periods, 45 instructions execute in twenty-four oscillator periods, and mUltiply and divide take only forty-eight oscillator periods. The number of bytes in each instruc tion and the number of oscillator periods required for . Figure 2.32. Unconditional Branch execution are listed in Table 2-1. (Indirect) Operation 2.7.2 Organization of the Instruction Set 2.7 INSTRUCTION SeT Instructions are described here in four functional groups: 2.7.1 What the Instruction Set Is • Data Transfer An instruction set is a set of codes that directs a computer • Arithmetic to perform its operations. The ease of understanding the • Logic instruction set does not depend upon the structure of the • Control Transfer AFN-01488A-22 18 8051 Architectural Specification and Functional Description

The Data Transfer, Arithmetic and Logic groups men Single-Operand Operations. Seven single-operand logical tioned in the preceding list are further subdivided into an . operations are provided: array of codes that specify whether the operation is to CLR is used to set eitber the A register, the C act upon immediate, RB register, accumulator, SFR or register, or any Direct Addressed bit to zero (0). memory locations; whether bits, nibbles, bytes or double SETB sets either the C register or any Direct bytes are to be processed; and what addressing methods Addressed bit to one (1). are to be employed. CPL either forms the one's complement of the operand in the A register and returns the result DATA TRANSFER to the A register without affecting flags or forms . Data transfer operations are divided into three classes: the one's complement of the C register or any • General Purpose Direct Addressed bit. • Accumulator-Specific RL, RLC, RR, RRC, SWAP. Five rotate opera • Address-Object tions can be performed on the A register; RL None affect the flag settings except a POP or MOV into (rotate left), RR (rotate right), RLC (rotate left the PSW. through C), RRC (rotate right through C) and ~~~:·~~·.;·1'··: ... SW AP (rotate left four). For RLC and RRC the C General Purpose Transfers. Three general purpose data flag becomes equal to the last bit rotated out. transfer operations are provided. These may be applied SWAP rotates the A register left four places to to most operands, though there are specific exceptions. exchange bits 3 through 0 with bits 7 through 4. MOV performs a bit or a byte transfer from the source operand to the destination operand. Two-Operand Operations. Three two-operand logical PUSH increments the SP register and then trans operations are provided: fers a byte from the source operand to the stack ANL performs the bitwise logical conjunction of element currently addressed by SP. two source operands (for both bit and byte oper POP transfers a byte operand from the stack ands) and returns the result to the location of the element addressed by the SP register to the first operand. destination operand and then decrements SP. ORL performs the bitwise logical inclusive dis junction of two source operands (for both bit and Accumulator-Specific Transfers. Four accumulator-specific byte operands) and returns the result to the loca transfer operations are provided: tion of the first operand. XCH exchanges the byte source operand with XRL performs the bitwise logical exclusive disjunc register A (accumulator). tion of the two source oPerands (byte operands) XCHD exchanges the low-order nibble of the and returns the result to the location of the first byte source operand with the low-order nibble of operand. register A. MOVX performs a byte move between the External Data Memory and the A register. The external address can be specified by the DPTR ARITHMETIC register (16-bit) or the Rl or RO register (8-bit). The 8051 provides the four basic mathematical operations. MOVC performs the move of a byte from the Only 8-bit operations using unsigned arithmetic are sup Program Memory to register A as follows. The ported directly. The overflow flag permits the addition operand in the A register is used as an index into and subtraction operations to serve for both unsigned and a 256-byte table pointed to by the base register signed binary integers. A correction operation is also (DPTR or PC). The byte operand accessed is provided to allow arithmetic to be peiformed directly on transferred to A. MOVC is used for table-look-up packed decimal (BCD) representations. byte translation and for accessing operands from code-in-line tables. Flag Register Settings. Three one-bit flag registers are set Address-Object Transfer or cleared by arithmetic operations to refl\!ct certain MOV DPTR,#data loads 16-bits of immediate properties of the result of the operation. These flags are data into a pair of destination registers, DPH and not affected by the increment and decrement instruc DPL (DPH from low-order address, DPL from tions. A fourth flag (P) denotes the parity of the eight high-order address). accumulator bits. These flag registers are located in the Program Status Word (PSW) register. Their bit assign LOGIC ment are shown below. A list of the instructions that The 8051 performs the basic logic operations on both bit affect these flags is provided in the "8051 Instruction Set and byte operands. Summary" in Table 2-\' . AFN-01488A-23 19 8051 Architectural Specification and Functional Description

operand (the accumulator), subtracts one (I) if CARRY DECIMAL PARITY CARRY the C flag is found previously set and returns the SYMBOLIC result to the A register. ADDRESS: ,...:::.:-....,...I.,...;;:....,....;.,;....,.....;.;.;;.;..-r-..;.;.;..;..,.....;...... ,....--r--P.., DEC (decrement) performs a subtraction of one REGISTER: (1) from the source operand and returns the

USER REGISTER BANK RESERVED results to the operand. FLAG SELECT Multiplication. PSW.7: CY: Carry Flag (also the C register) PSW.6: AC: Auxiliary-Carry Flag MUL performs an unsigned multiplication of the PSW.2: OV: Overflow Flag A register by the B register, returning a double PSW.O: P: Parity Flag byte result. Register A receives the low-order PSW.5: FO: User Flag 0 byte, B receives the high-order byte. OV is cleared PSW.I: reserved if the top half of the result is zero and is set if it PSW.4: RSI: Register Select MSb is non-zero. C is cleared. AC remains unaltered. PSW.3: RSO: Register Select LSb Division. Unless otherwise stated, the instructions obey these rules: DIV performs an unsigned division of the A CY is set if the operation results in a carry out of register by the B register and returns the integer (during addition) or a borrow into (during sub quotient to register A and returns the fractional traction) the high-order bit of the result; otherwise remainder to the B register. Division by zero leaves CY is cleared. indeterminate data in registers A and B and sets AC is set if the operation results in a carry out of OV, otherwise OV is cleared. C is cleared. AC the low-order four bits of the result (during addi remains unaltered. tion) or a borrow from the high-order bits into the low-order 4 bits (during subtraction); otherwise CONTROL TRANSFER AC is cleared. There are' three classes of control transfer operations: o V is set if the operation results in a carry into the unconditional calls, returns and jumps; conditional jumps; high-order bit of the result but not a carry out of and interrupts. All control transfer operations cause, some the high-order bit, or vice versa; otherwise OV is upon a specific condition, the program execution to cleared. OV is of use in two's-complement arith continue at a noIf-sequential location in program metic, since it becomes set when the signed result memory. cannot be represented in 8 bits. Unconditional Calls, Returns and Jumps. Unconditional P is set if the module 2 sum of the eight bits in the calls, returns and jumps transfer control from the current accumulator is I (odd parity); otherwise P is value of the Program Counter to the target address. Both cleared (even parity). When a value is written to direct and indirect transfers are supported. The three the PSW register, the P bit remains unchanged, as transfer operations are described below. it always reflects the parity of A. ACALL and LCALL push the address of the next Addition. Four addition operations are provided: instruction onto the stack (PCL to low-order INC (increment) performs an addition of the address, PCH to high-order address) and then source operand and one (I) and returns the result transfer control to the target address. Absolute Call to the operand. is a 2-byte instruction used when the target address ADD performs an addition between the A register is in the current 2K page. Long Call is a 3-byte and the second source operand and returns the instruction that addresses the full 64K program result to the A register. space. In ACALL, immediate data (i.e. an II bit ADDC (add with carry) performs an addition address field) is concatenated to the five most between the A register and the second source significant bits of the PC (which is pointing to the operand; adds one (1) if the C flag is found pre next instruction). If ACALL is in the last 2 bytes of viously set and returns the result to register A. a 2K page then the call will be made to the next DA (decimal-add-adjust for BCD addition) per page since the PC will have been incremented to forms a correction to the sum which resulted from the next instruction prior to execution. the binary addition of two two-digit decimal RET transfers control to the return address saved operands. The packed decimal sum formed by on the stack by a previous call operation and DA is returned to A. The carry flag is set if the decrements the SP register by two (2) to adjust the BCD result is greater than 99; else it is cleared. SP for the popped address. Subtraction. Two subtraction operations are provided: AJMP, LJMP and SJMP transfer control tothe SUBB (subtract with borrow) performs a subtrac target operand. The operation of AJ M P and tion of the second source operand from the first LJMP are analogous to ACALL and LCALL.

AFN-01488A-24 20 8051 Architectural Specification and Functional Description

The SJMP (short jump) instruction provides for stack to avoid corruption. Only one interrupt transfer transfers within a 256 byte range centered about operation is necessary: the starting address of the next instruction (-128 RETI transfers control in a manner identical to ' to + 127). The PC-relative short jump facilitates RET. In addition, RET! reenables interrupts for relocatable code. the current priority level. JMP@ A+DPTR performs ajump relative to the DPTR register. The operand in the A register is See section 2.8 for further details on the operation and used as the offset (0-255) to the address in the control of the interrupt system. DPTR register. Thus, the effective destination for 2. 7.3 Operand Addressing Modes & a jump can be anywhere in the Program Memory space. This indirect' jump is also useful for Associated Operations implementing N-way branches. In section 2.4 the instruction set was explained from the point of view of which operands could be used with each Conditional Jumps. In the control transfer group, the con operation. This section lists the operations that can be ditional jumps perform a jump contingent upon a specific used with each addressing method. condition. The destination will be within a 256-byte range centered about the starting address of the next instruction As an introduction, Figure 2.33.A tabulates the total (-128 to +127). addressing mode combinations for one-, two-, three-, and JZ performs a jump if the accumulator is zero. four-operand operations. The various combinations give JNZ performs a jump if the accumulator is not the 8051 programmer great flexibility in writing code. zero. The following pages provide a handy reference for deter JC performs a jump if the carry flag is set. mining which function mnemonic can be combined with JNC performs a jump if the carry flag is not set. the various operand addressing methods. The format JB performs a jump if the Direct Addressed bit permits a quick reference to how the 8051's memory is set. spaces may be manipulated. JNB performs a jump if the Direct Addressed bit is not set. • SIngte.O_d O_allon. (O_d 1) - OPERATION (Operud 1) JBC performs a jump if the Direct Addressed bit - DIRECTA_g - REGISTER AddntooIng is set and then clears the Direct Addressed bit. - REGISTER-INDIRECT Ad_1ng CJNE compares the first operand to the second • Tw.... O_ ... d Operallon. (Operand 1) _ (Operand 11 OPERATION (Ope

AFN-01488A-25 21 8051 Architectural Specification and Functional Description

• DIRECT Adchuing - Opet'llnd OperaUon • REGISTER-INDIRECT. DIRECT Addressing RAM (I11III 0-127) or SFA (I11III 128-255) SETB.CLR.CPL Operand 1 Operand 2 Operation RAM (0-127) or SFR (128-255) INC. DEC @R1, @RO[RAM (0-255)] RAM or SFA MOV • REGISTER Addressing @SP [RAM (0-255)] RAM or SFR PUSH. POP Operand Operation C SETB.CLR.CPL • REGISTER-INDIRECT, REGISTER Addressing A INC. DEC. DA, CLR. Operand 1 Opera~2 Operation CPL. RL, RLC. RR. RRC. @R1, @RO [RAM (0-255)] A MOV SWAP @R1. @RO [EXT DATA (0-255)] A MOYX R7oRO INC. DEC @DPTR[EXT DATA(o-64K)] A MOYX DPTR INC • REGISTER-INDIRECT. IMMEDIATE Addressing • REGISTER-INDIRECT Acldrealng Operand 1 Opera~ 2 Operation - Opet'llnd Operation @R1, @RO [RAM (0-255)] PM (immediate) MOV @R1. @RO [I•••• RAM (0-255)] INC. DEC Note, SFR = Special Funcllon Regia'"

Figure 2.33.C. Operand Addressing Figure 2.33.F. Operand Addressing Single-Operand Operations Two-Operand Operations

• DIRECT, DIRECT Ad~g • REGISTER, BASE-REGISTERopIus-INDEX-REGISTER-INDIRECT AddressIng - Opet'llnd 1 Operand 2 Operation Operand 1 Operand 2 • - Operand 3 . Opsrmlon RAM or SFA RAM or SFA MOV A @ DPTR+A MOVC A @PC+A MOVC • DIRECT. REGISTER Adchuing PC @ DPTR+A JMP (IndINcI) Opet'llnd 1 OperMCI 2 Operation RAM (I11III) or SFR (bI") C MOV. ANL, ORL • REGISTER. IMMEDIATE, REGISTER-INDIRECT AddressIng C~RAM(IIIIII) C ANL,ORL - Operand 1 - Operand 2 - Operand 3 OperatIon or SFR (I11III1 PC PM (Immediate) @SP LCALL, RAMorSFA A . MOV. ANL, ORL, XRL ACALL RAM or SFR RT-RD MOV • REGISTER, IMMEDIATE, DIRECT AcIdeuIng • DIRECT. REGISTER-INDIRECT AcIdreUIng Oper~ 1 Operand 2 Operand 3 Opsrmlon - Operand 1 - Operand 2 Operation PC PM RAM (I11III) or JB,JNB, RAM or SFR @R1. @RD MOV SFR(IIIIII) JBC PC PM RAM • SFA DJNZ • DIRECT. IMMEDIATE Addressing - Opmmd1 OperMCl2 Operation • REGISTER, IMMEDIATE, REGISTER Addrasling Operand' Operand Operand RAM or SFA PM (ImmedI"') MOV, ANL, ORL, XRL 2 3 0 ...... PC PM C JC,JNC Note: PM = Progr.... M.... ory PC PM A JZ.JNZ PC PM RT-RO DJNZ

Figure 2.33.D. Operand Addressing Figure 2.33.G. Operand Addressin'g Two-Operand Operations Three-Operand Operations

• REGISTER, DIRECT Addressing • REGISTER, IMMEDIATe, REGISTER. DIRECT AcIdnuIng Operand 1 Operand 2 Operalion - Operand 1 - Operand 2 - Operand 3 - Operand 4 - Operation C RAM (bils) or SFR (bl") MOV PC PM A RAM or SFA CJNE A RAMorSFR MOV, XCH. ADD, ADDC, SUBB,JI.NL, • REGISTER. IMMEDIATE. REGISTER. IMMEDIATE Addressing ORL, XRL - Operand 1 - Operand 2 - Oper~ 3 - Operand 4 - Operation RT-RO RAM or SFR MOV PC PM A PM CJNE PC PM RT-RO PM CJNE • REGISTER, REGISTER Addressing Operand 1 Operand 2 Operation • REGISTER, IMMEDIATE, REGISTER-INDIRECT, IMMEDIATE Addressing A R7-RD MOV, XCH, ADD, - Operand 1 - Operand 2 - Operand 3 - Operand 4 - Operation ADDC, SUBB,ANL, PC PM @R1. @RO PM CJNE ORL. XRL R7-RO A MOV A B MUL,DIV • REGISTER, REGISTER-INDIRECT Addressing Figure 2.33.H. Operand AddreSSing Operand 1 Operand 2 Operation FourmOperand Operations A @R1, @RO [RAM (0-255)] MOV, XCH, ADD, ADDC, SUBB, ANL. ORL, XRL, XCHD A @Rl,@RO [EXT DATA MOVX (0-255)] A @OPTR [EXT DATA (o-64K)] MOVX 2.8 INTERRUPT SYSTEM PC @SP[RAM (0-255)] RET, RETI • REGISTER, IMMEDIATE Addressing Interrupts result in a transfer of control to a new program Operand 1 Operand 2 Operation location. The program servicing the request begins at this A PM (Immedlale) MOV, ADD, ADDC, SUBB, ANL, ORL, address. In the 8051 there are five hardware resources that XRL R7-RO PM (Immediate) MOV can generate an interrupt request. The starting address of DPTR PM (Immedlale) MOV PC PM (Immediate) WMP,AJMP, the interrupt service program for each interrupt source is SJMP shown in Figure 2.34. Note: PM =Program Memory A resource requests an interrupt by setting its associated Figure 2.33.E. Operand Addressing interrupt request flag in the TCON or SCON register, as Two-Operand Operations detailed in Figure 2.35. The interrupt request will be AFN-Ol488A-26 22 8051 Architectural Specification and Functional Description

Setting/ clearing a bit in the Interrupt Priority register Interrupt Source Starting Address (IP) establishes its associated interrupt request as a External Request 0 3 (0003 H) high/low priority. If a low-priority level interrupt is being Internal Timer/Counter 0 II (OOOB H) serviced, a high-priority level interrupt will interrupt it. External Request I 19 (0013 H) However, an interrupt source cannot interrupt a service Internal Timer/ Counter I 27 (OOIB H) program of the same or higher level. Internal Serial Port 35 (0023 H) Priority Figure 2.34. Program Memory Location of Interrupt Priority Within Bit Service Programs Interrupt Source Flag Level Location External Request 0 PXO .0 (highest) IP.O acknowledged if its interrupt enable bit in the Interrupt Internal Timer / Counter 0 PTO .1 IP.l Enable register (shown in Figure 2.36) is set and if it is External Request 1 PXl .2 IP.2 the highest priority resource requesting an interrupt. A Internal Timer / resource's interrupt priority level is established as high Counter I PTI .3 IP.J or low by the polarity of a bit in the Interrupt Priority Internal Serial Port PS .4 (lowest) IP.4 register. These bit assignments are shown in Figure 2.37. Reserved None IP.5 Setting the resource's associated bit to a one (1) programs Reserved None IP.6 it to the higher level. The priority of mUltiple interrupt Reserved None IP.7 requests occurring simultaneously and assigned to the same priority level is also shown in Figure 2.37. Figure 2.37. Interrupt Priority Flags The servicing of a resource's interrupt request occurs at The processor records the active priority level(s) by setting the end of the instruction-in-progress. The processor internal flip-flop(s). One of these non-addressable flip transfers control to the starting address of this resource's flops is set while a low-level interrupt is being serviced. interrupt service program and begins execution. The other flip-flop is set while the high-level interrupt is being serviced. The appropriate flip-flop is set when the Request Bit processor transfers control to the service program. The Interrupt Source Flag Location flip-flop corresponding to the interrupt level being serviced is reset when the processor executes an RETI External Request 0 lEO TCON .1 Internal Timer/ Counter 0 TFO TCON.5 Instruction. External Request I lEI TCON.3 To summarize, the sequence of events for an interrupt is: Internal Timer/ Counter I TFI TCON.7 A resource provokes an interrupt by setting its Internal Serial Port (xmit) TI SCON.I associated interrupt request bit to let the processor know Internal Serial Port (rcvr) RI SCON.O an interrupt condition has occurred. The CPU's internal hardware latches the interrupt request near the falling Figure 2.35. Interrupt Request Flags edge of ALE in the tenth, twenty-second, thirty-fourth and forty-sixth oscillator period of the instruction-in Enable Bit progress. The Interrupt request is conditioned by bits in Interrupt Source Flag Location the interrupt enable and interrupt priority registers. The External Request 0 EXO lE.O processor acknowledges the interrupt by setting one of Internal Timer / Counter 0 ETO IE.! the two internal "priority-level active" flip-flops and per External Request I EXI 1E.2 forming a hardware subroutine call. This call pushes the Internal Timer/ Counter 1 ETI IE.3 PC (but not the PSW) onto the stack and, for most Internal Serial Port ES 1E.4 sources, clears the interrupt request flag. The service Reserved None 1E.5 program is then executed. Control is returned to the main Reserved None 1E.6 program when the RETI instruction is executed. The All Enabled EA 1E.7 RETI instruction also clears one of the internal "priority level active" flip-flops. Figure 2.36. Interrupt Enable Flags Most interrupt request flags (lEO, lEt, TFO and TFl) are Within the Interrupt Enable register (IE) there are six cleared when the processor transfers control to the firstl addressable flags. Five flags enable / disable the five inter instruction of the interrupt service program. The TI and rupt sources when set/cleared. Setting/clearing the sixth RI interrupt request flags are the exceptions and must be flag permits a global enable I disable of each enabled cleared as part of the serial port's interrupt service interrupt request. program. AFN-01488A-27 23 8051 Architectural Specification and Functional Description

The process whereby a high-level interrupt request inter can be programmed for either transition-activated or rupts a low-level interrupt service program is called level-activated operation. Control of the external inter nesting. In this case the address of the next instruction rupts is provided by the four low-order bits of TCON. in the low-priority service program is pushed onto the stack, the stack pointer is incremented by two (2) and Bit processor control is transferred to the Program Memory Function Flag Location location of the first instruction of the high-level service External Interrupt Request Flag I lEI TCON.3 program. The last instruction of the high-priority inter Input INTI Transition-Activated ITI TCON.2 rupt service program must be an RETI instruction. This External Interrupt Request Flag 0 lEO TCON.I instruction clears the higher "priority-level-active" flip Input INTO Transition Activated ITO TCON.O flop. RETI also returns processor control to the next instruction of the low-level interrupt service program. Figure 2.39. Function of Bits in TCON Since the lower "priority-level-active" flip-flop has (Lower Nibble) remained set, high priority interrupts are re-enabled When ITO and IT I are set to one (I), interrupt requests on while further low priority interrupts remain disabled. INTO and INTI are transition-activated (high-to-Iow); else they are low-level activated. lEO and lEI are the The highest-priority interrupt request gets serviced at the interrupt request flags. These flags are set when their end of the instruction-in-progress unless the request is ~sponding interrupt request inputs at INTO and made in the last fourteen oscillator periods of the INTI, respectively, are low when sampled by the 8051 instruction-in-progress. Under this circumstance, the next and the transition-activated scheme is selected by ITO instruction will also execute before the interrupt's sub and ITI. When ITO and ITI are programmed for level routine call is made. The first instruction of the service activated interrupts, the lEO and IE I flags are not affected program will begin execution twenty-four oscillator by the inputs at INTO and INTI respectively. periods (the time required for the hardware subroutine call) after the completion of the instruction-in-progress 2.8.1.1 TRANSITION-ACTIVATED INTERRUPTS or, under the circumstances mentioned earlier, twenty The external. interrupt request inputs (INTO and INTI) four oscillator periods after the next instruction . can be programmed for high-to-Iow transition-activated . . operation. For transition-activated operation, the input Thus, the greatest delay in response to an interrupt must remain low for greater than twelve oscillator periods, request is 86 oscillator periods (approximately 7 f.JSec @ but need not be synchronous with the oscillator. It is 12 MHz). Examples of the best and worst case conditions internally latched by the 8051 near the falling-edge of ALE are illustrated in Figure 2.38. during an instruction's tenth, twenty-second, thirty-fourth and forty-sixth oscillator periods and, if the input is low, Time lEO or lEI is set. The upward transition of a transition (Oscillator Periods) activated input may occur at any time after the twelve Instruction Best Worst oscillator period latching time, but the input must remain Case Case high for twelve oscillator periods before reactivation. 1) External interrupt request 2 + E 2-E 2.8.1.2 LEVEL-ACTIVATED INTERRUPTS generated immediately The external interrupt request inputs (INTO and INTI) before (best) / after (worst) can be programmed for level-activated operation. The the pin is sampled. (Time input is sampled by the 8051 near the falling-edge of ALE until end of bus cycle.) during the instruction's tenth, twenty-second, thirty-fourth 2) Current or next instruction 12 12 and forty-sixth oscillator periods. If the input is low finishes in 12 oscillator during the sampling that occurs fourteen oscillator periods periods before the end of the" instruction in progress, an inter 3) Next instruction is MUL don't 48 rupt subroutine call is made. The level-activated input or DIV care need be low only during the sampling that occurs fourteen 4) Internal latency for hard- 24 24 oscillator periods before the end of the instruction-in ware subroutine call progress and may remain low during the entire execution of the service program. However, the input must be raised 38 86 before the service program completes to avoid possibly Figure 2.38. Best and Worst Case Response to Inter envoking a second interrupt. rupt Request 2.9 PORTS AND I/O PINS 2.8.1 External Interrupts There are 32 I/O pins configured as four 8-bit ports. Each The external interrupt request inputs (INTO and INTI) pin can be individually and independently programmed AFN-01488A-28 24 8051 Architectural Specification and Functional Description

as an input or an output and each can be reconfigured READ (READ- dynamically (i.e., on-the-fly) under software control. MODIFY-WRITE) ----, An instruction that uses a port's bit/byte as a source operand reads a value that is the logical and of the last +5V value written to the bit / byte and the polarity being applied to the pin/pins by an external device (this - 2OK-40K assumes that none of the 8051's electrical specs are being Q INTERNAL violated). An instruction that reads a bit/byte, operates BUS D on the content, and writes the result back to the bit/byte, o reads the last value written to the bit/byte instead ofthe FLIP 1/0 FLOP PIN logic level at the pin/pins. Pins comprising a single port PORT", can be made a mixed collection of inputs and outputs by, 20R3 Q 1--+-+----1 writing a "one" to each pin that is to be an input. Each CLK time an instruction uses a port as the destination, the WRITE PULSE-+--..----' operation must write "ones" to those bits that correspond ZERO TO , to the input pins. An input to a port pin need not be TRANSITION synchronized to the oscillator. Each port pin is sampled near the falling-edge of ALE during the read instruction's READ (NON READ tenth or twenty-second oscillator period. If an input is in MODIFY transition when it is sampled near the falling-edge of ALE WRITE) it will be read as an indeterminate value. Figure 2.40.B. "Quasi-Bidirectional" The instructions that perform a read of,operation on, and Port Structure write to a port's bit/byte are INC, DEC, CPL, JBC, driver provides s01,lrce current for two oscillator periods CJNE, DJNZ, ANL, 0 RL, and XRL. The source read by if, and only if, software updates the bit in the output latch these operations is the last value that was written to the from a zero (0) to a one (I). Sourcing current only on a port, without regard to the levels being applied at the "zero to one" transition prevents.a pin, programmed as pins. This insures that bits written to a one (I) for use as an input, from sourcing current into the external device inputs are not inadvertently cleared. See Figure 2.40. . that is driving the input pin. The output drivers in Ports When used as a port, Port 0 has an open-drain output. 1,2 and 3 can sink/source one TTL load. When used as a bus, it has a standard three-state driver. Secondary functions (RD, WR, etc.) can be selected indi The Port 0 output driver can sink/source two TTL loads. vidually and independently for the pins of Port 3. Port 3 Ports I, 2 and 3 have quasi-bidirectional output drivers generates these secondary control signals automatically which incorporate a pullup resistor of 20K- to 40K-Ohms as long as the pin corresponding to the appropriate signal as shown in Figure 2.40.B. In Ports 1, 2 and 3 the output is programmed as an input.

READ (READ- MODIFY-WRITE) -----, 2.10 ACCESSING EXTERNAL MEMORY When accessing external memory the 8051 emits the upper address byte from Port 2 and the lower address +5V byte, as well as the data, from Port O. It uses ALE, PSEN and two pins from Port 3 (RD and WR) for memory control. ALE is used for latching the address into the Q INTERNAL 0 external memory. The PSEN signal enables the external BUS Program Memory to Port 0, the RD signal enables 0 FLIP External Data Memory to Port 0 and the WR signal FLOP latches the data byte emitted by Port 0 into the External Data Memory. Externally the PSEN and RD signals can Q be combined logically if a contiguous external program CLK and data memory space (similar to a "von Ne1,lman" WRITE PULSE ":" machine) is desired. The P3.7 (RD) and P3.6 (WR) output BUS CYCLE TIMING latches must be programmed to a one (1) if External Data Memory is to be accessed. When P3.7 and P3.6 are pro grammed as RD and WR respectively, the remaining pinsi READ (NON READ of Port 3 may be individually programmed as desired. MODIFY-WRITE) The 8051 can address 64K bytes of external Program Figure 2.40.A. "Bidirectional" Port Structure Memory when the EA pin is tied low. When EA is high, AFN-01488A-29 25 tsU~l ArcnneCtural :specification and Functional Description

the 8051 fetches instructions from internal Program address latching (MCS-85 memories with peripherals), Memory when the address is between 0 and 4095 and or it can be demultiplexed with an address latch to from external Program Memory when the addressed generate a non-multiple?Ced bus (MCS-80 peripherals memory location is between 4096 and 64K. In either case, and memory). During an external access the low-order Ports 2 and 0 are automatically configured as an external byte of the address and the data (for a write) is emitted bus based on the value of the Pc. Instruction executio[}o by the Port 0 output drivers. Ones (l's) are automatically times are the same for code fetched from internal or written to Port 0 at the very end of the bus cycle. Since external Program Memory. the Port Ooutput latches will contain ones (I 's) at the end of Up to 64K of External Data Memory can be accessed the bus cycle, Port 0 will be in its high impedance state using the MOVX instructions. These instructions auto when a bus cycle is not in progress. Port 2 emits the upper matically configure Port 0, and often Port 2, as an 8-bits of the address when a MOVX instruction using external bus. The MOVX instructions use the DPTR, DPTR is executed. Port 2's output drivers provide source RI or RO register as a pointer into the External Data current for two oscillator periods when emitting the Memory. The 16-bit DPTR register is used when succes address. Port 2's internal pullup resistors sustain the high sive accesses cover a wide range of the 64K space. The level. 8-bit Rl and RO registers provide greatest byte efficiency when successive accesses are constrained to a 256-byte 2.10.2 Accessing External Memory-Bus block of the External Data Memory space. When using Rl Cycle Timing and RO a subsequent block can be accessed by updating Program Memory Read Sequence (Figure 2.11) the output latch of Port. 2. Port 2 is not affected by Each Program Memory bus cycle consists of six oscil execution of a MOVX that uses Rl or RO such that, if lator periods. These are referred to as n, T2, T3, T4, T5 32K or less of external memory is present, only part of Port 2 needs to be used for selecting the desired block; and T6 on Figure 2.41. The address is emitted from the processor during T3. Data transfer occurs on the bus the remaining pins can be used for I/O. When a MOVX during T5, T6 and the following bus cycle's Tl. When using DPTR is executed, the value in Port 2's output latch is altered only during the external access and then fetching from external Program Memory, the 8051 will always fetch an even number of bytes. If an odd number is returned to its prior value. This permits efficient exter nal block moves by interleaving MOVX instructions that of bytes are executed prior to a branch or an External use DPTR and Rl or RO. Data Memory access the non-executed byte will be ignored by the 8051. An even number of idle bus cycles The ALE signal is generated every sixth oscillator period (each 6 oscillator periods in duration) can occur between during reads from either internal or external Program external bus cycles when the processor is fetching from Memory. The PSEN signal is generated every sixth oscil internal Program Memory. The read cycle begins during lator period when reading from the external Program T2, with the assertion of address latch enable signal ALE Memory. When a read or write from External Data The falling edge of ALE (3) is used to latch the Memory is being performed, a single ALE and a RD or a CD . address information, which is present on the bus at this WR signal is generated during a twelve oscillator period time CD ,into the 8282 latch if a non-multiplexed bus is interval. The 8051 always fetches an even number of bytes required. At T5, the address is removed from the Port 0 from its Program Memory. If an odd number of bytes bus and the processor's bus drivers go to the high are executed prior to a branch or to an External Data impedance sta~ . The program memory read Memory access, the non-executed byte is ignored by the control signal (PSEN) CD is also asserted during T5. 8051. If an instruction requires more oscillator periods PSEN causes the addressed device to enable its bus for its execution than for its fetch, the first byte of the drivers to the now-released bus. At some later time, valid next instruction is fetched repeatedly while the first instruction data will become available on the bus G) instruction completes execution. If the CPU does not When the 8051 subsequently returns PSEN to the high address External Data Memory then ALE is generated level (}) • the addressed device will then float its bus every sixth oscillator period and can be used as an drivers, relinquishing the bus again®. external clock. When External Data Memory is present, external logic may be used to combine the occurence of For the MOVC instruction the op-code is fetched in the RD, WR, and ALE to generate an external clock with a first six-oscillator period, the first byte of the next in period equal to six oscillator periods. struction is fetched during the second six-oscillator per iod, the table entry is fetched in a third six-oscillator 2.10.1 Accessing External Memory-Opera period and the first byte of the next instruction is again tion of Ports fetched in the fourth six-oscillator period. The Port 0 bus is time mUltiplexed to permit transfer of Data Memory Read Sequence (Figure 2.42) both addresses and data. This bus is used directly by Each External Data Memory bus cycle consists of twelve memory and peripheral devices that incorporate on-chip oscillator periods. These are shown as T I through T 12 on AFN-Ol488A-30 26 8051 Architectural Specification and Functional Description

T12

OSC

ALE

PORT 2

PORTO FLOAT

Figure 2.41. Program Memory Read Cycle Timing

ALE CD V \0 I V

RD ~0 CD 1/ 0 PORT 2 X ADDRESS A15-Aa

0 0 (6) ® ADD RESS FLOAT PORTO INST Irl FLOAT A7-Ao I FLOAT >( DATA IN I ORFLOAT I I I I I I Figure 2.42. Data Memory Read Cycle Timing

ALE G:: V \ II II

\0 @ II ® PORT 2 X ADDRESS A15-Aa

0 ~ 0 ADD RESS PORTO INST IN IFLOAT A7-Ao D< DATA OUT OR FLOAT I I I I I NOTE: In Figures 2.42 and 2.43 the Prior and Subsequent Machine Cycles access Program Memory. Figure 2.43. Data Memory Write Cycle Timing

AFN-01488A-31 27 8051 Architectural Specification and Functional Description

Figure 2.42. The twelve period External Data Memory The serial port receives a pulse each time that counter I cycle allows the 80S 1 to use peripherals that are relatively overflows. The standard UAR T modes divide this pulse slower than its program memories. The address is emitted rate to generate the transmission rate. from the processor during T3. Data transfer occurs on Counter 0 can also be configured in one of four modes: the bus during T7 through T12. TS and T6 is the period Modes 0-2) Modes 0-2 are the same as for counter I. during which the direction of the bus is changed for the. Mode 3) In Mode 3, the configuration of THO is not read operation. The read cycle begins during T2, with the affected by the bits in TMOD or TCON (see assertion of address latch enable signal ALE The CD . next section). It is configured solely as an 8-bit falling edge of ALE Q) is used to latch the address timer that is enabled for incrementing by information, which is present on the bus at this time CD ' TCON's TRI bit. Upon THO's overflow the into the 8282 latch if a non-multiplexed bus is desired. TFI flag gets set. Thus, neither TRI nor TFI At TS, the address is removed from the Port 0 bus and the processor's bus drivers go to the high-impedance is available to counter I when counter 0 is in state 0. The data memor~ad control signal RD Mode 3. The function of TR I can be done by CD ' is asserted during T7. RD causes the addressed placing counter I in Mode 3, so only the device to enable its bus drivers to the now-released bus. function of TF I is actually given up by At some later time, valid data will become available on counter I. In Mode 3, TLO is configured as an the bus ® . When the 80S1 subsequently returns RD 8-bit timer/counter and is controlled, as usual, by the Gate (TMOD.3), CIT (TMOD.2), TRO to the high level CD ' the addressed device will then float its bus drivers, relinquishing the bus again CD . (TCON.4) and TFO (TCON.S) control bits. Data Memory Write Sequence (Figure 2.43) 2.11.2 Configuring the Timer/Counter Input The write cycle, like the read cycle, begins with the asser The use of the timer/counters is determined by two 8-bit tion of ALE CD and the emission of an address Q) . registers, TMOD (timer mode) and TCON (timer con-" In T6, the processor emits the data to be written into the trol). The counter input circuitry is shown in Figures addressed data memory location CD . This data remains 2.46A and 2.468. The input to the counter circuitry is valid on the bus until the end of the following bus cycle's from an external reference (for use as a counter), or from T2 0. The write signal WR goes low at T6 CD and the on-chip oscillator (for use as a timer), depending on remains active through Tl2 ® . ' whether TMOD's CIT bit is set or cleared, respectively. 2.11 TIMER/COUNTER When used as a time base, the on-chip oscillator frequency is divided by twelve (12) before being input to Two independent 16-bit timer/counters are on-board the the counter circuitry. When TMOD's Gate bit is set (I), 80S 1 for use in measuring time intervals, measuring pulse the external reference input (TI, TO) or the oscillator widths, counting events, and causing periodic (repeti input is gated to the counter conditional upon a second tious) interrupts. external input (INTO, INTI) being high. When the Gate 2.11.1 Timer/Counter Mode Selection bit is zero (0), the external reference or oscillator input is unconditionally enabled. In either case, the normal Counter I can be configured in one of four modes: interrupt function of INTO and INT I is not affected by Mode 0) Provides an 8-bit counter with a divide-by-32 the counter's operation. If enabled, an interrupt will prescaler or an 8-bit timer with a divide-by-32 occur when the input at INTO or INT I is low. The prescaler. A read/write ofTHI accesses counter counters are enabled for incrementing when TCON's l's bits 12-S. A read/write of TLt accesses TR I and TRO bits are set. When the counters overflow counter l's bits 7-0. The programmer should the TFI and TFO bits in TCON get set and interrupt clear the prescaler (counter I's bits 4-0) before requests are generated. The functions of the bits in TCON setting the run flag. are shown in Figure 2.44. Mode I) Configures counter 1 as a 16-bit timer/counter. Mode 2) Configures counter I as an 8-bit auto-reload Bit timer / counter. TH I holds the reload value. TL I Function Flag Location is incremented. The value in TH I is reloaded into Counter interrupt request and TFI TCON.7 TL I when TLt overflows from all ones (I's). An overflow Flag 8048 compatible counter is achieved by configur Counter enable/disable bit TRI TCON.6 ing to mode 2 after zero-ing TH 1. Counter interrupt request and TFO TCON.S Mode 3) When counter I's mode is reprogrammed to overflow Flag mode 3 (from mode 0, I or 2), it disables the Counter enable/disable bit TRO TCON.4 incrementing of the counter. This mode is providt;d as an alternative to using the TR I Figure 2.44. Function of Bits in TeON bit (TCON.6) to start and stop counter I. (Upper Nibble) AFN-01488A-32 28 8051 Architectural Specification and Functional Description

The functions of the bits in TMOD are shown in Figure 2.11.4 Reading and Reloading the Timer/ 2.45. Recall from section 2.3 that the bits in TMOD are Counters not bit addressable. The timer/counters can be read and reloaded on the fly. However, the 16-bit timer/counters must be read and Bit loaded as two 8-bit bytes. During a read the potential Function Flag Location "phasing error" can be programmed around, as follows: Enable input at TI using INTI Gate TMOD.7 RTC MOV A, THO Counter 1/ Timer 1 select CIT TMOD.6 MOVB, TLO C I/T 1 Mode select MSb Ml TMOD.5 CJNE A, THO, RTC C I/T I Mode select LSb MO TMOD.4 Enable input to TO using INTO Gate TMOD.3 2.12 SERIAL CHANNEL - The 8051 has a serialchannel useful for serially linking Counter 0/ Timer 0 select CIT TMOD.2 UART (universal asynchronous receiver/transmitter) C OfT 0 Mode select MSb Ml TMOD.l devices and for expanding I/O. This full-duplex serial C 0/ T 0 Mode select LSb MO TMOD.O I/O port can be programmed to function in one of four operating modes. Figure 2.45. Functions of Bits in TMOD Mode 0) Synchronous I/O expansion using TIL or 2.11.3 Operation CMOS shift registers The counter circuitry counts up to all l's and then Mode 1) UART interface with to-bit frame overflows to either O's or the reload value. Upon and variable transmission rate overflow, TFI or TFO gets set. When an instruction Mode 2) U ART interface with II-bit frame changes the timer's mode or alters its control bits, the and fixed transmission rate actual change occurs at the end of the instruction's Mode 3) U ART interface with II-bit frame execution. and variable transmission rate The T I and TO inputs are sampled near the falling-edge Modes 2 and 3 also provide automatic wake-up of slave of ALE in the tenth, twenty-second, thirty-fourth and processors through interrupt driven address-frame forty-sixth oscillator periods of the instruction-in recognition for multiprocessor communications. Several progress. They are also sampled in the twenty-second schemes of UART interfacing are shown in Figure 2.47 oscillator period of MOVX despite the absence of ALE. and an I/O expansion technique is shown in Figure 2.48. Thus, an external reference's high and low times must each 2.12.1 Serial Port Control and Data Buffer be a minimum of twelve oscillator periods in duration. There is a twelve oscillator period delay from when a Registers toggled input (transition from high to low) is sampled to Data for transmission and from reception reside in the when the counter is incremented. serial port buffer register (SBUF). A write to SBUF

COUNTER 0 MODE 0: 8-8IT TIMER WITH PRESCALER/ 8-BIT COUNTER WITH PRESCALER MODE 1: l8-BIT TIMER/COUNTER MODE 2: 8-BIT AUTO-RELOAD TIMER/COUNTER MODE 3: 8-BIT TIMER/COUNTER (TLO)

TO-----'

XTAL1

Figure 2.46.A. Timer/Event Counter 0 Control and Status Flag Circuitry AFN-01488A-33 29 8051 Architectural Specification and Functional Description

PULSE TO COUNTER 1 SERIAL PORT MODE 0: 8-BIT TIMER WITH PRESCALER/ 8-BIT COUNTER WITH PRESCALER MODE 1: 16-BIT TIMER/COUNTER MODE 2: 8·BIT AUTO·RELOAD TIC MODE 3: PREVENTS INCREMENTING OF TIC

T1 ___--I

COUNTER 0 XTAL1

Figure 2.46.8. Timer/Event Counter 1 Control and Status Flag Circuitry

TXD RXD TXD RXD TXD RXD RXD TXD TXD RXD TXD RXD TXD r---- RXD RXD TXD PORT PIN ~ ffi 8051 8051 8051 8051 8051 8051 8051 8251

A. MULTI·8051 INTERCONNECT-HALF DUPLEX B. MULTI·8051 INTERCONNECT-FULL DUPLEX C. 8051·8251 INTERFACE

Figure 2.47. UART Interfacing Technique

updates the transmitter register, while a read from SBUF

8051 reads a buffer that is updated by the receiver register if / when flag RI is reset. The receiver is double buffered to eliminate the overrun that would occur ifthe CPU failed DATA 14----1 SIN CLOCK to respond to the receiver's interrupt before the beginning PORT PIN of the next frame. In general double buffering of the transmitter is not needed for the high performance 8051 A. IiOINPUT EXPANSION to maintain the serial link at its maximum rate. A minor degradation in data rate can occur in rare events. such as

8051 when the servicing of the transmittter has to wait for a lengthy interrupt service program to complete. In asynchronous mode, false start-bit rejection is provided .OATAt---.... as CLOCK on received frames. A two-out-of-three vote is taken on EN PORT PIN each received bit for noise rejection. The serial port's control and the monitoring of its status is provided by the B. IiOOUTPUT EXPANSION serial port control register (SCON). The contents of the 8-bit SCON register are shown in Figure 2.49. Figure 2.48. I/O Expansion Technique AFN·01488A·34 30 8051 Architectural Specification and Functional Description

following the instruction that updated SBUF. The first Bit bit shifted in from P3.0 is latohed by the clock's rising Function Flag Location edge in the twenty-fourth oscillator period following the Serial Port Operation SMO SCON.7 instruction that cleared the RI flag. One bit is shifted Mode (MSb) every twelvth oscillator period until all eight bits have Serial Port Operation SMI SCON.6 been shifted. Mode (LSb) Conditional Receiver SM2 SCON.5 2.12.2.2 OPERATING MODES 1-3 Enable In the UART Modes (i.e., I through 3), the transmission Receiver Enable REN SCON.4 rate is sub-divided into 16 "ticks." The value of a received Transmitter Data Bit 8 TB8 SCON.3 bit is determined by taking a majority vote after it has Received Data Bit 8 RB8 SCON.2 been sampled during the seventh, eighth and ninth Transmission Complete TI SCON. I "ticks". If two or three ones (I's) are detected, the bit will Interrupt Flag be given a one (I) value; if two or three zeros (O's) are Reception Complete RI SCON.O detected, the bit will be given a zero (0) value. Interrupt Flag Until a start bit arrives, the receiver samples the RXD Figure 2.49. Functions of Bits in SCaN input pin (P3.0) every "tick". One-half bit time (eight "ticks") after the start bit is detected (i.e., a low Mode control hits S MO and S M I program the serial port input level was sampled on "tick" one), the serial port in one of four operating modes. A detailed description of checks its validity (majority vote from "ticks" seven, eight the modes is. provided in section 2.12.2. The receiver and nine) and accepts or rejects it. This provides rejection enable bit (REN) resets the receiver's start/stop logic. of false start bits. When software sets REN to one (1), the receiver's transmission-rate generator is initialized and reception is The contents of the receiver's input shift register is moved enabled. REN must be set as part of the serial channel's to SBUF and RB8 (Modes 2 and 3), and RI is set, when initialization program. When REN is cleared, reception a frame's ninth (Mode 1) or tenth (Modes 2 and 3) bit is is disabled. received. Upon reception of a second frame's ninth or The CPU is informed that the transmitter portion .of tenth bit, the data bits in the shift register are again trans SB UF is empty or the receiver portion is full by TI and RI ferred to SBUF and RB8, but only if software has reset respectively. TI and RI must be cleared as part of the the RI flag. If RI has not been reset, then overrun will interrupt service program so as not to continuously occur since the shift register will continue to accept bits. interrupt the CPU. Since TI and RI are or-ed together to Double buffering the receiver provides the CPU with one generate the serial port's interrupt request, they must be frame-time in which to empty the SBUF and RB8 regis polled to determine· the source of the interrupt. ters. The RI flag is set and bit RB8 is loaded during the ninth "tick" of the received frame's ninth or tenth bit. 2.12.2 Operating Modes The serial port begins looking for the next start bit 2.12.2.1 OPERATING MODE 0 one-half bit time after the center of a stop bit is received. The 1/0 expansion mode, Mode 0, is used to expand the Data is transmitted from the TXD output pin (P3.1) each number of input and output pins. In this mode, a clock time a byte is written to SBUF, even if TI is set. TI is set output is provided for synchronizing the shifting of bits at the beginning of the transmitted tenth (Mode 1) or into or from an external register. Eight bits will be shifted eleventh (Modes 2 or 3) bit. After TI becomes set, if out each time a data byte is written to the serial channel's SBUF is written-to prior to the end of the stop (tenth or data buffer (SBUF), even if TI is set. Each time software eleventh) bit, the transmission of the next frame's start. clears the RI flag, eight bits are shifted into SBUF before bit will not begin until the end of the stop bit. the RI flag is again set. The receiver must be enabled [i.e., In Modes 2 and 3, ifSM2isset, frames are received but an REN set to one (I)] for reception to occur. interrupt request is generated only when the received data The synchronizing clock is output on pin P3.1 and toggles bit 8 (RB8) is a one (1). This feature permits interrupt from high to low near the falling-edge of ALE in the generated wake-up during interprocessor com fifteenth oscillator period following execution of the munications when mUltiple 8051 's are connected to a instruction that updated SBUF or cleared the RI flag. It serial bus. Thus, data bit 8 (RB8) awakens all processors then toggles near the falling-edge of ALE in each on the serial bus only when the master is changing the subsequent sixth oscillator period until 8-bits are address to a different processor. Each processor not transferred. The eighth rising-edge of clock (P3.1) sets the addressed then ignores the subsequent transmission of RI or TI flag. At this point shifting is complete and the control information and data. A protocol for multi-80S I clock is once again high. The first bit is shifted out of P3. 0 serial communications is shown in Figure 2.50. The SM2 at the beginning of the eighteenth oscillator period bit has no effect in Modes 0 and l. AFN-01488A-35 31 8051 Architectural Specification and Functional Description

110BAUDTTV 1. The hardware In each slave's serial port I START IDATA .01 .1 1·21 .31 .41 .51 .61 PARITY I STOP I STOP I begins by listening for an addre88. Receipt TYPICAL ASCII TERMINAL of an addre88 frame will force an Interrupt If START DATA .01 .1 1·21 .31 .41 .51 .61 PARITY 1 STOP the slave's SM2 bit Is set to one (1) to enable I I I "Interrupt on addre88 frame only". OR START 1 DATA.O 1 .1 .21 .31 .41 .51 .6 .7 1 PARITY j STOP 2. The master then transmits a frame con I I I I taining the 8-blt address of the slave that Is to receive the subsequent commands and data. A transmitted addre88 frame has Its OR ninth data bit (TB8) set equal to one (1). I STAAT IDATA.oj .1 1.21.31.41.51.&1.71.81 STOP I 3. When the addre88 frame Is received, each Figur.e 2.52. Typical Frame Formats s'ave's serial port Interrupts its CPU. The CPU then compares the addre88 sent to Its own. 2.12.4 Transmission Rate Generation 4. The 8051 stave which has been addressed The proper timing for the serial I/O data is provided by a then resets Its SM2 bit to zero (0) to receive transmission-rate generator. On-board the 8051, three all subsequent transmissions. All other different methods of transmission rate generation are 8051's leave their SM2 bits at a one (1) to provided. The transmission-rate achievable is dependent Ignore transmissions until a new address upon the operating mode of the serial port. arrives. In the I/O expansion mode (Mode 0) the oscillator 5. The master device then sends controllnfor frequency is simply divdied by 12 to generate the matlon and data, which In tum Is accepted transmission rate. This produces a transmission rate of by the previously addressed 8051 [i.e., the 1M bits per second at 12 MHz. If Modes lor 3 are being one that had set Its SM2 bit to zero (0)]. used, the transmission rate can be generated from the oscillator frequency or from an external reference fre Figure 2.50. Protocol for Multl- Processor quency. In these modes, either one-twelfth the oscillator Communications frequency or the TI input frequency is divided by 256- minus-the-value-in-TH I (counter I must be configured 2.12.3 The Serial Frame in auto-reload mode by software) and then divided by A frame is a string of bits. The frame transmitted and 32 to generate the transmission rate. When the oscillator received in Mode 0 is 8 bits in length. The data bits of the frequency input (rather than TI) is selected, this method frame are transmitted SBUF.O first and SBUF.7 last. produces a transmission rate of 122 to 31,250 bits per second (including start and stop bits) at 12 MHz. The TI The frame transmitted and received in Mode 1 is ten bits external input is selected by setting the C;Tbit to one (1). in length. The frame transmitted and received in Modes 2 When Mode 2 is used, the oscillator frequency is simply and 3 is eleven bits in length. These frames consist of one divided by 64 to generate the transmission rate. This start bit, eight or nine data bits and a stop bit. Data bits 0- produces a transmission rate of 187,500 bits per second 7 are loaded into SBUF.O-SBUF.7 respectively, and data (including start and stop bits) at 12 MHz. bit 8 into RB8 (receive) or TB8 (transmit). With nominal software overhead, the last data bit can be made a parity· bit, as shown in Figure 2.51.

MOV C, P ; Parity moved to carry (byte 2.12.5 UART Error Conditions already in A). There are two UART error conditions that should be MOV TB8, C ; Put carry into Transmitter Bit 8 accounted for when designing systems that use the serial MOV SBUF, A; Load Transmit Register channel.

Figure 2.51. Generating Parity and First, the 805I's serial channel provides no indication that Transmitting Frame a valid stop bit has been received. However, since a start bit is detected as a high-level to low-level transition, the UART will not receive additional frames if a stop bit is Figure 2.52 shows some typical frame formats for not received. different applications. The data bits of the frame are transmitted least significant bit first (SBUF.O) and TB8 Second, the RI flag is set and SBUF and RB8 are loaded last. from the receiver's input shift register when the received

AFN-01488A-36 32 8051 Architectural Specification and Functional Description

last data bit (i.e. ninth or tenth received bit) is sampled. The Schmitt-trigger input has a small internal pull down As long as RI is set, the loading of SBUF, the updating of resistor which permits power-on reset (as shown in Figure RB8 and the generation of further receiver interrupts is 2.54) using only a small capacitor tied to VCe. A con inhibited. Thus, overrun will occur if the programmer ventional external reset circuit, such as that in Figure does not reset RI before reception of the next frame's last 2.55, can also be used. data bit since the receiver's input shift register will shift in a third frame. +5V 2.13 EXTERNAL INTERFACE

2.13.1 Processor Reset and Initialization 8051 .... Processor initialization is accomplished with activation v of the RST /VPO pin. To reset the processor, this pin RSTNPD should be held high for at least twenty-four oscillator periods. Upon powering up, RST /VPO should be held high for at least I ms after the power supply stabilizes to allow the oscillator to stabilize. Upon receipt of RST, the +5V processor ceases instruction execution and remains dormant for the duration of the pUlse. The low-going transition then initiates a sequence which requires 8051 approximately twelve oscillator periods to execute before L~o-~~-._R_S_TN_P_O;- ____ ~ ALE is generated and normal operation commences with the instruction at absolute location OOOOH. This sequence ends with registers initialized as shown in Figure 2.53. t Register Content Figure 2.55. External Reset PC OOOOH SP 07H 2.13.2 Power Down (Standby) Operation of PSW, OPH, OPL, A, B, OOH Internal RAM IP, IE, SCaN, TCON, OOH Data can be maintained valid in the Internal Data RAM TMOO, THl, THO, OOH while the remainder of the 8051 is powered down. When TLl, TLO OOH powered down, the 8051 consumes about 10% of its SBUF Indeterminate normal operating power. During normal operation, both Port 3-PQrt 0 FFH (configures all I/O the CPU and the internal RAM derive their power from pins as inputs) VCC. However, the internal RAM will derive its power Internal RAM Unchanged if VPO from RST/VPD when the voltage on VCC is more than applied; else a diode drop below that on RST/VPD. indeterminate

Figure 2.53 Register Initialization VCC ------i'-...... ___rffl---- I I In addition, certain of the control pins are driven to a wro~~------~~~~~I__ I I __ ------+II ____ ---- TTL high level during initialization. These are ALE/ (POWER·FAIL) INTERRUPT I I I I PROG and PSEN. Thus, no ALE or PSEN signals are I I ~i-----tl ______generated while RST / VPD is high. When the processor RSTNPO ------_. • is reset all ports are immediately written with ones (l's). NORMAL OPERATION SERVICE PROGRAM NORMAL OPERATION

+5V Figure 2.56. Power-Down Sequence 8051 When a power-supply failure is imminent, the user's t system generates a "power-failure" signal to interrupt the RSTNPD processor via INTO or INTI. This power-failure signal must be early enough to allow the 8051 to save all data that is relevant for recovery before VCC falls below its operating limit. The program servicing the power-failure interrupt request must save any important data and Figure 2.54. Power-On Reset machine status into the Internal Data RAM. The service

AFN-01488A-37 33 8051 Architectural Specification and Functional Description

program must also enable the backup power supply to necessary) as the s.ystem clock. The 64K contiguous the RST/VPD pin. Applying power to the RST/VPD pin memory preempts the need for the SEL MBi instructions. resets the 805 I and retains the internal RAM data valid The SEL RBi instructions are preempted by instructions as the VCC power supply falls below limit. Normal opera that manipulate the PSW. tion resumes when RST/VPD is returned low. Figure 2.56 shows the waveforms for the power-down sequence. 2.16 DEVELOPMENT SYSTEM AND SOFTWARE SUPPORT 2.14 EPROM PROGRAMMING The 8051 is supported by a total range of Intel develop The 8751 is programmed and the 8051 and 8751 are ment tools. This broad range of support shortens the verified using the UPP-851 programming card. For pro product development cycle and thus brings the product gramming and verification, address is input on Port I to market sooner. and Port pins 2.0-2.3. Pins P2.4 and P2.5 are held to a • ASM51 Absolute macro assembler for the 8051. TTL low. Data is input and output through Port O. • CONV51 8048 assembly language source code to 8051 RST/VPD is held at a TTL high level and PSEN is held assembly source code conversion program. at a TTL low level during program and verify. To pro-· • EM-51 8051/8751 emulator board that uses a gram, ALE/PROG is held at a TTL low level. ALE/ modified 8051 and an EPROM. PROG is held at a TTL high level to verify the program. • ICE-5J™ Real-time in-circuit emulator. Port pin 2.7 forces the Port 0 output drivers to the high • UPP-851 PROM programmer personality card. impedence state when held at a TTL high level and is held • 8051 Workshop. at a TTL low level for verification. Erasure of an 8751 will leave the EPROM programmed to an all one's (I's) 8051 Software Development Package state. (ASM51 and CONV51) The 8051 software development package provides de- 2.15 THE 8051 AS AN EVOLUTION OF . velopment system support for the powerful 8051 family THE 8048 of single chip microcomputers. The package contains For every 8048 instruction there is a corresponding 8051 a symbolic macro assembler and 8.048 to 8051 source instruction, or in rare cases, a short sequence of instruc code converter. This diskette-based software package tions. An example of the latter is the adjustment required runs under ISIS-II on any Intellec® Microcomputer for the use the 8051 makes of PC- and DPTR-relative Development System with 64K bytes of memory. addressing. Thus, while the 8051 has new bit patterns in its instruction coding, the functions of the 8048 may 8051 Macro Assembler (ASM51) be performed by the 8051. For this purpose Intel provides The 8051 macro assembler translates symbolic 8051 as a conversion program (CONV-51) which translates 8048 sembly language instructions into machine exectuable assembly source code to 8051 assembly source code. In object code. These assembly language mnemonics are the 8051 the stack pointer has been changed from a 3-bit easier to program and are more readable than binary or field in the PSW to an 8-bit register. Therefore, the stack hexidecimal machine instructions. Also, by allowing the pointer does not "roll-over" from address 23 to address 8, programmer to give symbolic names to memory loca but will increment to address 24. In general, 8048 code tions rather than absolute addresses, software design that manipulates the stack pointer cannot be translated and debug are performed more quickly and reliably. by CONV-51. In translating 8048 code, upon an interrupt, ASM51 provides symbolic access for the many useful an unused RAM location can be used for storing the addressing methods in the 8051 architecture. These PSW using the PUSH instruction with Direct Addressing features include referencing bit and byte locations, and to keep the 8051 's stack size equivalent to that of the 8048. provide 4-bit operations for BCD arithmetic. The as 8048 and 8049 programs using only the low-order six or sembler also provides symbolic access to the bits and seven bits of RI and RO in Indirect Addressing must now bytes in the RAM and Special Function Register address use all eight bits. Thus, bit seven (and bit six for 8048 spaces. programs) must be zero. The assembler supports macro definitions and calls. This 8048 operations no longer necessary (and invalid) for the provides a convenient means of programming a frequent 8051 are MOVD, ANLD and ORLD. These instructions ly used code sequence only once. The assembler also control the 8243 I/O expander chip. Since the 8051 uses a provides conditional assembly capabilities. Cross refer shift register for low-cost I/O expansion, these are no encing is provided in the symbol table listing, which longer necessary. However, the 8051 can interface to an shows the user the lines in which each symbol was de 8243 using standard instructions on its ports. Also no fined and referenced. longer needed are the ENTO CLK and SEL MBi instruc If an 8051 program contains errors, the assembler pro tions. The 8051 uses ALE (along with RD and WR when vides a comprehensive set of error diagnostics, which are AFN-Ol488A-38 34 8051 Architectural Specification and Functional OescripUon

included in the assembly listing, or on another file. 8051 Workshop The object code generated may be used t.o program the The workshop provides the design engineer or system 8751 EPROM version of the chip or sent to Intel for designer hands-on experience with the 8051 microcom fabricating the 8051 RO M version. The assembler output puters. The course includes explanation of the Intel 8051 can also be debugged using the ICE-51 in-circuit emulator. architecture, system timing and input / output design. Lab sessions will allow the attendee to gain detailed familiar 8048 to 8051 Assembly Langu~ge Converter ity with the 8051 family and support tools. Utility Program (CONV51) INSITE™ Library The 8048 to 8051 assembly language converter is a utility to help users of the MCS-48 family of microcomputers The INSITE Library contains 8051 utilities and upgrade their designs to the high performance 8051 applications programs. architecture. By converting 8048 source code to 8051 source code, the investment in software developed for 2.17 8051 FAMILY PIN DESCRIPTION the 8048 is maintained when the system is upgraded. VSS 8051 Emulation BO.ard (EM-51) Circuit ground potential. The EM-51 8051 emulation board is a small (2.85" x Vee 5.25; board which emulates an 8031/8051/8751 micro computer using standard PROMs or EPROMs in place +SV power supply during operation, programming and of the 8051's on-chip program memory. The board in verification. cludes a modified 8051 microcomputer, supporting Port 0 circuits, and two sockets for program memory. The user Port 0 is an 8-bit open drain bidirectional 110 port. It is may select two 2716 EPROMs, a 2732 EPROM, or two also the multiplexed low-order address and data bus 3636 J:>ipolar PROMs depending on crystal frequency when using ~xternal memory. It is used for data input and and power requirements. output during programming and verification. Port 0 can sinkl source two TTL loads. 8051 In-Circuit Emulator (ICE-51™) Port 1 The 8051 In-Circuit Emulator resides in the Intellec Port 1 is an 8-bit quasi-bidirectional I/O port. It is used development system. The development system interfaces for the low-order address byte during programming and with the user's 8051 system through an in-cable module verification. Port I can sinkl source one TTL load. with the cable terminating in an 8051 pin-compatible Port 2 plug. Together these replace. the 8051 device in the sys tem. With the emulator plug in place, the designer can Port 2 is an 8-bit quasi-bidirectional 110 port. It also exercise the. system in real-time while collecting up to 255 emits the high-order 8 bits of address when aa:essing instruction cycles of real-time data. In addition, he can external memory. It is used for the high-order address and single step the system program. Static RAM memory is the control signals during programming and verification. available in the ICE-51 module to emulate the 8051's Port 2 can sink/ source one TTL load. internal and external program memories and external Port 3 data memory. The designer can display and alter the Port 3 is an 8-bit quasi-bidirectional 110 port. It also contents of intermil 8051 registers, internal data RAM, contains the interrupt, timer, serial port and RD and WR Special Function Registers, and replacement external pins that are used by various options. The output latch memory. Symbolic reference capability allows the de corresponding to a special function must be programmed signer to use meaningful symbols provided by ASM51 to a one (I) for that function to operate. Port 3 can rather than absolute values when examing and modifying sink/ source one TTL load. The special functions are the memory, registers, flags, and I/O ports in his system. assigned to the pins of Port 3, as follows: - RXD / data (P3.0). Serial port's receiver data input Universal PROM Programmer Personality (asynchronous) or data input I output (synchronous). Card (UPP-851) - TXD/clock (P3.I). Serial port's transmitter data The UPP-851 is a personality card for the UPP-\03 output (asynchronous) or clock output (synchronous). Universal PROM Programmer. The Universal PROM - INTO (P3.2). Interrupt 0 input or gate control input for Programmer is an Intellec system peripheral capable of counter O. programming and verifying the 8751. Programming and - INTI (P3.3). Interrupt 1 input or gate control input for verification operations are initiated from the Intellec counter 1. . development system console and are controlled by the - TO (P3.4). Input to counter O. Universal PROM Mapper (UPM) program. - TI (P3.5). Input to counter 1. AFN-Ol488A-39 35 8051 Architectural Specification and Functional Description

- WR (P3.6). The write control signal latches the data PSEN byte from Port 0 into the External Data Memory. The Program Store Enable output is a control signal that -RD (P3.7). The read control signal enables External enables the external Program Memory to the bus during Data Memory to Port O. normal fetch operations. RSTNpD . EAlVDD A low to high transition on this pin (at approximately 3V) When held at a TTL high level, the 80S I executes resets the 80S 1. If VPD is held within its spec (ap instructions from the internal ROM/EPROM when the proximately +SV), while VCC drops below spec, VPD PC is less than 4096. When held at a TTL low level, the will provide standby power to the RAM. When VPD is 80S I fetches all instructions from external Program low, the RAM's current is drawn from VCC. A small M~mory. The pin also receives the 21 V EPROM internal resistor permits power-on reset using only a programming supply voltage. capacitator connected to VCC. XTAL 1 ALE/PROG . Input to the oscillator's high gain amplifier. A crystal or Provides Address Latch Enable output used for latching external source can be used. the address into external memory during normal opera XTAL 2 tion. Receives the program pulse input during EPROM programming. Output from the oscillator's amplifier. Required when a crystal is used.

AFN·01488A·40 36 8051 Architectural Specification and Functional Description

TABLE 2-1 8051 INSTRUCTION SET SUMMARY Notes on instruction set and addressing modes: Interrupt Response Time: To finish execution of current instruction. Rn ·~Register R7-RO of the currently selected Register Bani<. respond to the interrupt request. push the PC and to vector to the first data -S-bit internal data location's address. This could be an Inter- instruction of the interrupt service progr.am requires 38 to 81 oscillator nal Data RAM location (0-127) or a SFR [i.e. (:0 port. con-. periods (3 to 71's @ 12 MHz). tTOI register. status register. etc. (128-255)]. INSTRUCTIONS THAT AFFECT FLAG SETTINGS' @Ri -g-bit Internal Data RAM location (0-255) addressed indir- ectly through register R I or RD. INSTRUCTION FLAG INSTRVCTION FLAG IIdata -8-bit constant included in instruction. C OV AC C OV AC IIdata 16 -16-bit constant included in instruction. ADD X X X CLR C 0 addrl6 -16-bit destination address. Used by LCALL & LJMP. A ADDC X X X CPL C X branch can be anywhere within the 64K-byte Program Mem SUBB X X X ANL C,bit X ory address space. 'MUL 0 X ANL C: bit X addrll -II-bit destination address. Used by ACALL & AJMP. The DIV 0 X ORL C, bit X branch will be within the same 2K-byte page of program DA X ORL C, bit X memory as the first byte of the following instruction. RRC X MOV C, 'bit X rei ·--Signed (two's complement) 8-bit offset byte. Used by SJMP RLC X CJNE X and all conditionaljumps. Range is-128 to + 127 bytes relative SETB C to first byte of the following instruction. bit -Direct Addressed bit in Internal Data RAM or Special Func tion Register. 'Note that operations on SFR byte address 20X or bit addresses 209-215 * - New operation not pTOvided by 8048 i 8049. (i.e. the PSW or bits in the PSW) will also affect nag settings.

Data Tra nafer Oscillator Logic Oscillator Mnemonic Description Bytes Periods Mnemonic Description Bytes Periods MOV A.Rn Move· register to A I 12 ANL A.Rn AND register to A I 12 "MOV A.data Move direct byte to A 2 12 "ANL A.data AND direct byte to A 2 12 MOV A.@Ri Move indirect RAM to A I 12 ANL A.@Ri AND indirect RAM to A I 12 MOV A.lldata Move immediate data io A 2 12 ANL A.lldata AND immediate data to A 2 12 MOV Rn.A Move A to register I 12 "ANL data.A AND A to direct byte 2 12 "MOV Rn.data Move direct byte to register 2 24 "ANL data.lldata AND immediate data to 3 24 MOV Rn.lldata Move immediate data to 2 12 direct byte register "ANL C,bit AND direct bit to carry 2 24 "MOV data.A Move A to direct byte 2 12 'ANL C,bit ... ND complement of 2 24 "MOV dala.Rn Move register 10 direct byte 2 24 direct bit to carry "MOV data.data Move direct byte to direct 3 24 ORL A.Rn OR register to A I 12 byte "ORL A.data OR direct byte to A 2 12 "MOV data.@Ri Move indirect RAM to 2 24 ORL A.@Ri OR indirect RAM to A I 12 direct byte ORL A.lldata OR immediate data to A 2 12 "MOV data.lldata Move immediate data to 3 24 "ORL data.A OR A to direct byte 2 12 direct byte 'ORL data.lldata OR immediate data to 3 24 [email protected] Move A to indirect RAM I 12 direct byte "MOV @Ri.data Move direct byte to 2 24 "ORL C,bit OR direct bit to carry 24 indirect RAM "ORL C, bit OR complement of direct 24 MOV @Ri,lIdata Move immediate data to 2 12 bit to carry indirect RAM XRL A.Rn Exclusive-OR register to A 12 "MOV DPTR. Move l6-bit constant to 24 "XRL A.data Exclusive-OR direct byte 12 IIdata 16 Data Pointer to A "MOV C,bit Move direct bit to carry 2 12 XRL A.@Ri Exclusive-OR indirect 12 "MOV bit.C Move carry to direct bit 2 24 RAM to A "MOVC A.@A+ Move Program Memory 24 XRL A.lldata Exclusive-OR immediate 12 DPTR byte addressed by data to A A+DPTR to A 'XRL data.A Exclusive-OR A to direct 2 12 "MOVC A.@A+PC Move Program Memory 24 byte byte addre"ed by "XRL data.lldata Exclusive-OR immediate 24 A+PC to A data to direct byte MOVX A.@Ri Move External Data 24 ·SETB C Set carry 1 12 (8-bit address) to A "SETB bit Set direct bit 2 12 "MOVX A.@DPTR Move External Data 24 CLR A Clear A 12 (l6-bit address) to A CLR c.: Clear carry 12 MOVX @Ri.A Move A to External Data 24 ·CLR bit Clear direct bit 2 12 (8-bit address) CPL A Complement A 12 ·MOVX @DPTR.A Move A to External Data 24 CPL C Complement carry 12 (l6-bit address) "CPL bit Complement direct bit 12 ·PUSH data Move direct byte to staci< 2 24 RL A Rotate A Left 12 and,inc. SP RLC A Rotate A Left through 12 'POP data Move direct byte from 2 24 carry staci< and dec. S P RR A Rotate A Right 12 XCH A.Rn Exchange register with A 12 RRC A Rotate A Right through 12 "XCH A.data Exchange direct byte 12 carry with A SWAP A Rotate A left four 12 XCH A.@Ri Exchange indirect RAM 12 (exchange nibbles within with A A) XCHD A.@Ri Exchange indirect RA M', 12 least sig nibble with A's LSN All mnemonics copyrighted© Intel Corporation 1980. AFN-01488A-41 37 8051 Architectural Specification and Functional Description

Arithmetic Oscillator ContrOl Trans'er (Branch) Oscillator Mnemonic Description Bytes Periods Mnemonic Description Byt.. Periods ADD A.Rn Add register to A I 12 AJMP addrll Absolute Jump 2 24 "ADD A.data Add direct byte to A 2 12 "LJMP addrl6 Long Jump 3 24 ADDA.@Ri Add indirect RAM to A I 12 "SJMP rei Short Jump 2 24 ADDA./Idata Add immediate data to A 2 12 "JMP @A+DPTR Jump indirect relative to 24 ADDC A.Rn Add register and carry flag to A I 12 the DPTR *ADDC A.data Add direct byte aild carry flag 2 12 JZ rei Jump if A is zero 2 24 toA JNZ rei Jump if A is not zero 2 24 ADDC A.@Ri Add indirect RAM and carry 12 JC rei Jump if carry is set 2 24 flag to A JNC rei Jump if carry is not set 2 24 ADDC A./Idata Add immediate data and carry 2 12 "JD bit. rei Jump relative if direct bit 3 24 flag to A is set "SUBD A.Rn Subtract register and carry flag 12 "JNB bit. rei Jump relative if direct bit 3 24 from A is not set "SUBD A.data Subtract direct byte and carry 2 12 " J DC bit.rel Jump relative if direct bit 3 24 flag from A is ser. then clear bit "SUBD A.@Ri Subtract indirect RA M and 12 "CJNE A.data.rel Compare direct byte to A 3 24 carry flag from A & Jump if not Eq. "SUBD A./Idata Subtract immediate data aild 2 12 See Note a. carry flag from A 'CJNE A.lldata.rel Compare immed. to A & Jump 3 24 INCA Increment A 12 if not Eq. See Note a. INC Rn Increment register 12 'CJNE Rn.lldata. Compare immed. to reg & 3 24 "INC data Increment direct byte 2 12 rei Jump if not Eq. See Note a. INC@Ri Increment indirect RAM 12 'CNJE @Ri. Compare immed. to indirect 3 24 DECA Decrement A I 12 IIdata.rel RAM & Jump if not Eq. DEC Rn Decrement register I 12 See Note a. "DEC data Decrement direct byte 2 12 DJNZ Rn.rel Decrement register & Jump 3 24 "DEC@Ri Decrement indirect RAM 12 if not zero "INC DPTR Increment Data Pointer 24 'DJNZ data. rei Decrement direct byte & 3 24 'MUL AB Multiply A times D 48 Jump if not zero 'DIV AD Divide A by D 48 Note a) Set C if the first operand is less than the second operand; DAA Decimal add Adjust of A 12 else clear

Control Trans'er (Subroutine) Oscillator Mnemonic Description Bytes Periods Other ACALL addrll Absolute Subroutine Call 2 24 Oscillator LCALL addrl6 Long Subroutine Call 3 24 Mnemonic D ..crlptlon Byt.. Periods RET Return from Subroutine Call 24 NOP No Operation I 12 RETI Return from Interrupt Call 24

All mnemonics copyrighted@ Intel Corporation 1980. AFN-01488A-42 38 INTEL CORPORATION, 3065 Bowers Avenue, Santa Clara, CA 95057 (408) 987-8080

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